target-xtensa/helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec/exec-all.h"
  30 #include "exec/gdbstub.h"
  31 #include "qemu/host-utils.h"
  32 #if !defined(CONFIG_USER_ONLY)
  33 #include "hw/loader.h"
  34 #endif
  35
  36 static struct XtensaConfigList *xtensa_cores;
  37
  38 static void xtensa_core_class_init(ObjectClass *oc, void *data)
  39 {
  40     CPUClass *cc = CPU_CLASS(oc);
  41     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
  42     const XtensaConfig *config = data;
  43
  44     xcc->config = config;
  45
  46     /* Use num_core_regs to see only non-privileged registers in an unmodified
  47      * gdb. Use num_regs to see all registers. gdb modification is required
  48      * for that: reset bit 0 in the 'flags' field of the registers definitions
  49      * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
  50      */
  51     cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
  52 }
  53
  54 void xtensa_finalize_config(XtensaConfig *config)
  55 {
  56     unsigned i, n = 0;
  57
  58     if (config->gdb_regmap.num_regs) {
  59         return;
  60     }
  61
  62     for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
  63         n += (config->gdb_regmap.reg[i].type != 6);
  64     }
  65     config->gdb_regmap.num_regs = n;
  66 }
  67
  68 void xtensa_register_core(XtensaConfigList *node)
  69 {
  70     TypeInfo type = {
  71         .parent = TYPE_XTENSA_CPU,
  72         .class_init = xtensa_core_class_init,
  73         .class_data = (void *)node->config,
  74     };
  75
  76     node->next = xtensa_cores;
  77     xtensa_cores = node;
  78     type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name);
  79     type_register(&type);
  80     g_free((gpointer)type.name);
  81 }
  82
  83 static uint32_t check_hw_breakpoints(CPUXtensaState *env)
  84 {
  85     unsigned i;
  86
  87     for (i = 0; i < env->config->ndbreak; ++i) {
  88         if (env->cpu_watchpoint[i] &&
  89                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
  90             return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
  91         }
  92     }
  93     return 0;
  94 }
  95
  96 void xtensa_breakpoint_handler(CPUState *cs)
  97 {
  98     XtensaCPU *cpu = XTENSA_CPU(cs);
  99     CPUXtensaState *env = &cpu->env;
 100
 101     if (cs->watchpoint_hit) {
 102         if (cs->watchpoint_hit->flags & BP_CPU) {
 103             uint32_t cause;
 104
 105             cs->watchpoint_hit = NULL;
 106             cause = check_hw_breakpoints(env);
 107             if (cause) {
 108                 debug_exception_env(env, cause);
 109             }
 110             cpu_resume_from_signal(cs, NULL);
 111         }
 112     }
 113 }
 114
 115 XtensaCPU *cpu_xtensa_init(const char *cpu_model)
 116 {
 117     ObjectClass *oc;
 118     XtensaCPU *cpu;
 119     CPUXtensaState *env;
 120
 121     oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
 122     if (oc == NULL) {
 123         return NULL;
 124     }
 125
 126     cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
 127     env = &cpu->env;
 128
 129     xtensa_irq_init(env);
 130
 131     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 132
 133     return cpu;
 134 }
 135
 136
 137 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 138 {
 139     XtensaConfigList *core = xtensa_cores;
 140     cpu_fprintf(f, "Available CPUs:\n");
 141     for (; core; core = core->next) {
 142         cpu_fprintf(f, "  %s\n", core->config->name);
 143     }
 144 }
 145
 146 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 147 {
 148     XtensaCPU *cpu = XTENSA_CPU(cs);
 149     uint32_t paddr;
 150     uint32_t page_size;
 151     unsigned access;
 152
 153     if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
 154                 &paddr, &page_size, &access) == 0) {
 155         return paddr;
 156     }
 157     if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
 158                 &paddr, &page_size, &access) == 0) {
 159         return paddr;
 160     }
 161     return ~0;
 162 }
 163
 164 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
 165 {
 166     if (xtensa_option_enabled(env->config,
 167                 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
 168         return vector - env->config->vecbase + env->sregs[VECBASE];
 169     } else {
 170         return vector;
 171     }
 172 }
 173
 174 /*!
 175  * Handle penging IRQ.
 176  * For the high priority interrupt jump to the corresponding interrupt vector.
 177  * For the level-1 interrupt convert it to either user, kernel or double
 178  * exception with the 'level-1 interrupt' exception cause.
 179  */
 180 static void handle_interrupt(CPUXtensaState *env)
 181 {
 182     int level = env->pending_irq_level;
 183
 184     if (level > xtensa_get_cintlevel(env) &&
 185             level <= env->config->nlevel &&
 186             (env->config->level_mask[level] &
 187              env->sregs[INTSET] &
 188              env->sregs[INTENABLE])) {
 189         CPUState *cs = CPU(xtensa_env_get_cpu(env));
 190
 191         if (level > 1) {
 192             env->sregs[EPC1 + level - 1] = env->pc;
 193             env->sregs[EPS2 + level - 2] = env->sregs[PS];
 194             env->sregs[PS] =
 195                 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
 196             env->pc = relocated_vector(env,
 197                     env->config->interrupt_vector[level]);
 198         } else {
 199             env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
 200
 201             if (env->sregs[PS] & PS_EXCM) {
 202                 if (env->config->ndepc) {
 203                     env->sregs[DEPC] = env->pc;
 204                 } else {
 205                     env->sregs[EPC1] = env->pc;
 206                 }
 207                 cs->exception_index = EXC_DOUBLE;
 208             } else {
 209                 env->sregs[EPC1] = env->pc;
 210                 cs->exception_index =
 211                     (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 212             }
 213             env->sregs[PS] |= PS_EXCM;
 214         }
 215         env->exception_taken = 1;
 216     }
 217 }
 218
 219 void xtensa_cpu_do_interrupt(CPUState *cs)
 220 {
 221     XtensaCPU *cpu = XTENSA_CPU(cs);
 222     CPUXtensaState *env = &cpu->env;
 223
 224     if (cs->exception_index == EXC_IRQ) {
 225         qemu_log_mask(CPU_LOG_INT,
 226                 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
 227                 "pc = %08x, a0 = %08x, ps = %08x, "
 228                 "intset = %08x, intenable = %08x, "
 229                 "ccount = %08x\n",
 230                 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
 231                 env->pc, env->regs[0], env->sregs[PS],
 232                 env->sregs[INTSET], env->sregs[INTENABLE],
 233                 env->sregs[CCOUNT]);
 234         handle_interrupt(env);
 235     }
 236
 237     switch (cs->exception_index) {
 238     case EXC_WINDOW_OVERFLOW4:
 239     case EXC_WINDOW_UNDERFLOW4:
 240     case EXC_WINDOW_OVERFLOW8:
 241     case EXC_WINDOW_UNDERFLOW8:
 242     case EXC_WINDOW_OVERFLOW12:
 243     case EXC_WINDOW_UNDERFLOW12:
 244     case EXC_KERNEL:
 245     case EXC_USER:
 246     case EXC_DOUBLE:
 247     case EXC_DEBUG:
 248         qemu_log_mask(CPU_LOG_INT, "%s(%d) "
 249                 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
 250                 __func__, cs->exception_index,
 251                 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
 252         if (env->config->exception_vector[cs->exception_index]) {
 253             env->pc = relocated_vector(env,
 254                     env->config->exception_vector[cs->exception_index]);
 255             env->exception_taken = 1;
 256         } else {
 257             qemu_log("%s(pc = %08x) bad exception_index: %d\n",
 258                     __func__, env->pc, cs->exception_index);
 259         }
 260         break;
 261
 262     case EXC_IRQ:
 263         break;
 264
 265     default:
 266         qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
 267                 __func__, env->pc, cs->exception_index);
 268         break;
 269     }
 270     check_interrupts(env);
 271 }
 272
 273 bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 274 {
 275     if (interrupt_request & CPU_INTERRUPT_HARD) {
 276         cs->exception_index = EXC_IRQ;
 277         xtensa_cpu_do_interrupt(cs);
 278         return true;
 279     }
 280     return false;
 281 }
 282
 283 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
 284         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 285 {
 286     unsigned wi, ei;
 287
 288     for (wi = 0; wi < tlb->nways; ++wi) {
 289         for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
 290             entry[wi][ei].asid = 0;
 291             entry[wi][ei].variable = true;
 292         }
 293     }
 294 }
 295
 296 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
 297         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 298 {
 299     if (!tlb->varway56) {
 300         static const xtensa_tlb_entry way5[] = {
 301             {
 302                 .vaddr = 0xd0000000,
 303                 .paddr = 0,
 304                 .asid = 1,
 305                 .attr = 7,
 306                 .variable = false,
 307             }, {
 308                 .vaddr = 0xd8000000,
 309                 .paddr = 0,
 310                 .asid = 1,
 311                 .attr = 3,
 312                 .variable = false,
 313             }
 314         };
 315         static const xtensa_tlb_entry way6[] = {
 316             {
 317                 .vaddr = 0xe0000000,
 318                 .paddr = 0xf0000000,
 319                 .asid = 1,
 320                 .attr = 7,
 321                 .variable = false,
 322             }, {
 323                 .vaddr = 0xf0000000,
 324                 .paddr = 0xf0000000,
 325                 .asid = 1,
 326                 .attr = 3,
 327                 .variable = false,
 328             }
 329         };
 330         memcpy(entry[5], way5, sizeof(way5));
 331         memcpy(entry[6], way6, sizeof(way6));
 332     } else {
 333         uint32_t ei;
 334         for (ei = 0; ei < 8; ++ei) {
 335             entry[6][ei].vaddr = ei << 29;
 336             entry[6][ei].paddr = ei << 29;
 337             entry[6][ei].asid = 1;
 338             entry[6][ei].attr = 3;
 339         }
 340     }
 341 }
 342
 343 static void reset_tlb_region_way0(CPUXtensaState *env,
 344         xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 345 {
 346     unsigned ei;
 347
 348     for (ei = 0; ei < 8; ++ei) {
 349         entry[0][ei].vaddr = ei << 29;
 350         entry[0][ei].paddr = ei << 29;
 351         entry[0][ei].asid = 1;
 352         entry[0][ei].attr = 2;
 353         entry[0][ei].variable = true;
 354     }
 355 }
 356
 357 void reset_mmu(CPUXtensaState *env)
 358 {
 359     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 360         env->sregs[RASID] = 0x04030201;
 361         env->sregs[ITLBCFG] = 0;
 362         env->sregs[DTLBCFG] = 0;
 363         env->autorefill_idx = 0;
 364         reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
 365         reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
 366         reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
 367         reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
 368     } else {
 369         reset_tlb_region_way0(env, env->itlb);
 370         reset_tlb_region_way0(env, env->dtlb);
 371     }
 372 }
 373
 374 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
 375 {
 376     unsigned i;
 377     for (i = 0; i < 4; ++i) {
 378         if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
 379             return i;
 380         }
 381     }
 382     return 0xff;
 383 }
 384
 385 /*!
 386  * Lookup xtensa TLB for the given virtual address.
 387  * See ISA, 4.6.2.2
 388  *
 389  * \param pwi: [out] way index
 390  * \param pei: [out] entry index
 391  * \param pring: [out] access ring
 392  * \return 0 if ok, exception cause code otherwise
 393  */
 394 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 395         uint32_t *pwi, uint32_t *pei, uint8_t *pring)
 396 {
 397     const xtensa_tlb *tlb = dtlb ?
 398         &env->config->dtlb : &env->config->itlb;
 399     const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
 400         env->dtlb : env->itlb;
 401
 402     int nhits = 0;
 403     unsigned wi;
 404
 405     for (wi = 0; wi < tlb->nways; ++wi) {
 406         uint32_t vpn;
 407         uint32_t ei;
 408         split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
 409         if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
 410             unsigned ring = get_ring(env, entry[wi][ei].asid);
 411             if (ring < 4) {
 412                 if (++nhits > 1) {
 413                     return dtlb ?
 414                         LOAD_STORE_TLB_MULTI_HIT_CAUSE :
 415                         INST_TLB_MULTI_HIT_CAUSE;
 416                 }
 417                 *pwi = wi;
 418                 *pei = ei;
 419                 *pring = ring;
 420             }
 421         }
 422     }
 423     return nhits ? 0 :
 424         (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
 425 }
 426
 427 /*!
 428  * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
 429  * See ISA, 4.6.5.10
 430  */
 431 static unsigned mmu_attr_to_access(uint32_t attr)
 432 {
 433     unsigned access = 0;
 434
 435     if (attr < 12) {
 436         access |= PAGE_READ;
 437         if (attr & 0x1) {
 438             access |= PAGE_EXEC;
 439         }
 440         if (attr & 0x2) {
 441             access |= PAGE_WRITE;
 442         }
 443
 444         switch (attr & 0xc) {
 445         case 0:
 446             access |= PAGE_CACHE_BYPASS;
 447             break;
 448
 449         case 4:
 450             access |= PAGE_CACHE_WB;
 451             break;
 452
 453         case 8:
 454             access |= PAGE_CACHE_WT;
 455             break;
 456         }
 457     } else if (attr == 13) {
 458         access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
 459     }
 460     return access;
 461 }
 462
 463 /*!
 464  * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
 465  * See ISA, 4.6.3.3
 466  */
 467 static unsigned region_attr_to_access(uint32_t attr)
 468 {
 469     static const unsigned access[16] = {
 470          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 471          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 472          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 473          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 474          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 475          [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 476         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 477     };
 478
 479     return access[attr & 0xf];
 480 }
 481
 482 /*!
 483  * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
 484  * See ISA, A.2.14 The Cache Attribute Register
 485  */
 486 static unsigned cacheattr_attr_to_access(uint32_t attr)
 487 {
 488     static const unsigned access[16] = {
 489          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 490          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 491          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 492          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 493          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 494         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 495     };
 496
 497     return access[attr & 0xf];
 498 }
 499
 500 static bool is_access_granted(unsigned access, int is_write)
 501 {
 502     switch (is_write) {
 503     case 0:
 504         return access & PAGE_READ;
 505
 506     case 1:
 507         return access & PAGE_WRITE;
 508
 509     case 2:
 510         return access & PAGE_EXEC;
 511
 512     default:
 513         return 0;
 514     }
 515 }
 516
 517 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
 518
 519 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
 520         uint32_t vaddr, int is_write, int mmu_idx,
 521         uint32_t *paddr, uint32_t *page_size, unsigned *access,
 522         bool may_lookup_pt)
 523 {
 524     bool dtlb = is_write != 2;
 525     uint32_t wi;
 526     uint32_t ei;
 527     uint8_t ring;
 528     uint32_t vpn;
 529     uint32_t pte;
 530     const xtensa_tlb_entry *entry = NULL;
 531     xtensa_tlb_entry tmp_entry;
 532     int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
 533
 534     if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
 535             may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
 536         ring = (pte >> 4) & 0x3;
 537         wi = 0;
 538         split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
 539
 540         if (update_tlb) {
 541             wi = ++env->autorefill_idx & 0x3;
 542             xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
 543             env->sregs[EXCVADDR] = vaddr;
 544             qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
 545                           __func__, vaddr, vpn, pte);
 546         } else {
 547             xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
 548             entry = &tmp_entry;
 549         }
 550         ret = 0;
 551     }
 552     if (ret != 0) {
 553         return ret;
 554     }
 555
 556     if (entry == NULL) {
 557         entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 558     }
 559
 560     if (ring < mmu_idx) {
 561         return dtlb ?
 562             LOAD_STORE_PRIVILEGE_CAUSE :
 563             INST_FETCH_PRIVILEGE_CAUSE;
 564     }
 565
 566     *access = mmu_attr_to_access(entry->attr) &
 567         ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
 568     if (!is_access_granted(*access, is_write)) {
 569         return dtlb ?
 570             (is_write ?
 571              STORE_PROHIBITED_CAUSE :
 572              LOAD_PROHIBITED_CAUSE) :
 573             INST_FETCH_PROHIBITED_CAUSE;
 574     }
 575
 576     *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
 577     *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 578
 579     return 0;
 580 }
 581
 582 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
 583 {
 584     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 585     uint32_t paddr;
 586     uint32_t page_size;
 587     unsigned access;
 588     uint32_t pt_vaddr =
 589         (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
 590     int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
 591             &paddr, &page_size, &access, false);
 592
 593     qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
 594                   __func__, vaddr, ret ? ~0 : paddr);
 595
 596     if (ret == 0) {
 597         *pte = ldl_phys(cs->as, paddr);
 598     }
 599     return ret;
 600 }
 601
 602 static int get_physical_addr_region(CPUXtensaState *env,
 603         uint32_t vaddr, int is_write, int mmu_idx,
 604         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 605 {
 606     bool dtlb = is_write != 2;
 607     uint32_t wi = 0;
 608     uint32_t ei = (vaddr >> 29) & 0x7;
 609     const xtensa_tlb_entry *entry =
 610         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 611
 612     *access = region_attr_to_access(entry->attr);
 613     if (!is_access_granted(*access, is_write)) {
 614         return dtlb ?
 615             (is_write ?
 616              STORE_PROHIBITED_CAUSE :
 617              LOAD_PROHIBITED_CAUSE) :
 618             INST_FETCH_PROHIBITED_CAUSE;
 619     }
 620
 621     *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
 622     *page_size = ~REGION_PAGE_MASK + 1;
 623
 624     return 0;
 625 }
 626
 627 /*!
 628  * Convert virtual address to physical addr.
 629  * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
 630  *
 631  * \return 0 if ok, exception cause code otherwise
 632  */
 633 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 634         uint32_t vaddr, int is_write, int mmu_idx,
 635         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 636 {
 637     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 638         return get_physical_addr_mmu(env, update_tlb,
 639                 vaddr, is_write, mmu_idx, paddr, page_size, access, true);
 640     } else if (xtensa_option_bits_enabled(env->config,
 641                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 642                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
 643         return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
 644                 paddr, page_size, access);
 645     } else {
 646         *paddr = vaddr;
 647         *page_size = TARGET_PAGE_SIZE;
 648         *access = cacheattr_attr_to_access(
 649                 env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
 650         return 0;
 651     }
 652 }
 653
 654 static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
 655         CPUXtensaState *env, bool dtlb)
 656 {
 657     unsigned wi, ei;
 658     const xtensa_tlb *conf =
 659         dtlb ? &env->config->dtlb : &env->config->itlb;
 660     unsigned (*attr_to_access)(uint32_t) =
 661         xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
 662         mmu_attr_to_access : region_attr_to_access;
 663
 664     for (wi = 0; wi < conf->nways; ++wi) {
 665         uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 666         const char *sz_text;
 667         bool print_header = true;
 668
 669         if (sz >= 0x100000) {
 670             sz >>= 20;
 671             sz_text = "MB";
 672         } else {
 673             sz >>= 10;
 674             sz_text = "KB";
 675         }
 676
 677         for (ei = 0; ei < conf->way_size[wi]; ++ei) {
 678             const xtensa_tlb_entry *entry =
 679                 xtensa_tlb_get_entry(env, dtlb, wi, ei);
 680
 681             if (entry->asid) {
 682                 static const char * const cache_text[8] = {
 683                     [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
 684                     [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
 685                     [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
 686                     [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
 687                 };
 688                 unsigned access = attr_to_access(entry->attr);
 689                 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
 690                     PAGE_CACHE_SHIFT;
 691
 692                 if (print_header) {
 693                     print_header = false;
 694                     cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
 695                     cpu_fprintf(f,
 696                             "\tVaddr       Paddr       ASID  Attr RWX Cache\n"
 697                             "\t----------  ----------  ----  ---- --- -------\n");
 698                 }
 699                 cpu_fprintf(f,
 700                         "\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c %-7s\n",
 701                         entry->vaddr,
 702                         entry->paddr,
 703                         entry->asid,
 704                         entry->attr,
 705                         (access & PAGE_READ) ? 'R' : '-',
 706                         (access & PAGE_WRITE) ? 'W' : '-',
 707                         (access & PAGE_EXEC) ? 'X' : '-',
 708                         cache_text[cache_idx] ? cache_text[cache_idx] :
 709                             "Invalid");
 710             }
 711         }
 712     }
 713 }
 714
 715 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
 716 {
 717     if (xtensa_option_bits_enabled(env->config,
 718                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 719                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
 720                 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
 721
 722         cpu_fprintf(f, "ITLB:\n");
 723         dump_tlb(f, cpu_fprintf, env, false);
 724         cpu_fprintf(f, "\nDTLB:\n");
 725         dump_tlb(f, cpu_fprintf, env, true);
 726     } else {
 727         cpu_fprintf(f, "No TLB for this CPU core\n");
 728     }
 729 }