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trace: portable simple trace backend using glib
[qemu.git] / hw / pci.c
blob5c4f071d28db5b0f4fe7cf451c7b8deb0c7076e4
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162 /* TODO: call the below unconditionally once all pci devices
163 * are qdevified */
164 if (dev->qdev.info) {
165 qdev_reset_all(&dev->qdev);
166 }
167
168 dev->irq_state = 0;
169 pci_update_irq_status(dev);
170 pci_device_deassert_intx(dev);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
173 pci_get_word(dev->wmask + PCI_COMMAND) |
174 pci_get_word(dev->w1cmask + PCI_COMMAND));
175 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
176 pci_get_word(dev->wmask + PCI_STATUS) |
177 pci_get_word(dev->w1cmask + PCI_STATUS));
178 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
179 dev->config[PCI_INTERRUPT_LINE] = 0x0;
180 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
181 PCIIORegion *region = &dev->io_regions[r];
182 if (!region->size) {
183 continue;
184 }
185
186 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
187 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
188 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
189 } else {
190 pci_set_long(dev->config + pci_bar(dev, r), region->type);
191 }
192 }
193 pci_update_mappings(dev);
194 }
195
196 /*
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
199 */
200 void pci_bus_reset(PCIBus *bus)
201 {
202 int i;
203
204 for (i = 0; i < bus->nirq; i++) {
205 bus->irq_count[i] = 0;
206 }
207 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
208 if (bus->devices[i]) {
209 pci_device_reset(bus->devices[i]);
210 }
211 }
212 }
213
214 static int pcibus_reset(BusState *qbus)
215 {
216 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
217
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
220 return 1;
221 }
222
223 static void pci_host_bus_register(int domain, PCIBus *bus)
224 {
225 struct PCIHostBus *host;
226 host = g_malloc0(sizeof(*host));
227 host->domain = domain;
228 host->bus = bus;
229 QLIST_INSERT_HEAD(&host_buses, host, next);
230 }
231
232 PCIBus *pci_find_root_bus(int domain)
233 {
234 struct PCIHostBus *host;
235
236 QLIST_FOREACH(host, &host_buses, next) {
237 if (host->domain == domain) {
238 return host->bus;
239 }
240 }
241
242 return NULL;
243 }
244
245 int pci_find_domain(const PCIBus *bus)
246 {
247 PCIDevice *d;
248 struct PCIHostBus *host;
249
250 /* obtain root bus */
251 while ((d = bus->parent_dev) != NULL) {
252 bus = d->bus;
253 }
254
255 QLIST_FOREACH(host, &host_buses, next) {
256 if (host->bus == bus) {
257 return host->domain;
258 }
259 }
260
261 abort(); /* should not be reached */
262 return -1;
263 }
264
265 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
266 const char *name,
267 MemoryRegion *address_space_mem,
268 MemoryRegion *address_space_io,
269 uint8_t devfn_min)
270 {
271 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
272 assert(PCI_FUNC(devfn_min) == 0);
273 bus->devfn_min = devfn_min;
274 bus->address_space_mem = address_space_mem;
275 bus->address_space_io = address_space_io;
276
277 /* host bridge */
278 QLIST_INIT(&bus->child);
279 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
280
281 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
282 }
283
284 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
285 MemoryRegion *address_space_mem,
286 MemoryRegion *address_space_io,
287 uint8_t devfn_min)
288 {
289 PCIBus *bus;
290
291 bus = g_malloc0(sizeof(*bus));
292 bus->qbus.qdev_allocated = 1;
293 pci_bus_new_inplace(bus, parent, name, address_space_mem,
294 address_space_io, devfn_min);
295 return bus;
296 }
297
298 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
299 void *irq_opaque, int nirq)
300 {
301 bus->set_irq = set_irq;
302 bus->map_irq = map_irq;
303 bus->irq_opaque = irq_opaque;
304 bus->nirq = nirq;
305 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
306 }
307
308 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
309 {
310 bus->qbus.allow_hotplug = 1;
311 bus->hotplug = hotplug;
312 bus->hotplug_qdev = qdev;
313 }
314
315 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
316 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
317 void *irq_opaque,
318 MemoryRegion *address_space_mem,
319 MemoryRegion *address_space_io,
320 uint8_t devfn_min, int nirq)
321 {
322 PCIBus *bus;
323
324 bus = pci_bus_new(parent, name, address_space_mem,
325 address_space_io, devfn_min);
326 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
327 return bus;
328 }
329
330 int pci_bus_num(PCIBus *s)
331 {
332 if (!s->parent_dev)
333 return 0; /* pci host bridge */
334 return s->parent_dev->config[PCI_SECONDARY_BUS];
335 }
336
337 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
338 {
339 PCIDevice *s = container_of(pv, PCIDevice, config);
340 uint8_t *config;
341 int i;
342
343 assert(size == pci_config_size(s));
344 config = g_malloc(size);
345
346 qemu_get_buffer(f, config, size);
347 for (i = 0; i < size; ++i) {
348 if ((config[i] ^ s->config[i]) &
349 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
350 g_free(config);
351 return -EINVAL;
352 }
353 }
354 memcpy(s->config, config, size);
355
356 pci_update_mappings(s);
357
358 g_free(config);
359 return 0;
360 }
361
362 /* just put buffer */
363 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
364 {
365 const uint8_t **v = pv;
366 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
367 qemu_put_buffer(f, *v, size);
368 }
369
370 static VMStateInfo vmstate_info_pci_config = {
371 .name = "pci config",
372 .get = get_pci_config_device,
373 .put = put_pci_config_device,
374 };
375
376 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
377 {
378 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
379 uint32_t irq_state[PCI_NUM_PINS];
380 int i;
381 for (i = 0; i < PCI_NUM_PINS; ++i) {
382 irq_state[i] = qemu_get_be32(f);
383 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
384 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
385 irq_state[i]);
386 return -EINVAL;
387 }
388 }
389
390 for (i = 0; i < PCI_NUM_PINS; ++i) {
391 pci_set_irq_state(s, i, irq_state[i]);
392 }
393
394 return 0;
395 }
396
397 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
398 {
399 int i;
400 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
401
402 for (i = 0; i < PCI_NUM_PINS; ++i) {
403 qemu_put_be32(f, pci_irq_state(s, i));
404 }
405 }
406
407 static VMStateInfo vmstate_info_pci_irq_state = {
408 .name = "pci irq state",
409 .get = get_pci_irq_state,
410 .put = put_pci_irq_state,
411 };
412
413 const VMStateDescription vmstate_pci_device = {
414 .name = "PCIDevice",
415 .version_id = 2,
416 .minimum_version_id = 1,
417 .minimum_version_id_old = 1,
418 .fields = (VMStateField []) {
419 VMSTATE_INT32_LE(version_id, PCIDevice),
420 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
421 vmstate_info_pci_config,
422 PCI_CONFIG_SPACE_SIZE),
423 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
424 vmstate_info_pci_irq_state,
425 PCI_NUM_PINS * sizeof(int32_t)),
426 VMSTATE_END_OF_LIST()
427 }
428 };
429
430 const VMStateDescription vmstate_pcie_device = {
431 .name = "PCIDevice",
432 .version_id = 2,
433 .minimum_version_id = 1,
434 .minimum_version_id_old = 1,
435 .fields = (VMStateField []) {
436 VMSTATE_INT32_LE(version_id, PCIDevice),
437 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
438 vmstate_info_pci_config,
439 PCIE_CONFIG_SPACE_SIZE),
440 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
441 vmstate_info_pci_irq_state,
442 PCI_NUM_PINS * sizeof(int32_t)),
443 VMSTATE_END_OF_LIST()
444 }
445 };
446
447 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
448 {
449 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
450 }
451
452 void pci_device_save(PCIDevice *s, QEMUFile *f)
453 {
454 /* Clear interrupt status bit: it is implicit
455 * in irq_state which we are saving.
456 * This makes us compatible with old devices
457 * which never set or clear this bit. */
458 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
459 vmstate_save_state(f, pci_get_vmstate(s), s);
460 /* Restore the interrupt status bit. */
461 pci_update_irq_status(s);
462 }
463
464 int pci_device_load(PCIDevice *s, QEMUFile *f)
465 {
466 int ret;
467 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
468 /* Restore the interrupt status bit. */
469 pci_update_irq_status(s);
470 return ret;
471 }
472
473 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
474 {
475 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
476 pci_default_sub_vendor_id);
477 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
478 pci_default_sub_device_id);
479 }
480
481 /*
482 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
483 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
484 */
485 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
486 unsigned int *slotp, unsigned int *funcp)
487 {
488 const char *p;
489 char *e;
490 unsigned long val;
491 unsigned long dom = 0, bus = 0;
492 unsigned int slot = 0;
493 unsigned int func = 0;
494
495 p = addr;
496 val = strtoul(p, &e, 16);
497 if (e == p)
498 return -1;
499 if (*e == ':') {
500 bus = val;
501 p = e + 1;
502 val = strtoul(p, &e, 16);
503 if (e == p)
504 return -1;
505 if (*e == ':') {
506 dom = bus;
507 bus = val;
508 p = e + 1;
509 val = strtoul(p, &e, 16);
510 if (e == p)
511 return -1;
512 }
513 }
514
515 slot = val;
516
517 if (funcp != NULL) {
518 if (*e != '.')
519 return -1;
520
521 p = e + 1;
522 val = strtoul(p, &e, 16);
523 if (e == p)
524 return -1;
525
526 func = val;
527 }
528
529 /* if funcp == NULL func is 0 */
530 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
531 return -1;
532
533 if (*e)
534 return -1;
535
536 /* Note: QEMU doesn't implement domains other than 0 */
537 if (!pci_find_bus(pci_find_root_bus(dom), bus))
538 return -1;
539
540 *domp = dom;
541 *busp = bus;
542 *slotp = slot;
543 if (funcp != NULL)
544 *funcp = func;
545 return 0;
546 }
547
548 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
549 unsigned *slotp)
550 {
551 /* strip legacy tag */
552 if (!strncmp(addr, "pci_addr=", 9)) {
553 addr += 9;
554 }
555 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
556 monitor_printf(mon, "Invalid pci address\n");
557 return -1;
558 }
559 return 0;
560 }
561
562 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
563 {
564 int dom, bus;
565 unsigned slot;
566
567 if (!devaddr) {
568 *devfnp = -1;
569 return pci_find_bus(pci_find_root_bus(0), 0);
570 }
571
572 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
573 return NULL;
574 }
575
576 *devfnp = PCI_DEVFN(slot, 0);
577 return pci_find_bus(pci_find_root_bus(dom), bus);
578 }
579
580 static void pci_init_cmask(PCIDevice *dev)
581 {
582 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
583 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
584 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
585 dev->cmask[PCI_REVISION_ID] = 0xff;
586 dev->cmask[PCI_CLASS_PROG] = 0xff;
587 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
588 dev->cmask[PCI_HEADER_TYPE] = 0xff;
589 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
590 }
591
592 static void pci_init_wmask(PCIDevice *dev)
593 {
594 int config_size = pci_config_size(dev);
595
596 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
597 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
598 pci_set_word(dev->wmask + PCI_COMMAND,
599 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
600 PCI_COMMAND_INTX_DISABLE);
601 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
602 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
603 }
604
605 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
606 config_size - PCI_CONFIG_HEADER_SIZE);
607 }
608
609 static void pci_init_w1cmask(PCIDevice *dev)
610 {
611 /*
612 * Note: It's okay to set w1cmask even for readonly bits as
613 * long as their value is hardwired to 0.
614 */
615 pci_set_word(dev->w1cmask + PCI_STATUS,
616 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
617 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
618 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
619 }
620
621 static void pci_init_wmask_bridge(PCIDevice *d)
622 {
623 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
624 PCI_SEC_LETENCY_TIMER */
625 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
626
627 /* base and limit */
628 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
629 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
630 pci_set_word(d->wmask + PCI_MEMORY_BASE,
631 PCI_MEMORY_RANGE_MASK & 0xffff);
632 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
633 PCI_MEMORY_RANGE_MASK & 0xffff);
634 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
635 PCI_PREF_RANGE_MASK & 0xffff);
636 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
637 PCI_PREF_RANGE_MASK & 0xffff);
638
639 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
640 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
641
642 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
643 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
644 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
645 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
646 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
647 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
648 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
649 PCI_BRIDGE_CTL_PARITY |
650 PCI_BRIDGE_CTL_SERR |
651 PCI_BRIDGE_CTL_ISA |
652 PCI_BRIDGE_CTL_VGA |
653 PCI_BRIDGE_CTL_VGA_16BIT |
654 PCI_BRIDGE_CTL_MASTER_ABORT |
655 PCI_BRIDGE_CTL_BUS_RESET |
656 PCI_BRIDGE_CTL_FAST_BACK |
657 PCI_BRIDGE_CTL_DISCARD |
658 PCI_BRIDGE_CTL_SEC_DISCARD |
659 PCI_BRIDGE_CTL_DISCARD_SERR);
660 /* Below does not do anything as we never set this bit, put here for
661 * completeness. */
662 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
663 PCI_BRIDGE_CTL_DISCARD_STATUS);
664 }
665
666 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
667 {
668 uint8_t slot = PCI_SLOT(dev->devfn);
669 uint8_t func;
670
671 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
672 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
673 }
674
675 /*
676 * multifunction bit is interpreted in two ways as follows.
677 * - all functions must set the bit to 1.
678 * Example: Intel X53
679 * - function 0 must set the bit, but the rest function (> 0)
680 * is allowed to leave the bit to 0.
681 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
682 *
683 * So OS (at least Linux) checks the bit of only function 0,
684 * and doesn't see the bit of function > 0.
685 *
686 * The below check allows both interpretation.
687 */
688 if (PCI_FUNC(dev->devfn)) {
689 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
690 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
691 /* function 0 should set multifunction bit */
692 error_report("PCI: single function device can't be populated "
693 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
694 return -1;
695 }
696 return 0;
697 }
698
699 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
700 return 0;
701 }
702 /* function 0 indicates single function, so function > 0 must be NULL */
703 for (func = 1; func < PCI_FUNC_MAX; ++func) {
704 if (bus->devices[PCI_DEVFN(slot, func)]) {
705 error_report("PCI: %x.0 indicates single function, "
706 "but %x.%x is already populated.",
707 slot, slot, func);
708 return -1;
709 }
710 }
711 return 0;
712 }
713
714 static void pci_config_alloc(PCIDevice *pci_dev)
715 {
716 int config_size = pci_config_size(pci_dev);
717
718 pci_dev->config = g_malloc0(config_size);
719 pci_dev->cmask = g_malloc0(config_size);
720 pci_dev->wmask = g_malloc0(config_size);
721 pci_dev->w1cmask = g_malloc0(config_size);
722 pci_dev->used = g_malloc0(config_size);
723 }
724
725 static void pci_config_free(PCIDevice *pci_dev)
726 {
727 g_free(pci_dev->config);
728 g_free(pci_dev->cmask);
729 g_free(pci_dev->wmask);
730 g_free(pci_dev->w1cmask);
731 g_free(pci_dev->used);
732 }
733
734 /* -1 for devfn means auto assign */
735 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
736 const char *name, int devfn,
737 const PCIDeviceInfo *info)
738 {
739 PCIConfigReadFunc *config_read = info->config_read;
740 PCIConfigWriteFunc *config_write = info->config_write;
741
742 if (devfn < 0) {
743 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
744 devfn += PCI_FUNC_MAX) {
745 if (!bus->devices[devfn])
746 goto found;
747 }
748 error_report("PCI: no slot/function available for %s, all in use", name);
749 return NULL;
750 found: ;
751 } else if (bus->devices[devfn]) {
752 error_report("PCI: slot %d function %d not available for %s, in use by %s",
753 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
754 return NULL;
755 }
756 pci_dev->bus = bus;
757 pci_dev->devfn = devfn;
758 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
759 pci_dev->irq_state = 0;
760 pci_config_alloc(pci_dev);
761
762 pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
763 pci_config_set_device_id(pci_dev->config, info->device_id);
764 pci_config_set_revision(pci_dev->config, info->revision);
765 pci_config_set_class(pci_dev->config, info->class_id);
766
767 if (!info->is_bridge) {
768 if (info->subsystem_vendor_id || info->subsystem_id) {
769 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
770 info->subsystem_vendor_id);
771 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
772 info->subsystem_id);
773 } else {
774 pci_set_default_subsystem_id(pci_dev);
775 }
776 } else {
777 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
778 assert(!info->subsystem_vendor_id);
779 assert(!info->subsystem_id);
780 }
781 pci_init_cmask(pci_dev);
782 pci_init_wmask(pci_dev);
783 pci_init_w1cmask(pci_dev);
784 if (info->is_bridge) {
785 pci_init_wmask_bridge(pci_dev);
786 }
787 if (pci_init_multifunction(bus, pci_dev)) {
788 pci_config_free(pci_dev);
789 return NULL;
790 }
791
792 if (!config_read)
793 config_read = pci_default_read_config;
794 if (!config_write)
795 config_write = pci_default_write_config;
796 pci_dev->config_read = config_read;
797 pci_dev->config_write = config_write;
798 bus->devices[devfn] = pci_dev;
799 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
800 pci_dev->version_id = 2; /* Current pci device vmstate version */
801 return pci_dev;
802 }
803
804 static void do_pci_unregister_device(PCIDevice *pci_dev)
805 {
806 qemu_free_irqs(pci_dev->irq);
807 pci_dev->bus->devices[pci_dev->devfn] = NULL;
808 pci_config_free(pci_dev);
809 }
810
811 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
812 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
813 int instance_size, int devfn,
814 PCIConfigReadFunc *config_read,
815 PCIConfigWriteFunc *config_write)
816 {
817 PCIDevice *pci_dev;
818 PCIDeviceInfo info = {
819 .config_read = config_read,
820 .config_write = config_write,
821 };
822
823 pci_dev = g_malloc0(instance_size);
824 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
825 if (pci_dev == NULL) {
826 hw_error("PCI: can't register device\n");
827 }
828 return pci_dev;
829 }
830
831 static void pci_unregister_io_regions(PCIDevice *pci_dev)
832 {
833 PCIIORegion *r;
834 int i;
835
836 for(i = 0; i < PCI_NUM_REGIONS; i++) {
837 r = &pci_dev->io_regions[i];
838 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
839 continue;
840 memory_region_del_subregion(r->address_space, r->memory);
841 }
842 }
843
844 static int pci_unregister_device(DeviceState *dev)
845 {
846 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
847 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
848 int ret = 0;
849
850 if (info->exit)
851 ret = info->exit(pci_dev);
852 if (ret)
853 return ret;
854
855 pci_unregister_io_regions(pci_dev);
856 pci_del_option_rom(pci_dev);
857 g_free(pci_dev->romfile);
858 do_pci_unregister_device(pci_dev);
859 return 0;
860 }
861
862 void pci_register_bar(PCIDevice *pci_dev, int region_num,
863 uint8_t type, MemoryRegion *memory)
864 {
865 PCIIORegion *r;
866 uint32_t addr;
867 uint64_t wmask;
868 pcibus_t size = memory_region_size(memory);
869
870 assert(region_num >= 0);
871 assert(region_num < PCI_NUM_REGIONS);
872 if (size & (size-1)) {
873 fprintf(stderr, "ERROR: PCI region size must be pow2 "
874 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
875 exit(1);
876 }
877
878 r = &pci_dev->io_regions[region_num];
879 r->addr = PCI_BAR_UNMAPPED;
880 r->size = size;
881 r->type = type;
882 r->memory = NULL;
883
884 wmask = ~(size - 1);
885 addr = pci_bar(pci_dev, region_num);
886 if (region_num == PCI_ROM_SLOT) {
887 /* ROM enable bit is writable */
888 wmask |= PCI_ROM_ADDRESS_ENABLE;
889 }
890 pci_set_long(pci_dev->config + addr, type);
891 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
892 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
893 pci_set_quad(pci_dev->wmask + addr, wmask);
894 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
895 } else {
896 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
897 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
898 }
899 pci_dev->io_regions[region_num].memory = memory;
900 pci_dev->io_regions[region_num].address_space
901 = type & PCI_BASE_ADDRESS_SPACE_IO
902 ? pci_dev->bus->address_space_io
903 : pci_dev->bus->address_space_mem;
904 }
905
906 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
907 {
908 return pci_dev->io_regions[region_num].addr;
909 }
910
911 static pcibus_t pci_bar_address(PCIDevice *d,
912 int reg, uint8_t type, pcibus_t size)
913 {
914 pcibus_t new_addr, last_addr;
915 int bar = pci_bar(d, reg);
916 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
917
918 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
919 if (!(cmd & PCI_COMMAND_IO)) {
920 return PCI_BAR_UNMAPPED;
921 }
922 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
923 last_addr = new_addr + size - 1;
924 /* NOTE: we have only 64K ioports on PC */
925 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
926 return PCI_BAR_UNMAPPED;
927 }
928 return new_addr;
929 }
930
931 if (!(cmd & PCI_COMMAND_MEMORY)) {
932 return PCI_BAR_UNMAPPED;
933 }
934 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
935 new_addr = pci_get_quad(d->config + bar);
936 } else {
937 new_addr = pci_get_long(d->config + bar);
938 }
939 /* the ROM slot has a specific enable bit */
940 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
941 return PCI_BAR_UNMAPPED;
942 }
943 new_addr &= ~(size - 1);
944 last_addr = new_addr + size - 1;
945 /* NOTE: we do not support wrapping */
946 /* XXX: as we cannot support really dynamic
947 mappings, we handle specific values as invalid
948 mappings. */
949 if (last_addr <= new_addr || new_addr == 0 ||
950 last_addr == PCI_BAR_UNMAPPED) {
951 return PCI_BAR_UNMAPPED;
952 }
953
954 /* Now pcibus_t is 64bit.
955 * Check if 32 bit BAR wraps around explicitly.
956 * Without this, PC ide doesn't work well.
957 * TODO: remove this work around.
958 */
959 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
960 return PCI_BAR_UNMAPPED;
961 }
962
963 /*
964 * OS is allowed to set BAR beyond its addressable
965 * bits. For example, 32 bit OS can set 64bit bar
966 * to >4G. Check it. TODO: we might need to support
967 * it in the future for e.g. PAE.
968 */
969 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
970 return PCI_BAR_UNMAPPED;
971 }
972
973 return new_addr;
974 }
975
976 static void pci_update_mappings(PCIDevice *d)
977 {
978 PCIIORegion *r;
979 int i;
980 pcibus_t new_addr;
981
982 for(i = 0; i < PCI_NUM_REGIONS; i++) {
983 r = &d->io_regions[i];
984
985 /* this region isn't registered */
986 if (!r->size)
987 continue;
988
989 new_addr = pci_bar_address(d, i, r->type, r->size);
990
991 /* This bar isn't changed */
992 if (new_addr == r->addr)
993 continue;
994
995 /* now do the real mapping */
996 if (r->addr != PCI_BAR_UNMAPPED) {
997 memory_region_del_subregion(r->address_space, r->memory);
998 }
999 r->addr = new_addr;
1000 if (r->addr != PCI_BAR_UNMAPPED) {
1001 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1002 memory_region_add_subregion_overlap(r->address_space,
1003 r->addr,
1004 r->memory,
1005 1);
1006 } else {
1007 memory_region_add_subregion_overlap(r->address_space,
1008 r->addr,
1009 r->memory,
1010 1);
1011 }
1012 }
1013 }
1014 }
1015
1016 static inline int pci_irq_disabled(PCIDevice *d)
1017 {
1018 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1019 }
1020
1021 /* Called after interrupt disabled field update in config space,
1022 * assert/deassert interrupts if necessary.
1023 * Gets original interrupt disable bit value (before update). */
1024 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1025 {
1026 int i, disabled = pci_irq_disabled(d);
1027 if (disabled == was_irq_disabled)
1028 return;
1029 for (i = 0; i < PCI_NUM_PINS; ++i) {
1030 int state = pci_irq_state(d, i);
1031 pci_change_irq_level(d, i, disabled ? -state : state);
1032 }
1033 }
1034
1035 uint32_t pci_default_read_config(PCIDevice *d,
1036 uint32_t address, int len)
1037 {
1038 uint32_t val = 0;
1039
1040 memcpy(&val, d->config + address, len);
1041 return le32_to_cpu(val);
1042 }
1043
1044 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1045 {
1046 int i, was_irq_disabled = pci_irq_disabled(d);
1047
1048 for (i = 0; i < l; val >>= 8, ++i) {
1049 uint8_t wmask = d->wmask[addr + i];
1050 uint8_t w1cmask = d->w1cmask[addr + i];
1051 assert(!(wmask & w1cmask));
1052 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1053 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1054 }
1055 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1056 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1057 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1058 range_covers_byte(addr, l, PCI_COMMAND))
1059 pci_update_mappings(d);
1060
1061 if (range_covers_byte(addr, l, PCI_COMMAND))
1062 pci_update_irq_disabled(d, was_irq_disabled);
1063 }
1064
1065 /***********************************************************/
1066 /* generic PCI irq support */
1067
1068 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1069 static void pci_set_irq(void *opaque, int irq_num, int level)
1070 {
1071 PCIDevice *pci_dev = opaque;
1072 int change;
1073
1074 change = level - pci_irq_state(pci_dev, irq_num);
1075 if (!change)
1076 return;
1077
1078 pci_set_irq_state(pci_dev, irq_num, level);
1079 pci_update_irq_status(pci_dev);
1080 if (pci_irq_disabled(pci_dev))
1081 return;
1082 pci_change_irq_level(pci_dev, irq_num, change);
1083 }
1084
1085 /***********************************************************/
1086 /* monitor info on PCI */
1087
1088 typedef struct {
1089 uint16_t class;
1090 const char *desc;
1091 const char *fw_name;
1092 uint16_t fw_ign_bits;
1093 } pci_class_desc;
1094
1095 static const pci_class_desc pci_class_descriptions[] =
1096 {
1097 { 0x0001, "VGA controller", "display"},
1098 { 0x0100, "SCSI controller", "scsi"},
1099 { 0x0101, "IDE controller", "ide"},
1100 { 0x0102, "Floppy controller", "fdc"},
1101 { 0x0103, "IPI controller", "ipi"},
1102 { 0x0104, "RAID controller", "raid"},
1103 { 0x0106, "SATA controller"},
1104 { 0x0107, "SAS controller"},
1105 { 0x0180, "Storage controller"},
1106 { 0x0200, "Ethernet controller", "ethernet"},
1107 { 0x0201, "Token Ring controller", "token-ring"},
1108 { 0x0202, "FDDI controller", "fddi"},
1109 { 0x0203, "ATM controller", "atm"},
1110 { 0x0280, "Network controller"},
1111 { 0x0300, "VGA controller", "display", 0x00ff},
1112 { 0x0301, "XGA controller"},
1113 { 0x0302, "3D controller"},
1114 { 0x0380, "Display controller"},
1115 { 0x0400, "Video controller", "video"},
1116 { 0x0401, "Audio controller", "sound"},
1117 { 0x0402, "Phone"},
1118 { 0x0403, "Audio controller", "sound"},
1119 { 0x0480, "Multimedia controller"},
1120 { 0x0500, "RAM controller", "memory"},
1121 { 0x0501, "Flash controller", "flash"},
1122 { 0x0580, "Memory controller"},
1123 { 0x0600, "Host bridge", "host"},
1124 { 0x0601, "ISA bridge", "isa"},
1125 { 0x0602, "EISA bridge", "eisa"},
1126 { 0x0603, "MC bridge", "mca"},
1127 { 0x0604, "PCI bridge", "pci"},
1128 { 0x0605, "PCMCIA bridge", "pcmcia"},
1129 { 0x0606, "NUBUS bridge", "nubus"},
1130 { 0x0607, "CARDBUS bridge", "cardbus"},
1131 { 0x0608, "RACEWAY bridge"},
1132 { 0x0680, "Bridge"},
1133 { 0x0700, "Serial port", "serial"},
1134 { 0x0701, "Parallel port", "parallel"},
1135 { 0x0800, "Interrupt controller", "interrupt-controller"},
1136 { 0x0801, "DMA controller", "dma-controller"},
1137 { 0x0802, "Timer", "timer"},
1138 { 0x0803, "RTC", "rtc"},
1139 { 0x0900, "Keyboard", "keyboard"},
1140 { 0x0901, "Pen", "pen"},
1141 { 0x0902, "Mouse", "mouse"},
1142 { 0x0A00, "Dock station", "dock", 0x00ff},
1143 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1144 { 0x0c00, "Fireware contorller", "fireware"},
1145 { 0x0c01, "Access bus controller", "access-bus"},
1146 { 0x0c02, "SSA controller", "ssa"},
1147 { 0x0c03, "USB controller", "usb"},
1148 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1149 { 0, NULL}
1150 };
1151
1152 static void pci_for_each_device_under_bus(PCIBus *bus,
1153 void (*fn)(PCIBus *b, PCIDevice *d))
1154 {
1155 PCIDevice *d;
1156 int devfn;
1157
1158 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1159 d = bus->devices[devfn];
1160 if (d) {
1161 fn(bus, d);
1162 }
1163 }
1164 }
1165
1166 void pci_for_each_device(PCIBus *bus, int bus_num,
1167 void (*fn)(PCIBus *b, PCIDevice *d))
1168 {
1169 bus = pci_find_bus(bus, bus_num);
1170
1171 if (bus) {
1172 pci_for_each_device_under_bus(bus, fn);
1173 }
1174 }
1175
1176 static void pci_device_print(Monitor *mon, QDict *device)
1177 {
1178 QDict *qdict;
1179 QListEntry *entry;
1180 uint64_t addr, size;
1181
1182 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1183 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1184 qdict_get_int(device, "slot"),
1185 qdict_get_int(device, "function"));
1186 monitor_printf(mon, " ");
1187
1188 qdict = qdict_get_qdict(device, "class_info");
1189 if (qdict_haskey(qdict, "desc")) {
1190 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1191 } else {
1192 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1193 }
1194
1195 qdict = qdict_get_qdict(device, "id");
1196 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1197 qdict_get_int(qdict, "device"),
1198 qdict_get_int(qdict, "vendor"));
1199
1200 if (qdict_haskey(device, "irq")) {
1201 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1202 qdict_get_int(device, "irq"));
1203 }
1204
1205 if (qdict_haskey(device, "pci_bridge")) {
1206 QDict *info;
1207
1208 qdict = qdict_get_qdict(device, "pci_bridge");
1209
1210 info = qdict_get_qdict(qdict, "bus");
1211 monitor_printf(mon, " BUS %" PRId64 ".\n",
1212 qdict_get_int(info, "number"));
1213 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1214 qdict_get_int(info, "secondary"));
1215 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1216 qdict_get_int(info, "subordinate"));
1217
1218 info = qdict_get_qdict(qdict, "io_range");
1219 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1220 qdict_get_int(info, "base"),
1221 qdict_get_int(info, "limit"));
1222
1223 info = qdict_get_qdict(qdict, "memory_range");
1224 monitor_printf(mon,
1225 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1226 qdict_get_int(info, "base"),
1227 qdict_get_int(info, "limit"));
1228
1229 info = qdict_get_qdict(qdict, "prefetchable_range");
1230 monitor_printf(mon, " prefetchable memory range "
1231 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1232 qdict_get_int(info, "base"),
1233 qdict_get_int(info, "limit"));
1234 }
1235
1236 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1237 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1238 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1239
1240 addr = qdict_get_int(qdict, "address");
1241 size = qdict_get_int(qdict, "size");
1242
1243 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1244 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1245 " [0x%04"FMT_PCIBUS"].\n",
1246 addr, addr + size - 1);
1247 } else {
1248 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1249 " [0x%08"FMT_PCIBUS"].\n",
1250 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1251 qdict_get_bool(qdict, "prefetch") ?
1252 " prefetchable" : "", addr, addr + size - 1);
1253 }
1254 }
1255
1256 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1257
1258 if (qdict_haskey(device, "pci_bridge")) {
1259 qdict = qdict_get_qdict(device, "pci_bridge");
1260 if (qdict_haskey(qdict, "devices")) {
1261 QListEntry *dev;
1262 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1263 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1264 }
1265 }
1266 }
1267 }
1268
1269 void do_pci_info_print(Monitor *mon, const QObject *data)
1270 {
1271 QListEntry *bus, *dev;
1272
1273 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1274 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1275 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1276 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1277 }
1278 }
1279 }
1280
1281 static QObject *pci_get_dev_class(const PCIDevice *dev)
1282 {
1283 int class;
1284 const pci_class_desc *desc;
1285
1286 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1287 desc = pci_class_descriptions;
1288 while (desc->desc && class != desc->class)
1289 desc++;
1290
1291 if (desc->desc) {
1292 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1293 desc->desc, class);
1294 } else {
1295 return qobject_from_jsonf("{ 'class': %d }", class);
1296 }
1297 }
1298
1299 static QObject *pci_get_dev_id(const PCIDevice *dev)
1300 {
1301 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1302 pci_get_word(dev->config + PCI_VENDOR_ID),
1303 pci_get_word(dev->config + PCI_DEVICE_ID));
1304 }
1305
1306 static QObject *pci_get_regions_list(const PCIDevice *dev)
1307 {
1308 int i;
1309 QList *regions_list;
1310
1311 regions_list = qlist_new();
1312
1313 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1314 QObject *obj;
1315 const PCIIORegion *r = &dev->io_regions[i];
1316
1317 if (!r->size) {
1318 continue;
1319 }
1320
1321 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1322 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1323 "'address': %" PRId64 ", "
1324 "'size': %" PRId64 " }",
1325 i, r->addr, r->size);
1326 } else {
1327 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1328
1329 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1330 "'mem_type_64': %i, 'prefetch': %i, "
1331 "'address': %" PRId64 ", "
1332 "'size': %" PRId64 " }",
1333 i, mem_type_64,
1334 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1335 r->addr, r->size);
1336 }
1337
1338 qlist_append_obj(regions_list, obj);
1339 }
1340
1341 return QOBJECT(regions_list);
1342 }
1343
1344 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1345
1346 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1347 {
1348 uint8_t type;
1349 QObject *obj;
1350
1351 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1352 " 'qdev_id': %s }",
1353 bus_num,
1354 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1355 pci_get_dev_class(dev), pci_get_dev_id(dev),
1356 pci_get_regions_list(dev),
1357 dev->qdev.id ? dev->qdev.id : "");
1358
1359 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1360 QDict *qdict = qobject_to_qdict(obj);
1361 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1362 }
1363
1364 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1365 if (type == PCI_HEADER_TYPE_BRIDGE) {
1366 QDict *qdict;
1367 QObject *pci_bridge;
1368
1369 pci_bridge = qobject_from_jsonf("{ 'bus': "
1370 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1371 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1372 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1373 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1374 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1375 dev->config[PCI_SUBORDINATE_BUS],
1376 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1377 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1378 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1379 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1380 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1381 PCI_BASE_ADDRESS_MEM_PREFETCH),
1382 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1383 PCI_BASE_ADDRESS_MEM_PREFETCH));
1384
1385 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1386 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1387
1388 if (child_bus) {
1389 qdict = qobject_to_qdict(pci_bridge);
1390 qdict_put_obj(qdict, "devices",
1391 pci_get_devices_list(child_bus,
1392 dev->config[PCI_SECONDARY_BUS]));
1393 }
1394 }
1395 qdict = qobject_to_qdict(obj);
1396 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1397 }
1398
1399 return obj;
1400 }
1401
1402 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1403 {
1404 int devfn;
1405 PCIDevice *dev;
1406 QList *dev_list;
1407
1408 dev_list = qlist_new();
1409
1410 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1411 dev = bus->devices[devfn];
1412 if (dev) {
1413 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1414 }
1415 }
1416
1417 return QOBJECT(dev_list);
1418 }
1419
1420 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1421 {
1422 bus = pci_find_bus(bus, bus_num);
1423 if (bus) {
1424 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1425 bus_num, pci_get_devices_list(bus, bus_num));
1426 }
1427
1428 return NULL;
1429 }
1430
1431 void do_pci_info(Monitor *mon, QObject **ret_data)
1432 {
1433 QList *bus_list;
1434 struct PCIHostBus *host;
1435
1436 bus_list = qlist_new();
1437
1438 QLIST_FOREACH(host, &host_buses, next) {
1439 QObject *obj = pci_get_bus_dict(host->bus, 0);
1440 if (obj) {
1441 qlist_append_obj(bus_list, obj);
1442 }
1443 }
1444
1445 *ret_data = QOBJECT(bus_list);
1446 }
1447
1448 static const char * const pci_nic_models[] = {
1449 "ne2k_pci",
1450 "i82551",
1451 "i82557b",
1452 "i82559er",
1453 "rtl8139",
1454 "e1000",
1455 "pcnet",
1456 "virtio",
1457 NULL
1458 };
1459
1460 static const char * const pci_nic_names[] = {
1461 "ne2k_pci",
1462 "i82551",
1463 "i82557b",
1464 "i82559er",
1465 "rtl8139",
1466 "e1000",
1467 "pcnet",
1468 "virtio-net-pci",
1469 NULL
1470 };
1471
1472 /* Initialize a PCI NIC. */
1473 /* FIXME callers should check for failure, but don't */
1474 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1475 const char *default_devaddr)
1476 {
1477 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1478 PCIBus *bus;
1479 int devfn;
1480 PCIDevice *pci_dev;
1481 DeviceState *dev;
1482 int i;
1483
1484 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1485 if (i < 0)
1486 return NULL;
1487
1488 bus = pci_get_bus_devfn(&devfn, devaddr);
1489 if (!bus) {
1490 error_report("Invalid PCI device address %s for device %s",
1491 devaddr, pci_nic_names[i]);
1492 return NULL;
1493 }
1494
1495 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1496 dev = &pci_dev->qdev;
1497 qdev_set_nic_properties(dev, nd);
1498 if (qdev_init(dev) < 0)
1499 return NULL;
1500 return pci_dev;
1501 }
1502
1503 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1504 const char *default_devaddr)
1505 {
1506 PCIDevice *res;
1507
1508 if (qemu_show_nic_models(nd->model, pci_nic_models))
1509 exit(0);
1510
1511 res = pci_nic_init(nd, default_model, default_devaddr);
1512 if (!res)
1513 exit(1);
1514 return res;
1515 }
1516
1517 /* Whether a given bus number is in range of the secondary
1518 * bus of the given bridge device. */
1519 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1520 {
1521 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1522 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1523 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1524 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1525 }
1526
1527 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1528 {
1529 PCIBus *sec;
1530
1531 if (!bus) {
1532 return NULL;
1533 }
1534
1535 if (pci_bus_num(bus) == bus_num) {
1536 return bus;
1537 }
1538
1539 /* Consider all bus numbers in range for the host pci bridge. */
1540 if (bus->parent_dev &&
1541 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1542 return NULL;
1543 }
1544
1545 /* try child bus */
1546 for (; bus; bus = sec) {
1547 QLIST_FOREACH(sec, &bus->child, sibling) {
1548 assert(sec->parent_dev);
1549 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1550 return sec;
1551 }
1552 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1553 break;
1554 }
1555 }
1556 }
1557
1558 return NULL;
1559 }
1560
1561 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1562 {
1563 bus = pci_find_bus(bus, bus_num);
1564
1565 if (!bus)
1566 return NULL;
1567
1568 return bus->devices[devfn];
1569 }
1570
1571 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1572 {
1573 PCIDevice *pci_dev = (PCIDevice *)qdev;
1574 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1575 PCIBus *bus;
1576 int rc;
1577 bool is_default_rom;
1578
1579 /* initialize cap_present for pci_is_express() and pci_config_size() */
1580 if (info->is_express) {
1581 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1582 }
1583
1584 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1585 pci_dev = do_pci_register_device(pci_dev, bus, base->name,
1586 pci_dev->devfn, info);
1587 if (pci_dev == NULL)
1588 return -1;
1589 if (qdev->hotplugged && info->no_hotplug) {
1590 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1591 do_pci_unregister_device(pci_dev);
1592 return -1;
1593 }
1594 if (info->init) {
1595 rc = info->init(pci_dev);
1596 if (rc != 0) {
1597 do_pci_unregister_device(pci_dev);
1598 return rc;
1599 }
1600 }
1601
1602 /* rom loading */
1603 is_default_rom = false;
1604 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1605 pci_dev->romfile = g_strdup(info->romfile);
1606 is_default_rom = true;
1607 }
1608 pci_add_option_rom(pci_dev, is_default_rom);
1609
1610 if (bus->hotplug) {
1611 /* Let buses differentiate between hotplug and when device is
1612 * enabled during qemu machine creation. */
1613 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1614 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1615 PCI_COLDPLUG_ENABLED);
1616 if (rc != 0) {
1617 int r = pci_unregister_device(&pci_dev->qdev);
1618 assert(!r);
1619 return rc;
1620 }
1621 }
1622 return 0;
1623 }
1624
1625 static int pci_unplug_device(DeviceState *qdev)
1626 {
1627 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1628 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1629
1630 if (info->no_hotplug) {
1631 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1632 return -1;
1633 }
1634 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1635 PCI_HOTPLUG_DISABLED);
1636 }
1637
1638 void pci_qdev_register(PCIDeviceInfo *info)
1639 {
1640 info->qdev.init = pci_qdev_init;
1641 info->qdev.unplug = pci_unplug_device;
1642 info->qdev.exit = pci_unregister_device;
1643 info->qdev.bus_info = &pci_bus_info;
1644 qdev_register(&info->qdev);
1645 }
1646
1647 void pci_qdev_register_many(PCIDeviceInfo *info)
1648 {
1649 while (info->qdev.name) {
1650 pci_qdev_register(info);
1651 info++;
1652 }
1653 }
1654
1655 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1656 const char *name)
1657 {
1658 DeviceState *dev;
1659
1660 dev = qdev_create(&bus->qbus, name);
1661 qdev_prop_set_uint32(dev, "addr", devfn);
1662 qdev_prop_set_bit(dev, "multifunction", multifunction);
1663 return DO_UPCAST(PCIDevice, qdev, dev);
1664 }
1665
1666 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
1667 bool multifunction,
1668 const char *name)
1669 {
1670 DeviceState *dev;
1671
1672 dev = qdev_try_create(&bus->qbus, name);
1673 if (!dev) {
1674 return NULL;
1675 }
1676 qdev_prop_set_uint32(dev, "addr", devfn);
1677 qdev_prop_set_bit(dev, "multifunction", multifunction);
1678 return DO_UPCAST(PCIDevice, qdev, dev);
1679 }
1680
1681 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1682 bool multifunction,
1683 const char *name)
1684 {
1685 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1686 qdev_init_nofail(&dev->qdev);
1687 return dev;
1688 }
1689
1690 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1691 {
1692 return pci_create_multifunction(bus, devfn, false, name);
1693 }
1694
1695 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1696 {
1697 return pci_create_simple_multifunction(bus, devfn, false, name);
1698 }
1699
1700 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
1701 {
1702 return pci_try_create_multifunction(bus, devfn, false, name);
1703 }
1704
1705 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1706 {
1707 int config_size = pci_config_size(pdev);
1708 int offset = PCI_CONFIG_HEADER_SIZE;
1709 int i;
1710 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1711 if (pdev->used[i])
1712 offset = i + 1;
1713 else if (i - offset + 1 == size)
1714 return offset;
1715 return 0;
1716 }
1717
1718 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1719 uint8_t *prev_p)
1720 {
1721 uint8_t next, prev;
1722
1723 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1724 return 0;
1725
1726 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1727 prev = next + PCI_CAP_LIST_NEXT)
1728 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1729 break;
1730
1731 if (prev_p)
1732 *prev_p = prev;
1733 return next;
1734 }
1735
1736 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1737 {
1738 uint8_t next, prev, found = 0;
1739
1740 if (!(pdev->used[offset])) {
1741 return 0;
1742 }
1743
1744 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1745
1746 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1747 prev = next + PCI_CAP_LIST_NEXT) {
1748 if (next <= offset && next > found) {
1749 found = next;
1750 }
1751 }
1752 return found;
1753 }
1754
1755 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1756 This is needed for an option rom which is used for more than one device. */
1757 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1758 {
1759 uint16_t vendor_id;
1760 uint16_t device_id;
1761 uint16_t rom_vendor_id;
1762 uint16_t rom_device_id;
1763 uint16_t rom_magic;
1764 uint16_t pcir_offset;
1765 uint8_t checksum;
1766
1767 /* Words in rom data are little endian (like in PCI configuration),
1768 so they can be read / written with pci_get_word / pci_set_word. */
1769
1770 /* Only a valid rom will be patched. */
1771 rom_magic = pci_get_word(ptr);
1772 if (rom_magic != 0xaa55) {
1773 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1774 return;
1775 }
1776 pcir_offset = pci_get_word(ptr + 0x18);
1777 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1778 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1779 return;
1780 }
1781
1782 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1783 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1784 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1785 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1786
1787 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1788 vendor_id, device_id, rom_vendor_id, rom_device_id);
1789
1790 checksum = ptr[6];
1791
1792 if (vendor_id != rom_vendor_id) {
1793 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1794 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1795 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1796 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1797 ptr[6] = checksum;
1798 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1799 }
1800
1801 if (device_id != rom_device_id) {
1802 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1803 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1804 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1805 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1806 ptr[6] = checksum;
1807 pci_set_word(ptr + pcir_offset + 6, device_id);
1808 }
1809 }
1810
1811 /* Add an option rom for the device */
1812 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1813 {
1814 int size;
1815 char *path;
1816 void *ptr;
1817 char name[32];
1818
1819 if (!pdev->romfile)
1820 return 0;
1821 if (strlen(pdev->romfile) == 0)
1822 return 0;
1823
1824 if (!pdev->rom_bar) {
1825 /*
1826 * Load rom via fw_cfg instead of creating a rom bar,
1827 * for 0.11 compatibility.
1828 */
1829 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1830 if (class == 0x0300) {
1831 rom_add_vga(pdev->romfile);
1832 } else {
1833 rom_add_option(pdev->romfile, -1);
1834 }
1835 return 0;
1836 }
1837
1838 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1839 if (path == NULL) {
1840 path = g_strdup(pdev->romfile);
1841 }
1842
1843 size = get_image_size(path);
1844 if (size < 0) {
1845 error_report("%s: failed to find romfile \"%s\"",
1846 __FUNCTION__, pdev->romfile);
1847 g_free(path);
1848 return -1;
1849 }
1850 if (size & (size - 1)) {
1851 size = 1 << qemu_fls(size);
1852 }
1853
1854 if (pdev->qdev.info->vmsd)
1855 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1856 else
1857 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1858 pdev->has_rom = true;
1859 memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
1860 ptr = memory_region_get_ram_ptr(&pdev->rom);
1861 load_image(path, ptr);
1862 g_free(path);
1863
1864 if (is_default_rom) {
1865 /* Only the default rom images will be patched (if needed). */
1866 pci_patch_ids(pdev, ptr, size);
1867 }
1868
1869 qemu_put_ram_ptr(ptr);
1870
1871 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1872
1873 return 0;
1874 }
1875
1876 static void pci_del_option_rom(PCIDevice *pdev)
1877 {
1878 if (!pdev->has_rom)
1879 return;
1880
1881 memory_region_destroy(&pdev->rom);
1882 pdev->has_rom = false;
1883 }
1884
1885 /*
1886 * if !offset
1887 * Reserve space and add capability to the linked list in pci config space
1888 *
1889 * if offset = 0,
1890 * Find and reserve space and add capability to the linked list
1891 * in pci config space */
1892 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1893 uint8_t offset, uint8_t size)
1894 {
1895 uint8_t *config;
1896 int i, overlapping_cap;
1897
1898 if (!offset) {
1899 offset = pci_find_space(pdev, size);
1900 if (!offset) {
1901 return -ENOSPC;
1902 }
1903 } else {
1904 /* Verify that capabilities don't overlap. Note: device assignment
1905 * depends on this check to verify that the device is not broken.
1906 * Should never trigger for emulated devices, but it's helpful
1907 * for debugging these. */
1908 for (i = offset; i < offset + size; i++) {
1909 overlapping_cap = pci_find_capability_at_offset(pdev, i);
1910 if (overlapping_cap) {
1911 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
1912 "Attempt to add PCI capability %x at offset "
1913 "%x overlaps existing capability %x at offset %x\n",
1914 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
1915 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1916 cap_id, offset, overlapping_cap, i);
1917 return -EINVAL;
1918 }
1919 }
1920 }
1921
1922 config = pdev->config + offset;
1923 config[PCI_CAP_LIST_ID] = cap_id;
1924 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1925 pdev->config[PCI_CAPABILITY_LIST] = offset;
1926 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1927 memset(pdev->used + offset, 0xFF, size);
1928 /* Make capability read-only by default */
1929 memset(pdev->wmask + offset, 0, size);
1930 /* Check capability by default */
1931 memset(pdev->cmask + offset, 0xFF, size);
1932 return offset;
1933 }
1934
1935 /* Unlink capability from the pci config space. */
1936 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1937 {
1938 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1939 if (!offset)
1940 return;
1941 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1942 /* Make capability writable again */
1943 memset(pdev->wmask + offset, 0xff, size);
1944 memset(pdev->w1cmask + offset, 0, size);
1945 /* Clear cmask as device-specific registers can't be checked */
1946 memset(pdev->cmask + offset, 0, size);
1947 memset(pdev->used + offset, 0, size);
1948
1949 if (!pdev->config[PCI_CAPABILITY_LIST])
1950 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1951 }
1952
1953 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1954 {
1955 return pci_find_capability_list(pdev, cap_id, NULL);
1956 }
1957
1958 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1959 {
1960 PCIDevice *d = (PCIDevice *)dev;
1961 const pci_class_desc *desc;
1962 char ctxt[64];
1963 PCIIORegion *r;
1964 int i, class;
1965
1966 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1967 desc = pci_class_descriptions;
1968 while (desc->desc && class != desc->class)
1969 desc++;
1970 if (desc->desc) {
1971 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1972 } else {
1973 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1974 }
1975
1976 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1977 "pci id %04x:%04x (sub %04x:%04x)\n",
1978 indent, "", ctxt, pci_bus_num(d->bus),
1979 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1980 pci_get_word(d->config + PCI_VENDOR_ID),
1981 pci_get_word(d->config + PCI_DEVICE_ID),
1982 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1983 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1984 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1985 r = &d->io_regions[i];
1986 if (!r->size)
1987 continue;
1988 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1989 " [0x%"FMT_PCIBUS"]\n",
1990 indent, "",
1991 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1992 r->addr, r->addr + r->size - 1);
1993 }
1994 }
1995
1996 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1997 {
1998 PCIDevice *d = (PCIDevice *)dev;
1999 const char *name = NULL;
2000 const pci_class_desc *desc = pci_class_descriptions;
2001 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2002
2003 while (desc->desc &&
2004 (class & ~desc->fw_ign_bits) !=
2005 (desc->class & ~desc->fw_ign_bits)) {
2006 desc++;
2007 }
2008
2009 if (desc->desc) {
2010 name = desc->fw_name;
2011 }
2012
2013 if (name) {
2014 pstrcpy(buf, len, name);
2015 } else {
2016 snprintf(buf, len, "pci%04x,%04x",
2017 pci_get_word(d->config + PCI_VENDOR_ID),
2018 pci_get_word(d->config + PCI_DEVICE_ID));
2019 }
2020
2021 return buf;
2022 }
2023
2024 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2025 {
2026 PCIDevice *d = (PCIDevice *)dev;
2027 char path[50], name[33];
2028 int off;
2029
2030 off = snprintf(path, sizeof(path), "%s@%x",
2031 pci_dev_fw_name(dev, name, sizeof name),
2032 PCI_SLOT(d->devfn));
2033 if (PCI_FUNC(d->devfn))
2034 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2035 return strdup(path);
2036 }
2037
2038 static char *pcibus_get_dev_path(DeviceState *dev)
2039 {
2040 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2041 PCIDevice *t;
2042 int slot_depth;
2043 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2044 * 00 is added here to make this format compatible with
2045 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2046 * Slot.Function list specifies the slot and function numbers for all
2047 * devices on the path from root to the specific device. */
2048 char domain[] = "DDDD:00";
2049 char slot[] = ":SS.F";
2050 int domain_len = sizeof domain - 1 /* For '\0' */;
2051 int slot_len = sizeof slot - 1 /* For '\0' */;
2052 int path_len;
2053 char *path, *p;
2054 int s;
2055
2056 /* Calculate # of slots on path between device and root. */;
2057 slot_depth = 0;
2058 for (t = d; t; t = t->bus->parent_dev) {
2059 ++slot_depth;
2060 }
2061
2062 path_len = domain_len + slot_len * slot_depth;
2063
2064 /* Allocate memory, fill in the terminating null byte. */
2065 path = g_malloc(path_len + 1 /* For '\0' */);
2066 path[path_len] = '\0';
2067
2068 /* First field is the domain. */
2069 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2070 assert(s == domain_len);
2071 memcpy(path, domain, domain_len);
2072
2073 /* Fill in slot numbers. We walk up from device to root, so need to print
2074 * them in the reverse order, last to first. */
2075 p = path + path_len;
2076 for (t = d; t; t = t->bus->parent_dev) {
2077 p -= slot_len;
2078 s = snprintf(slot, sizeof slot, ":%02x.%x",
2079 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2080 assert(s == slot_len);
2081 memcpy(p, slot, slot_len);
2082 }
2083
2084 return path;
2085 }
2086
2087 static int pci_qdev_find_recursive(PCIBus *bus,
2088 const char *id, PCIDevice **pdev)
2089 {
2090 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2091 if (!qdev) {
2092 return -ENODEV;
2093 }
2094
2095 /* roughly check if given qdev is pci device */
2096 if (qdev->info->init == &pci_qdev_init &&
2097 qdev->parent_bus->info == &pci_bus_info) {
2098 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2099 return 0;
2100 }
2101 return -EINVAL;
2102 }
2103
2104 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2105 {
2106 struct PCIHostBus *host;
2107 int rc = -ENODEV;
2108
2109 QLIST_FOREACH(host, &host_buses, next) {
2110 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2111 if (!tmp) {
2112 rc = 0;
2113 break;
2114 }
2115 if (tmp != -ENODEV) {
2116 rc = tmp;
2117 }
2118 }
2119
2120 return rc;
2121 }
2122
2123 MemoryRegion *pci_address_space(PCIDevice *dev)
2124 {
2125 return dev->bus->address_space_mem;
2126 }
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