?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
trace: portable simple trace backend using glib
[qemu.git] / hw / fdc.c
blob433af73ad710b110784b8dfe42e8bfd43ad1b299
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 /* Floppy disk drive emulation */
66 typedef enum FDiskFlags {
67 FDISK_DBL_SIDES = 0x01,
68 } FDiskFlags;
69
70 typedef struct FDrive {
71 BlockDriverState *bs;
72 /* Drive status */
73 FDriveType drive;
74 uint8_t perpendicular; /* 2.88 MB access mode */
75 /* Position */
76 uint8_t head;
77 uint8_t track;
78 uint8_t sect;
79 /* Media */
80 FDiskFlags flags;
81 uint8_t last_sect; /* Nb sector per track */
82 uint8_t max_track; /* Nb of tracks */
83 uint16_t bps; /* Bytes per sector */
84 uint8_t ro; /* Is read-only */
85 uint8_t media_changed; /* Is media changed */
86 } FDrive;
87
88 static void fd_init(FDrive *drv)
89 {
90 /* Drive */
91 drv->drive = FDRIVE_DRV_NONE;
92 drv->perpendicular = 0;
93 /* Disk */
94 drv->last_sect = 0;
95 drv->max_track = 0;
96 }
97
98 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
99 uint8_t last_sect)
100 {
101 return (((track * 2) + head) * last_sect) + sect - 1;
102 }
103
104 /* Returns current position, in sectors, for given drive */
105 static int fd_sector(FDrive *drv)
106 {
107 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
108 }
109
110 /* Seek to a new position:
111 * returns 0 if already on right track
112 * returns 1 if track changed
113 * returns 2 if track is invalid
114 * returns 3 if sector is invalid
115 * returns 4 if seek is disabled
116 */
117 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
118 int enable_seek)
119 {
120 uint32_t sector;
121 int ret;
122
123 if (track > drv->max_track ||
124 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
125 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
126 head, track, sect, 1,
127 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
128 drv->max_track, drv->last_sect);
129 return 2;
130 }
131 if (sect > drv->last_sect) {
132 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
133 head, track, sect, 1,
134 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
135 drv->max_track, drv->last_sect);
136 return 3;
137 }
138 sector = fd_sector_calc(head, track, sect, drv->last_sect);
139 ret = 0;
140 if (sector != fd_sector(drv)) {
141 #if 0
142 if (!enable_seek) {
143 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
144 head, track, sect, 1, drv->max_track, drv->last_sect);
145 return 4;
146 }
147 #endif
148 drv->head = head;
149 if (drv->track != track)
150 ret = 1;
151 drv->track = track;
152 drv->sect = sect;
153 }
154
155 return ret;
156 }
157
158 /* Set drive back to track 0 */
159 static void fd_recalibrate(FDrive *drv)
160 {
161 FLOPPY_DPRINTF("recalibrate\n");
162 drv->head = 0;
163 drv->track = 0;
164 drv->sect = 1;
165 }
166
167 /* Revalidate a disk drive after a disk change */
168 static void fd_revalidate(FDrive *drv)
169 {
170 int nb_heads, max_track, last_sect, ro;
171 FDriveType drive;
172
173 FLOPPY_DPRINTF("revalidate\n");
174 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
175 ro = bdrv_is_read_only(drv->bs);
176 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
177 &last_sect, drv->drive, &drive);
178 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
179 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
180 nb_heads - 1, max_track, last_sect);
181 } else {
182 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
183 max_track, last_sect, ro ? "ro" : "rw");
184 }
185 if (nb_heads == 1) {
186 drv->flags &= ~FDISK_DBL_SIDES;
187 } else {
188 drv->flags |= FDISK_DBL_SIDES;
189 }
190 drv->max_track = max_track;
191 drv->last_sect = last_sect;
192 drv->ro = ro;
193 drv->drive = drive;
194 } else {
195 FLOPPY_DPRINTF("No disk in drive\n");
196 drv->last_sect = 0;
197 drv->max_track = 0;
198 drv->flags &= ~FDISK_DBL_SIDES;
199 }
200 }
201
202 /********************************************************/
203 /* Intel 82078 floppy disk controller emulation */
204
205 typedef struct FDCtrl FDCtrl;
206
207 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
208 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
209 static int fdctrl_transfer_handler (void *opaque, int nchan,
210 int dma_pos, int dma_len);
211 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
212
213 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
214 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
215 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
216 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
217 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
218 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
219 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
220 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
221 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
222 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
223 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
224
225 enum {
226 FD_DIR_WRITE = 0,
227 FD_DIR_READ = 1,
228 FD_DIR_SCANE = 2,
229 FD_DIR_SCANL = 3,
230 FD_DIR_SCANH = 4,
231 };
232
233 enum {
234 FD_STATE_MULTI = 0x01, /* multi track flag */
235 FD_STATE_FORMAT = 0x02, /* format flag */
236 FD_STATE_SEEK = 0x04, /* seek flag */
237 };
238
239 enum {
240 FD_REG_SRA = 0x00,
241 FD_REG_SRB = 0x01,
242 FD_REG_DOR = 0x02,
243 FD_REG_TDR = 0x03,
244 FD_REG_MSR = 0x04,
245 FD_REG_DSR = 0x04,
246 FD_REG_FIFO = 0x05,
247 FD_REG_DIR = 0x07,
248 };
249
250 enum {
251 FD_CMD_READ_TRACK = 0x02,
252 FD_CMD_SPECIFY = 0x03,
253 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
254 FD_CMD_WRITE = 0x05,
255 FD_CMD_READ = 0x06,
256 FD_CMD_RECALIBRATE = 0x07,
257 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
258 FD_CMD_WRITE_DELETED = 0x09,
259 FD_CMD_READ_ID = 0x0a,
260 FD_CMD_READ_DELETED = 0x0c,
261 FD_CMD_FORMAT_TRACK = 0x0d,
262 FD_CMD_DUMPREG = 0x0e,
263 FD_CMD_SEEK = 0x0f,
264 FD_CMD_VERSION = 0x10,
265 FD_CMD_SCAN_EQUAL = 0x11,
266 FD_CMD_PERPENDICULAR_MODE = 0x12,
267 FD_CMD_CONFIGURE = 0x13,
268 FD_CMD_LOCK = 0x14,
269 FD_CMD_VERIFY = 0x16,
270 FD_CMD_POWERDOWN_MODE = 0x17,
271 FD_CMD_PART_ID = 0x18,
272 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
273 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
274 FD_CMD_SAVE = 0x2e,
275 FD_CMD_OPTION = 0x33,
276 FD_CMD_RESTORE = 0x4e,
277 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
278 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
279 FD_CMD_FORMAT_AND_WRITE = 0xcd,
280 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
281 };
282
283 enum {
284 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
285 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
286 FD_CONFIG_POLL = 0x10, /* Poll enabled */
287 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
288 FD_CONFIG_EIS = 0x40, /* No implied seeks */
289 };
290
291 enum {
292 FD_SR0_EQPMT = 0x10,
293 FD_SR0_SEEK = 0x20,
294 FD_SR0_ABNTERM = 0x40,
295 FD_SR0_INVCMD = 0x80,
296 FD_SR0_RDYCHG = 0xc0,
297 };
298
299 enum {
300 FD_SR1_EC = 0x80, /* End of cylinder */
301 };
302
303 enum {
304 FD_SR2_SNS = 0x04, /* Scan not satisfied */
305 FD_SR2_SEH = 0x08, /* Scan equal hit */
306 };
307
308 enum {
309 FD_SRA_DIR = 0x01,
310 FD_SRA_nWP = 0x02,
311 FD_SRA_nINDX = 0x04,
312 FD_SRA_HDSEL = 0x08,
313 FD_SRA_nTRK0 = 0x10,
314 FD_SRA_STEP = 0x20,
315 FD_SRA_nDRV2 = 0x40,
316 FD_SRA_INTPEND = 0x80,
317 };
318
319 enum {
320 FD_SRB_MTR0 = 0x01,
321 FD_SRB_MTR1 = 0x02,
322 FD_SRB_WGATE = 0x04,
323 FD_SRB_RDATA = 0x08,
324 FD_SRB_WDATA = 0x10,
325 FD_SRB_DR0 = 0x20,
326 };
327
328 enum {
329 #if MAX_FD == 4
330 FD_DOR_SELMASK = 0x03,
331 #else
332 FD_DOR_SELMASK = 0x01,
333 #endif
334 FD_DOR_nRESET = 0x04,
335 FD_DOR_DMAEN = 0x08,
336 FD_DOR_MOTEN0 = 0x10,
337 FD_DOR_MOTEN1 = 0x20,
338 FD_DOR_MOTEN2 = 0x40,
339 FD_DOR_MOTEN3 = 0x80,
340 };
341
342 enum {
343 #if MAX_FD == 4
344 FD_TDR_BOOTSEL = 0x0c,
345 #else
346 FD_TDR_BOOTSEL = 0x04,
347 #endif
348 };
349
350 enum {
351 FD_DSR_DRATEMASK= 0x03,
352 FD_DSR_PWRDOWN = 0x40,
353 FD_DSR_SWRESET = 0x80,
354 };
355
356 enum {
357 FD_MSR_DRV0BUSY = 0x01,
358 FD_MSR_DRV1BUSY = 0x02,
359 FD_MSR_DRV2BUSY = 0x04,
360 FD_MSR_DRV3BUSY = 0x08,
361 FD_MSR_CMDBUSY = 0x10,
362 FD_MSR_NONDMA = 0x20,
363 FD_MSR_DIO = 0x40,
364 FD_MSR_RQM = 0x80,
365 };
366
367 enum {
368 FD_DIR_DSKCHG = 0x80,
369 };
370
371 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
372 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
373 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
374
375 struct FDCtrl {
376 qemu_irq irq;
377 /* Controller state */
378 QEMUTimer *result_timer;
379 int dma_chann;
380 /* Controller's identification */
381 uint8_t version;
382 /* HW */
383 uint8_t sra;
384 uint8_t srb;
385 uint8_t dor;
386 uint8_t dor_vmstate; /* only used as temp during vmstate */
387 uint8_t tdr;
388 uint8_t dsr;
389 uint8_t msr;
390 uint8_t cur_drv;
391 uint8_t status0;
392 uint8_t status1;
393 uint8_t status2;
394 /* Command FIFO */
395 uint8_t *fifo;
396 int32_t fifo_size;
397 uint32_t data_pos;
398 uint32_t data_len;
399 uint8_t data_state;
400 uint8_t data_dir;
401 uint8_t eot; /* last wanted sector */
402 /* States kept only to be returned back */
403 /* precompensation */
404 uint8_t precomp_trk;
405 uint8_t config;
406 uint8_t lock;
407 /* Power down config (also with status regB access mode */
408 uint8_t pwrd;
409 /* Floppy drives */
410 uint8_t num_floppies;
411 /* Sun4m quirks? */
412 int sun4m;
413 FDrive drives[MAX_FD];
414 int reset_sensei;
415 /* Timers state */
416 uint8_t timer0;
417 uint8_t timer1;
418 };
419
420 typedef struct FDCtrlSysBus {
421 SysBusDevice busdev;
422 struct FDCtrl state;
423 } FDCtrlSysBus;
424
425 typedef struct FDCtrlISABus {
426 ISADevice busdev;
427 struct FDCtrl state;
428 int32_t bootindexA;
429 int32_t bootindexB;
430 } FDCtrlISABus;
431
432 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
433 {
434 FDCtrl *fdctrl = opaque;
435 uint32_t retval;
436
437 switch (reg) {
438 case FD_REG_SRA:
439 retval = fdctrl_read_statusA(fdctrl);
440 break;
441 case FD_REG_SRB:
442 retval = fdctrl_read_statusB(fdctrl);
443 break;
444 case FD_REG_DOR:
445 retval = fdctrl_read_dor(fdctrl);
446 break;
447 case FD_REG_TDR:
448 retval = fdctrl_read_tape(fdctrl);
449 break;
450 case FD_REG_MSR:
451 retval = fdctrl_read_main_status(fdctrl);
452 break;
453 case FD_REG_FIFO:
454 retval = fdctrl_read_data(fdctrl);
455 break;
456 case FD_REG_DIR:
457 retval = fdctrl_read_dir(fdctrl);
458 break;
459 default:
460 retval = (uint32_t)(-1);
461 break;
462 }
463 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
464
465 return retval;
466 }
467
468 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
469 {
470 FDCtrl *fdctrl = opaque;
471
472 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
473
474 switch (reg) {
475 case FD_REG_DOR:
476 fdctrl_write_dor(fdctrl, value);
477 break;
478 case FD_REG_TDR:
479 fdctrl_write_tape(fdctrl, value);
480 break;
481 case FD_REG_DSR:
482 fdctrl_write_rate(fdctrl, value);
483 break;
484 case FD_REG_FIFO:
485 fdctrl_write_data(fdctrl, value);
486 break;
487 default:
488 break;
489 }
490 }
491
492 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
493 {
494 return fdctrl_read(opaque, reg & 7);
495 }
496
497 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
498 {
499 fdctrl_write(opaque, reg & 7, value);
500 }
501
502 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
503 {
504 return fdctrl_read(opaque, (uint32_t)reg);
505 }
506
507 static void fdctrl_write_mem (void *opaque,
508 target_phys_addr_t reg, uint32_t value)
509 {
510 fdctrl_write(opaque, (uint32_t)reg, value);
511 }
512
513 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
514 fdctrl_read_mem,
515 fdctrl_read_mem,
516 fdctrl_read_mem,
517 };
518
519 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
520 fdctrl_write_mem,
521 fdctrl_write_mem,
522 fdctrl_write_mem,
523 };
524
525 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
526 fdctrl_read_mem,
527 NULL,
528 NULL,
529 };
530
531 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
532 fdctrl_write_mem,
533 NULL,
534 NULL,
535 };
536
537 static bool fdrive_media_changed_needed(void *opaque)
538 {
539 FDrive *drive = opaque;
540
541 return (drive->bs != NULL && drive->media_changed != 1);
542 }
543
544 static const VMStateDescription vmstate_fdrive_media_changed = {
545 .name = "fdrive/media_changed",
546 .version_id = 1,
547 .minimum_version_id = 1,
548 .minimum_version_id_old = 1,
549 .fields = (VMStateField[]) {
550 VMSTATE_UINT8(media_changed, FDrive),
551 VMSTATE_END_OF_LIST()
552 }
553 };
554
555 static const VMStateDescription vmstate_fdrive = {
556 .name = "fdrive",
557 .version_id = 1,
558 .minimum_version_id = 1,
559 .minimum_version_id_old = 1,
560 .fields = (VMStateField[]) {
561 VMSTATE_UINT8(head, FDrive),
562 VMSTATE_UINT8(track, FDrive),
563 VMSTATE_UINT8(sect, FDrive),
564 VMSTATE_END_OF_LIST()
565 },
566 .subsections = (VMStateSubsection[]) {
567 {
568 .vmsd = &vmstate_fdrive_media_changed,
569 .needed = &fdrive_media_changed_needed,
570 } , {
571 /* empty */
572 }
573 }
574 };
575
576 static void fdc_pre_save(void *opaque)
577 {
578 FDCtrl *s = opaque;
579
580 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
581 }
582
583 static int fdc_post_load(void *opaque, int version_id)
584 {
585 FDCtrl *s = opaque;
586
587 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
588 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
589 return 0;
590 }
591
592 static const VMStateDescription vmstate_fdc = {
593 .name = "fdc",
594 .version_id = 2,
595 .minimum_version_id = 2,
596 .minimum_version_id_old = 2,
597 .pre_save = fdc_pre_save,
598 .post_load = fdc_post_load,
599 .fields = (VMStateField []) {
600 /* Controller State */
601 VMSTATE_UINT8(sra, FDCtrl),
602 VMSTATE_UINT8(srb, FDCtrl),
603 VMSTATE_UINT8(dor_vmstate, FDCtrl),
604 VMSTATE_UINT8(tdr, FDCtrl),
605 VMSTATE_UINT8(dsr, FDCtrl),
606 VMSTATE_UINT8(msr, FDCtrl),
607 VMSTATE_UINT8(status0, FDCtrl),
608 VMSTATE_UINT8(status1, FDCtrl),
609 VMSTATE_UINT8(status2, FDCtrl),
610 /* Command FIFO */
611 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
612 uint8_t),
613 VMSTATE_UINT32(data_pos, FDCtrl),
614 VMSTATE_UINT32(data_len, FDCtrl),
615 VMSTATE_UINT8(data_state, FDCtrl),
616 VMSTATE_UINT8(data_dir, FDCtrl),
617 VMSTATE_UINT8(eot, FDCtrl),
618 /* States kept only to be returned back */
619 VMSTATE_UINT8(timer0, FDCtrl),
620 VMSTATE_UINT8(timer1, FDCtrl),
621 VMSTATE_UINT8(precomp_trk, FDCtrl),
622 VMSTATE_UINT8(config, FDCtrl),
623 VMSTATE_UINT8(lock, FDCtrl),
624 VMSTATE_UINT8(pwrd, FDCtrl),
625 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
626 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
627 vmstate_fdrive, FDrive),
628 VMSTATE_END_OF_LIST()
629 }
630 };
631
632 static void fdctrl_external_reset_sysbus(DeviceState *d)
633 {
634 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
635 FDCtrl *s = &sys->state;
636
637 fdctrl_reset(s, 0);
638 }
639
640 static void fdctrl_external_reset_isa(DeviceState *d)
641 {
642 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
643 FDCtrl *s = &isa->state;
644
645 fdctrl_reset(s, 0);
646 }
647
648 static void fdctrl_handle_tc(void *opaque, int irq, int level)
649 {
650 //FDCtrl *s = opaque;
651
652 if (level) {
653 // XXX
654 FLOPPY_DPRINTF("TC pulsed\n");
655 }
656 }
657
658 /* Change IRQ state */
659 static void fdctrl_reset_irq(FDCtrl *fdctrl)
660 {
661 if (!(fdctrl->sra & FD_SRA_INTPEND))
662 return;
663 FLOPPY_DPRINTF("Reset interrupt\n");
664 qemu_set_irq(fdctrl->irq, 0);
665 fdctrl->sra &= ~FD_SRA_INTPEND;
666 }
667
668 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
669 {
670 /* Sparc mutation */
671 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
672 /* XXX: not sure */
673 fdctrl->msr &= ~FD_MSR_CMDBUSY;
674 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
675 fdctrl->status0 = status0;
676 return;
677 }
678 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
679 qemu_set_irq(fdctrl->irq, 1);
680 fdctrl->sra |= FD_SRA_INTPEND;
681 }
682 fdctrl->reset_sensei = 0;
683 fdctrl->status0 = status0;
684 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
685 }
686
687 /* Reset controller */
688 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
689 {
690 int i;
691
692 FLOPPY_DPRINTF("reset controller\n");
693 fdctrl_reset_irq(fdctrl);
694 /* Initialise controller */
695 fdctrl->sra = 0;
696 fdctrl->srb = 0xc0;
697 if (!fdctrl->drives[1].bs)
698 fdctrl->sra |= FD_SRA_nDRV2;
699 fdctrl->cur_drv = 0;
700 fdctrl->dor = FD_DOR_nRESET;
701 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
702 fdctrl->msr = FD_MSR_RQM;
703 /* FIFO state */
704 fdctrl->data_pos = 0;
705 fdctrl->data_len = 0;
706 fdctrl->data_state = 0;
707 fdctrl->data_dir = FD_DIR_WRITE;
708 for (i = 0; i < MAX_FD; i++)
709 fd_recalibrate(&fdctrl->drives[i]);
710 fdctrl_reset_fifo(fdctrl);
711 if (do_irq) {
712 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
713 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
714 }
715 }
716
717 static inline FDrive *drv0(FDCtrl *fdctrl)
718 {
719 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
720 }
721
722 static inline FDrive *drv1(FDCtrl *fdctrl)
723 {
724 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
725 return &fdctrl->drives[1];
726 else
727 return &fdctrl->drives[0];
728 }
729
730 #if MAX_FD == 4
731 static inline FDrive *drv2(FDCtrl *fdctrl)
732 {
733 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
734 return &fdctrl->drives[2];
735 else
736 return &fdctrl->drives[1];
737 }
738
739 static inline FDrive *drv3(FDCtrl *fdctrl)
740 {
741 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
742 return &fdctrl->drives[3];
743 else
744 return &fdctrl->drives[2];
745 }
746 #endif
747
748 static FDrive *get_cur_drv(FDCtrl *fdctrl)
749 {
750 switch (fdctrl->cur_drv) {
751 case 0: return drv0(fdctrl);
752 case 1: return drv1(fdctrl);
753 #if MAX_FD == 4
754 case 2: return drv2(fdctrl);
755 case 3: return drv3(fdctrl);
756 #endif
757 default: return NULL;
758 }
759 }
760
761 /* Status A register : 0x00 (read-only) */
762 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
763 {
764 uint32_t retval = fdctrl->sra;
765
766 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
767
768 return retval;
769 }
770
771 /* Status B register : 0x01 (read-only) */
772 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
773 {
774 uint32_t retval = fdctrl->srb;
775
776 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
777
778 return retval;
779 }
780
781 /* Digital output register : 0x02 */
782 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
783 {
784 uint32_t retval = fdctrl->dor;
785
786 /* Selected drive */
787 retval |= fdctrl->cur_drv;
788 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
789
790 return retval;
791 }
792
793 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
794 {
795 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
796
797 /* Motors */
798 if (value & FD_DOR_MOTEN0)
799 fdctrl->srb |= FD_SRB_MTR0;
800 else
801 fdctrl->srb &= ~FD_SRB_MTR0;
802 if (value & FD_DOR_MOTEN1)
803 fdctrl->srb |= FD_SRB_MTR1;
804 else
805 fdctrl->srb &= ~FD_SRB_MTR1;
806
807 /* Drive */
808 if (value & 1)
809 fdctrl->srb |= FD_SRB_DR0;
810 else
811 fdctrl->srb &= ~FD_SRB_DR0;
812
813 /* Reset */
814 if (!(value & FD_DOR_nRESET)) {
815 if (fdctrl->dor & FD_DOR_nRESET) {
816 FLOPPY_DPRINTF("controller enter RESET state\n");
817 }
818 } else {
819 if (!(fdctrl->dor & FD_DOR_nRESET)) {
820 FLOPPY_DPRINTF("controller out of RESET state\n");
821 fdctrl_reset(fdctrl, 1);
822 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
823 }
824 }
825 /* Selected drive */
826 fdctrl->cur_drv = value & FD_DOR_SELMASK;
827
828 fdctrl->dor = value;
829 }
830
831 /* Tape drive register : 0x03 */
832 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
833 {
834 uint32_t retval = fdctrl->tdr;
835
836 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
837
838 return retval;
839 }
840
841 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
842 {
843 /* Reset mode */
844 if (!(fdctrl->dor & FD_DOR_nRESET)) {
845 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
846 return;
847 }
848 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
849 /* Disk boot selection indicator */
850 fdctrl->tdr = value & FD_TDR_BOOTSEL;
851 /* Tape indicators: never allow */
852 }
853
854 /* Main status register : 0x04 (read) */
855 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
856 {
857 uint32_t retval = fdctrl->msr;
858
859 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
860 fdctrl->dor |= FD_DOR_nRESET;
861
862 /* Sparc mutation */
863 if (fdctrl->sun4m) {
864 retval |= FD_MSR_DIO;
865 fdctrl_reset_irq(fdctrl);
866 };
867
868 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
869
870 return retval;
871 }
872
873 /* Data select rate register : 0x04 (write) */
874 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
875 {
876 /* Reset mode */
877 if (!(fdctrl->dor & FD_DOR_nRESET)) {
878 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
879 return;
880 }
881 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
882 /* Reset: autoclear */
883 if (value & FD_DSR_SWRESET) {
884 fdctrl->dor &= ~FD_DOR_nRESET;
885 fdctrl_reset(fdctrl, 1);
886 fdctrl->dor |= FD_DOR_nRESET;
887 }
888 if (value & FD_DSR_PWRDOWN) {
889 fdctrl_reset(fdctrl, 1);
890 }
891 fdctrl->dsr = value;
892 }
893
894 static int fdctrl_media_changed(FDrive *drv)
895 {
896 int ret;
897
898 if (!drv->bs)
899 return 0;
900 if (drv->media_changed) {
901 drv->media_changed = 0;
902 ret = 1;
903 } else {
904 ret = bdrv_media_changed(drv->bs);
905 if (ret < 0) {
906 ret = 0; /* we don't know, assume no */
907 }
908 }
909 if (ret) {
910 fd_revalidate(drv);
911 }
912 return ret;
913 }
914
915 /* Digital input register : 0x07 (read-only) */
916 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
917 {
918 uint32_t retval = 0;
919
920 if (fdctrl_media_changed(drv0(fdctrl))
921 || fdctrl_media_changed(drv1(fdctrl))
922 #if MAX_FD == 4
923 || fdctrl_media_changed(drv2(fdctrl))
924 || fdctrl_media_changed(drv3(fdctrl))
925 #endif
926 )
927 retval |= FD_DIR_DSKCHG;
928 if (retval != 0) {
929 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
930 }
931
932 return retval;
933 }
934
935 /* FIFO state control */
936 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
937 {
938 fdctrl->data_dir = FD_DIR_WRITE;
939 fdctrl->data_pos = 0;
940 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
941 }
942
943 /* Set FIFO status for the host to read */
944 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
945 {
946 fdctrl->data_dir = FD_DIR_READ;
947 fdctrl->data_len = fifo_len;
948 fdctrl->data_pos = 0;
949 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
950 if (do_irq)
951 fdctrl_raise_irq(fdctrl, 0x00);
952 }
953
954 /* Set an error: unimplemented/unknown command */
955 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
956 {
957 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
958 fdctrl->fifo[0] = FD_SR0_INVCMD;
959 fdctrl_set_fifo(fdctrl, 1, 0);
960 }
961
962 /* Seek to next sector */
963 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
964 {
965 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
966 cur_drv->head, cur_drv->track, cur_drv->sect,
967 fd_sector(cur_drv));
968 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
969 error in fact */
970 if (cur_drv->sect >= cur_drv->last_sect ||
971 cur_drv->sect == fdctrl->eot) {
972 cur_drv->sect = 1;
973 if (FD_MULTI_TRACK(fdctrl->data_state)) {
974 if (cur_drv->head == 0 &&
975 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
976 cur_drv->head = 1;
977 } else {
978 cur_drv->head = 0;
979 cur_drv->track++;
980 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
981 return 0;
982 }
983 } else {
984 cur_drv->track++;
985 return 0;
986 }
987 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
988 cur_drv->head, cur_drv->track,
989 cur_drv->sect, fd_sector(cur_drv));
990 } else {
991 cur_drv->sect++;
992 }
993 return 1;
994 }
995
996 /* Callback for transfer end (stop or abort) */
997 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
998 uint8_t status1, uint8_t status2)
999 {
1000 FDrive *cur_drv;
1001
1002 cur_drv = get_cur_drv(fdctrl);
1003 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1004 status0, status1, status2,
1005 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1006 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1007 fdctrl->fifo[1] = status1;
1008 fdctrl->fifo[2] = status2;
1009 fdctrl->fifo[3] = cur_drv->track;
1010 fdctrl->fifo[4] = cur_drv->head;
1011 fdctrl->fifo[5] = cur_drv->sect;
1012 fdctrl->fifo[6] = FD_SECTOR_SC;
1013 fdctrl->data_dir = FD_DIR_READ;
1014 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1015 DMA_release_DREQ(fdctrl->dma_chann);
1016 }
1017 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1018 fdctrl->msr &= ~FD_MSR_NONDMA;
1019 fdctrl_set_fifo(fdctrl, 7, 1);
1020 }
1021
1022 /* Prepare a data transfer (either DMA or FIFO) */
1023 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1024 {
1025 FDrive *cur_drv;
1026 uint8_t kh, kt, ks;
1027 int did_seek = 0;
1028
1029 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1030 cur_drv = get_cur_drv(fdctrl);
1031 kt = fdctrl->fifo[2];
1032 kh = fdctrl->fifo[3];
1033 ks = fdctrl->fifo[4];
1034 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1035 GET_CUR_DRV(fdctrl), kh, kt, ks,
1036 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1037 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1038 case 2:
1039 /* sect too big */
1040 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1041 fdctrl->fifo[3] = kt;
1042 fdctrl->fifo[4] = kh;
1043 fdctrl->fifo[5] = ks;
1044 return;
1045 case 3:
1046 /* track too big */
1047 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1048 fdctrl->fifo[3] = kt;
1049 fdctrl->fifo[4] = kh;
1050 fdctrl->fifo[5] = ks;
1051 return;
1052 case 4:
1053 /* No seek enabled */
1054 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1055 fdctrl->fifo[3] = kt;
1056 fdctrl->fifo[4] = kh;
1057 fdctrl->fifo[5] = ks;
1058 return;
1059 case 1:
1060 did_seek = 1;
1061 break;
1062 default:
1063 break;
1064 }
1065
1066 /* Set the FIFO state */
1067 fdctrl->data_dir = direction;
1068 fdctrl->data_pos = 0;
1069 fdctrl->msr |= FD_MSR_CMDBUSY;
1070 if (fdctrl->fifo[0] & 0x80)
1071 fdctrl->data_state |= FD_STATE_MULTI;
1072 else
1073 fdctrl->data_state &= ~FD_STATE_MULTI;
1074 if (did_seek)
1075 fdctrl->data_state |= FD_STATE_SEEK;
1076 else
1077 fdctrl->data_state &= ~FD_STATE_SEEK;
1078 if (fdctrl->fifo[5] == 00) {
1079 fdctrl->data_len = fdctrl->fifo[8];
1080 } else {
1081 int tmp;
1082 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1083 tmp = (fdctrl->fifo[6] - ks + 1);
1084 if (fdctrl->fifo[0] & 0x80)
1085 tmp += fdctrl->fifo[6];
1086 fdctrl->data_len *= tmp;
1087 }
1088 fdctrl->eot = fdctrl->fifo[6];
1089 if (fdctrl->dor & FD_DOR_DMAEN) {
1090 int dma_mode;
1091 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1092 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1093 dma_mode = (dma_mode >> 2) & 3;
1094 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1095 dma_mode, direction,
1096 (128 << fdctrl->fifo[5]) *
1097 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1098 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1099 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1100 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1101 (direction == FD_DIR_READ && dma_mode == 1)) {
1102 /* No access is allowed until DMA transfer has completed */
1103 fdctrl->msr &= ~FD_MSR_RQM;
1104 /* Now, we just have to wait for the DMA controller to
1105 * recall us...
1106 */
1107 DMA_hold_DREQ(fdctrl->dma_chann);
1108 DMA_schedule(fdctrl->dma_chann);
1109 return;
1110 } else {
1111 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1112 }
1113 }
1114 FLOPPY_DPRINTF("start non-DMA transfer\n");
1115 fdctrl->msr |= FD_MSR_NONDMA;
1116 if (direction != FD_DIR_WRITE)
1117 fdctrl->msr |= FD_MSR_DIO;
1118 /* IO based transfer: calculate len */
1119 fdctrl_raise_irq(fdctrl, 0x00);
1120
1121 return;
1122 }
1123
1124 /* Prepare a transfer of deleted data */
1125 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1126 {
1127 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1128
1129 /* We don't handle deleted data,
1130 * so we don't return *ANYTHING*
1131 */
1132 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1133 }
1134
1135 /* handlers for DMA transfers */
1136 static int fdctrl_transfer_handler (void *opaque, int nchan,
1137 int dma_pos, int dma_len)
1138 {
1139 FDCtrl *fdctrl;
1140 FDrive *cur_drv;
1141 int len, start_pos, rel_pos;
1142 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1143
1144 fdctrl = opaque;
1145 if (fdctrl->msr & FD_MSR_RQM) {
1146 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1147 return 0;
1148 }
1149 cur_drv = get_cur_drv(fdctrl);
1150 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1151 fdctrl->data_dir == FD_DIR_SCANH)
1152 status2 = FD_SR2_SNS;
1153 if (dma_len > fdctrl->data_len)
1154 dma_len = fdctrl->data_len;
1155 if (cur_drv->bs == NULL) {
1156 if (fdctrl->data_dir == FD_DIR_WRITE)
1157 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1158 else
1159 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1160 len = 0;
1161 goto transfer_error;
1162 }
1163 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1164 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1165 len = dma_len - fdctrl->data_pos;
1166 if (len + rel_pos > FD_SECTOR_LEN)
1167 len = FD_SECTOR_LEN - rel_pos;
1168 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1169 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1170 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1171 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1172 fd_sector(cur_drv) * FD_SECTOR_LEN);
1173 if (fdctrl->data_dir != FD_DIR_WRITE ||
1174 len < FD_SECTOR_LEN || rel_pos != 0) {
1175 /* READ & SCAN commands and realign to a sector for WRITE */
1176 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1177 fdctrl->fifo, 1) < 0) {
1178 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1179 fd_sector(cur_drv));
1180 /* Sure, image size is too small... */
1181 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1182 }
1183 }
1184 switch (fdctrl->data_dir) {
1185 case FD_DIR_READ:
1186 /* READ commands */
1187 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1188 fdctrl->data_pos, len);
1189 break;
1190 case FD_DIR_WRITE:
1191 /* WRITE commands */
1192 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1193 fdctrl->data_pos, len);
1194 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1195 fdctrl->fifo, 1) < 0) {
1196 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1197 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1198 goto transfer_error;
1199 }
1200 break;
1201 default:
1202 /* SCAN commands */
1203 {
1204 uint8_t tmpbuf[FD_SECTOR_LEN];
1205 int ret;
1206 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1207 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1208 if (ret == 0) {
1209 status2 = FD_SR2_SEH;
1210 goto end_transfer;
1211 }
1212 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1213 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1214 status2 = 0x00;
1215 goto end_transfer;
1216 }
1217 }
1218 break;
1219 }
1220 fdctrl->data_pos += len;
1221 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1222 if (rel_pos == 0) {
1223 /* Seek to next sector */
1224 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1225 break;
1226 }
1227 }
1228 end_transfer:
1229 len = fdctrl->data_pos - start_pos;
1230 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1231 fdctrl->data_pos, len, fdctrl->data_len);
1232 if (fdctrl->data_dir == FD_DIR_SCANE ||
1233 fdctrl->data_dir == FD_DIR_SCANL ||
1234 fdctrl->data_dir == FD_DIR_SCANH)
1235 status2 = FD_SR2_SEH;
1236 if (FD_DID_SEEK(fdctrl->data_state))
1237 status0 |= FD_SR0_SEEK;
1238 fdctrl->data_len -= len;
1239 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1240 transfer_error:
1241
1242 return len;
1243 }
1244
1245 /* Data register : 0x05 */
1246 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1247 {
1248 FDrive *cur_drv;
1249 uint32_t retval = 0;
1250 int pos;
1251
1252 cur_drv = get_cur_drv(fdctrl);
1253 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1254 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1255 FLOPPY_ERROR("controller not ready for reading\n");
1256 return 0;
1257 }
1258 pos = fdctrl->data_pos;
1259 if (fdctrl->msr & FD_MSR_NONDMA) {
1260 pos %= FD_SECTOR_LEN;
1261 if (pos == 0) {
1262 if (fdctrl->data_pos != 0)
1263 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1264 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1265 fd_sector(cur_drv));
1266 return 0;
1267 }
1268 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1269 FLOPPY_DPRINTF("error getting sector %d\n",
1270 fd_sector(cur_drv));
1271 /* Sure, image size is too small... */
1272 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1273 }
1274 }
1275 }
1276 retval = fdctrl->fifo[pos];
1277 if (++fdctrl->data_pos == fdctrl->data_len) {
1278 fdctrl->data_pos = 0;
1279 /* Switch from transfer mode to status mode
1280 * then from status mode to command mode
1281 */
1282 if (fdctrl->msr & FD_MSR_NONDMA) {
1283 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1284 } else {
1285 fdctrl_reset_fifo(fdctrl);
1286 fdctrl_reset_irq(fdctrl);
1287 }
1288 }
1289 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1290
1291 return retval;
1292 }
1293
1294 static void fdctrl_format_sector(FDCtrl *fdctrl)
1295 {
1296 FDrive *cur_drv;
1297 uint8_t kh, kt, ks;
1298
1299 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1300 cur_drv = get_cur_drv(fdctrl);
1301 kt = fdctrl->fifo[6];
1302 kh = fdctrl->fifo[7];
1303 ks = fdctrl->fifo[8];
1304 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1305 GET_CUR_DRV(fdctrl), kh, kt, ks,
1306 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1307 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1308 case 2:
1309 /* sect too big */
1310 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1311 fdctrl->fifo[3] = kt;
1312 fdctrl->fifo[4] = kh;
1313 fdctrl->fifo[5] = ks;
1314 return;
1315 case 3:
1316 /* track too big */
1317 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1318 fdctrl->fifo[3] = kt;
1319 fdctrl->fifo[4] = kh;
1320 fdctrl->fifo[5] = ks;
1321 return;
1322 case 4:
1323 /* No seek enabled */
1324 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1325 fdctrl->fifo[3] = kt;
1326 fdctrl->fifo[4] = kh;
1327 fdctrl->fifo[5] = ks;
1328 return;
1329 case 1:
1330 fdctrl->data_state |= FD_STATE_SEEK;
1331 break;
1332 default:
1333 break;
1334 }
1335 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1336 if (cur_drv->bs == NULL ||
1337 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1338 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1339 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1340 } else {
1341 if (cur_drv->sect == cur_drv->last_sect) {
1342 fdctrl->data_state &= ~FD_STATE_FORMAT;
1343 /* Last sector done */
1344 if (FD_DID_SEEK(fdctrl->data_state))
1345 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1346 else
1347 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1348 } else {
1349 /* More to do */
1350 fdctrl->data_pos = 0;
1351 fdctrl->data_len = 4;
1352 }
1353 }
1354 }
1355
1356 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1357 {
1358 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1359 fdctrl->fifo[0] = fdctrl->lock << 4;
1360 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1361 }
1362
1363 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1364 {
1365 FDrive *cur_drv = get_cur_drv(fdctrl);
1366
1367 /* Drives position */
1368 fdctrl->fifo[0] = drv0(fdctrl)->track;
1369 fdctrl->fifo[1] = drv1(fdctrl)->track;
1370 #if MAX_FD == 4
1371 fdctrl->fifo[2] = drv2(fdctrl)->track;
1372 fdctrl->fifo[3] = drv3(fdctrl)->track;
1373 #else
1374 fdctrl->fifo[2] = 0;
1375 fdctrl->fifo[3] = 0;
1376 #endif
1377 /* timers */
1378 fdctrl->fifo[4] = fdctrl->timer0;
1379 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1380 fdctrl->fifo[6] = cur_drv->last_sect;
1381 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1382 (cur_drv->perpendicular << 2);
1383 fdctrl->fifo[8] = fdctrl->config;
1384 fdctrl->fifo[9] = fdctrl->precomp_trk;
1385 fdctrl_set_fifo(fdctrl, 10, 0);
1386 }
1387
1388 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1389 {
1390 /* Controller's version */
1391 fdctrl->fifo[0] = fdctrl->version;
1392 fdctrl_set_fifo(fdctrl, 1, 1);
1393 }
1394
1395 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1396 {
1397 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1398 fdctrl_set_fifo(fdctrl, 1, 0);
1399 }
1400
1401 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1402 {
1403 FDrive *cur_drv = get_cur_drv(fdctrl);
1404
1405 /* Drives position */
1406 drv0(fdctrl)->track = fdctrl->fifo[3];
1407 drv1(fdctrl)->track = fdctrl->fifo[4];
1408 #if MAX_FD == 4
1409 drv2(fdctrl)->track = fdctrl->fifo[5];
1410 drv3(fdctrl)->track = fdctrl->fifo[6];
1411 #endif
1412 /* timers */
1413 fdctrl->timer0 = fdctrl->fifo[7];
1414 fdctrl->timer1 = fdctrl->fifo[8];
1415 cur_drv->last_sect = fdctrl->fifo[9];
1416 fdctrl->lock = fdctrl->fifo[10] >> 7;
1417 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1418 fdctrl->config = fdctrl->fifo[11];
1419 fdctrl->precomp_trk = fdctrl->fifo[12];
1420 fdctrl->pwrd = fdctrl->fifo[13];
1421 fdctrl_reset_fifo(fdctrl);
1422 }
1423
1424 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1425 {
1426 FDrive *cur_drv = get_cur_drv(fdctrl);
1427
1428 fdctrl->fifo[0] = 0;
1429 fdctrl->fifo[1] = 0;
1430 /* Drives position */
1431 fdctrl->fifo[2] = drv0(fdctrl)->track;
1432 fdctrl->fifo[3] = drv1(fdctrl)->track;
1433 #if MAX_FD == 4
1434 fdctrl->fifo[4] = drv2(fdctrl)->track;
1435 fdctrl->fifo[5] = drv3(fdctrl)->track;
1436 #else
1437 fdctrl->fifo[4] = 0;
1438 fdctrl->fifo[5] = 0;
1439 #endif
1440 /* timers */
1441 fdctrl->fifo[6] = fdctrl->timer0;
1442 fdctrl->fifo[7] = fdctrl->timer1;
1443 fdctrl->fifo[8] = cur_drv->last_sect;
1444 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1445 (cur_drv->perpendicular << 2);
1446 fdctrl->fifo[10] = fdctrl->config;
1447 fdctrl->fifo[11] = fdctrl->precomp_trk;
1448 fdctrl->fifo[12] = fdctrl->pwrd;
1449 fdctrl->fifo[13] = 0;
1450 fdctrl->fifo[14] = 0;
1451 fdctrl_set_fifo(fdctrl, 15, 1);
1452 }
1453
1454 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1455 {
1456 FDrive *cur_drv = get_cur_drv(fdctrl);
1457
1458 /* XXX: should set main status register to busy */
1459 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1460 qemu_mod_timer(fdctrl->result_timer,
1461 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1462 }
1463
1464 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1465 {
1466 FDrive *cur_drv;
1467
1468 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1469 cur_drv = get_cur_drv(fdctrl);
1470 fdctrl->data_state |= FD_STATE_FORMAT;
1471 if (fdctrl->fifo[0] & 0x80)
1472 fdctrl->data_state |= FD_STATE_MULTI;
1473 else
1474 fdctrl->data_state &= ~FD_STATE_MULTI;
1475 fdctrl->data_state &= ~FD_STATE_SEEK;
1476 cur_drv->bps =
1477 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1478 #if 0
1479 cur_drv->last_sect =
1480 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1481 fdctrl->fifo[3] / 2;
1482 #else
1483 cur_drv->last_sect = fdctrl->fifo[3];
1484 #endif
1485 /* TODO: implement format using DMA expected by the Bochs BIOS
1486 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1487 * the sector with the specified fill byte
1488 */
1489 fdctrl->data_state &= ~FD_STATE_FORMAT;
1490 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1491 }
1492
1493 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1494 {
1495 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1496 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1497 if (fdctrl->fifo[2] & 1)
1498 fdctrl->dor &= ~FD_DOR_DMAEN;
1499 else
1500 fdctrl->dor |= FD_DOR_DMAEN;
1501 /* No result back */
1502 fdctrl_reset_fifo(fdctrl);
1503 }
1504
1505 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1506 {
1507 FDrive *cur_drv;
1508
1509 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1510 cur_drv = get_cur_drv(fdctrl);
1511 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1512 /* 1 Byte status back */
1513 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1514 (cur_drv->track == 0 ? 0x10 : 0x00) |
1515 (cur_drv->head << 2) |
1516 GET_CUR_DRV(fdctrl) |
1517 0x28;
1518 fdctrl_set_fifo(fdctrl, 1, 0);
1519 }
1520
1521 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1522 {
1523 FDrive *cur_drv;
1524
1525 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1526 cur_drv = get_cur_drv(fdctrl);
1527 fd_recalibrate(cur_drv);
1528 fdctrl_reset_fifo(fdctrl);
1529 /* Raise Interrupt */
1530 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1531 }
1532
1533 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1534 {
1535 FDrive *cur_drv = get_cur_drv(fdctrl);
1536
1537 if(fdctrl->reset_sensei > 0) {
1538 fdctrl->fifo[0] =
1539 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1540 fdctrl->reset_sensei--;
1541 } else {
1542 /* XXX: status0 handling is broken for read/write
1543 commands, so we do this hack. It should be suppressed
1544 ASAP */
1545 fdctrl->fifo[0] =
1546 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1547 }
1548
1549 fdctrl->fifo[1] = cur_drv->track;
1550 fdctrl_set_fifo(fdctrl, 2, 0);
1551 fdctrl_reset_irq(fdctrl);
1552 fdctrl->status0 = FD_SR0_RDYCHG;
1553 }
1554
1555 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1556 {
1557 FDrive *cur_drv;
1558
1559 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1560 cur_drv = get_cur_drv(fdctrl);
1561 fdctrl_reset_fifo(fdctrl);
1562 if (fdctrl->fifo[2] > cur_drv->max_track) {
1563 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1564 } else {
1565 cur_drv->track = fdctrl->fifo[2];
1566 /* Raise Interrupt */
1567 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1568 }
1569 }
1570
1571 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1572 {
1573 FDrive *cur_drv = get_cur_drv(fdctrl);
1574
1575 if (fdctrl->fifo[1] & 0x80)
1576 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1577 /* No result back */
1578 fdctrl_reset_fifo(fdctrl);
1579 }
1580
1581 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1582 {
1583 fdctrl->config = fdctrl->fifo[2];
1584 fdctrl->precomp_trk = fdctrl->fifo[3];
1585 /* No result back */
1586 fdctrl_reset_fifo(fdctrl);
1587 }
1588
1589 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1590 {
1591 fdctrl->pwrd = fdctrl->fifo[1];
1592 fdctrl->fifo[0] = fdctrl->fifo[1];
1593 fdctrl_set_fifo(fdctrl, 1, 1);
1594 }
1595
1596 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1597 {
1598 /* No result back */
1599 fdctrl_reset_fifo(fdctrl);
1600 }
1601
1602 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1603 {
1604 FDrive *cur_drv = get_cur_drv(fdctrl);
1605
1606 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1607 /* Command parameters done */
1608 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1609 fdctrl->fifo[0] = fdctrl->fifo[1];
1610 fdctrl->fifo[2] = 0;
1611 fdctrl->fifo[3] = 0;
1612 fdctrl_set_fifo(fdctrl, 4, 1);
1613 } else {
1614 fdctrl_reset_fifo(fdctrl);
1615 }
1616 } else if (fdctrl->data_len > 7) {
1617 /* ERROR */
1618 fdctrl->fifo[0] = 0x80 |
1619 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1620 fdctrl_set_fifo(fdctrl, 1, 1);
1621 }
1622 }
1623
1624 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1625 {
1626 FDrive *cur_drv;
1627
1628 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1629 cur_drv = get_cur_drv(fdctrl);
1630 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1631 cur_drv->track = cur_drv->max_track - 1;
1632 } else {
1633 cur_drv->track += fdctrl->fifo[2];
1634 }
1635 fdctrl_reset_fifo(fdctrl);
1636 /* Raise Interrupt */
1637 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1638 }
1639
1640 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1641 {
1642 FDrive *cur_drv;
1643
1644 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1645 cur_drv = get_cur_drv(fdctrl);
1646 if (fdctrl->fifo[2] > cur_drv->track) {
1647 cur_drv->track = 0;
1648 } else {
1649 cur_drv->track -= fdctrl->fifo[2];
1650 }
1651 fdctrl_reset_fifo(fdctrl);
1652 /* Raise Interrupt */
1653 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1654 }
1655
1656 static const struct {
1657 uint8_t value;
1658 uint8_t mask;
1659 const char* name;
1660 int parameters;
1661 void (*handler)(FDCtrl *fdctrl, int direction);
1662 int direction;
1663 } handlers[] = {
1664 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1665 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1666 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1667 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1668 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1669 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1670 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1671 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1672 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1673 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1674 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1675 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1676 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1677 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1678 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1679 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1680 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1681 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1682 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1683 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1684 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1685 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1686 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1687 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1688 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1689 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1690 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1691 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1692 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1693 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1694 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1695 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1696 };
1697 /* Associate command to an index in the 'handlers' array */
1698 static uint8_t command_to_handler[256];
1699
1700 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1701 {
1702 FDrive *cur_drv;
1703 int pos;
1704
1705 /* Reset mode */
1706 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1707 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1708 return;
1709 }
1710 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1711 FLOPPY_ERROR("controller not ready for writing\n");
1712 return;
1713 }
1714 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1715 /* Is it write command time ? */
1716 if (fdctrl->msr & FD_MSR_NONDMA) {
1717 /* FIFO data write */
1718 pos = fdctrl->data_pos++;
1719 pos %= FD_SECTOR_LEN;
1720 fdctrl->fifo[pos] = value;
1721 if (pos == FD_SECTOR_LEN - 1 ||
1722 fdctrl->data_pos == fdctrl->data_len) {
1723 cur_drv = get_cur_drv(fdctrl);
1724 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1725 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1726 return;
1727 }
1728 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1729 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1730 fd_sector(cur_drv));
1731 return;
1732 }
1733 }
1734 /* Switch from transfer mode to status mode
1735 * then from status mode to command mode
1736 */
1737 if (fdctrl->data_pos == fdctrl->data_len)
1738 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1739 return;
1740 }
1741 if (fdctrl->data_pos == 0) {
1742 /* Command */
1743 pos = command_to_handler[value & 0xff];
1744 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1745 fdctrl->data_len = handlers[pos].parameters + 1;
1746 }
1747
1748 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1749 fdctrl->fifo[fdctrl->data_pos++] = value;
1750 if (fdctrl->data_pos == fdctrl->data_len) {
1751 /* We now have all parameters
1752 * and will be able to treat the command
1753 */
1754 if (fdctrl->data_state & FD_STATE_FORMAT) {
1755 fdctrl_format_sector(fdctrl);
1756 return;
1757 }
1758
1759 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1760 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1761 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1762 }
1763 }
1764
1765 static void fdctrl_result_timer(void *opaque)
1766 {
1767 FDCtrl *fdctrl = opaque;
1768 FDrive *cur_drv = get_cur_drv(fdctrl);
1769
1770 /* Pretend we are spinning.
1771 * This is needed for Coherent, which uses READ ID to check for
1772 * sector interleaving.
1773 */
1774 if (cur_drv->last_sect != 0) {
1775 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1776 }
1777 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1778 }
1779
1780 static void fdctrl_change_cb(void *opaque, bool load)
1781 {
1782 FDrive *drive = opaque;
1783
1784 drive->media_changed = 1;
1785 }
1786
1787 static const BlockDevOps fdctrl_block_ops = {
1788 .change_media_cb = fdctrl_change_cb,
1789 };
1790
1791 /* Init functions */
1792 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1793 {
1794 unsigned int i;
1795 FDrive *drive;
1796
1797 for (i = 0; i < MAX_FD; i++) {
1798 drive = &fdctrl->drives[i];
1799
1800 if (drive->bs) {
1801 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1802 error_report("fdc doesn't support drive option werror");
1803 return -1;
1804 }
1805 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1806 error_report("fdc doesn't support drive option rerror");
1807 return -1;
1808 }
1809 }
1810
1811 fd_init(drive);
1812 fd_revalidate(drive);
1813 if (drive->bs) {
1814 drive->media_changed = 1;
1815 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1816 }
1817 }
1818 return 0;
1819 }
1820
1821 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1822 target_phys_addr_t mmio_base, DriveInfo **fds)
1823 {
1824 FDCtrl *fdctrl;
1825 DeviceState *dev;
1826 FDCtrlSysBus *sys;
1827
1828 dev = qdev_create(NULL, "sysbus-fdc");
1829 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1830 fdctrl = &sys->state;
1831 fdctrl->dma_chann = dma_chann; /* FIXME */
1832 if (fds[0]) {
1833 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1834 }
1835 if (fds[1]) {
1836 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1837 }
1838 qdev_init_nofail(dev);
1839 sysbus_connect_irq(&sys->busdev, 0, irq);
1840 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1841 }
1842
1843 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1844 DriveInfo **fds, qemu_irq *fdc_tc)
1845 {
1846 DeviceState *dev;
1847 FDCtrlSysBus *sys;
1848
1849 dev = qdev_create(NULL, "SUNW,fdtwo");
1850 if (fds[0]) {
1851 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1852 }
1853 qdev_init_nofail(dev);
1854 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1855 sysbus_connect_irq(&sys->busdev, 0, irq);
1856 sysbus_mmio_map(&sys->busdev, 0, io_base);
1857 *fdc_tc = qdev_get_gpio_in(dev, 0);
1858 }
1859
1860 static int fdctrl_init_common(FDCtrl *fdctrl)
1861 {
1862 int i, j;
1863 static int command_tables_inited = 0;
1864
1865 /* Fill 'command_to_handler' lookup table */
1866 if (!command_tables_inited) {
1867 command_tables_inited = 1;
1868 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1869 for (j = 0; j < sizeof(command_to_handler); j++) {
1870 if ((j & handlers[i].mask) == handlers[i].value) {
1871 command_to_handler[j] = i;
1872 }
1873 }
1874 }
1875 }
1876
1877 FLOPPY_DPRINTF("init controller\n");
1878 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1879 fdctrl->fifo_size = 512;
1880 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1881 fdctrl_result_timer, fdctrl);
1882
1883 fdctrl->version = 0x90; /* Intel 82078 controller */
1884 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1885 fdctrl->num_floppies = MAX_FD;
1886
1887 if (fdctrl->dma_chann != -1)
1888 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1889 return fdctrl_connect_drives(fdctrl);
1890 }
1891
1892 static int isabus_fdc_init1(ISADevice *dev)
1893 {
1894 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1895 FDCtrl *fdctrl = &isa->state;
1896 int iobase = 0x3f0;
1897 int isairq = 6;
1898 int dma_chann = 2;
1899 int ret;
1900
1901 register_ioport_read(iobase + 0x01, 5, 1,
1902 &fdctrl_read_port, fdctrl);
1903 register_ioport_read(iobase + 0x07, 1, 1,
1904 &fdctrl_read_port, fdctrl);
1905 register_ioport_write(iobase + 0x01, 5, 1,
1906 &fdctrl_write_port, fdctrl);
1907 register_ioport_write(iobase + 0x07, 1, 1,
1908 &fdctrl_write_port, fdctrl);
1909 isa_init_ioport_range(dev, iobase, 6);
1910 isa_init_ioport(dev, iobase + 7);
1911
1912 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1913 fdctrl->dma_chann = dma_chann;
1914
1915 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1916 ret = fdctrl_init_common(fdctrl);
1917
1918 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1919 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1920
1921 return ret;
1922 }
1923
1924 static int sysbus_fdc_init1(SysBusDevice *dev)
1925 {
1926 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1927 FDCtrl *fdctrl = &sys->state;
1928 int io;
1929 int ret;
1930
1931 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
1932 DEVICE_NATIVE_ENDIAN);
1933 sysbus_init_mmio(dev, 0x08, io);
1934 sysbus_init_irq(dev, &fdctrl->irq);
1935 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1936 fdctrl->dma_chann = -1;
1937
1938 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
1939 ret = fdctrl_init_common(fdctrl);
1940
1941 return ret;
1942 }
1943
1944 static int sun4m_fdc_init1(SysBusDevice *dev)
1945 {
1946 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
1947 int io;
1948
1949 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1950 fdctrl_mem_write_strict, fdctrl,
1951 DEVICE_NATIVE_ENDIAN);
1952 sysbus_init_mmio(dev, 0x08, io);
1953 sysbus_init_irq(dev, &fdctrl->irq);
1954 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1955
1956 fdctrl->sun4m = 1;
1957 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
1958 return fdctrl_init_common(fdctrl);
1959 }
1960
1961 static const VMStateDescription vmstate_isa_fdc ={
1962 .name = "fdc",
1963 .version_id = 2,
1964 .minimum_version_id = 2,
1965 .fields = (VMStateField []) {
1966 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
1967 VMSTATE_END_OF_LIST()
1968 }
1969 };
1970
1971 static ISADeviceInfo isa_fdc_info = {
1972 .init = isabus_fdc_init1,
1973 .qdev.name = "isa-fdc",
1974 .qdev.fw_name = "fdc",
1975 .qdev.size = sizeof(FDCtrlISABus),
1976 .qdev.no_user = 1,
1977 .qdev.vmsd = &vmstate_isa_fdc,
1978 .qdev.reset = fdctrl_external_reset_isa,
1979 .qdev.props = (Property[]) {
1980 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
1981 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
1982 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
1983 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
1984 DEFINE_PROP_END_OF_LIST(),
1985 },
1986 };
1987
1988 static const VMStateDescription vmstate_sysbus_fdc ={
1989 .name = "fdc",
1990 .version_id = 2,
1991 .minimum_version_id = 2,
1992 .fields = (VMStateField []) {
1993 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
1994 VMSTATE_END_OF_LIST()
1995 }
1996 };
1997
1998 static SysBusDeviceInfo sysbus_fdc_info = {
1999 .init = sysbus_fdc_init1,
2000 .qdev.name = "sysbus-fdc",
2001 .qdev.size = sizeof(FDCtrlSysBus),
2002 .qdev.vmsd = &vmstate_sysbus_fdc,
2003 .qdev.reset = fdctrl_external_reset_sysbus,
2004 .qdev.props = (Property[]) {
2005 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2006 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2007 DEFINE_PROP_END_OF_LIST(),
2008 },
2009 };
2010
2011 static SysBusDeviceInfo sun4m_fdc_info = {
2012 .init = sun4m_fdc_init1,
2013 .qdev.name = "SUNW,fdtwo",
2014 .qdev.size = sizeof(FDCtrlSysBus),
2015 .qdev.vmsd = &vmstate_sysbus_fdc,
2016 .qdev.reset = fdctrl_external_reset_sysbus,
2017 .qdev.props = (Property[]) {
2018 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2019 DEFINE_PROP_END_OF_LIST(),
2020 },
2021 };
2022
2023 static void fdc_register_devices(void)
2024 {
2025 isa_qdev_register(&isa_fdc_info);
2026 sysbus_register_withprop(&sysbus_fdc_info);
2027 sysbus_register_withprop(&sun4m_fdc_info);
2028 }
2029
2030 device_init(fdc_register_devices)
QEmu