hw/parallel.c

   1 /*
   2  * QEMU Parallel PORT emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2007 Marko Kohtala
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29
  30 //#define DEBUG_PARALLEL
  31
  32 #ifdef DEBUG_PARALLEL
  33 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
  34 #else
  35 #define pdebug(fmt, ...) ((void)0)
  36 #endif
  37
  38 #define PARA_REG_DATA 0
  39 #define PARA_REG_STS 1
  40 #define PARA_REG_CTR 2
  41 #define PARA_REG_EPP_ADDR 3
  42 #define PARA_REG_EPP_DATA 4
  43
  44 /*
  45  * These are the definitions for the Printer Status Register
  46  */
  47 #define PARA_STS_BUSY   0x80    /* Busy complement */
  48 #define PARA_STS_ACK    0x40    /* Acknowledge */
  49 #define PARA_STS_PAPER  0x20    /* Out of paper */
  50 #define PARA_STS_ONLINE 0x10    /* Online */
  51 #define PARA_STS_ERROR  0x08    /* Error complement */
  52 #define PARA_STS_TMOUT  0x01    /* EPP timeout */
  53
  54 /*
  55  * These are the definitions for the Printer Control Register
  56  */
  57 #define PARA_CTR_DIR    0x20    /* Direction (1=read, 0=write) */
  58 #define PARA_CTR_INTEN  0x10    /* IRQ Enable */
  59 #define PARA_CTR_SELECT 0x08    /* Select In complement */
  60 #define PARA_CTR_INIT   0x04    /* Initialize Printer complement */
  61 #define PARA_CTR_AUTOLF 0x02    /* Auto linefeed complement */
  62 #define PARA_CTR_STROBE 0x01    /* Strobe complement */
  63
  64 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
  65
  66 struct ParallelState {
  67     uint8_t dataw;
  68     uint8_t datar;
  69     uint8_t status;
  70     uint8_t control;
  71     qemu_irq irq;
  72     int irq_pending;
  73     CharDriverState *chr;
  74     int hw_driver;
  75     int epp_timeout;
  76     uint32_t last_read_offset; /* For debugging */
  77     /* Memory-mapped interface */
  78     int it_shift;
  79 };
  80
  81 typedef struct ISAParallelState {
  82     ISADevice dev;
  83     uint32_t iobase;
  84     uint32_t isairq;
  85     ParallelState state;
  86 } ISAParallelState;
  87
  88 static void parallel_update_irq(ParallelState *s)
  89 {
  90     if (s->irq_pending)
  91         qemu_irq_raise(s->irq);
  92     else
  93         qemu_irq_lower(s->irq);
  94 }
  95
  96 static void
  97 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
  98 {
  99     ParallelState *s = opaque;
 100
 101     pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
 102
 103     addr &= 7;
 104     switch(addr) {
 105     case PARA_REG_DATA:
 106         s->dataw = val;
 107         parallel_update_irq(s);
 108         break;
 109     case PARA_REG_CTR:
 110         val |= 0xc0;
 111         if ((val & PARA_CTR_INIT) == 0 ) {
 112             s->status = PARA_STS_BUSY;
 113             s->status |= PARA_STS_ACK;
 114             s->status |= PARA_STS_ONLINE;
 115             s->status |= PARA_STS_ERROR;
 116         }
 117         else if (val & PARA_CTR_SELECT) {
 118             if (val & PARA_CTR_STROBE) {
 119                 s->status &= ~PARA_STS_BUSY;
 120                 if ((s->control & PARA_CTR_STROBE) == 0)
 121                     qemu_chr_write(s->chr, &s->dataw, 1);
 122             } else {
 123                 if (s->control & PARA_CTR_INTEN) {
 124                     s->irq_pending = 1;
 125                 }
 126             }
 127         }
 128         parallel_update_irq(s);
 129         s->control = val;
 130         break;
 131     }
 132 }
 133
 134 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
 135 {
 136     ParallelState *s = opaque;
 137     uint8_t parm = val;
 138     int dir;
 139
 140     /* Sometimes programs do several writes for timing purposes on old
 141        HW. Take care not to waste time on writes that do nothing. */
 142
 143     s->last_read_offset = ~0U;
 144
 145     addr &= 7;
 146     switch(addr) {
 147     case PARA_REG_DATA:
 148         if (s->dataw == val)
 149             return;
 150         pdebug("wd%02x\n", val);
 151         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
 152         s->dataw = val;
 153         break;
 154     case PARA_REG_STS:
 155         pdebug("ws%02x\n", val);
 156         if (val & PARA_STS_TMOUT)
 157             s->epp_timeout = 0;
 158         break;
 159     case PARA_REG_CTR:
 160         val |= 0xc0;
 161         if (s->control == val)
 162             return;
 163         pdebug("wc%02x\n", val);
 164
 165         if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
 166             if (val & PARA_CTR_DIR) {
 167                 dir = 1;
 168             } else {
 169                 dir = 0;
 170             }
 171             qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
 172             parm &= ~PARA_CTR_DIR;
 173         }
 174
 175         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
 176         s->control = val;
 177         break;
 178     case PARA_REG_EPP_ADDR:
 179         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 180             /* Controls not correct for EPP address cycle, so do nothing */
 181             pdebug("wa%02x s\n", val);
 182         else {
 183             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 184             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
 185                 s->epp_timeout = 1;
 186                 pdebug("wa%02x t\n", val);
 187             }
 188             else
 189                 pdebug("wa%02x\n", val);
 190         }
 191         break;
 192     case PARA_REG_EPP_DATA:
 193         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 194             /* Controls not correct for EPP data cycle, so do nothing */
 195             pdebug("we%02x s\n", val);
 196         else {
 197             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 198             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
 199                 s->epp_timeout = 1;
 200                 pdebug("we%02x t\n", val);
 201             }
 202             else
 203                 pdebug("we%02x\n", val);
 204         }
 205         break;
 206     }
 207 }
 208
 209 static void
 210 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
 211 {
 212     ParallelState *s = opaque;
 213     uint16_t eppdata = cpu_to_le16(val);
 214     int err;
 215     struct ParallelIOArg ioarg = {
 216         .buffer = &eppdata, .count = sizeof(eppdata)
 217     };
 218     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 219         /* Controls not correct for EPP data cycle, so do nothing */
 220         pdebug("we%04x s\n", val);
 221         return;
 222     }
 223     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 224     if (err) {
 225         s->epp_timeout = 1;
 226         pdebug("we%04x t\n", val);
 227     }
 228     else
 229         pdebug("we%04x\n", val);
 230 }
 231
 232 static void
 233 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
 234 {
 235     ParallelState *s = opaque;
 236     uint32_t eppdata = cpu_to_le32(val);
 237     int err;
 238     struct ParallelIOArg ioarg = {
 239         .buffer = &eppdata, .count = sizeof(eppdata)
 240     };
 241     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 242         /* Controls not correct for EPP data cycle, so do nothing */
 243         pdebug("we%08x s\n", val);
 244         return;
 245     }
 246     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 247     if (err) {
 248         s->epp_timeout = 1;
 249         pdebug("we%08x t\n", val);
 250     }
 251     else
 252         pdebug("we%08x\n", val);
 253 }
 254
 255 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
 256 {
 257     ParallelState *s = opaque;
 258     uint32_t ret = 0xff;
 259
 260     addr &= 7;
 261     switch(addr) {
 262     case PARA_REG_DATA:
 263         if (s->control & PARA_CTR_DIR)
 264             ret = s->datar;
 265         else
 266             ret = s->dataw;
 267         break;
 268     case PARA_REG_STS:
 269         ret = s->status;
 270         s->irq_pending = 0;
 271         if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
 272             /* XXX Fixme: wait 5 microseconds */
 273             if (s->status & PARA_STS_ACK)
 274                 s->status &= ~PARA_STS_ACK;
 275             else {
 276                 /* XXX Fixme: wait 5 microseconds */
 277                 s->status |= PARA_STS_ACK;
 278                 s->status |= PARA_STS_BUSY;
 279             }
 280         }
 281         parallel_update_irq(s);
 282         break;
 283     case PARA_REG_CTR:
 284         ret = s->control;
 285         break;
 286     }
 287     pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
 288     return ret;
 289 }
 290
 291 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
 292 {
 293     ParallelState *s = opaque;
 294     uint8_t ret = 0xff;
 295     addr &= 7;
 296     switch(addr) {
 297     case PARA_REG_DATA:
 298         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
 299         if (s->last_read_offset != addr || s->datar != ret)
 300             pdebug("rd%02x\n", ret);
 301         s->datar = ret;
 302         break;
 303     case PARA_REG_STS:
 304         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
 305         ret &= ~PARA_STS_TMOUT;
 306         if (s->epp_timeout)
 307             ret |= PARA_STS_TMOUT;
 308         if (s->last_read_offset != addr || s->status != ret)
 309             pdebug("rs%02x\n", ret);
 310         s->status = ret;
 311         break;
 312     case PARA_REG_CTR:
 313         /* s->control has some bits fixed to 1. It is zero only when
 314            it has not been yet written to.  */
 315         if (s->control == 0) {
 316             qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
 317             if (s->last_read_offset != addr)
 318                 pdebug("rc%02x\n", ret);
 319             s->control = ret;
 320         }
 321         else {
 322             ret = s->control;
 323             if (s->last_read_offset != addr)
 324                 pdebug("rc%02x\n", ret);
 325         }
 326         break;
 327     case PARA_REG_EPP_ADDR:
 328         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
 329             /* Controls not correct for EPP addr cycle, so do nothing */
 330             pdebug("ra%02x s\n", ret);
 331         else {
 332             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 333             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
 334                 s->epp_timeout = 1;
 335                 pdebug("ra%02x t\n", ret);
 336             }
 337             else
 338                 pdebug("ra%02x\n", ret);
 339         }
 340         break;
 341     case PARA_REG_EPP_DATA:
 342         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
 343             /* Controls not correct for EPP data cycle, so do nothing */
 344             pdebug("re%02x s\n", ret);
 345         else {
 346             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 347             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
 348                 s->epp_timeout = 1;
 349                 pdebug("re%02x t\n", ret);
 350             }
 351             else
 352                 pdebug("re%02x\n", ret);
 353         }
 354         break;
 355     }
 356     s->last_read_offset = addr;
 357     return ret;
 358 }
 359
 360 static uint32_t
 361 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
 362 {
 363     ParallelState *s = opaque;
 364     uint32_t ret;
 365     uint16_t eppdata = ~0;
 366     int err;
 367     struct ParallelIOArg ioarg = {
 368         .buffer = &eppdata, .count = sizeof(eppdata)
 369     };
 370     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 371         /* Controls not correct for EPP data cycle, so do nothing */
 372         pdebug("re%04x s\n", eppdata);
 373         return eppdata;
 374     }
 375     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 376     ret = le16_to_cpu(eppdata);
 377
 378     if (err) {
 379         s->epp_timeout = 1;
 380         pdebug("re%04x t\n", ret);
 381     }
 382     else
 383         pdebug("re%04x\n", ret);
 384     return ret;
 385 }
 386
 387 static uint32_t
 388 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
 389 {
 390     ParallelState *s = opaque;
 391     uint32_t ret;
 392     uint32_t eppdata = ~0U;
 393     int err;
 394     struct ParallelIOArg ioarg = {
 395         .buffer = &eppdata, .count = sizeof(eppdata)
 396     };
 397     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 398         /* Controls not correct for EPP data cycle, so do nothing */
 399         pdebug("re%08x s\n", eppdata);
 400         return eppdata;
 401     }
 402     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 403     ret = le32_to_cpu(eppdata);
 404
 405     if (err) {
 406         s->epp_timeout = 1;
 407         pdebug("re%08x t\n", ret);
 408     }
 409     else
 410         pdebug("re%08x\n", ret);
 411     return ret;
 412 }
 413
 414 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
 415 {
 416     addr &= 7;
 417     pdebug("wecp%d=%02x\n", addr, val);
 418 }
 419
 420 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
 421 {
 422     uint8_t ret = 0xff;
 423     addr &= 7;
 424     pdebug("recp%d:%02x\n", addr, ret);
 425     return ret;
 426 }
 427
 428 static void parallel_reset(void *opaque)
 429 {
 430     ParallelState *s = opaque;
 431
 432     s->datar = ~0;
 433     s->dataw = ~0;
 434     s->status = PARA_STS_BUSY;
 435     s->status |= PARA_STS_ACK;
 436     s->status |= PARA_STS_ONLINE;
 437     s->status |= PARA_STS_ERROR;
 438     s->status |= PARA_STS_TMOUT;
 439     s->control = PARA_CTR_SELECT;
 440     s->control |= PARA_CTR_INIT;
 441     s->control |= 0xc0;
 442     s->irq_pending = 0;
 443     s->hw_driver = 0;
 444     s->epp_timeout = 0;
 445     s->last_read_offset = ~0U;
 446 }
 447
 448 static int parallel_isa_initfn(ISADevice *dev)
 449 {
 450     ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
 451     ParallelState *s = &isa->state;
 452     int base = isa->iobase;
 453     uint8_t dummy;
 454
 455     if (!s->chr) {
 456         fprintf(stderr, "Can't create parallel device, empty char device\n");
 457         exit(1);
 458     }
 459
 460     isa_init_irq(dev, &s->irq, isa->isairq);
 461     parallel_reset(s);
 462     qemu_register_reset(parallel_reset, s);
 463
 464     if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
 465         s->hw_driver = 1;
 466         s->status = dummy;
 467     }
 468
 469     if (s->hw_driver) {
 470         register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
 471         register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
 472         register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
 473         register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
 474         register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
 475         register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
 476         register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
 477         register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
 478     }
 479     else {
 480         register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
 481         register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
 482     }
 483     return 0;
 484 }
 485
 486 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 487
 488 ParallelState *parallel_init(int index, CharDriverState *chr)
 489 {
 490     ISADevice *dev;
 491
 492     dev = isa_create("isa-parallel");
 493     qdev_prop_set_uint32(&dev->qdev, "iobase", isa_parallel_io[index]);
 494     qdev_prop_set_uint32(&dev->qdev, "irq", 7);
 495     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
 496     if (qdev_init(&dev->qdev) < 0)
 497         return NULL;
 498     return &DO_UPCAST(ISAParallelState, dev, dev)->state;
 499 }
 500
 501 /* Memory mapped interface */
 502 static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
 503 {
 504     ParallelState *s = opaque;
 505
 506     return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
 507 }
 508
 509 static void parallel_mm_writeb (void *opaque,
 510                                 target_phys_addr_t addr, uint32_t value)
 511 {
 512     ParallelState *s = opaque;
 513
 514     parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
 515 }
 516
 517 static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
 518 {
 519     ParallelState *s = opaque;
 520
 521     return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
 522 }
 523
 524 static void parallel_mm_writew (void *opaque,
 525                                 target_phys_addr_t addr, uint32_t value)
 526 {
 527     ParallelState *s = opaque;
 528
 529     parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
 530 }
 531
 532 static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
 533 {
 534     ParallelState *s = opaque;
 535
 536     return parallel_ioport_read_sw(s, addr >> s->it_shift);
 537 }
 538
 539 static void parallel_mm_writel (void *opaque,
 540                                 target_phys_addr_t addr, uint32_t value)
 541 {
 542     ParallelState *s = opaque;
 543
 544     parallel_ioport_write_sw(s, addr >> s->it_shift, value);
 545 }
 546
 547 static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
 548     &parallel_mm_readb,
 549     &parallel_mm_readw,
 550     &parallel_mm_readl,
 551 };
 552
 553 static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
 554     &parallel_mm_writeb,
 555     &parallel_mm_writew,
 556     &parallel_mm_writel,
 557 };
 558
 559 /* If fd is zero, it means that the parallel device uses the console */
 560 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
 561 {
 562     ParallelState *s;
 563     int io_sw;
 564
 565     s = qemu_mallocz(sizeof(ParallelState));
 566     s->irq = irq;
 567     s->chr = chr;
 568     s->it_shift = it_shift;
 569     parallel_reset(s);
 570     qemu_register_reset(parallel_reset, s);
 571
 572     io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
 573     cpu_register_physical_memory(base, 8 << it_shift, io_sw);
 574     return s;
 575 }
 576
 577 static ISADeviceInfo parallel_isa_info = {
 578     .qdev.name  = "isa-parallel",
 579     .qdev.size  = sizeof(ISAParallelState),
 580     .init       = parallel_isa_initfn,
 581     .qdev.props = (Property[]) {
 582         DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase,  0x378),
 583         DEFINE_PROP_UINT32("irq",   ISAParallelState, isairq,  7),
 584         DEFINE_PROP_CHR("chardev",  ISAParallelState, state.chr),
 585         DEFINE_PROP_END_OF_LIST(),
 586     },
 587 };
 588
 589 static void parallel_register_devices(void)
 590 {
 591     isa_qdev_register(&parallel_isa_info);
 592 }
 593
 594 device_init(parallel_register_devices)