hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu-common.h"
  23 #include "cpu.h"
  24 #include "hw/i386/apic.h"
  25 #include "hw/i386/apic_internal.h"
  26 #include "trace.h"
  27 #include "sysemu/kvm.h"
  28 #include "hw/qdev.h"
  29 #include "hw/sysbus.h"
  30
  31 static int apic_irq_delivered;
  32 bool apic_report_tpr_access;
  33
  34 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
  35 {
  36     trace_cpu_set_apic_base(val);
  37
  38     if (dev) {
  39         APICCommonState *s = APIC_COMMON(dev);
  40         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  41         info->set_base(s, val);
  42     }
  43 }
  44
  45 uint64_t cpu_get_apic_base(DeviceState *dev)
  46 {
  47     if (dev) {
  48         APICCommonState *s = APIC_COMMON(dev);
  49         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  50         return s->apicbase;
  51     } else {
  52         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  53         return MSR_IA32_APICBASE_BSP;
  54     }
  55 }
  56
  57 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  58 {
  59     APICCommonState *s;
  60     APICCommonClass *info;
  61
  62     if (!dev) {
  63         return;
  64     }
  65
  66     s = APIC_COMMON(dev);
  67     info = APIC_COMMON_GET_CLASS(s);
  68
  69     info->set_tpr(s, val);
  70 }
  71
  72 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  73 {
  74     APICCommonState *s;
  75     APICCommonClass *info;
  76
  77     if (!dev) {
  78         return 0;
  79     }
  80
  81     s = APIC_COMMON(dev);
  82     info = APIC_COMMON_GET_CLASS(s);
  83
  84     return info->get_tpr(s);
  85 }
  86
  87 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
  88 {
  89     APICCommonState *s = APIC_COMMON(dev);
  90     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  91
  92     apic_report_tpr_access = enable;
  93     if (info->enable_tpr_reporting) {
  94         info->enable_tpr_reporting(s, enable);
  95     }
  96 }
  97
  98 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
  99 {
 100     APICCommonState *s = APIC_COMMON(dev);
 101     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 102
 103     s->vapic_paddr = paddr;
 104     info->vapic_base_update(s);
 105 }
 106
 107 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 108                                    TPRAccess access)
 109 {
 110     APICCommonState *s = APIC_COMMON(dev);
 111
 112     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 113 }
 114
 115 void apic_report_irq_delivered(int delivered)
 116 {
 117     apic_irq_delivered += delivered;
 118
 119     trace_apic_report_irq_delivered(apic_irq_delivered);
 120 }
 121
 122 void apic_reset_irq_delivered(void)
 123 {
 124     /* Copy this into a local variable to encourage gcc to emit a plain
 125      * register for a sys/sdt.h marker.  For details on this workaround, see:
 126      * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
 127      */
 128     volatile int a_i_d = apic_irq_delivered;
 129     trace_apic_reset_irq_delivered(a_i_d);
 130
 131     apic_irq_delivered = 0;
 132 }
 133
 134 int apic_get_irq_delivered(void)
 135 {
 136     trace_apic_get_irq_delivered(apic_irq_delivered);
 137
 138     return apic_irq_delivered;
 139 }
 140
 141 void apic_deliver_nmi(DeviceState *dev)
 142 {
 143     APICCommonState *s = APIC_COMMON(dev);
 144     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 145
 146     info->external_nmi(s);
 147 }
 148
 149 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 150 {
 151     int64_t d;
 152
 153     /* We need to store the timer state separately to support APIC
 154      * implementations that maintain a non-QEMU timer, e.g. inside the
 155      * host kernel. This open-coded state allows us to migrate between
 156      * both models. */
 157     s->timer_expiry = -1;
 158
 159     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 160         return false;
 161     }
 162
 163     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 164
 165     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 166         if (!s->initial_count) {
 167             return false;
 168         }
 169         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 170             ((uint64_t)s->initial_count + 1);
 171     } else {
 172         if (d >= s->initial_count) {
 173             return false;
 174         }
 175         d = (uint64_t)s->initial_count + 1;
 176     }
 177     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 178     s->timer_expiry = s->next_time;
 179     return true;
 180 }
 181
 182 void apic_init_reset(DeviceState *dev)
 183 {
 184     APICCommonState *s;
 185     APICCommonClass *info;
 186     int i;
 187
 188     if (!dev) {
 189         return;
 190     }
 191     s = APIC_COMMON(dev);
 192     s->tpr = 0;
 193     s->spurious_vec = 0xff;
 194     s->log_dest = 0;
 195     s->dest_mode = 0xf;
 196     memset(s->isr, 0, sizeof(s->isr));
 197     memset(s->tmr, 0, sizeof(s->tmr));
 198     memset(s->irr, 0, sizeof(s->irr));
 199     for (i = 0; i < APIC_LVT_NB; i++) {
 200         s->lvt[i] = APIC_LVT_MASKED;
 201     }
 202     s->esr = 0;
 203     memset(s->icr, 0, sizeof(s->icr));
 204     s->divide_conf = 0;
 205     s->count_shift = 0;
 206     s->initial_count = 0;
 207     s->initial_count_load_time = 0;
 208     s->next_time = 0;
 209     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 210
 211     if (s->timer) {
 212         timer_del(s->timer);
 213     }
 214     s->timer_expiry = -1;
 215
 216     info = APIC_COMMON_GET_CLASS(s);
 217     if (info->reset) {
 218         info->reset(s);
 219     }
 220 }
 221
 222 void apic_designate_bsp(DeviceState *dev, bool bsp)
 223 {
 224     if (dev == NULL) {
 225         return;
 226     }
 227
 228     APICCommonState *s = APIC_COMMON(dev);
 229     if (bsp) {
 230         s->apicbase |= MSR_IA32_APICBASE_BSP;
 231     } else {
 232         s->apicbase &= ~MSR_IA32_APICBASE_BSP;
 233     }
 234 }
 235
 236 static void apic_reset_common(DeviceState *dev)
 237 {
 238     APICCommonState *s = APIC_COMMON(dev);
 239     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 240     uint32_t bsp;
 241
 242     bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
 243     s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
 244
 245     s->vapic_paddr = 0;
 246     info->vapic_base_update(s);
 247
 248     apic_init_reset(dev);
 249 }
 250
 251 /* This function is only used for old state version 1 and 2 */
 252 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 253 {
 254     APICCommonState *s = opaque;
 255     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 256     int i;
 257
 258     if (version_id > 2) {
 259         return -EINVAL;
 260     }
 261
 262     /* XXX: what if the base changes? (registered memory regions) */
 263     qemu_get_be32s(f, &s->apicbase);
 264     qemu_get_8s(f, &s->id);
 265     qemu_get_8s(f, &s->arb_id);
 266     qemu_get_8s(f, &s->tpr);
 267     qemu_get_be32s(f, &s->spurious_vec);
 268     qemu_get_8s(f, &s->log_dest);
 269     qemu_get_8s(f, &s->dest_mode);
 270     for (i = 0; i < 8; i++) {
 271         qemu_get_be32s(f, &s->isr[i]);
 272         qemu_get_be32s(f, &s->tmr[i]);
 273         qemu_get_be32s(f, &s->irr[i]);
 274     }
 275     for (i = 0; i < APIC_LVT_NB; i++) {
 276         qemu_get_be32s(f, &s->lvt[i]);
 277     }
 278     qemu_get_be32s(f, &s->esr);
 279     qemu_get_be32s(f, &s->icr[0]);
 280     qemu_get_be32s(f, &s->icr[1]);
 281     qemu_get_be32s(f, &s->divide_conf);
 282     s->count_shift = qemu_get_be32(f);
 283     qemu_get_be32s(f, &s->initial_count);
 284     s->initial_count_load_time = qemu_get_be64(f);
 285     s->next_time = qemu_get_be64(f);
 286
 287     if (version_id >= 2) {
 288         s->timer_expiry = qemu_get_be64(f);
 289     }
 290
 291     if (info->post_load) {
 292         info->post_load(s);
 293     }
 294     return 0;
 295 }
 296
 297 static void apic_common_realize(DeviceState *dev, Error **errp)
 298 {
 299     APICCommonState *s = APIC_COMMON(dev);
 300     APICCommonClass *info;
 301     static DeviceState *vapic;
 302     static int apic_no;
 303
 304     if (apic_no >= MAX_APICS) {
 305         error_setg(errp, "%s initialization failed.",
 306                    object_get_typename(OBJECT(dev)));
 307         return;
 308     }
 309     s->idx = apic_no++;
 310
 311     info = APIC_COMMON_GET_CLASS(s);
 312     info->realize(dev, errp);
 313
 314     /* Note: We need at least 1M to map the VAPIC option ROM */
 315     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 316         ram_size >= 1024 * 1024) {
 317         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 318     }
 319     s->vapic = vapic;
 320     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 321         info->enable_tpr_reporting(s, true);
 322     }
 323
 324 }
 325
 326 static int apic_pre_load(void *opaque)
 327 {
 328     APICCommonState *s = APIC_COMMON(opaque);
 329
 330     /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
 331      * so that's what apic_common_sipi_needed checks for.  Reset to
 332      * the value that is assumed when the apic_sipi subsection is
 333      * absent.
 334      */
 335     s->wait_for_sipi = 0;
 336     return 0;
 337 }
 338
 339 static void apic_dispatch_pre_save(void *opaque)
 340 {
 341     APICCommonState *s = APIC_COMMON(opaque);
 342     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 343
 344     if (info->pre_save) {
 345         info->pre_save(s);
 346     }
 347 }
 348
 349 static int apic_dispatch_post_load(void *opaque, int version_id)
 350 {
 351     APICCommonState *s = APIC_COMMON(opaque);
 352     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 353
 354     if (info->post_load) {
 355         info->post_load(s);
 356     }
 357     return 0;
 358 }
 359
 360 static bool apic_common_sipi_needed(void *opaque)
 361 {
 362     APICCommonState *s = APIC_COMMON(opaque);
 363     return s->wait_for_sipi != 0;
 364 }
 365
 366 static const VMStateDescription vmstate_apic_common_sipi = {
 367     .name = "apic_sipi",
 368     .version_id = 1,
 369     .minimum_version_id = 1,
 370     .needed = apic_common_sipi_needed,
 371     .fields = (VMStateField[]) {
 372         VMSTATE_INT32(sipi_vector, APICCommonState),
 373         VMSTATE_INT32(wait_for_sipi, APICCommonState),
 374         VMSTATE_END_OF_LIST()
 375     }
 376 };
 377
 378 static const VMStateDescription vmstate_apic_common = {
 379     .name = "apic",
 380     .version_id = 3,
 381     .minimum_version_id = 3,
 382     .minimum_version_id_old = 1,
 383     .load_state_old = apic_load_old,
 384     .pre_load = apic_pre_load,
 385     .pre_save = apic_dispatch_pre_save,
 386     .post_load = apic_dispatch_post_load,
 387     .fields = (VMStateField[]) {
 388         VMSTATE_UINT32(apicbase, APICCommonState),
 389         VMSTATE_UINT8(id, APICCommonState),
 390         VMSTATE_UINT8(arb_id, APICCommonState),
 391         VMSTATE_UINT8(tpr, APICCommonState),
 392         VMSTATE_UINT32(spurious_vec, APICCommonState),
 393         VMSTATE_UINT8(log_dest, APICCommonState),
 394         VMSTATE_UINT8(dest_mode, APICCommonState),
 395         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 396         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 397         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 398         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 399         VMSTATE_UINT32(esr, APICCommonState),
 400         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 401         VMSTATE_UINT32(divide_conf, APICCommonState),
 402         VMSTATE_INT32(count_shift, APICCommonState),
 403         VMSTATE_UINT32(initial_count, APICCommonState),
 404         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 405         VMSTATE_INT64(next_time, APICCommonState),
 406         VMSTATE_INT64(timer_expiry,
 407                       APICCommonState), /* open-coded timer state */
 408         VMSTATE_END_OF_LIST()
 409     },
 410     .subsections = (const VMStateDescription*[]) {
 411         &vmstate_apic_common_sipi,
 412         NULL
 413     }
 414 };
 415
 416 static Property apic_properties_common[] = {
 417     DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
 418     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 419     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 420                     true),
 421     DEFINE_PROP_END_OF_LIST(),
 422 };
 423
 424 static void apic_common_class_init(ObjectClass *klass, void *data)
 425 {
 426     DeviceClass *dc = DEVICE_CLASS(klass);
 427
 428     dc->vmsd = &vmstate_apic_common;
 429     dc->reset = apic_reset_common;
 430     dc->props = apic_properties_common;
 431     dc->realize = apic_common_realize;
 432     /*
 433      * Reason: APIC and CPU need to be wired up by
 434      * x86_cpu_apic_create()
 435      */
 436     dc->cannot_instantiate_with_device_add_yet = true;
 437 }
 438
 439 static const TypeInfo apic_common_type = {
 440     .name = TYPE_APIC_COMMON,
 441     .parent = TYPE_DEVICE,
 442     .instance_size = sizeof(APICCommonState),
 443     .class_size = sizeof(APICCommonClass),
 444     .class_init = apic_common_class_init,
 445     .abstract = true,
 446 };
 447
 448 static void apic_common_register_types(void)
 449 {
 450     type_register_static(&apic_common_type);
 451 }
 452
 453 type_init(apic_common_register_types)