2 * Cortex-A9MPCore internal peripheral emulation.
4 * Copyright (c) 2009 CodeSourcery.
5 * Copyright (c) 2011 Linaro Limited.
6 * Written by Paul Brook, Peter Maydell.
8 * This code is licensed under the GPL.
13 /* A9MP private memory region. */
15 typedef struct A9MPPrivState
{
19 uint32_t old_timer_status
[8];
21 MemoryRegion scu_iomem
;
22 MemoryRegion container
;
28 static uint64_t a9_scu_read(void *opaque
, hwaddr offset
,
31 A9MPPrivState
*s
= (A9MPPrivState
*)opaque
;
33 case 0x00: /* Control */
34 return s
->scu_control
;
35 case 0x04: /* Configuration */
36 return (((1 << s
->num_cpu
) - 1) << 4) | (s
->num_cpu
- 1);
37 case 0x08: /* CPU Power Status */
39 case 0x09: /* CPU status. */
40 return s
->scu_status
>> 8;
41 case 0x0a: /* CPU status. */
42 return s
->scu_status
>> 16;
43 case 0x0b: /* CPU status. */
44 return s
->scu_status
>> 24;
45 case 0x0c: /* Invalidate All Registers In Secure State */
47 case 0x40: /* Filtering Start Address Register */
48 case 0x44: /* Filtering End Address Register */
49 /* RAZ/WI, like an implementation with only one AXI master */
51 case 0x50: /* SCU Access Control Register */
52 case 0x54: /* SCU Non-secure Access Control Register */
53 /* unimplemented, fall through */
59 static void a9_scu_write(void *opaque
, hwaddr offset
,
60 uint64_t value
, unsigned size
)
62 A9MPPrivState
*s
= (A9MPPrivState
*)opaque
;
76 fprintf(stderr
, "Invalid size %u in write to a9 scu register %x\n",
77 size
, (unsigned)offset
);
82 case 0x00: /* Control */
83 s
->scu_control
= value
& 1;
85 case 0x4: /* Configuration: RO */
87 case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
88 shift
= (offset
- 0x8) * 8;
89 s
->scu_status
&= ~(mask
<< shift
);
90 s
->scu_status
|= ((value
& mask
) << shift
);
92 case 0x0c: /* Invalidate All Registers In Secure State */
93 /* no-op as we do not implement caches */
95 case 0x40: /* Filtering Start Address Register */
96 case 0x44: /* Filtering End Address Register */
97 /* RAZ/WI, like an implementation with only one AXI master */
99 case 0x50: /* SCU Access Control Register */
100 case 0x54: /* SCU Non-secure Access Control Register */
101 /* unimplemented, fall through */
107 static const MemoryRegionOps a9_scu_ops
= {
109 .write
= a9_scu_write
,
110 .endianness
= DEVICE_NATIVE_ENDIAN
,
113 static void a9mp_priv_reset(DeviceState
*dev
)
115 A9MPPrivState
*s
= FROM_SYSBUS(A9MPPrivState
, SYS_BUS_DEVICE(dev
));
118 for (i
= 0; i
< ARRAY_SIZE(s
->old_timer_status
); i
++) {
119 s
->old_timer_status
[i
] = 0;
123 static void a9mp_priv_set_irq(void *opaque
, int irq
, int level
)
125 A9MPPrivState
*s
= (A9MPPrivState
*)opaque
;
126 qemu_set_irq(qdev_get_gpio_in(s
->gic
, irq
), level
);
129 static int a9mp_priv_init(SysBusDevice
*dev
)
131 A9MPPrivState
*s
= FROM_SYSBUS(A9MPPrivState
, dev
);
132 SysBusDevice
*busdev
, *gicbusdev
;
135 s
->gic
= qdev_create(NULL
, "arm_gic");
136 qdev_prop_set_uint32(s
->gic
, "num-cpu", s
->num_cpu
);
137 qdev_prop_set_uint32(s
->gic
, "num-irq", s
->num_irq
);
138 qdev_init_nofail(s
->gic
);
139 gicbusdev
= SYS_BUS_DEVICE(s
->gic
);
141 /* Pass through outbound IRQ lines from the GIC */
142 sysbus_pass_irq(dev
, gicbusdev
);
144 /* Pass through inbound GPIO lines to the GIC */
145 qdev_init_gpio_in(&s
->busdev
.qdev
, a9mp_priv_set_irq
, s
->num_irq
- 32);
147 s
->mptimer
= qdev_create(NULL
, "arm_mptimer");
148 qdev_prop_set_uint32(s
->mptimer
, "num-cpu", s
->num_cpu
);
149 qdev_init_nofail(s
->mptimer
);
150 busdev
= SYS_BUS_DEVICE(s
->mptimer
);
152 /* Memory map (addresses are offsets from PERIPHBASE):
153 * 0x0000-0x00ff -- Snoop Control Unit
154 * 0x0100-0x01ff -- GIC CPU interface
155 * 0x0200-0x02ff -- Global Timer
156 * 0x0300-0x05ff -- nothing
157 * 0x0600-0x06ff -- private timers and watchdogs
158 * 0x0700-0x0fff -- nothing
159 * 0x1000-0x1fff -- GIC Distributor
161 * We should implement the global timer but don't currently do so.
163 memory_region_init(&s
->container
, "a9mp-priv-container", 0x2000);
164 memory_region_init_io(&s
->scu_iomem
, &a9_scu_ops
, s
, "a9mp-scu", 0x100);
165 memory_region_add_subregion(&s
->container
, 0, &s
->scu_iomem
);
166 /* GIC CPU interface */
167 memory_region_add_subregion(&s
->container
, 0x100,
168 sysbus_mmio_get_region(gicbusdev
, 1));
169 /* Note that the A9 exposes only the "timer/watchdog for this core"
170 * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
172 memory_region_add_subregion(&s
->container
, 0x600,
173 sysbus_mmio_get_region(busdev
, 0));
174 memory_region_add_subregion(&s
->container
, 0x620,
175 sysbus_mmio_get_region(busdev
, 1));
176 memory_region_add_subregion(&s
->container
, 0x1000,
177 sysbus_mmio_get_region(gicbusdev
, 0));
179 sysbus_init_mmio(dev
, &s
->container
);
181 /* Wire up the interrupt from each watchdog and timer.
182 * For each core the timer is PPI 29 and the watchdog PPI 30.
184 for (i
= 0; i
< s
->num_cpu
; i
++) {
185 int ppibase
= (s
->num_irq
- 32) + i
* 32;
186 sysbus_connect_irq(busdev
, i
* 2,
187 qdev_get_gpio_in(s
->gic
, ppibase
+ 29));
188 sysbus_connect_irq(busdev
, i
* 2 + 1,
189 qdev_get_gpio_in(s
->gic
, ppibase
+ 30));
194 static const VMStateDescription vmstate_a9mp_priv
= {
195 .name
= "a9mpcore_priv",
197 .minimum_version_id
= 1,
198 .fields
= (VMStateField
[]) {
199 VMSTATE_UINT32(scu_control
, A9MPPrivState
),
200 VMSTATE_UINT32_ARRAY(old_timer_status
, A9MPPrivState
, 8),
201 VMSTATE_UINT32_V(scu_status
, A9MPPrivState
, 2),
202 VMSTATE_END_OF_LIST()
206 static Property a9mp_priv_properties
[] = {
207 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState
, num_cpu
, 1),
208 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
209 * IRQ lines (with another 32 internal). We default to 64+32, which
210 * is the number provided by the Cortex-A9MP test chip in the
211 * Realview PBX-A9 and Versatile Express A9 development boards.
212 * Other boards may differ and should set this property appropriately.
214 DEFINE_PROP_UINT32("num-irq", A9MPPrivState
, num_irq
, 96),
215 DEFINE_PROP_END_OF_LIST(),
218 static void a9mp_priv_class_init(ObjectClass
*klass
, void *data
)
220 DeviceClass
*dc
= DEVICE_CLASS(klass
);
221 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
223 k
->init
= a9mp_priv_init
;
224 dc
->props
= a9mp_priv_properties
;
225 dc
->vmsd
= &vmstate_a9mp_priv
;
226 dc
->reset
= a9mp_priv_reset
;
229 static const TypeInfo a9mp_priv_info
= {
230 .name
= "a9mpcore_priv",
231 .parent
= TYPE_SYS_BUS_DEVICE
,
232 .instance_size
= sizeof(A9MPPrivState
),
233 .class_init
= a9mp_priv_class_init
,
236 static void a9mp_register_types(void)
238 type_register_static(&a9mp_priv_info
);
241 type_init(a9mp_register_types
)