4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
37 #define ENABLE_ARCH_5J 0
38 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
43 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
45 /* internal defines */
46 typedef struct DisasContext
{
49 /* Nonzero if this instruction has been conditionally skipped. */
51 /* The label that will be jumped to when the instruction is skipped. */
53 /* Thumb-2 condtional execution bits. */
56 struct TranslationBlock
*tb
;
57 int singlestep_enabled
;
59 #if !defined(CONFIG_USER_ONLY)
64 #if defined(CONFIG_USER_ONLY)
67 #define IS_USER(s) (s->user)
70 /* These instructions trap after executing, so defer them until after the
71 conditional executions state has been updated. */
75 static TCGv_ptr cpu_env
;
76 /* We reuse the same 64-bit temporaries for efficiency. */
77 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
78 static TCGv_i32 cpu_R
[16];
80 /* FIXME: These should be removed. */
81 static TCGv cpu_F0s
, cpu_F1s
;
82 static TCGv_i64 cpu_F0d
, cpu_F1d
;
84 #include "gen-icount.h"
86 static const char *regnames
[] =
87 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
88 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
90 /* initialize TCG globals. */
91 void arm_translate_init(void)
95 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
97 for (i
= 0; i
< 16; i
++) {
98 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
99 offsetof(CPUState
, regs
[i
]),
107 static int num_temps
;
109 /* Allocate a temporary variable. */
110 static TCGv_i32
new_tmp(void)
113 return tcg_temp_new_i32();
116 /* Release a temporary variable. */
117 static void dead_tmp(TCGv tmp
)
123 static inline TCGv
load_cpu_offset(int offset
)
125 TCGv tmp
= new_tmp();
126 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
130 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
132 static inline void store_cpu_offset(TCGv var
, int offset
)
134 tcg_gen_st_i32(var
, cpu_env
, offset
);
138 #define store_cpu_field(var, name) \
139 store_cpu_offset(var, offsetof(CPUState, name))
141 /* Set a variable to the value of a CPU register. */
142 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
146 /* normaly, since we updated PC, we need only to add one insn */
148 addr
= (long)s
->pc
+ 2;
150 addr
= (long)s
->pc
+ 4;
151 tcg_gen_movi_i32(var
, addr
);
153 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
157 /* Create a new temporary and set it to the value of a CPU register. */
158 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
160 TCGv tmp
= new_tmp();
161 load_reg_var(s
, tmp
, reg
);
165 /* Set a CPU register. The source must be a temporary and will be
167 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
170 tcg_gen_andi_i32(var
, var
, ~1);
171 s
->is_jmp
= DISAS_JUMP
;
173 tcg_gen_mov_i32(cpu_R
[reg
], var
);
177 /* Value extensions. */
178 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
179 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
180 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
181 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
183 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
184 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
187 static inline void gen_set_cpsr(TCGv var
, uint32_t mask
)
189 TCGv tmp_mask
= tcg_const_i32(mask
);
190 gen_helper_cpsr_write(var
, tmp_mask
);
191 tcg_temp_free_i32(tmp_mask
);
193 /* Set NZCV flags from the high 4 bits of var. */
194 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
196 static void gen_exception(int excp
)
198 TCGv tmp
= new_tmp();
199 tcg_gen_movi_i32(tmp
, excp
);
200 gen_helper_exception(tmp
);
204 static void gen_smul_dual(TCGv a
, TCGv b
)
206 TCGv tmp1
= new_tmp();
207 TCGv tmp2
= new_tmp();
208 tcg_gen_ext16s_i32(tmp1
, a
);
209 tcg_gen_ext16s_i32(tmp2
, b
);
210 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
212 tcg_gen_sari_i32(a
, a
, 16);
213 tcg_gen_sari_i32(b
, b
, 16);
214 tcg_gen_mul_i32(b
, b
, a
);
215 tcg_gen_mov_i32(a
, tmp1
);
219 /* Byteswap each halfword. */
220 static void gen_rev16(TCGv var
)
222 TCGv tmp
= new_tmp();
223 tcg_gen_shri_i32(tmp
, var
, 8);
224 tcg_gen_andi_i32(tmp
, tmp
, 0x00ff00ff);
225 tcg_gen_shli_i32(var
, var
, 8);
226 tcg_gen_andi_i32(var
, var
, 0xff00ff00);
227 tcg_gen_or_i32(var
, var
, tmp
);
231 /* Byteswap low halfword and sign extend. */
232 static void gen_revsh(TCGv var
)
234 TCGv tmp
= new_tmp();
235 tcg_gen_shri_i32(tmp
, var
, 8);
236 tcg_gen_andi_i32(tmp
, tmp
, 0x00ff);
237 tcg_gen_shli_i32(var
, var
, 8);
238 tcg_gen_ext8s_i32(var
, var
);
239 tcg_gen_or_i32(var
, var
, tmp
);
243 /* Unsigned bitfield extract. */
244 static void gen_ubfx(TCGv var
, int shift
, uint32_t mask
)
247 tcg_gen_shri_i32(var
, var
, shift
);
248 tcg_gen_andi_i32(var
, var
, mask
);
251 /* Signed bitfield extract. */
252 static void gen_sbfx(TCGv var
, int shift
, int width
)
257 tcg_gen_sari_i32(var
, var
, shift
);
258 if (shift
+ width
< 32) {
259 signbit
= 1u << (width
- 1);
260 tcg_gen_andi_i32(var
, var
, (1u << width
) - 1);
261 tcg_gen_xori_i32(var
, var
, signbit
);
262 tcg_gen_subi_i32(var
, var
, signbit
);
266 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
267 static void gen_bfi(TCGv dest
, TCGv base
, TCGv val
, int shift
, uint32_t mask
)
269 tcg_gen_andi_i32(val
, val
, mask
);
270 tcg_gen_shli_i32(val
, val
, shift
);
271 tcg_gen_andi_i32(base
, base
, ~(mask
<< shift
));
272 tcg_gen_or_i32(dest
, base
, val
);
275 /* Round the top 32 bits of a 64-bit value. */
276 static void gen_roundqd(TCGv a
, TCGv b
)
278 tcg_gen_shri_i32(a
, a
, 31);
279 tcg_gen_add_i32(a
, a
, b
);
282 /* FIXME: Most targets have native widening multiplication.
283 It would be good to use that instead of a full wide multiply. */
284 /* 32x32->64 multiply. Marks inputs as dead. */
285 static TCGv_i64
gen_mulu_i64_i32(TCGv a
, TCGv b
)
287 TCGv_i64 tmp1
= tcg_temp_new_i64();
288 TCGv_i64 tmp2
= tcg_temp_new_i64();
290 tcg_gen_extu_i32_i64(tmp1
, a
);
292 tcg_gen_extu_i32_i64(tmp2
, b
);
294 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
295 tcg_temp_free_i64(tmp2
);
299 static TCGv_i64
gen_muls_i64_i32(TCGv a
, TCGv b
)
301 TCGv_i64 tmp1
= tcg_temp_new_i64();
302 TCGv_i64 tmp2
= tcg_temp_new_i64();
304 tcg_gen_ext_i32_i64(tmp1
, a
);
306 tcg_gen_ext_i32_i64(tmp2
, b
);
308 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
309 tcg_temp_free_i64(tmp2
);
313 /* Signed 32x32->64 multiply. */
314 static void gen_imull(TCGv a
, TCGv b
)
316 TCGv_i64 tmp1
= tcg_temp_new_i64();
317 TCGv_i64 tmp2
= tcg_temp_new_i64();
319 tcg_gen_ext_i32_i64(tmp1
, a
);
320 tcg_gen_ext_i32_i64(tmp2
, b
);
321 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
322 tcg_temp_free_i64(tmp2
);
323 tcg_gen_trunc_i64_i32(a
, tmp1
);
324 tcg_gen_shri_i64(tmp1
, tmp1
, 32);
325 tcg_gen_trunc_i64_i32(b
, tmp1
);
326 tcg_temp_free_i64(tmp1
);
329 /* Swap low and high halfwords. */
330 static void gen_swap_half(TCGv var
)
332 TCGv tmp
= new_tmp();
333 tcg_gen_shri_i32(tmp
, var
, 16);
334 tcg_gen_shli_i32(var
, var
, 16);
335 tcg_gen_or_i32(var
, var
, tmp
);
339 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
340 tmp = (t0 ^ t1) & 0x8000;
343 t0 = (t0 + t1) ^ tmp;
346 static void gen_add16(TCGv t0
, TCGv t1
)
348 TCGv tmp
= new_tmp();
349 tcg_gen_xor_i32(tmp
, t0
, t1
);
350 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
351 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
352 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
353 tcg_gen_add_i32(t0
, t0
, t1
);
354 tcg_gen_xor_i32(t0
, t0
, tmp
);
359 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
361 /* Set CF to the top bit of var. */
362 static void gen_set_CF_bit31(TCGv var
)
364 TCGv tmp
= new_tmp();
365 tcg_gen_shri_i32(tmp
, var
, 31);
370 /* Set N and Z flags from var. */
371 static inline void gen_logic_CC(TCGv var
)
373 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, NF
));
374 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, ZF
));
378 static void gen_adc(TCGv t0
, TCGv t1
)
381 tcg_gen_add_i32(t0
, t0
, t1
);
382 tmp
= load_cpu_field(CF
);
383 tcg_gen_add_i32(t0
, t0
, tmp
);
387 /* dest = T0 + T1 + CF. */
388 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
391 tcg_gen_add_i32(dest
, t0
, t1
);
392 tmp
= load_cpu_field(CF
);
393 tcg_gen_add_i32(dest
, dest
, tmp
);
397 /* dest = T0 - T1 + CF - 1. */
398 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
401 tcg_gen_sub_i32(dest
, t0
, t1
);
402 tmp
= load_cpu_field(CF
);
403 tcg_gen_add_i32(dest
, dest
, tmp
);
404 tcg_gen_subi_i32(dest
, dest
, 1);
408 /* T0 &= ~T1. Clobbers T1. */
409 /* FIXME: Implement bic natively. */
410 static inline void tcg_gen_bic_i32(TCGv dest
, TCGv t0
, TCGv t1
)
412 TCGv tmp
= new_tmp();
413 tcg_gen_not_i32(tmp
, t1
);
414 tcg_gen_and_i32(dest
, t0
, tmp
);
418 /* FIXME: Implement this natively. */
419 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
421 /* FIXME: Implement this natively. */
422 static void tcg_gen_rori_i32(TCGv t0
, TCGv t1
, int i
)
430 tcg_gen_shri_i32(tmp
, t1
, i
);
431 tcg_gen_shli_i32(t1
, t1
, 32 - i
);
432 tcg_gen_or_i32(t0
, t1
, tmp
);
436 static void shifter_out_im(TCGv var
, int shift
)
438 TCGv tmp
= new_tmp();
440 tcg_gen_andi_i32(tmp
, var
, 1);
442 tcg_gen_shri_i32(tmp
, var
, shift
);
444 tcg_gen_andi_i32(tmp
, tmp
, 1);
450 /* Shift by immediate. Includes special handling for shift == 0. */
451 static inline void gen_arm_shift_im(TCGv var
, int shiftop
, int shift
, int flags
)
457 shifter_out_im(var
, 32 - shift
);
458 tcg_gen_shli_i32(var
, var
, shift
);
464 tcg_gen_shri_i32(var
, var
, 31);
467 tcg_gen_movi_i32(var
, 0);
470 shifter_out_im(var
, shift
- 1);
471 tcg_gen_shri_i32(var
, var
, shift
);
478 shifter_out_im(var
, shift
- 1);
481 tcg_gen_sari_i32(var
, var
, shift
);
483 case 3: /* ROR/RRX */
486 shifter_out_im(var
, shift
- 1);
487 tcg_gen_rori_i32(var
, var
, shift
); break;
489 TCGv tmp
= load_cpu_field(CF
);
491 shifter_out_im(var
, 0);
492 tcg_gen_shri_i32(var
, var
, 1);
493 tcg_gen_shli_i32(tmp
, tmp
, 31);
494 tcg_gen_or_i32(var
, var
, tmp
);
500 static inline void gen_arm_shift_reg(TCGv var
, int shiftop
,
501 TCGv shift
, int flags
)
505 case 0: gen_helper_shl_cc(var
, var
, shift
); break;
506 case 1: gen_helper_shr_cc(var
, var
, shift
); break;
507 case 2: gen_helper_sar_cc(var
, var
, shift
); break;
508 case 3: gen_helper_ror_cc(var
, var
, shift
); break;
512 case 0: gen_helper_shl(var
, var
, shift
); break;
513 case 1: gen_helper_shr(var
, var
, shift
); break;
514 case 2: gen_helper_sar(var
, var
, shift
); break;
515 case 3: gen_helper_ror(var
, var
, shift
); break;
521 #define PAS_OP(pfx) \
523 case 0: gen_pas_helper(glue(pfx,add16)); break; \
524 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
525 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
526 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
527 case 4: gen_pas_helper(glue(pfx,add8)); break; \
528 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
530 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
535 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
537 tmp
= tcg_temp_new_ptr();
538 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
540 tcg_temp_free_ptr(tmp
);
543 tmp
= tcg_temp_new_ptr();
544 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
546 tcg_temp_free_ptr(tmp
);
548 #undef gen_pas_helper
549 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
562 #undef gen_pas_helper
567 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
568 #define PAS_OP(pfx) \
570 case 0: gen_pas_helper(glue(pfx,add8)); break; \
571 case 1: gen_pas_helper(glue(pfx,add16)); break; \
572 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
573 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
574 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
575 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
577 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
582 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
584 tmp
= tcg_temp_new_ptr();
585 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
587 tcg_temp_free_ptr(tmp
);
590 tmp
= tcg_temp_new_ptr();
591 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
593 tcg_temp_free_ptr(tmp
);
595 #undef gen_pas_helper
596 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
609 #undef gen_pas_helper
614 static void gen_test_cc(int cc
, int label
)
622 tmp
= load_cpu_field(ZF
);
623 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
626 tmp
= load_cpu_field(ZF
);
627 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
630 tmp
= load_cpu_field(CF
);
631 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
634 tmp
= load_cpu_field(CF
);
635 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
638 tmp
= load_cpu_field(NF
);
639 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
642 tmp
= load_cpu_field(NF
);
643 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
646 tmp
= load_cpu_field(VF
);
647 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
650 tmp
= load_cpu_field(VF
);
651 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
653 case 8: /* hi: C && !Z */
654 inv
= gen_new_label();
655 tmp
= load_cpu_field(CF
);
656 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
658 tmp
= load_cpu_field(ZF
);
659 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
662 case 9: /* ls: !C || Z */
663 tmp
= load_cpu_field(CF
);
664 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
666 tmp
= load_cpu_field(ZF
);
667 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
669 case 10: /* ge: N == V -> N ^ V == 0 */
670 tmp
= load_cpu_field(VF
);
671 tmp2
= load_cpu_field(NF
);
672 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
674 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
676 case 11: /* lt: N != V -> N ^ V != 0 */
677 tmp
= load_cpu_field(VF
);
678 tmp2
= load_cpu_field(NF
);
679 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
681 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
683 case 12: /* gt: !Z && N == V */
684 inv
= gen_new_label();
685 tmp
= load_cpu_field(ZF
);
686 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
688 tmp
= load_cpu_field(VF
);
689 tmp2
= load_cpu_field(NF
);
690 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
692 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
695 case 13: /* le: Z || N != V */
696 tmp
= load_cpu_field(ZF
);
697 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
699 tmp
= load_cpu_field(VF
);
700 tmp2
= load_cpu_field(NF
);
701 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
703 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
706 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
712 static const uint8_t table_logic_cc
[16] = {
731 /* Set PC and Thumb state from an immediate address. */
732 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
736 s
->is_jmp
= DISAS_UPDATE
;
737 if (s
->thumb
!= (addr
& 1)) {
739 tcg_gen_movi_i32(tmp
, addr
& 1);
740 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, thumb
));
743 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
746 /* Set PC and Thumb state from var. var is marked as dead. */
747 static inline void gen_bx(DisasContext
*s
, TCGv var
)
749 s
->is_jmp
= DISAS_UPDATE
;
750 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
751 tcg_gen_andi_i32(var
, var
, 1);
752 store_cpu_field(var
, thumb
);
755 /* Variant of store_reg which uses branch&exchange logic when storing
756 to r15 in ARM architecture v7 and above. The source must be a temporary
757 and will be marked as dead. */
758 static inline void store_reg_bx(CPUState
*env
, DisasContext
*s
,
761 if (reg
== 15 && ENABLE_ARCH_7
) {
764 store_reg(s
, reg
, var
);
768 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
770 TCGv tmp
= new_tmp();
771 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
774 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
776 TCGv tmp
= new_tmp();
777 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
780 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
782 TCGv tmp
= new_tmp();
783 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
786 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
788 TCGv tmp
= new_tmp();
789 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
792 static inline TCGv
gen_ld32(TCGv addr
, int index
)
794 TCGv tmp
= new_tmp();
795 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
798 static inline TCGv_i64
gen_ld64(TCGv addr
, int index
)
800 TCGv_i64 tmp
= tcg_temp_new_i64();
801 tcg_gen_qemu_ld64(tmp
, addr
, index
);
804 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
806 tcg_gen_qemu_st8(val
, addr
, index
);
809 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
811 tcg_gen_qemu_st16(val
, addr
, index
);
814 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
816 tcg_gen_qemu_st32(val
, addr
, index
);
819 static inline void gen_st64(TCGv_i64 val
, TCGv addr
, int index
)
821 tcg_gen_qemu_st64(val
, addr
, index
);
822 tcg_temp_free_i64(val
);
825 static inline void gen_set_pc_im(uint32_t val
)
827 tcg_gen_movi_i32(cpu_R
[15], val
);
830 /* Force a TB lookup after an instruction that changes the CPU state. */
831 static inline void gen_lookup_tb(DisasContext
*s
)
833 tcg_gen_movi_i32(cpu_R
[15], s
->pc
& ~1);
834 s
->is_jmp
= DISAS_UPDATE
;
837 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
840 int val
, rm
, shift
, shiftop
;
843 if (!(insn
& (1 << 25))) {
846 if (!(insn
& (1 << 23)))
849 tcg_gen_addi_i32(var
, var
, val
);
853 shift
= (insn
>> 7) & 0x1f;
854 shiftop
= (insn
>> 5) & 3;
855 offset
= load_reg(s
, rm
);
856 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
857 if (!(insn
& (1 << 23)))
858 tcg_gen_sub_i32(var
, var
, offset
);
860 tcg_gen_add_i32(var
, var
, offset
);
865 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
871 if (insn
& (1 << 22)) {
873 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
874 if (!(insn
& (1 << 23)))
878 tcg_gen_addi_i32(var
, var
, val
);
882 tcg_gen_addi_i32(var
, var
, extra
);
884 offset
= load_reg(s
, rm
);
885 if (!(insn
& (1 << 23)))
886 tcg_gen_sub_i32(var
, var
, offset
);
888 tcg_gen_add_i32(var
, var
, offset
);
893 #define VFP_OP2(name) \
894 static inline void gen_vfp_##name(int dp) \
897 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
899 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
909 static inline void gen_vfp_abs(int dp
)
912 gen_helper_vfp_absd(cpu_F0d
, cpu_F0d
);
914 gen_helper_vfp_abss(cpu_F0s
, cpu_F0s
);
917 static inline void gen_vfp_neg(int dp
)
920 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
922 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
925 static inline void gen_vfp_sqrt(int dp
)
928 gen_helper_vfp_sqrtd(cpu_F0d
, cpu_F0d
, cpu_env
);
930 gen_helper_vfp_sqrts(cpu_F0s
, cpu_F0s
, cpu_env
);
933 static inline void gen_vfp_cmp(int dp
)
936 gen_helper_vfp_cmpd(cpu_F0d
, cpu_F1d
, cpu_env
);
938 gen_helper_vfp_cmps(cpu_F0s
, cpu_F1s
, cpu_env
);
941 static inline void gen_vfp_cmpe(int dp
)
944 gen_helper_vfp_cmped(cpu_F0d
, cpu_F1d
, cpu_env
);
946 gen_helper_vfp_cmpes(cpu_F0s
, cpu_F1s
, cpu_env
);
949 static inline void gen_vfp_F1_ld0(int dp
)
952 tcg_gen_movi_i64(cpu_F1d
, 0);
954 tcg_gen_movi_i32(cpu_F1s
, 0);
957 static inline void gen_vfp_uito(int dp
)
960 gen_helper_vfp_uitod(cpu_F0d
, cpu_F0s
, cpu_env
);
962 gen_helper_vfp_uitos(cpu_F0s
, cpu_F0s
, cpu_env
);
965 static inline void gen_vfp_sito(int dp
)
968 gen_helper_vfp_sitod(cpu_F0d
, cpu_F0s
, cpu_env
);
970 gen_helper_vfp_sitos(cpu_F0s
, cpu_F0s
, cpu_env
);
973 static inline void gen_vfp_toui(int dp
)
976 gen_helper_vfp_touid(cpu_F0s
, cpu_F0d
, cpu_env
);
978 gen_helper_vfp_touis(cpu_F0s
, cpu_F0s
, cpu_env
);
981 static inline void gen_vfp_touiz(int dp
)
984 gen_helper_vfp_touizd(cpu_F0s
, cpu_F0d
, cpu_env
);
986 gen_helper_vfp_touizs(cpu_F0s
, cpu_F0s
, cpu_env
);
989 static inline void gen_vfp_tosi(int dp
)
992 gen_helper_vfp_tosid(cpu_F0s
, cpu_F0d
, cpu_env
);
994 gen_helper_vfp_tosis(cpu_F0s
, cpu_F0s
, cpu_env
);
997 static inline void gen_vfp_tosiz(int dp
)
1000 gen_helper_vfp_tosizd(cpu_F0s
, cpu_F0d
, cpu_env
);
1002 gen_helper_vfp_tosizs(cpu_F0s
, cpu_F0s
, cpu_env
);
1005 #define VFP_GEN_FIX(name) \
1006 static inline void gen_vfp_##name(int dp, int shift) \
1008 TCGv tmp_shift = tcg_const_i32(shift); \
1010 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1012 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1013 tcg_temp_free_i32(tmp_shift); \
1025 static inline void gen_vfp_ld(DisasContext
*s
, int dp
, TCGv addr
)
1028 tcg_gen_qemu_ld64(cpu_F0d
, addr
, IS_USER(s
));
1030 tcg_gen_qemu_ld32u(cpu_F0s
, addr
, IS_USER(s
));
1033 static inline void gen_vfp_st(DisasContext
*s
, int dp
, TCGv addr
)
1036 tcg_gen_qemu_st64(cpu_F0d
, addr
, IS_USER(s
));
1038 tcg_gen_qemu_st32(cpu_F0s
, addr
, IS_USER(s
));
1042 vfp_reg_offset (int dp
, int reg
)
1045 return offsetof(CPUARMState
, vfp
.regs
[reg
]);
1047 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1048 + offsetof(CPU_DoubleU
, l
.upper
);
1050 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1051 + offsetof(CPU_DoubleU
, l
.lower
);
1055 /* Return the offset of a 32-bit piece of a NEON register.
1056 zero is the least significant end of the register. */
1058 neon_reg_offset (int reg
, int n
)
1062 return vfp_reg_offset(0, sreg
);
1065 static TCGv
neon_load_reg(int reg
, int pass
)
1067 TCGv tmp
= new_tmp();
1068 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1072 static void neon_store_reg(int reg
, int pass
, TCGv var
)
1074 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1078 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1080 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1083 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1085 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1088 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1089 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1090 #define tcg_gen_st_f32 tcg_gen_st_i32
1091 #define tcg_gen_st_f64 tcg_gen_st_i64
1093 static inline void gen_mov_F0_vreg(int dp
, int reg
)
1096 tcg_gen_ld_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1098 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1101 static inline void gen_mov_F1_vreg(int dp
, int reg
)
1104 tcg_gen_ld_f64(cpu_F1d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1106 tcg_gen_ld_f32(cpu_F1s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1109 static inline void gen_mov_vreg_F0(int dp
, int reg
)
1112 tcg_gen_st_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1114 tcg_gen_st_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1117 #define ARM_CP_RW_BIT (1 << 20)
1119 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1121 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1124 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1126 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1129 static inline TCGv
iwmmxt_load_creg(int reg
)
1131 TCGv var
= new_tmp();
1132 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1136 static inline void iwmmxt_store_creg(int reg
, TCGv var
)
1138 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1141 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1143 iwmmxt_store_reg(cpu_M0
, rn
);
1146 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1148 iwmmxt_load_reg(cpu_M0
, rn
);
1151 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1153 iwmmxt_load_reg(cpu_V1
, rn
);
1154 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1157 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1159 iwmmxt_load_reg(cpu_V1
, rn
);
1160 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1163 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1165 iwmmxt_load_reg(cpu_V1
, rn
);
1166 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1169 #define IWMMXT_OP(name) \
1170 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1172 iwmmxt_load_reg(cpu_V1, rn); \
1173 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1176 #define IWMMXT_OP_ENV(name) \
1177 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1179 iwmmxt_load_reg(cpu_V1, rn); \
1180 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1183 #define IWMMXT_OP_ENV_SIZE(name) \
1184 IWMMXT_OP_ENV(name##b) \
1185 IWMMXT_OP_ENV(name##w) \
1186 IWMMXT_OP_ENV(name##l)
1188 #define IWMMXT_OP_ENV1(name) \
1189 static inline void gen_op_iwmmxt_##name##_M0(void) \
1191 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1205 IWMMXT_OP_ENV_SIZE(unpackl
)
1206 IWMMXT_OP_ENV_SIZE(unpackh
)
1208 IWMMXT_OP_ENV1(unpacklub
)
1209 IWMMXT_OP_ENV1(unpackluw
)
1210 IWMMXT_OP_ENV1(unpacklul
)
1211 IWMMXT_OP_ENV1(unpackhub
)
1212 IWMMXT_OP_ENV1(unpackhuw
)
1213 IWMMXT_OP_ENV1(unpackhul
)
1214 IWMMXT_OP_ENV1(unpacklsb
)
1215 IWMMXT_OP_ENV1(unpacklsw
)
1216 IWMMXT_OP_ENV1(unpacklsl
)
1217 IWMMXT_OP_ENV1(unpackhsb
)
1218 IWMMXT_OP_ENV1(unpackhsw
)
1219 IWMMXT_OP_ENV1(unpackhsl
)
1221 IWMMXT_OP_ENV_SIZE(cmpeq
)
1222 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1223 IWMMXT_OP_ENV_SIZE(cmpgts
)
1225 IWMMXT_OP_ENV_SIZE(mins
)
1226 IWMMXT_OP_ENV_SIZE(minu
)
1227 IWMMXT_OP_ENV_SIZE(maxs
)
1228 IWMMXT_OP_ENV_SIZE(maxu
)
1230 IWMMXT_OP_ENV_SIZE(subn
)
1231 IWMMXT_OP_ENV_SIZE(addn
)
1232 IWMMXT_OP_ENV_SIZE(subu
)
1233 IWMMXT_OP_ENV_SIZE(addu
)
1234 IWMMXT_OP_ENV_SIZE(subs
)
1235 IWMMXT_OP_ENV_SIZE(adds
)
1237 IWMMXT_OP_ENV(avgb0
)
1238 IWMMXT_OP_ENV(avgb1
)
1239 IWMMXT_OP_ENV(avgw0
)
1240 IWMMXT_OP_ENV(avgw1
)
1244 IWMMXT_OP_ENV(packuw
)
1245 IWMMXT_OP_ENV(packul
)
1246 IWMMXT_OP_ENV(packuq
)
1247 IWMMXT_OP_ENV(packsw
)
1248 IWMMXT_OP_ENV(packsl
)
1249 IWMMXT_OP_ENV(packsq
)
1251 static void gen_op_iwmmxt_set_mup(void)
1254 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1255 tcg_gen_ori_i32(tmp
, tmp
, 2);
1256 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1259 static void gen_op_iwmmxt_set_cup(void)
1262 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1263 tcg_gen_ori_i32(tmp
, tmp
, 1);
1264 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1267 static void gen_op_iwmmxt_setpsr_nz(void)
1269 TCGv tmp
= new_tmp();
1270 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1271 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1274 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1276 iwmmxt_load_reg(cpu_V1
, rn
);
1277 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1278 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1281 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
, TCGv dest
)
1287 rd
= (insn
>> 16) & 0xf;
1288 tmp
= load_reg(s
, rd
);
1290 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1291 if (insn
& (1 << 24)) {
1293 if (insn
& (1 << 23))
1294 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1296 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1297 tcg_gen_mov_i32(dest
, tmp
);
1298 if (insn
& (1 << 21))
1299 store_reg(s
, rd
, tmp
);
1302 } else if (insn
& (1 << 21)) {
1304 tcg_gen_mov_i32(dest
, tmp
);
1305 if (insn
& (1 << 23))
1306 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1308 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1309 store_reg(s
, rd
, tmp
);
1310 } else if (!(insn
& (1 << 23)))
1315 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv dest
)
1317 int rd
= (insn
>> 0) & 0xf;
1320 if (insn
& (1 << 8)) {
1321 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1324 tmp
= iwmmxt_load_creg(rd
);
1328 iwmmxt_load_reg(cpu_V0
, rd
);
1329 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
1331 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1332 tcg_gen_mov_i32(dest
, tmp
);
1337 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1338 (ie. an undefined instruction). */
1339 static int disas_iwmmxt_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
1342 int rdhi
, rdlo
, rd0
, rd1
, i
;
1344 TCGv tmp
, tmp2
, tmp3
;
1346 if ((insn
& 0x0e000e00) == 0x0c000000) {
1347 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1349 rdlo
= (insn
>> 12) & 0xf;
1350 rdhi
= (insn
>> 16) & 0xf;
1351 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1352 iwmmxt_load_reg(cpu_V0
, wrd
);
1353 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1354 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
1355 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1356 } else { /* TMCRR */
1357 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1358 iwmmxt_store_reg(cpu_V0
, wrd
);
1359 gen_op_iwmmxt_set_mup();
1364 wrd
= (insn
>> 12) & 0xf;
1366 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1370 if (insn
& ARM_CP_RW_BIT
) {
1371 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1373 tcg_gen_qemu_ld32u(tmp
, addr
, IS_USER(s
));
1374 iwmmxt_store_creg(wrd
, tmp
);
1377 if (insn
& (1 << 8)) {
1378 if (insn
& (1 << 22)) { /* WLDRD */
1379 tcg_gen_qemu_ld64(cpu_M0
, addr
, IS_USER(s
));
1381 } else { /* WLDRW wRd */
1382 tmp
= gen_ld32(addr
, IS_USER(s
));
1385 if (insn
& (1 << 22)) { /* WLDRH */
1386 tmp
= gen_ld16u(addr
, IS_USER(s
));
1387 } else { /* WLDRB */
1388 tmp
= gen_ld8u(addr
, IS_USER(s
));
1392 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1395 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1398 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1399 tmp
= iwmmxt_load_creg(wrd
);
1400 gen_st32(tmp
, addr
, IS_USER(s
));
1402 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1404 if (insn
& (1 << 8)) {
1405 if (insn
& (1 << 22)) { /* WSTRD */
1407 tcg_gen_qemu_st64(cpu_M0
, addr
, IS_USER(s
));
1408 } else { /* WSTRW wRd */
1409 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1410 gen_st32(tmp
, addr
, IS_USER(s
));
1413 if (insn
& (1 << 22)) { /* WSTRH */
1414 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1415 gen_st16(tmp
, addr
, IS_USER(s
));
1416 } else { /* WSTRB */
1417 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1418 gen_st8(tmp
, addr
, IS_USER(s
));
1426 if ((insn
& 0x0f000000) != 0x0e000000)
1429 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1430 case 0x000: /* WOR */
1431 wrd
= (insn
>> 12) & 0xf;
1432 rd0
= (insn
>> 0) & 0xf;
1433 rd1
= (insn
>> 16) & 0xf;
1434 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1435 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1436 gen_op_iwmmxt_setpsr_nz();
1437 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1438 gen_op_iwmmxt_set_mup();
1439 gen_op_iwmmxt_set_cup();
1441 case 0x011: /* TMCR */
1444 rd
= (insn
>> 12) & 0xf;
1445 wrd
= (insn
>> 16) & 0xf;
1447 case ARM_IWMMXT_wCID
:
1448 case ARM_IWMMXT_wCASF
:
1450 case ARM_IWMMXT_wCon
:
1451 gen_op_iwmmxt_set_cup();
1453 case ARM_IWMMXT_wCSSF
:
1454 tmp
= iwmmxt_load_creg(wrd
);
1455 tmp2
= load_reg(s
, rd
);
1456 tcg_gen_bic_i32(tmp
, tmp
, tmp2
);
1458 iwmmxt_store_creg(wrd
, tmp
);
1460 case ARM_IWMMXT_wCGR0
:
1461 case ARM_IWMMXT_wCGR1
:
1462 case ARM_IWMMXT_wCGR2
:
1463 case ARM_IWMMXT_wCGR3
:
1464 gen_op_iwmmxt_set_cup();
1465 tmp
= load_reg(s
, rd
);
1466 iwmmxt_store_creg(wrd
, tmp
);
1472 case 0x100: /* WXOR */
1473 wrd
= (insn
>> 12) & 0xf;
1474 rd0
= (insn
>> 0) & 0xf;
1475 rd1
= (insn
>> 16) & 0xf;
1476 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1477 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1478 gen_op_iwmmxt_setpsr_nz();
1479 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1480 gen_op_iwmmxt_set_mup();
1481 gen_op_iwmmxt_set_cup();
1483 case 0x111: /* TMRC */
1486 rd
= (insn
>> 12) & 0xf;
1487 wrd
= (insn
>> 16) & 0xf;
1488 tmp
= iwmmxt_load_creg(wrd
);
1489 store_reg(s
, rd
, tmp
);
1491 case 0x300: /* WANDN */
1492 wrd
= (insn
>> 12) & 0xf;
1493 rd0
= (insn
>> 0) & 0xf;
1494 rd1
= (insn
>> 16) & 0xf;
1495 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1496 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1497 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1498 gen_op_iwmmxt_setpsr_nz();
1499 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1500 gen_op_iwmmxt_set_mup();
1501 gen_op_iwmmxt_set_cup();
1503 case 0x200: /* WAND */
1504 wrd
= (insn
>> 12) & 0xf;
1505 rd0
= (insn
>> 0) & 0xf;
1506 rd1
= (insn
>> 16) & 0xf;
1507 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1508 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1509 gen_op_iwmmxt_setpsr_nz();
1510 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1511 gen_op_iwmmxt_set_mup();
1512 gen_op_iwmmxt_set_cup();
1514 case 0x810: case 0xa10: /* WMADD */
1515 wrd
= (insn
>> 12) & 0xf;
1516 rd0
= (insn
>> 0) & 0xf;
1517 rd1
= (insn
>> 16) & 0xf;
1518 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1519 if (insn
& (1 << 21))
1520 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1522 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1523 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1524 gen_op_iwmmxt_set_mup();
1526 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1527 wrd
= (insn
>> 12) & 0xf;
1528 rd0
= (insn
>> 16) & 0xf;
1529 rd1
= (insn
>> 0) & 0xf;
1530 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1531 switch ((insn
>> 22) & 3) {
1533 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1536 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1539 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1544 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1545 gen_op_iwmmxt_set_mup();
1546 gen_op_iwmmxt_set_cup();
1548 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1549 wrd
= (insn
>> 12) & 0xf;
1550 rd0
= (insn
>> 16) & 0xf;
1551 rd1
= (insn
>> 0) & 0xf;
1552 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1553 switch ((insn
>> 22) & 3) {
1555 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1558 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1561 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1566 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1567 gen_op_iwmmxt_set_mup();
1568 gen_op_iwmmxt_set_cup();
1570 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1571 wrd
= (insn
>> 12) & 0xf;
1572 rd0
= (insn
>> 16) & 0xf;
1573 rd1
= (insn
>> 0) & 0xf;
1574 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1575 if (insn
& (1 << 22))
1576 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1578 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1579 if (!(insn
& (1 << 20)))
1580 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1581 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1582 gen_op_iwmmxt_set_mup();
1584 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1585 wrd
= (insn
>> 12) & 0xf;
1586 rd0
= (insn
>> 16) & 0xf;
1587 rd1
= (insn
>> 0) & 0xf;
1588 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1589 if (insn
& (1 << 21)) {
1590 if (insn
& (1 << 20))
1591 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1593 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1595 if (insn
& (1 << 20))
1596 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1598 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1600 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1601 gen_op_iwmmxt_set_mup();
1603 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1604 wrd
= (insn
>> 12) & 0xf;
1605 rd0
= (insn
>> 16) & 0xf;
1606 rd1
= (insn
>> 0) & 0xf;
1607 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1608 if (insn
& (1 << 21))
1609 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1611 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1612 if (!(insn
& (1 << 20))) {
1613 iwmmxt_load_reg(cpu_V1
, wrd
);
1614 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1616 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1617 gen_op_iwmmxt_set_mup();
1619 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1620 wrd
= (insn
>> 12) & 0xf;
1621 rd0
= (insn
>> 16) & 0xf;
1622 rd1
= (insn
>> 0) & 0xf;
1623 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1624 switch ((insn
>> 22) & 3) {
1626 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1629 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1632 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1637 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1638 gen_op_iwmmxt_set_mup();
1639 gen_op_iwmmxt_set_cup();
1641 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1642 wrd
= (insn
>> 12) & 0xf;
1643 rd0
= (insn
>> 16) & 0xf;
1644 rd1
= (insn
>> 0) & 0xf;
1645 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1646 if (insn
& (1 << 22)) {
1647 if (insn
& (1 << 20))
1648 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
1650 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
1652 if (insn
& (1 << 20))
1653 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
1655 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
1657 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1658 gen_op_iwmmxt_set_mup();
1659 gen_op_iwmmxt_set_cup();
1661 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1662 wrd
= (insn
>> 12) & 0xf;
1663 rd0
= (insn
>> 16) & 0xf;
1664 rd1
= (insn
>> 0) & 0xf;
1665 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1666 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
1667 tcg_gen_andi_i32(tmp
, tmp
, 7);
1668 iwmmxt_load_reg(cpu_V1
, rd1
);
1669 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
1671 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1672 gen_op_iwmmxt_set_mup();
1674 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1675 if (((insn
>> 6) & 3) == 3)
1677 rd
= (insn
>> 12) & 0xf;
1678 wrd
= (insn
>> 16) & 0xf;
1679 tmp
= load_reg(s
, rd
);
1680 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1681 switch ((insn
>> 6) & 3) {
1683 tmp2
= tcg_const_i32(0xff);
1684 tmp3
= tcg_const_i32((insn
& 7) << 3);
1687 tmp2
= tcg_const_i32(0xffff);
1688 tmp3
= tcg_const_i32((insn
& 3) << 4);
1691 tmp2
= tcg_const_i32(0xffffffff);
1692 tmp3
= tcg_const_i32((insn
& 1) << 5);
1698 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
1699 tcg_temp_free(tmp3
);
1700 tcg_temp_free(tmp2
);
1702 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1703 gen_op_iwmmxt_set_mup();
1705 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1706 rd
= (insn
>> 12) & 0xf;
1707 wrd
= (insn
>> 16) & 0xf;
1708 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
1710 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1712 switch ((insn
>> 22) & 3) {
1714 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
1715 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1717 tcg_gen_ext8s_i32(tmp
, tmp
);
1719 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
1723 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
1724 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1726 tcg_gen_ext16s_i32(tmp
, tmp
);
1728 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
1732 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
1733 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1736 store_reg(s
, rd
, tmp
);
1738 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1739 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1741 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1742 switch ((insn
>> 22) & 3) {
1744 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
1747 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
1750 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
1753 tcg_gen_shli_i32(tmp
, tmp
, 28);
1757 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1758 if (((insn
>> 6) & 3) == 3)
1760 rd
= (insn
>> 12) & 0xf;
1761 wrd
= (insn
>> 16) & 0xf;
1762 tmp
= load_reg(s
, rd
);
1763 switch ((insn
>> 6) & 3) {
1765 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
1768 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
1771 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
1775 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1776 gen_op_iwmmxt_set_mup();
1778 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1779 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1781 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1783 tcg_gen_mov_i32(tmp2
, tmp
);
1784 switch ((insn
>> 22) & 3) {
1786 for (i
= 0; i
< 7; i
++) {
1787 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1788 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1792 for (i
= 0; i
< 3; i
++) {
1793 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1794 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1798 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1799 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1806 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1807 wrd
= (insn
>> 12) & 0xf;
1808 rd0
= (insn
>> 16) & 0xf;
1809 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1810 switch ((insn
>> 22) & 3) {
1812 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
1815 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
1818 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
1823 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1824 gen_op_iwmmxt_set_mup();
1826 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1827 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1829 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1831 tcg_gen_mov_i32(tmp2
, tmp
);
1832 switch ((insn
>> 22) & 3) {
1834 for (i
= 0; i
< 7; i
++) {
1835 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1836 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1840 for (i
= 0; i
< 3; i
++) {
1841 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1842 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1846 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1847 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1854 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1855 rd
= (insn
>> 12) & 0xf;
1856 rd0
= (insn
>> 16) & 0xf;
1857 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
1859 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1861 switch ((insn
>> 22) & 3) {
1863 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
1866 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
1869 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
1872 store_reg(s
, rd
, tmp
);
1874 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1875 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1876 wrd
= (insn
>> 12) & 0xf;
1877 rd0
= (insn
>> 16) & 0xf;
1878 rd1
= (insn
>> 0) & 0xf;
1879 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1880 switch ((insn
>> 22) & 3) {
1882 if (insn
& (1 << 21))
1883 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
1885 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
1888 if (insn
& (1 << 21))
1889 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
1891 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
1894 if (insn
& (1 << 21))
1895 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
1897 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
1902 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1903 gen_op_iwmmxt_set_mup();
1904 gen_op_iwmmxt_set_cup();
1906 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1907 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1908 wrd
= (insn
>> 12) & 0xf;
1909 rd0
= (insn
>> 16) & 0xf;
1910 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1911 switch ((insn
>> 22) & 3) {
1913 if (insn
& (1 << 21))
1914 gen_op_iwmmxt_unpacklsb_M0();
1916 gen_op_iwmmxt_unpacklub_M0();
1919 if (insn
& (1 << 21))
1920 gen_op_iwmmxt_unpacklsw_M0();
1922 gen_op_iwmmxt_unpackluw_M0();
1925 if (insn
& (1 << 21))
1926 gen_op_iwmmxt_unpacklsl_M0();
1928 gen_op_iwmmxt_unpacklul_M0();
1933 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1934 gen_op_iwmmxt_set_mup();
1935 gen_op_iwmmxt_set_cup();
1937 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1938 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1939 wrd
= (insn
>> 12) & 0xf;
1940 rd0
= (insn
>> 16) & 0xf;
1941 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1942 switch ((insn
>> 22) & 3) {
1944 if (insn
& (1 << 21))
1945 gen_op_iwmmxt_unpackhsb_M0();
1947 gen_op_iwmmxt_unpackhub_M0();
1950 if (insn
& (1 << 21))
1951 gen_op_iwmmxt_unpackhsw_M0();
1953 gen_op_iwmmxt_unpackhuw_M0();
1956 if (insn
& (1 << 21))
1957 gen_op_iwmmxt_unpackhsl_M0();
1959 gen_op_iwmmxt_unpackhul_M0();
1964 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1965 gen_op_iwmmxt_set_mup();
1966 gen_op_iwmmxt_set_cup();
1968 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1969 case 0x214: case 0x614: case 0xa14: case 0xe14:
1970 if (((insn
>> 22) & 3) == 0)
1972 wrd
= (insn
>> 12) & 0xf;
1973 rd0
= (insn
>> 16) & 0xf;
1974 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1976 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
1980 switch ((insn
>> 22) & 3) {
1982 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
1985 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
1988 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
1992 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1993 gen_op_iwmmxt_set_mup();
1994 gen_op_iwmmxt_set_cup();
1996 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1997 case 0x014: case 0x414: case 0x814: case 0xc14:
1998 if (((insn
>> 22) & 3) == 0)
2000 wrd
= (insn
>> 12) & 0xf;
2001 rd0
= (insn
>> 16) & 0xf;
2002 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2004 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2008 switch ((insn
>> 22) & 3) {
2010 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2013 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2016 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2020 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2021 gen_op_iwmmxt_set_mup();
2022 gen_op_iwmmxt_set_cup();
2024 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2025 case 0x114: case 0x514: case 0x914: case 0xd14:
2026 if (((insn
>> 22) & 3) == 0)
2028 wrd
= (insn
>> 12) & 0xf;
2029 rd0
= (insn
>> 16) & 0xf;
2030 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2032 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2036 switch ((insn
>> 22) & 3) {
2038 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2041 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2044 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2048 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2049 gen_op_iwmmxt_set_mup();
2050 gen_op_iwmmxt_set_cup();
2052 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2053 case 0x314: case 0x714: case 0xb14: case 0xf14:
2054 if (((insn
>> 22) & 3) == 0)
2056 wrd
= (insn
>> 12) & 0xf;
2057 rd0
= (insn
>> 16) & 0xf;
2058 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2060 switch ((insn
>> 22) & 3) {
2062 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2066 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2069 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2073 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2076 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2080 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2084 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2085 gen_op_iwmmxt_set_mup();
2086 gen_op_iwmmxt_set_cup();
2088 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2089 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2090 wrd
= (insn
>> 12) & 0xf;
2091 rd0
= (insn
>> 16) & 0xf;
2092 rd1
= (insn
>> 0) & 0xf;
2093 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2094 switch ((insn
>> 22) & 3) {
2096 if (insn
& (1 << 21))
2097 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2099 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2102 if (insn
& (1 << 21))
2103 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2105 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2108 if (insn
& (1 << 21))
2109 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2111 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2116 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2117 gen_op_iwmmxt_set_mup();
2119 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2120 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2121 wrd
= (insn
>> 12) & 0xf;
2122 rd0
= (insn
>> 16) & 0xf;
2123 rd1
= (insn
>> 0) & 0xf;
2124 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2125 switch ((insn
>> 22) & 3) {
2127 if (insn
& (1 << 21))
2128 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2130 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2133 if (insn
& (1 << 21))
2134 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2136 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2139 if (insn
& (1 << 21))
2140 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2142 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2147 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2148 gen_op_iwmmxt_set_mup();
2150 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2151 case 0x402: case 0x502: case 0x602: case 0x702:
2152 wrd
= (insn
>> 12) & 0xf;
2153 rd0
= (insn
>> 16) & 0xf;
2154 rd1
= (insn
>> 0) & 0xf;
2155 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2156 tmp
= tcg_const_i32((insn
>> 20) & 3);
2157 iwmmxt_load_reg(cpu_V1
, rd1
);
2158 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2160 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2161 gen_op_iwmmxt_set_mup();
2163 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2164 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2165 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2166 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2167 wrd
= (insn
>> 12) & 0xf;
2168 rd0
= (insn
>> 16) & 0xf;
2169 rd1
= (insn
>> 0) & 0xf;
2170 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2171 switch ((insn
>> 20) & 0xf) {
2173 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2176 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2179 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2182 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2185 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2188 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2191 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2194 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2197 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2202 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2203 gen_op_iwmmxt_set_mup();
2204 gen_op_iwmmxt_set_cup();
2206 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2207 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2208 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2209 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2210 wrd
= (insn
>> 12) & 0xf;
2211 rd0
= (insn
>> 16) & 0xf;
2212 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2213 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2214 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2216 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2217 gen_op_iwmmxt_set_mup();
2218 gen_op_iwmmxt_set_cup();
2220 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2221 case 0x418: case 0x518: case 0x618: case 0x718:
2222 case 0x818: case 0x918: case 0xa18: case 0xb18:
2223 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2224 wrd
= (insn
>> 12) & 0xf;
2225 rd0
= (insn
>> 16) & 0xf;
2226 rd1
= (insn
>> 0) & 0xf;
2227 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2228 switch ((insn
>> 20) & 0xf) {
2230 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2233 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2236 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2239 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2242 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2245 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2248 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2251 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2254 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2259 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2260 gen_op_iwmmxt_set_mup();
2261 gen_op_iwmmxt_set_cup();
2263 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2264 case 0x408: case 0x508: case 0x608: case 0x708:
2265 case 0x808: case 0x908: case 0xa08: case 0xb08:
2266 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2267 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2269 wrd
= (insn
>> 12) & 0xf;
2270 rd0
= (insn
>> 16) & 0xf;
2271 rd1
= (insn
>> 0) & 0xf;
2272 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2273 switch ((insn
>> 22) & 3) {
2275 if (insn
& (1 << 21))
2276 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2278 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2281 if (insn
& (1 << 21))
2282 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2284 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2287 if (insn
& (1 << 21))
2288 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2290 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2293 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2294 gen_op_iwmmxt_set_mup();
2295 gen_op_iwmmxt_set_cup();
2297 case 0x201: case 0x203: case 0x205: case 0x207:
2298 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2299 case 0x211: case 0x213: case 0x215: case 0x217:
2300 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2301 wrd
= (insn
>> 5) & 0xf;
2302 rd0
= (insn
>> 12) & 0xf;
2303 rd1
= (insn
>> 0) & 0xf;
2304 if (rd0
== 0xf || rd1
== 0xf)
2306 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2307 tmp
= load_reg(s
, rd0
);
2308 tmp2
= load_reg(s
, rd1
);
2309 switch ((insn
>> 16) & 0xf) {
2310 case 0x0: /* TMIA */
2311 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2313 case 0x8: /* TMIAPH */
2314 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2316 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2317 if (insn
& (1 << 16))
2318 tcg_gen_shri_i32(tmp
, tmp
, 16);
2319 if (insn
& (1 << 17))
2320 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2321 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2330 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2331 gen_op_iwmmxt_set_mup();
2340 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2341 (ie. an undefined instruction). */
2342 static int disas_dsp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2344 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2347 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2348 /* Multiply with Internal Accumulate Format */
2349 rd0
= (insn
>> 12) & 0xf;
2351 acc
= (insn
>> 5) & 7;
2356 tmp
= load_reg(s
, rd0
);
2357 tmp2
= load_reg(s
, rd1
);
2358 switch ((insn
>> 16) & 0xf) {
2360 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2362 case 0x8: /* MIAPH */
2363 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2365 case 0xc: /* MIABB */
2366 case 0xd: /* MIABT */
2367 case 0xe: /* MIATB */
2368 case 0xf: /* MIATT */
2369 if (insn
& (1 << 16))
2370 tcg_gen_shri_i32(tmp
, tmp
, 16);
2371 if (insn
& (1 << 17))
2372 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2373 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2381 gen_op_iwmmxt_movq_wRn_M0(acc
);
2385 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2386 /* Internal Accumulator Access Format */
2387 rdhi
= (insn
>> 16) & 0xf;
2388 rdlo
= (insn
>> 12) & 0xf;
2394 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2395 iwmmxt_load_reg(cpu_V0
, acc
);
2396 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2397 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
2398 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2399 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2401 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2402 iwmmxt_store_reg(cpu_V0
, acc
);
2410 /* Disassemble system coprocessor instruction. Return nonzero if
2411 instruction is not defined. */
2412 static int disas_cp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2415 uint32_t rd
= (insn
>> 12) & 0xf;
2416 uint32_t cp
= (insn
>> 8) & 0xf;
2421 if (insn
& ARM_CP_RW_BIT
) {
2422 if (!env
->cp
[cp
].cp_read
)
2424 gen_set_pc_im(s
->pc
);
2426 tmp2
= tcg_const_i32(insn
);
2427 gen_helper_get_cp(tmp
, cpu_env
, tmp2
);
2428 tcg_temp_free(tmp2
);
2429 store_reg(s
, rd
, tmp
);
2431 if (!env
->cp
[cp
].cp_write
)
2433 gen_set_pc_im(s
->pc
);
2434 tmp
= load_reg(s
, rd
);
2435 tmp2
= tcg_const_i32(insn
);
2436 gen_helper_set_cp(cpu_env
, tmp2
, tmp
);
2437 tcg_temp_free(tmp2
);
2443 static int cp15_user_ok(uint32_t insn
)
2445 int cpn
= (insn
>> 16) & 0xf;
2446 int cpm
= insn
& 0xf;
2447 int op
= ((insn
>> 5) & 7) | ((insn
>> 18) & 0x38);
2449 if (cpn
== 13 && cpm
== 0) {
2451 if (op
== 2 || (op
== 3 && (insn
& ARM_CP_RW_BIT
)))
2455 /* ISB, DSB, DMB. */
2456 if ((cpm
== 5 && op
== 4)
2457 || (cpm
== 10 && (op
== 4 || op
== 5)))
2463 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2464 instruction is not defined. */
2465 static int disas_cp15_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2470 /* M profile cores use memory mapped registers instead of cp15. */
2471 if (arm_feature(env
, ARM_FEATURE_M
))
2474 if ((insn
& (1 << 25)) == 0) {
2475 if (insn
& (1 << 20)) {
2479 /* mcrr. Used for block cache operations, so implement as no-op. */
2482 if ((insn
& (1 << 4)) == 0) {
2486 if (IS_USER(s
) && !cp15_user_ok(insn
)) {
2489 if ((insn
& 0x0fff0fff) == 0x0e070f90
2490 || (insn
& 0x0fff0fff) == 0x0e070f58) {
2491 /* Wait for interrupt. */
2492 gen_set_pc_im(s
->pc
);
2493 s
->is_jmp
= DISAS_WFI
;
2496 rd
= (insn
>> 12) & 0xf;
2497 tmp2
= tcg_const_i32(insn
);
2498 if (insn
& ARM_CP_RW_BIT
) {
2500 gen_helper_get_cp15(tmp
, cpu_env
, tmp2
);
2501 /* If the destination register is r15 then sets condition codes. */
2503 store_reg(s
, rd
, tmp
);
2507 tmp
= load_reg(s
, rd
);
2508 gen_helper_set_cp15(cpu_env
, tmp2
, tmp
);
2510 /* Normally we would always end the TB here, but Linux
2511 * arch/arm/mach-pxa/sleep.S expects two instructions following
2512 * an MMU enable to execute from cache. Imitate this behaviour. */
2513 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) ||
2514 (insn
& 0x0fff0fff) != 0x0e010f10)
2517 tcg_temp_free_i32(tmp2
);
2521 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2522 #define VFP_SREG(insn, bigbit, smallbit) \
2523 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2524 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2525 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2526 reg = (((insn) >> (bigbit)) & 0x0f) \
2527 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2529 if (insn & (1 << (smallbit))) \
2531 reg = ((insn) >> (bigbit)) & 0x0f; \
2534 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2535 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2536 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2537 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2538 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2539 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2541 /* Move between integer and VFP cores. */
2542 static TCGv
gen_vfp_mrs(void)
2544 TCGv tmp
= new_tmp();
2545 tcg_gen_mov_i32(tmp
, cpu_F0s
);
2549 static void gen_vfp_msr(TCGv tmp
)
2551 tcg_gen_mov_i32(cpu_F0s
, tmp
);
2556 vfp_enabled(CPUState
* env
)
2558 return ((env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) != 0);
2561 static void gen_neon_dup_u8(TCGv var
, int shift
)
2563 TCGv tmp
= new_tmp();
2565 tcg_gen_shri_i32(var
, var
, shift
);
2566 tcg_gen_ext8u_i32(var
, var
);
2567 tcg_gen_shli_i32(tmp
, var
, 8);
2568 tcg_gen_or_i32(var
, var
, tmp
);
2569 tcg_gen_shli_i32(tmp
, var
, 16);
2570 tcg_gen_or_i32(var
, var
, tmp
);
2574 static void gen_neon_dup_low16(TCGv var
)
2576 TCGv tmp
= new_tmp();
2577 tcg_gen_ext16u_i32(var
, var
);
2578 tcg_gen_shli_i32(tmp
, var
, 16);
2579 tcg_gen_or_i32(var
, var
, tmp
);
2583 static void gen_neon_dup_high16(TCGv var
)
2585 TCGv tmp
= new_tmp();
2586 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2587 tcg_gen_shri_i32(tmp
, var
, 16);
2588 tcg_gen_or_i32(var
, var
, tmp
);
2592 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2593 (ie. an undefined instruction). */
2594 static int disas_vfp_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
2596 uint32_t rd
, rn
, rm
, op
, i
, n
, offset
, delta_d
, delta_m
, bank_mask
;
2602 if (!arm_feature(env
, ARM_FEATURE_VFP
))
2605 if (!vfp_enabled(env
)) {
2606 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2607 if ((insn
& 0x0fe00fff) != 0x0ee00a10)
2609 rn
= (insn
>> 16) & 0xf;
2610 if (rn
!= ARM_VFP_FPSID
&& rn
!= ARM_VFP_FPEXC
2611 && rn
!= ARM_VFP_MVFR1
&& rn
!= ARM_VFP_MVFR0
)
2614 dp
= ((insn
& 0xf00) == 0xb00);
2615 switch ((insn
>> 24) & 0xf) {
2617 if (insn
& (1 << 4)) {
2618 /* single register transfer */
2619 rd
= (insn
>> 12) & 0xf;
2624 VFP_DREG_N(rn
, insn
);
2627 if (insn
& 0x00c00060
2628 && !arm_feature(env
, ARM_FEATURE_NEON
))
2631 pass
= (insn
>> 21) & 1;
2632 if (insn
& (1 << 22)) {
2634 offset
= ((insn
>> 5) & 3) * 8;
2635 } else if (insn
& (1 << 5)) {
2637 offset
= (insn
& (1 << 6)) ? 16 : 0;
2642 if (insn
& ARM_CP_RW_BIT
) {
2644 tmp
= neon_load_reg(rn
, pass
);
2648 tcg_gen_shri_i32(tmp
, tmp
, offset
);
2649 if (insn
& (1 << 23))
2655 if (insn
& (1 << 23)) {
2657 tcg_gen_shri_i32(tmp
, tmp
, 16);
2663 tcg_gen_sari_i32(tmp
, tmp
, 16);
2672 store_reg(s
, rd
, tmp
);
2675 tmp
= load_reg(s
, rd
);
2676 if (insn
& (1 << 23)) {
2679 gen_neon_dup_u8(tmp
, 0);
2680 } else if (size
== 1) {
2681 gen_neon_dup_low16(tmp
);
2683 for (n
= 0; n
<= pass
* 2; n
++) {
2685 tcg_gen_mov_i32(tmp2
, tmp
);
2686 neon_store_reg(rn
, n
, tmp2
);
2688 neon_store_reg(rn
, n
, tmp
);
2693 tmp2
= neon_load_reg(rn
, pass
);
2694 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xff);
2698 tmp2
= neon_load_reg(rn
, pass
);
2699 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xffff);
2705 neon_store_reg(rn
, pass
, tmp
);
2709 if ((insn
& 0x6f) != 0x00)
2711 rn
= VFP_SREG_N(insn
);
2712 if (insn
& ARM_CP_RW_BIT
) {
2714 if (insn
& (1 << 21)) {
2715 /* system register */
2720 /* VFP2 allows access to FSID from userspace.
2721 VFP3 restricts all id registers to privileged
2724 && arm_feature(env
, ARM_FEATURE_VFP3
))
2726 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2731 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2733 case ARM_VFP_FPINST
:
2734 case ARM_VFP_FPINST2
:
2735 /* Not present in VFP3. */
2737 || arm_feature(env
, ARM_FEATURE_VFP3
))
2739 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2743 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
2744 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
2747 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
2753 || !arm_feature(env
, ARM_FEATURE_VFP3
))
2755 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2761 gen_mov_F0_vreg(0, rn
);
2762 tmp
= gen_vfp_mrs();
2765 /* Set the 4 flag bits in the CPSR. */
2769 store_reg(s
, rd
, tmp
);
2773 tmp
= load_reg(s
, rd
);
2774 if (insn
& (1 << 21)) {
2776 /* system register */
2781 /* Writes are ignored. */
2784 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
2791 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2794 case ARM_VFP_FPINST
:
2795 case ARM_VFP_FPINST2
:
2796 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2803 gen_mov_vreg_F0(0, rn
);
2808 /* data processing */
2809 /* The opcode is in bits 23, 21, 20 and 6. */
2810 op
= ((insn
>> 20) & 8) | ((insn
>> 19) & 6) | ((insn
>> 6) & 1);
2814 rn
= ((insn
>> 15) & 0x1e) | ((insn
>> 7) & 1);
2816 /* rn is register number */
2817 VFP_DREG_N(rn
, insn
);
2820 if (op
== 15 && (rn
== 15 || rn
> 17)) {
2821 /* Integer or single precision destination. */
2822 rd
= VFP_SREG_D(insn
);
2824 VFP_DREG_D(rd
, insn
);
2827 if (op
== 15 && (rn
== 16 || rn
== 17)) {
2828 /* Integer source. */
2829 rm
= ((insn
<< 1) & 0x1e) | ((insn
>> 5) & 1);
2831 VFP_DREG_M(rm
, insn
);
2834 rn
= VFP_SREG_N(insn
);
2835 if (op
== 15 && rn
== 15) {
2836 /* Double precision destination. */
2837 VFP_DREG_D(rd
, insn
);
2839 rd
= VFP_SREG_D(insn
);
2841 rm
= VFP_SREG_M(insn
);
2844 veclen
= env
->vfp
.vec_len
;
2845 if (op
== 15 && rn
> 3)
2848 /* Shut up compiler warnings. */
2859 /* Figure out what type of vector operation this is. */
2860 if ((rd
& bank_mask
) == 0) {
2865 delta_d
= (env
->vfp
.vec_stride
>> 1) + 1;
2867 delta_d
= env
->vfp
.vec_stride
+ 1;
2869 if ((rm
& bank_mask
) == 0) {
2870 /* mixed scalar/vector */
2879 /* Load the initial operands. */
2884 /* Integer source */
2885 gen_mov_F0_vreg(0, rm
);
2890 gen_mov_F0_vreg(dp
, rd
);
2891 gen_mov_F1_vreg(dp
, rm
);
2895 /* Compare with zero */
2896 gen_mov_F0_vreg(dp
, rd
);
2907 /* Source and destination the same. */
2908 gen_mov_F0_vreg(dp
, rd
);
2911 /* One source operand. */
2912 gen_mov_F0_vreg(dp
, rm
);
2916 /* Two source operands. */
2917 gen_mov_F0_vreg(dp
, rn
);
2918 gen_mov_F1_vreg(dp
, rm
);
2922 /* Perform the calculation. */
2924 case 0: /* mac: fd + (fn * fm) */
2926 gen_mov_F1_vreg(dp
, rd
);
2929 case 1: /* nmac: fd - (fn * fm) */
2932 gen_mov_F1_vreg(dp
, rd
);
2935 case 2: /* msc: -fd + (fn * fm) */
2937 gen_mov_F1_vreg(dp
, rd
);
2940 case 3: /* nmsc: -fd - (fn * fm) */
2943 gen_mov_F1_vreg(dp
, rd
);
2946 case 4: /* mul: fn * fm */
2949 case 5: /* nmul: -(fn * fm) */
2953 case 6: /* add: fn + fm */
2956 case 7: /* sub: fn - fm */
2959 case 8: /* div: fn / fm */
2962 case 14: /* fconst */
2963 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
2966 n
= (insn
<< 12) & 0x80000000;
2967 i
= ((insn
>> 12) & 0x70) | (insn
& 0xf);
2974 tcg_gen_movi_i64(cpu_F0d
, ((uint64_t)n
) << 32);
2981 tcg_gen_movi_i32(cpu_F0s
, n
);
2984 case 15: /* extension space */
3007 case 11: /* cmpez */
3011 case 15: /* single<->double conversion */
3013 gen_helper_vfp_fcvtsd(cpu_F0s
, cpu_F0d
, cpu_env
);
3015 gen_helper_vfp_fcvtds(cpu_F0d
, cpu_F0s
, cpu_env
);
3017 case 16: /* fuito */
3020 case 17: /* fsito */
3023 case 20: /* fshto */
3024 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3026 gen_vfp_shto(dp
, 16 - rm
);
3028 case 21: /* fslto */
3029 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3031 gen_vfp_slto(dp
, 32 - rm
);
3033 case 22: /* fuhto */
3034 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3036 gen_vfp_uhto(dp
, 16 - rm
);
3038 case 23: /* fulto */
3039 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3041 gen_vfp_ulto(dp
, 32 - rm
);
3043 case 24: /* ftoui */
3046 case 25: /* ftouiz */
3049 case 26: /* ftosi */
3052 case 27: /* ftosiz */
3055 case 28: /* ftosh */
3056 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3058 gen_vfp_tosh(dp
, 16 - rm
);
3060 case 29: /* ftosl */
3061 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3063 gen_vfp_tosl(dp
, 32 - rm
);
3065 case 30: /* ftouh */
3066 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3068 gen_vfp_touh(dp
, 16 - rm
);
3070 case 31: /* ftoul */
3071 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3073 gen_vfp_toul(dp
, 32 - rm
);
3075 default: /* undefined */
3076 printf ("rn:%d\n", rn
);
3080 default: /* undefined */
3081 printf ("op:%d\n", op
);
3085 /* Write back the result. */
3086 if (op
== 15 && (rn
>= 8 && rn
<= 11))
3087 ; /* Comparison, do nothing. */
3088 else if (op
== 15 && rn
> 17)
3089 /* Integer result. */
3090 gen_mov_vreg_F0(0, rd
);
3091 else if (op
== 15 && rn
== 15)
3093 gen_mov_vreg_F0(!dp
, rd
);
3095 gen_mov_vreg_F0(dp
, rd
);
3097 /* break out of the loop if we have finished */
3101 if (op
== 15 && delta_m
== 0) {
3102 /* single source one-many */
3104 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3106 gen_mov_vreg_F0(dp
, rd
);
3110 /* Setup the next operands. */
3112 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3116 /* One source operand. */
3117 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3119 gen_mov_F0_vreg(dp
, rm
);
3121 /* Two source operands. */
3122 rn
= ((rn
+ delta_d
) & (bank_mask
- 1))
3124 gen_mov_F0_vreg(dp
, rn
);
3126 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3128 gen_mov_F1_vreg(dp
, rm
);
3136 if (dp
&& (insn
& 0x03e00000) == 0x00400000) {
3137 /* two-register transfer */
3138 rn
= (insn
>> 16) & 0xf;
3139 rd
= (insn
>> 12) & 0xf;
3141 VFP_DREG_M(rm
, insn
);
3143 rm
= VFP_SREG_M(insn
);
3146 if (insn
& ARM_CP_RW_BIT
) {
3149 gen_mov_F0_vreg(0, rm
* 2);
3150 tmp
= gen_vfp_mrs();
3151 store_reg(s
, rd
, tmp
);
3152 gen_mov_F0_vreg(0, rm
* 2 + 1);
3153 tmp
= gen_vfp_mrs();
3154 store_reg(s
, rn
, tmp
);
3156 gen_mov_F0_vreg(0, rm
);
3157 tmp
= gen_vfp_mrs();
3158 store_reg(s
, rn
, tmp
);
3159 gen_mov_F0_vreg(0, rm
+ 1);
3160 tmp
= gen_vfp_mrs();
3161 store_reg(s
, rd
, tmp
);
3166 tmp
= load_reg(s
, rd
);
3168 gen_mov_vreg_F0(0, rm
* 2);
3169 tmp
= load_reg(s
, rn
);
3171 gen_mov_vreg_F0(0, rm
* 2 + 1);
3173 tmp
= load_reg(s
, rn
);
3175 gen_mov_vreg_F0(0, rm
);
3176 tmp
= load_reg(s
, rd
);
3178 gen_mov_vreg_F0(0, rm
+ 1);
3183 rn
= (insn
>> 16) & 0xf;
3185 VFP_DREG_D(rd
, insn
);
3187 rd
= VFP_SREG_D(insn
);
3188 if (s
->thumb
&& rn
== 15) {
3190 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
3192 addr
= load_reg(s
, rn
);
3194 if ((insn
& 0x01200000) == 0x01000000) {
3195 /* Single load/store */
3196 offset
= (insn
& 0xff) << 2;
3197 if ((insn
& (1 << 23)) == 0)
3199 tcg_gen_addi_i32(addr
, addr
, offset
);
3200 if (insn
& (1 << 20)) {
3201 gen_vfp_ld(s
, dp
, addr
);
3202 gen_mov_vreg_F0(dp
, rd
);
3204 gen_mov_F0_vreg(dp
, rd
);
3205 gen_vfp_st(s
, dp
, addr
);
3209 /* load/store multiple */
3211 n
= (insn
>> 1) & 0x7f;
3215 if (insn
& (1 << 24)) /* pre-decrement */
3216 tcg_gen_addi_i32(addr
, addr
, -((insn
& 0xff) << 2));
3222 for (i
= 0; i
< n
; i
++) {
3223 if (insn
& ARM_CP_RW_BIT
) {
3225 gen_vfp_ld(s
, dp
, addr
);
3226 gen_mov_vreg_F0(dp
, rd
+ i
);
3229 gen_mov_F0_vreg(dp
, rd
+ i
);
3230 gen_vfp_st(s
, dp
, addr
);
3232 tcg_gen_addi_i32(addr
, addr
, offset
);
3234 if (insn
& (1 << 21)) {
3236 if (insn
& (1 << 24))
3237 offset
= -offset
* n
;
3238 else if (dp
&& (insn
& 1))
3244 tcg_gen_addi_i32(addr
, addr
, offset
);
3245 store_reg(s
, rn
, addr
);
3253 /* Should never happen. */
3259 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
3261 TranslationBlock
*tb
;
3264 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
3266 gen_set_pc_im(dest
);
3267 tcg_gen_exit_tb((long)tb
+ n
);
3269 gen_set_pc_im(dest
);
3274 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
3276 if (unlikely(s
->singlestep_enabled
)) {
3277 /* An indirect jump so that we still trigger the debug exception. */
3282 gen_goto_tb(s
, 0, dest
);
3283 s
->is_jmp
= DISAS_TB_JUMP
;
3287 static inline void gen_mulxy(TCGv t0
, TCGv t1
, int x
, int y
)
3290 tcg_gen_sari_i32(t0
, t0
, 16);
3294 tcg_gen_sari_i32(t1
, t1
, 16);
3297 tcg_gen_mul_i32(t0
, t0
, t1
);
3300 /* Return the mask of PSR bits set by a MSR instruction. */
3301 static uint32_t msr_mask(CPUState
*env
, DisasContext
*s
, int flags
, int spsr
) {
3305 if (flags
& (1 << 0))
3307 if (flags
& (1 << 1))
3309 if (flags
& (1 << 2))
3311 if (flags
& (1 << 3))
3314 /* Mask out undefined bits. */
3315 mask
&= ~CPSR_RESERVED
;
3316 if (!arm_feature(env
, ARM_FEATURE_V6
))
3317 mask
&= ~(CPSR_E
| CPSR_GE
);
3318 if (!arm_feature(env
, ARM_FEATURE_THUMB2
))
3320 /* Mask out execution state bits. */
3323 /* Mask out privileged bits. */
3329 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3330 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv t0
)
3334 /* ??? This is also undefined in system mode. */
3338 tmp
= load_cpu_field(spsr
);
3339 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
3340 tcg_gen_andi_i32(t0
, t0
, mask
);
3341 tcg_gen_or_i32(tmp
, tmp
, t0
);
3342 store_cpu_field(tmp
, spsr
);
3344 gen_set_cpsr(t0
, mask
);
3351 /* Returns nonzero if access to the PSR is not permitted. */
3352 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
3356 tcg_gen_movi_i32(tmp
, val
);
3357 return gen_set_psr(s
, mask
, spsr
, tmp
);
3360 /* Generate an old-style exception return. Marks pc as dead. */
3361 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
3364 store_reg(s
, 15, pc
);
3365 tmp
= load_cpu_field(spsr
);
3366 gen_set_cpsr(tmp
, 0xffffffff);
3368 s
->is_jmp
= DISAS_UPDATE
;
3371 /* Generate a v6 exception return. Marks both values as dead. */
3372 static void gen_rfe(DisasContext
*s
, TCGv pc
, TCGv cpsr
)
3374 gen_set_cpsr(cpsr
, 0xffffffff);
3376 store_reg(s
, 15, pc
);
3377 s
->is_jmp
= DISAS_UPDATE
;
3381 gen_set_condexec (DisasContext
*s
)
3383 if (s
->condexec_mask
) {
3384 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
3385 TCGv tmp
= new_tmp();
3386 tcg_gen_movi_i32(tmp
, val
);
3387 store_cpu_field(tmp
, condexec_bits
);
3391 static void gen_nop_hint(DisasContext
*s
, int val
)
3395 gen_set_pc_im(s
->pc
);
3396 s
->is_jmp
= DISAS_WFI
;
3400 /* TODO: Implement SEV and WFE. May help SMP performance. */
3406 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3408 static inline int gen_neon_add(int size
, TCGv t0
, TCGv t1
)
3411 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
3412 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
3413 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3419 static inline void gen_neon_rsb(int size
, TCGv t0
, TCGv t1
)
3422 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3423 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3424 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3429 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3430 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3431 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3432 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3433 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3435 /* FIXME: This is wrong. They set the wrong overflow bit. */
3436 #define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c)
3437 #define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c)
3438 #define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c)
3439 #define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c)
3441 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3442 switch ((size << 1) | u) { \
3444 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3447 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3450 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3453 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3456 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3459 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3461 default: return 1; \
3464 #define GEN_NEON_INTEGER_OP(name) do { \
3465 switch ((size << 1) | u) { \
3467 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3470 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3473 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3476 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3479 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3482 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3484 default: return 1; \
3487 static TCGv
neon_load_scratch(int scratch
)
3489 TCGv tmp
= new_tmp();
3490 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3494 static void neon_store_scratch(int scratch
, TCGv var
)
3496 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3500 static inline TCGv
neon_get_scalar(int size
, int reg
)
3504 tmp
= neon_load_reg(reg
>> 1, reg
& 1);
3506 tmp
= neon_load_reg(reg
>> 2, (reg
>> 1) & 1);
3508 gen_neon_dup_low16(tmp
);
3510 gen_neon_dup_high16(tmp
);
3516 static void gen_neon_unzip_u8(TCGv t0
, TCGv t1
)
3524 tcg_gen_andi_i32(rd
, t0
, 0xff);
3525 tcg_gen_shri_i32(tmp
, t0
, 8);
3526 tcg_gen_andi_i32(tmp
, tmp
, 0xff00);
3527 tcg_gen_or_i32(rd
, rd
, tmp
);
3528 tcg_gen_shli_i32(tmp
, t1
, 16);
3529 tcg_gen_andi_i32(tmp
, tmp
, 0xff0000);
3530 tcg_gen_or_i32(rd
, rd
, tmp
);
3531 tcg_gen_shli_i32(tmp
, t1
, 8);
3532 tcg_gen_andi_i32(tmp
, tmp
, 0xff000000);
3533 tcg_gen_or_i32(rd
, rd
, tmp
);
3535 tcg_gen_shri_i32(rm
, t0
, 8);
3536 tcg_gen_andi_i32(rm
, rm
, 0xff);
3537 tcg_gen_shri_i32(tmp
, t0
, 16);
3538 tcg_gen_andi_i32(tmp
, tmp
, 0xff00);
3539 tcg_gen_or_i32(rm
, rm
, tmp
);
3540 tcg_gen_shli_i32(tmp
, t1
, 8);
3541 tcg_gen_andi_i32(tmp
, tmp
, 0xff0000);
3542 tcg_gen_or_i32(rm
, rm
, tmp
);
3543 tcg_gen_andi_i32(tmp
, t1
, 0xff000000);
3544 tcg_gen_or_i32(t1
, rm
, tmp
);
3545 tcg_gen_mov_i32(t0
, rd
);
3552 static void gen_neon_zip_u8(TCGv t0
, TCGv t1
)
3560 tcg_gen_andi_i32(rd
, t0
, 0xff);
3561 tcg_gen_shli_i32(tmp
, t1
, 8);
3562 tcg_gen_andi_i32(tmp
, tmp
, 0xff00);
3563 tcg_gen_or_i32(rd
, rd
, tmp
);
3564 tcg_gen_shli_i32(tmp
, t0
, 16);
3565 tcg_gen_andi_i32(tmp
, tmp
, 0xff0000);
3566 tcg_gen_or_i32(rd
, rd
, tmp
);
3567 tcg_gen_shli_i32(tmp
, t1
, 24);
3568 tcg_gen_andi_i32(tmp
, tmp
, 0xff000000);
3569 tcg_gen_or_i32(rd
, rd
, tmp
);
3571 tcg_gen_andi_i32(rm
, t1
, 0xff000000);
3572 tcg_gen_shri_i32(tmp
, t0
, 8);
3573 tcg_gen_andi_i32(tmp
, tmp
, 0xff0000);
3574 tcg_gen_or_i32(rm
, rm
, tmp
);
3575 tcg_gen_shri_i32(tmp
, t1
, 8);
3576 tcg_gen_andi_i32(tmp
, tmp
, 0xff00);
3577 tcg_gen_or_i32(rm
, rm
, tmp
);
3578 tcg_gen_shri_i32(tmp
, t0
, 16);
3579 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
3580 tcg_gen_or_i32(t1
, rm
, tmp
);
3581 tcg_gen_mov_i32(t0
, rd
);
3588 static void gen_neon_zip_u16(TCGv t0
, TCGv t1
)
3595 tcg_gen_andi_i32(tmp
, t0
, 0xffff);
3596 tcg_gen_shli_i32(tmp2
, t1
, 16);
3597 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3598 tcg_gen_andi_i32(t1
, t1
, 0xffff0000);
3599 tcg_gen_shri_i32(tmp2
, t0
, 16);
3600 tcg_gen_or_i32(t1
, t1
, tmp2
);
3601 tcg_gen_mov_i32(t0
, tmp
);
3607 static void gen_neon_unzip(int reg
, int q
, int tmp
, int size
)
3612 for (n
= 0; n
< q
+ 1; n
+= 2) {
3613 t0
= neon_load_reg(reg
, n
);
3614 t1
= neon_load_reg(reg
, n
+ 1);
3616 case 0: gen_neon_unzip_u8(t0
, t1
); break;
3617 case 1: gen_neon_zip_u16(t0
, t1
); break; /* zip and unzip are the same. */
3618 case 2: /* no-op */; break;
3621 neon_store_scratch(tmp
+ n
, t0
);
3622 neon_store_scratch(tmp
+ n
+ 1, t1
);
3626 static void gen_neon_trn_u8(TCGv t0
, TCGv t1
)
3633 tcg_gen_shli_i32(rd
, t0
, 8);
3634 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
3635 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
3636 tcg_gen_or_i32(rd
, rd
, tmp
);
3638 tcg_gen_shri_i32(t1
, t1
, 8);
3639 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
3640 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
3641 tcg_gen_or_i32(t1
, t1
, tmp
);
3642 tcg_gen_mov_i32(t0
, rd
);
3648 static void gen_neon_trn_u16(TCGv t0
, TCGv t1
)
3655 tcg_gen_shli_i32(rd
, t0
, 16);
3656 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
3657 tcg_gen_or_i32(rd
, rd
, tmp
);
3658 tcg_gen_shri_i32(t1
, t1
, 16);
3659 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
3660 tcg_gen_or_i32(t1
, t1
, tmp
);
3661 tcg_gen_mov_i32(t0
, rd
);
3672 } neon_ls_element_type
[11] = {
3686 /* Translate a NEON load/store element instruction. Return nonzero if the
3687 instruction is invalid. */
3688 static int disas_neon_ls_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
3707 if (!vfp_enabled(env
))
3709 VFP_DREG_D(rd
, insn
);
3710 rn
= (insn
>> 16) & 0xf;
3712 load
= (insn
& (1 << 21)) != 0;
3714 if ((insn
& (1 << 23)) == 0) {
3715 /* Load store all elements. */
3716 op
= (insn
>> 8) & 0xf;
3717 size
= (insn
>> 6) & 3;
3720 nregs
= neon_ls_element_type
[op
].nregs
;
3721 interleave
= neon_ls_element_type
[op
].interleave
;
3722 spacing
= neon_ls_element_type
[op
].spacing
;
3723 if (size
== 3 && (interleave
| spacing
) != 1)
3725 load_reg_var(s
, addr
, rn
);
3726 stride
= (1 << size
) * interleave
;
3727 for (reg
= 0; reg
< nregs
; reg
++) {
3728 if (interleave
> 2 || (interleave
== 2 && nregs
== 2)) {
3729 load_reg_var(s
, addr
, rn
);
3730 tcg_gen_addi_i32(addr
, addr
, (1 << size
) * reg
);
3731 } else if (interleave
== 2 && nregs
== 4 && reg
== 2) {
3732 load_reg_var(s
, addr
, rn
);
3733 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3737 tmp64
= gen_ld64(addr
, IS_USER(s
));
3738 neon_store_reg64(tmp64
, rd
);
3739 tcg_temp_free_i64(tmp64
);
3741 tmp64
= tcg_temp_new_i64();
3742 neon_load_reg64(tmp64
, rd
);
3743 gen_st64(tmp64
, addr
, IS_USER(s
));
3745 tcg_gen_addi_i32(addr
, addr
, stride
);
3747 for (pass
= 0; pass
< 2; pass
++) {
3750 tmp
= gen_ld32(addr
, IS_USER(s
));
3751 neon_store_reg(rd
, pass
, tmp
);
3753 tmp
= neon_load_reg(rd
, pass
);
3754 gen_st32(tmp
, addr
, IS_USER(s
));
3756 tcg_gen_addi_i32(addr
, addr
, stride
);
3757 } else if (size
== 1) {
3759 tmp
= gen_ld16u(addr
, IS_USER(s
));
3760 tcg_gen_addi_i32(addr
, addr
, stride
);
3761 tmp2
= gen_ld16u(addr
, IS_USER(s
));
3762 tcg_gen_addi_i32(addr
, addr
, stride
);
3763 gen_bfi(tmp
, tmp
, tmp2
, 16, 0xffff);
3765 neon_store_reg(rd
, pass
, tmp
);
3767 tmp
= neon_load_reg(rd
, pass
);
3769 tcg_gen_shri_i32(tmp2
, tmp
, 16);
3770 gen_st16(tmp
, addr
, IS_USER(s
));
3771 tcg_gen_addi_i32(addr
, addr
, stride
);
3772 gen_st16(tmp2
, addr
, IS_USER(s
));
3773 tcg_gen_addi_i32(addr
, addr
, stride
);
3775 } else /* size == 0 */ {
3778 for (n
= 0; n
< 4; n
++) {
3779 tmp
= gen_ld8u(addr
, IS_USER(s
));
3780 tcg_gen_addi_i32(addr
, addr
, stride
);
3784 gen_bfi(tmp2
, tmp2
, tmp
, n
* 8, 0xff);
3788 neon_store_reg(rd
, pass
, tmp2
);
3790 tmp2
= neon_load_reg(rd
, pass
);
3791 for (n
= 0; n
< 4; n
++) {
3794 tcg_gen_mov_i32(tmp
, tmp2
);
3796 tcg_gen_shri_i32(tmp
, tmp2
, n
* 8);
3798 gen_st8(tmp
, addr
, IS_USER(s
));
3799 tcg_gen_addi_i32(addr
, addr
, stride
);
3810 size
= (insn
>> 10) & 3;
3812 /* Load single element to all lanes. */
3815 size
= (insn
>> 6) & 3;
3816 nregs
= ((insn
>> 8) & 3) + 1;
3817 stride
= (insn
& (1 << 5)) ? 2 : 1;
3818 load_reg_var(s
, addr
, rn
);
3819 for (reg
= 0; reg
< nregs
; reg
++) {
3822 tmp
= gen_ld8u(addr
, IS_USER(s
));
3823 gen_neon_dup_u8(tmp
, 0);
3826 tmp
= gen_ld16u(addr
, IS_USER(s
));
3827 gen_neon_dup_low16(tmp
);
3830 tmp
= gen_ld32(addr
, IS_USER(s
));
3834 default: /* Avoid compiler warnings. */
3837 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3839 tcg_gen_mov_i32(tmp2
, tmp
);
3840 neon_store_reg(rd
, 0, tmp2
);
3841 neon_store_reg(rd
, 1, tmp
);
3844 stride
= (1 << size
) * nregs
;
3846 /* Single element. */
3847 pass
= (insn
>> 7) & 1;
3850 shift
= ((insn
>> 5) & 3) * 8;
3854 shift
= ((insn
>> 6) & 1) * 16;
3855 stride
= (insn
& (1 << 5)) ? 2 : 1;
3859 stride
= (insn
& (1 << 6)) ? 2 : 1;
3864 nregs
= ((insn
>> 8) & 3) + 1;
3865 load_reg_var(s
, addr
, rn
);
3866 for (reg
= 0; reg
< nregs
; reg
++) {
3870 tmp
= gen_ld8u(addr
, IS_USER(s
));
3873 tmp
= gen_ld16u(addr
, IS_USER(s
));
3876 tmp
= gen_ld32(addr
, IS_USER(s
));
3878 default: /* Avoid compiler warnings. */
3882 tmp2
= neon_load_reg(rd
, pass
);
3883 gen_bfi(tmp
, tmp2
, tmp
, shift
, size
? 0xffff : 0xff);
3886 neon_store_reg(rd
, pass
, tmp
);
3887 } else { /* Store */
3888 tmp
= neon_load_reg(rd
, pass
);
3890 tcg_gen_shri_i32(tmp
, tmp
, shift
);
3893 gen_st8(tmp
, addr
, IS_USER(s
));
3896 gen_st16(tmp
, addr
, IS_USER(s
));
3899 gen_st32(tmp
, addr
, IS_USER(s
));
3904 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3906 stride
= nregs
* (1 << size
);
3913 base
= load_reg(s
, rn
);
3915 tcg_gen_addi_i32(base
, base
, stride
);
3918 index
= load_reg(s
, rm
);
3919 tcg_gen_add_i32(base
, base
, index
);
3922 store_reg(s
, rn
, base
);
3927 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
3928 static void gen_neon_bsl(TCGv dest
, TCGv t
, TCGv f
, TCGv c
)
3930 tcg_gen_and_i32(t
, t
, c
);
3931 tcg_gen_bic_i32(f
, f
, c
);
3932 tcg_gen_or_i32(dest
, t
, f
);
3935 static inline void gen_neon_narrow(int size
, TCGv dest
, TCGv_i64 src
)
3938 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
3939 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
3940 case 2: tcg_gen_trunc_i64_i32(dest
, src
); break;
3945 static inline void gen_neon_narrow_sats(int size
, TCGv dest
, TCGv_i64 src
)
3948 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
3949 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
3950 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
3955 static inline void gen_neon_narrow_satu(int size
, TCGv dest
, TCGv_i64 src
)
3958 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
3959 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
3960 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
3965 static inline void gen_neon_shift_narrow(int size
, TCGv var
, TCGv shift
,
3971 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
3972 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
3977 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
3978 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
3985 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
3986 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
3991 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
3992 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
3999 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv src
, int size
, int u
)
4003 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
4004 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
4005 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
4010 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
4011 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
4012 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
4019 static inline void gen_neon_addl(int size
)
4022 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
4023 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
4024 case 2: tcg_gen_add_i64(CPU_V001
); break;
4029 static inline void gen_neon_subl(int size
)
4032 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
4033 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
4034 case 2: tcg_gen_sub_i64(CPU_V001
); break;
4039 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
4042 case 0: gen_helper_neon_negl_u16(var
, var
); break;
4043 case 1: gen_helper_neon_negl_u32(var
, var
); break;
4044 case 2: gen_helper_neon_negl_u64(var
, var
); break;
4049 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
4052 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
4053 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
4058 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv a
, TCGv b
, int size
, int u
)
4062 switch ((size
<< 1) | u
) {
4063 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
4064 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
4065 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
4066 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
4068 tmp
= gen_muls_i64_i32(a
, b
);
4069 tcg_gen_mov_i64(dest
, tmp
);
4072 tmp
= gen_mulu_i64_i32(a
, b
);
4073 tcg_gen_mov_i64(dest
, tmp
);
4079 /* Translate a NEON data processing instruction. Return nonzero if the
4080 instruction is invalid.
4081 We process data in a mixture of 32-bit and 64-bit chunks.
4082 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4084 static int disas_neon_data_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
4097 TCGv tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
4100 if (!vfp_enabled(env
))
4102 q
= (insn
& (1 << 6)) != 0;
4103 u
= (insn
>> 24) & 1;
4104 VFP_DREG_D(rd
, insn
);
4105 VFP_DREG_N(rn
, insn
);
4106 VFP_DREG_M(rm
, insn
);
4107 size
= (insn
>> 20) & 3;
4108 if ((insn
& (1 << 23)) == 0) {
4109 /* Three register same length. */
4110 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
4111 if (size
== 3 && (op
== 1 || op
== 5 || op
== 8 || op
== 9
4112 || op
== 10 || op
== 11 || op
== 16)) {
4113 /* 64-bit element instructions. */
4114 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
4115 neon_load_reg64(cpu_V0
, rn
+ pass
);
4116 neon_load_reg64(cpu_V1
, rm
+ pass
);
4120 gen_helper_neon_add_saturate_u64(CPU_V001
);
4122 gen_helper_neon_add_saturate_s64(CPU_V001
);
4127 gen_helper_neon_sub_saturate_u64(CPU_V001
);
4129 gen_helper_neon_sub_saturate_s64(CPU_V001
);
4134 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4136 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4141 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
4144 gen_helper_neon_qshl_s64(cpu_V1
, cpu_env
,
4148 case 10: /* VRSHL */
4150 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4152 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4155 case 11: /* VQRSHL */
4157 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_env
,
4160 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_env
,
4166 tcg_gen_sub_i64(CPU_V001
);
4168 tcg_gen_add_i64(CPU_V001
);
4174 neon_store_reg64(cpu_V0
, rd
+ pass
);
4181 case 10: /* VRSHL */
4182 case 11: /* VQRSHL */
4185 /* Shift instruction operands are reversed. */
4192 case 20: /* VPMAX */
4193 case 21: /* VPMIN */
4194 case 23: /* VPADD */
4197 case 26: /* VPADD (float) */
4198 pairwise
= (u
&& size
< 2);
4200 case 30: /* VPMIN/VPMAX (float) */
4208 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4217 tmp
= neon_load_reg(rn
, n
);
4218 tmp2
= neon_load_reg(rn
, n
+ 1);
4220 tmp
= neon_load_reg(rm
, n
);
4221 tmp2
= neon_load_reg(rm
, n
+ 1);
4225 tmp
= neon_load_reg(rn
, pass
);
4226 tmp2
= neon_load_reg(rm
, pass
);
4230 GEN_NEON_INTEGER_OP(hadd
);
4233 GEN_NEON_INTEGER_OP_ENV(qadd
);
4235 case 2: /* VRHADD */
4236 GEN_NEON_INTEGER_OP(rhadd
);
4238 case 3: /* Logic ops. */
4239 switch ((u
<< 2) | size
) {
4241 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
4244 tcg_gen_bic_i32(tmp
, tmp
, tmp2
);
4247 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4250 tcg_gen_not_i32(tmp2
, tmp2
);
4251 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4254 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
4257 tmp3
= neon_load_reg(rd
, pass
);
4258 gen_neon_bsl(tmp
, tmp
, tmp2
, tmp3
);
4262 tmp3
= neon_load_reg(rd
, pass
);
4263 gen_neon_bsl(tmp
, tmp
, tmp3
, tmp2
);
4267 tmp3
= neon_load_reg(rd
, pass
);
4268 gen_neon_bsl(tmp
, tmp3
, tmp
, tmp2
);
4274 GEN_NEON_INTEGER_OP(hsub
);
4277 GEN_NEON_INTEGER_OP_ENV(qsub
);
4280 GEN_NEON_INTEGER_OP(cgt
);
4283 GEN_NEON_INTEGER_OP(cge
);
4286 GEN_NEON_INTEGER_OP(shl
);
4289 GEN_NEON_INTEGER_OP_ENV(qshl
);
4291 case 10: /* VRSHL */
4292 GEN_NEON_INTEGER_OP(rshl
);
4294 case 11: /* VQRSHL */
4295 GEN_NEON_INTEGER_OP_ENV(qrshl
);
4298 GEN_NEON_INTEGER_OP(max
);
4301 GEN_NEON_INTEGER_OP(min
);
4304 GEN_NEON_INTEGER_OP(abd
);
4307 GEN_NEON_INTEGER_OP(abd
);
4309 tmp2
= neon_load_reg(rd
, pass
);
4310 gen_neon_add(size
, tmp
, tmp2
);
4313 if (!u
) { /* VADD */
4314 if (gen_neon_add(size
, tmp
, tmp2
))
4318 case 0: gen_helper_neon_sub_u8(tmp
, tmp
, tmp2
); break;
4319 case 1: gen_helper_neon_sub_u16(tmp
, tmp
, tmp2
); break;
4320 case 2: tcg_gen_sub_i32(tmp
, tmp
, tmp2
); break;
4326 if (!u
) { /* VTST */
4328 case 0: gen_helper_neon_tst_u8(tmp
, tmp
, tmp2
); break;
4329 case 1: gen_helper_neon_tst_u16(tmp
, tmp
, tmp2
); break;
4330 case 2: gen_helper_neon_tst_u32(tmp
, tmp
, tmp2
); break;
4335 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
4336 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
4337 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
4342 case 18: /* Multiply. */
4344 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4345 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4346 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4350 tmp2
= neon_load_reg(rd
, pass
);
4352 gen_neon_rsb(size
, tmp
, tmp2
);
4354 gen_neon_add(size
, tmp
, tmp2
);
4358 if (u
) { /* polynomial */
4359 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
4360 } else { /* Integer */
4362 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4363 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4364 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4369 case 20: /* VPMAX */
4370 GEN_NEON_INTEGER_OP(pmax
);
4372 case 21: /* VPMIN */
4373 GEN_NEON_INTEGER_OP(pmin
);
4375 case 22: /* Hultiply high. */
4376 if (!u
) { /* VQDMULH */
4378 case 1: gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
); break;
4379 case 2: gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
); break;
4382 } else { /* VQRDHMUL */
4384 case 1: gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
); break;
4385 case 2: gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
); break;
4390 case 23: /* VPADD */
4394 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
4395 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
4396 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
4400 case 26: /* Floating point arithnetic. */
4401 switch ((u
<< 2) | size
) {
4403 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4406 gen_helper_neon_sub_f32(tmp
, tmp
, tmp2
);
4409 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4412 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
);
4418 case 27: /* Float multiply. */
4419 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
4422 tmp2
= neon_load_reg(rd
, pass
);
4424 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4426 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
4430 case 28: /* Float compare. */
4432 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
4435 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
4437 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
4440 case 29: /* Float compare absolute. */
4444 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
);
4446 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
);
4448 case 30: /* Float min/max. */
4450 gen_helper_neon_max_f32(tmp
, tmp
, tmp2
);
4452 gen_helper_neon_min_f32(tmp
, tmp
, tmp2
);
4456 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
4458 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
4465 /* Save the result. For elementwise operations we can put it
4466 straight into the destination register. For pairwise operations
4467 we have to be careful to avoid clobbering the source operands. */
4468 if (pairwise
&& rd
== rm
) {
4469 neon_store_scratch(pass
, tmp
);
4471 neon_store_reg(rd
, pass
, tmp
);
4475 if (pairwise
&& rd
== rm
) {
4476 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4477 tmp
= neon_load_scratch(pass
);
4478 neon_store_reg(rd
, pass
, tmp
);
4481 /* End of 3 register same size operations. */
4482 } else if (insn
& (1 << 4)) {
4483 if ((insn
& 0x00380080) != 0) {
4484 /* Two registers and shift. */
4485 op
= (insn
>> 8) & 0xf;
4486 if (insn
& (1 << 7)) {
4491 while ((insn
& (1 << (size
+ 19))) == 0)
4494 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
4495 /* To avoid excessive dumplication of ops we implement shift
4496 by immediate using the variable shift operations. */
4498 /* Shift by immediate:
4499 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4500 /* Right shifts are encoded as N - shift, where N is the
4501 element size in bits. */
4503 shift
= shift
- (1 << (size
+ 3));
4511 imm
= (uint8_t) shift
;
4516 imm
= (uint16_t) shift
;
4527 for (pass
= 0; pass
< count
; pass
++) {
4529 neon_load_reg64(cpu_V0
, rm
+ pass
);
4530 tcg_gen_movi_i64(cpu_V1
, imm
);
4535 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4537 gen_helper_neon_shl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4542 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4544 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4549 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4551 case 5: /* VSHL, VSLI */
4552 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4556 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
, cpu_V0
, cpu_V1
);
4558 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
, cpu_V0
, cpu_V1
);
4560 case 7: /* VQSHLU */
4561 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
, cpu_V0
, cpu_V1
);
4564 if (op
== 1 || op
== 3) {
4566 neon_load_reg64(cpu_V0
, rd
+ pass
);
4567 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
4568 } else if (op
== 4 || (op
== 5 && u
)) {
4570 cpu_abort(env
, "VS[LR]I.64 not implemented");
4572 neon_store_reg64(cpu_V0
, rd
+ pass
);
4573 } else { /* size < 3 */
4574 /* Operands in T0 and T1. */
4575 tmp
= neon_load_reg(rm
, pass
);
4577 tcg_gen_movi_i32(tmp2
, imm
);
4581 GEN_NEON_INTEGER_OP(shl
);
4585 GEN_NEON_INTEGER_OP(rshl
);
4590 GEN_NEON_INTEGER_OP(shl
);
4592 case 5: /* VSHL, VSLI */
4594 case 0: gen_helper_neon_shl_u8(tmp
, tmp
, tmp2
); break;
4595 case 1: gen_helper_neon_shl_u16(tmp
, tmp
, tmp2
); break;
4596 case 2: gen_helper_neon_shl_u32(tmp
, tmp
, tmp2
); break;
4601 GEN_NEON_INTEGER_OP_ENV(qshl
);
4603 case 7: /* VQSHLU */
4605 case 0: gen_helper_neon_qshl_u8(tmp
, cpu_env
, tmp
, tmp2
); break;
4606 case 1: gen_helper_neon_qshl_u16(tmp
, cpu_env
, tmp
, tmp2
); break;
4607 case 2: gen_helper_neon_qshl_u32(tmp
, cpu_env
, tmp
, tmp2
); break;
4614 if (op
== 1 || op
== 3) {
4616 tmp2
= neon_load_reg(rd
, pass
);
4617 gen_neon_add(size
, tmp2
, tmp
);
4619 } else if (op
== 4 || (op
== 5 && u
)) {
4624 imm
= 0xff >> -shift
;
4626 imm
= (uint8_t)(0xff << shift
);
4632 imm
= 0xffff >> -shift
;
4634 imm
= (uint16_t)(0xffff << shift
);
4639 imm
= 0xffffffffu
>> -shift
;
4641 imm
= 0xffffffffu
<< shift
;
4646 tmp2
= neon_load_reg(rd
, pass
);
4647 tcg_gen_andi_i32(tmp
, tmp
, imm
);
4648 tcg_gen_andi_i32(tmp2
, tmp2
, ~imm
);
4649 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4652 neon_store_reg(rd
, pass
, tmp
);
4655 } else if (op
< 10) {
4656 /* Shift by immediate and narrow:
4657 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4658 shift
= shift
- (1 << (size
+ 3));
4662 imm
= (uint16_t)shift
;
4664 tmp2
= tcg_const_i32(imm
);
4665 TCGV_UNUSED_I64(tmp64
);
4668 imm
= (uint32_t)shift
;
4669 tmp2
= tcg_const_i32(imm
);
4670 TCGV_UNUSED_I64(tmp64
);
4673 tmp64
= tcg_const_i64(shift
);
4680 for (pass
= 0; pass
< 2; pass
++) {
4682 neon_load_reg64(cpu_V0
, rm
+ pass
);
4685 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, tmp64
);
4687 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, tmp64
);
4690 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, tmp64
);
4692 gen_helper_neon_shl_s64(cpu_V0
, cpu_V0
, tmp64
);
4695 tmp
= neon_load_reg(rm
+ pass
, 0);
4696 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
, u
);
4697 tmp3
= neon_load_reg(rm
+ pass
, 1);
4698 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
, u
);
4699 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
4704 if (op
== 8 && !u
) {
4705 gen_neon_narrow(size
- 1, tmp
, cpu_V0
);
4708 gen_neon_narrow_sats(size
- 1, tmp
, cpu_V0
);
4710 gen_neon_narrow_satu(size
- 1, tmp
, cpu_V0
);
4712 neon_store_reg(rd
, pass
, tmp
);
4715 tcg_temp_free_i64(tmp64
);
4719 } else if (op
== 10) {
4723 tmp
= neon_load_reg(rm
, 0);
4724 tmp2
= neon_load_reg(rm
, 1);
4725 for (pass
= 0; pass
< 2; pass
++) {
4729 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
4732 /* The shift is less than the width of the source
4733 type, so we can just shift the whole register. */
4734 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
4735 if (size
< 2 || !u
) {
4738 imm
= (0xffu
>> (8 - shift
));
4741 imm
= 0xffff >> (16 - shift
);
4743 imm64
= imm
| (((uint64_t)imm
) << 32);
4744 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, imm64
);
4747 neon_store_reg64(cpu_V0
, rd
+ pass
);
4749 } else if (op
== 15 || op
== 16) {
4750 /* VCVT fixed-point. */
4751 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4752 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, pass
));
4755 gen_vfp_ulto(0, shift
);
4757 gen_vfp_slto(0, shift
);
4760 gen_vfp_toul(0, shift
);
4762 gen_vfp_tosl(0, shift
);
4764 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, pass
));
4769 } else { /* (insn & 0x00380080) == 0 */
4772 op
= (insn
>> 8) & 0xf;
4773 /* One register and immediate. */
4774 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
4775 invert
= (insn
& (1 << 5)) != 0;
4793 imm
= (imm
<< 8) | (imm
<< 24);
4796 imm
= (imm
< 8) | 0xff;
4799 imm
= (imm
<< 16) | 0xffff;
4802 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
4807 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
4808 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
4814 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4815 if (op
& 1 && op
< 12) {
4816 tmp
= neon_load_reg(rd
, pass
);
4818 /* The immediate value has already been inverted, so
4820 tcg_gen_andi_i32(tmp
, tmp
, imm
);
4822 tcg_gen_ori_i32(tmp
, tmp
, imm
);
4827 if (op
== 14 && invert
) {
4830 for (n
= 0; n
< 4; n
++) {
4831 if (imm
& (1 << (n
+ (pass
& 1) * 4)))
4832 val
|= 0xff << (n
* 8);
4834 tcg_gen_movi_i32(tmp
, val
);
4836 tcg_gen_movi_i32(tmp
, imm
);
4839 neon_store_reg(rd
, pass
, tmp
);
4842 } else { /* (insn & 0x00800010 == 0x00800000) */
4844 op
= (insn
>> 8) & 0xf;
4845 if ((insn
& (1 << 6)) == 0) {
4846 /* Three registers of different lengths. */
4850 /* prewiden, src1_wide, src2_wide */
4851 static const int neon_3reg_wide
[16][3] = {
4852 {1, 0, 0}, /* VADDL */
4853 {1, 1, 0}, /* VADDW */
4854 {1, 0, 0}, /* VSUBL */
4855 {1, 1, 0}, /* VSUBW */
4856 {0, 1, 1}, /* VADDHN */
4857 {0, 0, 0}, /* VABAL */
4858 {0, 1, 1}, /* VSUBHN */
4859 {0, 0, 0}, /* VABDL */
4860 {0, 0, 0}, /* VMLAL */
4861 {0, 0, 0}, /* VQDMLAL */
4862 {0, 0, 0}, /* VMLSL */
4863 {0, 0, 0}, /* VQDMLSL */
4864 {0, 0, 0}, /* Integer VMULL */
4865 {0, 0, 0}, /* VQDMULL */
4866 {0, 0, 0} /* Polynomial VMULL */
4869 prewiden
= neon_3reg_wide
[op
][0];
4870 src1_wide
= neon_3reg_wide
[op
][1];
4871 src2_wide
= neon_3reg_wide
[op
][2];
4873 if (size
== 0 && (op
== 9 || op
== 11 || op
== 13))
4876 /* Avoid overlapping operands. Wide source operands are
4877 always aligned so will never overlap with wide
4878 destinations in problematic ways. */
4879 if (rd
== rm
&& !src2_wide
) {
4880 tmp
= neon_load_reg(rm
, 1);
4881 neon_store_scratch(2, tmp
);
4882 } else if (rd
== rn
&& !src1_wide
) {
4883 tmp
= neon_load_reg(rn
, 1);
4884 neon_store_scratch(2, tmp
);
4887 for (pass
= 0; pass
< 2; pass
++) {
4889 neon_load_reg64(cpu_V0
, rn
+ pass
);
4892 if (pass
== 1 && rd
== rn
) {
4893 tmp
= neon_load_scratch(2);
4895 tmp
= neon_load_reg(rn
, pass
);
4898 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
4902 neon_load_reg64(cpu_V1
, rm
+ pass
);
4905 if (pass
== 1 && rd
== rm
) {
4906 tmp2
= neon_load_scratch(2);
4908 tmp2
= neon_load_reg(rm
, pass
);
4911 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
4915 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
4916 gen_neon_addl(size
);
4918 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHL, VRSUBHL */
4919 gen_neon_subl(size
);
4921 case 5: case 7: /* VABAL, VABDL */
4922 switch ((size
<< 1) | u
) {
4924 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
4927 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
4930 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
4933 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
4936 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
4939 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
4946 case 8: case 9: case 10: case 11: case 12: case 13:
4947 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
4948 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
4952 case 14: /* Polynomial VMULL */
4953 cpu_abort(env
, "Polynomial VMULL not implemented");
4955 default: /* 15 is RESERVED. */
4958 if (op
== 5 || op
== 13 || (op
>= 8 && op
<= 11)) {
4960 if (op
== 10 || op
== 11) {
4961 gen_neon_negl(cpu_V0
, size
);
4965 neon_load_reg64(cpu_V1
, rd
+ pass
);
4969 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
4970 gen_neon_addl(size
);
4972 case 9: case 11: /* VQDMLAL, VQDMLSL */
4973 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
4974 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
4977 case 13: /* VQDMULL */
4978 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
4983 neon_store_reg64(cpu_V0
, rd
+ pass
);
4984 } else if (op
== 4 || op
== 6) {
4985 /* Narrowing operation. */
4990 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
4993 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
4996 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
4997 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5004 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
5007 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
5010 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
5011 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
5012 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5020 neon_store_reg(rd
, 0, tmp3
);
5021 neon_store_reg(rd
, 1, tmp
);
5024 /* Write back the result. */
5025 neon_store_reg64(cpu_V0
, rd
+ pass
);
5029 /* Two registers and a scalar. */
5031 case 0: /* Integer VMLA scalar */
5032 case 1: /* Float VMLA scalar */
5033 case 4: /* Integer VMLS scalar */
5034 case 5: /* Floating point VMLS scalar */
5035 case 8: /* Integer VMUL scalar */
5036 case 9: /* Floating point VMUL scalar */
5037 case 12: /* VQDMULH scalar */
5038 case 13: /* VQRDMULH scalar */
5039 tmp
= neon_get_scalar(size
, rm
);
5040 neon_store_scratch(0, tmp
);
5041 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
5042 tmp
= neon_load_scratch(0);
5043 tmp2
= neon_load_reg(rn
, pass
);
5046 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5048 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5050 } else if (op
== 13) {
5052 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5054 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5056 } else if (op
& 1) {
5057 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
5060 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5061 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5062 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5069 tmp2
= neon_load_reg(rd
, pass
);
5072 gen_neon_add(size
, tmp
, tmp2
);
5075 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
5078 gen_neon_rsb(size
, tmp
, tmp2
);
5081 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
5088 neon_store_reg(rd
, pass
, tmp
);
5091 case 2: /* VMLAL sclar */
5092 case 3: /* VQDMLAL scalar */
5093 case 6: /* VMLSL scalar */
5094 case 7: /* VQDMLSL scalar */
5095 case 10: /* VMULL scalar */
5096 case 11: /* VQDMULL scalar */
5097 if (size
== 0 && (op
== 3 || op
== 7 || op
== 11))
5100 tmp2
= neon_get_scalar(size
, rm
);
5101 tmp3
= neon_load_reg(rn
, 1);
5103 for (pass
= 0; pass
< 2; pass
++) {
5105 tmp
= neon_load_reg(rn
, 0);
5109 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5111 if (op
== 6 || op
== 7) {
5112 gen_neon_negl(cpu_V0
, size
);
5115 neon_load_reg64(cpu_V1
, rd
+ pass
);
5119 gen_neon_addl(size
);
5122 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5123 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5129 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5134 neon_store_reg64(cpu_V0
, rd
+ pass
);
5140 default: /* 14 and 15 are RESERVED */
5144 } else { /* size == 3 */
5147 imm
= (insn
>> 8) & 0xf;
5154 neon_load_reg64(cpu_V0
, rn
);
5156 neon_load_reg64(cpu_V1
, rn
+ 1);
5158 } else if (imm
== 8) {
5159 neon_load_reg64(cpu_V0
, rn
+ 1);
5161 neon_load_reg64(cpu_V1
, rm
);
5164 tmp64
= tcg_temp_new_i64();
5166 neon_load_reg64(cpu_V0
, rn
);
5167 neon_load_reg64(tmp64
, rn
+ 1);
5169 neon_load_reg64(cpu_V0
, rn
+ 1);
5170 neon_load_reg64(tmp64
, rm
);
5172 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
5173 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
5174 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5176 neon_load_reg64(cpu_V1
, rm
);
5178 neon_load_reg64(cpu_V1
, rm
+ 1);
5181 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5182 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
5183 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
5184 tcg_temp_free_i64(tmp64
);
5187 neon_load_reg64(cpu_V0
, rn
);
5188 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
5189 neon_load_reg64(cpu_V1
, rm
);
5190 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5191 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5193 neon_store_reg64(cpu_V0
, rd
);
5195 neon_store_reg64(cpu_V1
, rd
+ 1);
5197 } else if ((insn
& (1 << 11)) == 0) {
5198 /* Two register misc. */
5199 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
5200 size
= (insn
>> 18) & 3;
5202 case 0: /* VREV64 */
5205 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5206 tmp
= neon_load_reg(rm
, pass
* 2);
5207 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
5209 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5210 case 1: gen_swap_half(tmp
); break;
5211 case 2: /* no-op */ break;
5214 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
5216 neon_store_reg(rd
, pass
* 2, tmp2
);
5219 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
5220 case 1: gen_swap_half(tmp2
); break;
5223 neon_store_reg(rd
, pass
* 2, tmp2
);
5227 case 4: case 5: /* VPADDL */
5228 case 12: case 13: /* VPADAL */
5231 for (pass
= 0; pass
< q
+ 1; pass
++) {
5232 tmp
= neon_load_reg(rm
, pass
* 2);
5233 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
5234 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
5235 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
5237 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
5238 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
5239 case 2: tcg_gen_add_i64(CPU_V001
); break;
5244 neon_load_reg64(cpu_V1
, rd
+ pass
);
5245 gen_neon_addl(size
);
5247 neon_store_reg64(cpu_V0
, rd
+ pass
);
5252 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
5253 tmp
= neon_load_reg(rm
, n
);
5254 tmp2
= neon_load_reg(rd
, n
+ 1);
5255 neon_store_reg(rm
, n
, tmp2
);
5256 neon_store_reg(rd
, n
+ 1, tmp
);
5264 Rd A3 A2 A1 A0 B2 B0 A2 A0
5265 Rm B3 B2 B1 B0 B3 B1 A3 A1
5269 gen_neon_unzip(rd
, q
, 0, size
);
5270 gen_neon_unzip(rm
, q
, 4, size
);
5272 static int unzip_order_q
[8] =
5273 {0, 2, 4, 6, 1, 3, 5, 7};
5274 for (n
= 0; n
< 8; n
++) {
5275 int reg
= (n
< 4) ? rd
: rm
;
5276 tmp
= neon_load_scratch(unzip_order_q
[n
]);
5277 neon_store_reg(reg
, n
% 4, tmp
);
5280 static int unzip_order
[4] =
5282 for (n
= 0; n
< 4; n
++) {
5283 int reg
= (n
< 2) ? rd
: rm
;
5284 tmp
= neon_load_scratch(unzip_order
[n
]);
5285 neon_store_reg(reg
, n
% 2, tmp
);
5291 Rd A3 A2 A1 A0 B1 A1 B0 A0
5292 Rm B3 B2 B1 B0 B3 A3 B2 A2
5296 count
= (q
? 4 : 2);
5297 for (n
= 0; n
< count
; n
++) {
5298 tmp
= neon_load_reg(rd
, n
);
5299 tmp2
= neon_load_reg(rd
, n
);
5301 case 0: gen_neon_zip_u8(tmp
, tmp2
); break;
5302 case 1: gen_neon_zip_u16(tmp
, tmp2
); break;
5303 case 2: /* no-op */; break;
5306 neon_store_scratch(n
* 2, tmp
);
5307 neon_store_scratch(n
* 2 + 1, tmp2
);
5309 for (n
= 0; n
< count
* 2; n
++) {
5310 int reg
= (n
< count
) ? rd
: rm
;
5311 tmp
= neon_load_scratch(n
);
5312 neon_store_reg(reg
, n
% count
, tmp
);
5315 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5319 for (pass
= 0; pass
< 2; pass
++) {
5320 neon_load_reg64(cpu_V0
, rm
+ pass
);
5322 if (op
== 36 && q
== 0) {
5323 gen_neon_narrow(size
, tmp
, cpu_V0
);
5325 gen_neon_narrow_satu(size
, tmp
, cpu_V0
);
5327 gen_neon_narrow_sats(size
, tmp
, cpu_V0
);
5332 neon_store_reg(rd
, 0, tmp2
);
5333 neon_store_reg(rd
, 1, tmp
);
5337 case 38: /* VSHLL */
5340 tmp
= neon_load_reg(rm
, 0);
5341 tmp2
= neon_load_reg(rm
, 1);
5342 for (pass
= 0; pass
< 2; pass
++) {
5345 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
5346 neon_store_reg64(cpu_V0
, rd
+ pass
);
5351 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5352 if (op
== 30 || op
== 31 || op
>= 58) {
5353 tcg_gen_ld_f32(cpu_F0s
, cpu_env
,
5354 neon_reg_offset(rm
, pass
));
5357 tmp
= neon_load_reg(rm
, pass
);
5360 case 1: /* VREV32 */
5362 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5363 case 1: gen_swap_half(tmp
); break;
5367 case 2: /* VREV16 */
5374 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
5375 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
5376 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
5382 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
5383 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
5384 case 2: gen_helper_clz(tmp
, tmp
); break;
5391 gen_helper_neon_cnt_u8(tmp
, tmp
);
5396 tcg_gen_not_i32(tmp
, tmp
);
5398 case 14: /* VQABS */
5400 case 0: gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
); break;
5401 case 1: gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
); break;
5402 case 2: gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
); break;
5406 case 15: /* VQNEG */
5408 case 0: gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
); break;
5409 case 1: gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
); break;
5410 case 2: gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
); break;
5414 case 16: case 19: /* VCGT #0, VCLE #0 */
5415 tmp2
= tcg_const_i32(0);
5417 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
5418 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
5419 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
5422 tcg_temp_free(tmp2
);
5424 tcg_gen_not_i32(tmp
, tmp
);
5426 case 17: case 20: /* VCGE #0, VCLT #0 */
5427 tmp2
= tcg_const_i32(0);
5429 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
5430 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
5431 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
5434 tcg_temp_free(tmp2
);
5436 tcg_gen_not_i32(tmp
, tmp
);
5438 case 18: /* VCEQ #0 */
5439 tmp2
= tcg_const_i32(0);
5441 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
5442 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
5443 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
5446 tcg_temp_free(tmp2
);
5450 case 0: gen_helper_neon_abs_s8(tmp
, tmp
); break;
5451 case 1: gen_helper_neon_abs_s16(tmp
, tmp
); break;
5452 case 2: tcg_gen_abs_i32(tmp
, tmp
); break;
5459 tmp2
= tcg_const_i32(0);
5460 gen_neon_rsb(size
, tmp
, tmp2
);
5461 tcg_temp_free(tmp2
);
5463 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5464 tmp2
= tcg_const_i32(0);
5465 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
5466 tcg_temp_free(tmp2
);
5468 tcg_gen_not_i32(tmp
, tmp
);
5470 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5471 tmp2
= tcg_const_i32(0);
5472 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
5473 tcg_temp_free(tmp2
);
5475 tcg_gen_not_i32(tmp
, tmp
);
5477 case 26: /* Float VCEQ #0 */
5478 tmp2
= tcg_const_i32(0);
5479 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
5480 tcg_temp_free(tmp2
);
5482 case 30: /* Float VABS */
5485 case 31: /* Float VNEG */
5489 tmp2
= neon_load_reg(rd
, pass
);
5490 neon_store_reg(rm
, pass
, tmp2
);
5493 tmp2
= neon_load_reg(rd
, pass
);
5495 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
5496 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
5500 neon_store_reg(rm
, pass
, tmp2
);
5502 case 56: /* Integer VRECPE */
5503 gen_helper_recpe_u32(tmp
, tmp
, cpu_env
);
5505 case 57: /* Integer VRSQRTE */
5506 gen_helper_rsqrte_u32(tmp
, tmp
, cpu_env
);
5508 case 58: /* Float VRECPE */
5509 gen_helper_recpe_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
5511 case 59: /* Float VRSQRTE */
5512 gen_helper_rsqrte_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
5514 case 60: /* VCVT.F32.S32 */
5517 case 61: /* VCVT.F32.U32 */
5520 case 62: /* VCVT.S32.F32 */
5523 case 63: /* VCVT.U32.F32 */
5527 /* Reserved: 21, 29, 39-56 */
5530 if (op
== 30 || op
== 31 || op
>= 58) {
5531 tcg_gen_st_f32(cpu_F0s
, cpu_env
,
5532 neon_reg_offset(rd
, pass
));
5534 neon_store_reg(rd
, pass
, tmp
);
5539 } else if ((insn
& (1 << 10)) == 0) {
5541 n
= ((insn
>> 5) & 0x18) + 8;
5542 if (insn
& (1 << 6)) {
5543 tmp
= neon_load_reg(rd
, 0);
5546 tcg_gen_movi_i32(tmp
, 0);
5548 tmp2
= neon_load_reg(rm
, 0);
5549 tmp4
= tcg_const_i32(rn
);
5550 tmp5
= tcg_const_i32(n
);
5551 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, tmp4
, tmp5
);
5553 if (insn
& (1 << 6)) {
5554 tmp
= neon_load_reg(rd
, 1);
5557 tcg_gen_movi_i32(tmp
, 0);
5559 tmp3
= neon_load_reg(rm
, 1);
5560 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, tmp4
, tmp5
);
5561 tcg_temp_free_i32(tmp5
);
5562 tcg_temp_free_i32(tmp4
);
5563 neon_store_reg(rd
, 0, tmp2
);
5564 neon_store_reg(rd
, 1, tmp3
);
5566 } else if ((insn
& 0x380) == 0) {
5568 if (insn
& (1 << 19)) {
5569 tmp
= neon_load_reg(rm
, 1);
5571 tmp
= neon_load_reg(rm
, 0);
5573 if (insn
& (1 << 16)) {
5574 gen_neon_dup_u8(tmp
, ((insn
>> 17) & 3) * 8);
5575 } else if (insn
& (1 << 17)) {
5576 if ((insn
>> 18) & 1)
5577 gen_neon_dup_high16(tmp
);
5579 gen_neon_dup_low16(tmp
);
5581 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5583 tcg_gen_mov_i32(tmp2
, tmp
);
5584 neon_store_reg(rd
, pass
, tmp2
);
5595 static int disas_cp14_read(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5597 int crn
= (insn
>> 16) & 0xf;
5598 int crm
= insn
& 0xf;
5599 int op1
= (insn
>> 21) & 7;
5600 int op2
= (insn
>> 5) & 7;
5601 int rt
= (insn
>> 12) & 0xf;
5604 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5605 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
5609 tmp
= load_cpu_field(teecr
);
5610 store_reg(s
, rt
, tmp
);
5613 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
5615 if (IS_USER(s
) && (env
->teecr
& 1))
5617 tmp
= load_cpu_field(teehbr
);
5618 store_reg(s
, rt
, tmp
);
5622 fprintf(stderr
, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5623 op1
, crn
, crm
, op2
);
5627 static int disas_cp14_write(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5629 int crn
= (insn
>> 16) & 0xf;
5630 int crm
= insn
& 0xf;
5631 int op1
= (insn
>> 21) & 7;
5632 int op2
= (insn
>> 5) & 7;
5633 int rt
= (insn
>> 12) & 0xf;
5636 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5637 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
5641 tmp
= load_reg(s
, rt
);
5642 gen_helper_set_teecr(cpu_env
, tmp
);
5646 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
5648 if (IS_USER(s
) && (env
->teecr
& 1))
5650 tmp
= load_reg(s
, rt
);
5651 store_cpu_field(tmp
, teehbr
);
5655 fprintf(stderr
, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5656 op1
, crn
, crm
, op2
);
5660 static int disas_coproc_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
5664 cpnum
= (insn
>> 8) & 0xf;
5665 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
5666 && ((env
->cp15
.c15_cpar
^ 0x3fff) & (1 << cpnum
)))
5672 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
5673 return disas_iwmmxt_insn(env
, s
, insn
);
5674 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5675 return disas_dsp_insn(env
, s
, insn
);
5680 return disas_vfp_insn (env
, s
, insn
);
5682 /* Coprocessors 7-15 are architecturally reserved by ARM.
5683 Unfortunately Intel decided to ignore this. */
5684 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
5686 if (insn
& (1 << 20))
5687 return disas_cp14_read(env
, s
, insn
);
5689 return disas_cp14_write(env
, s
, insn
);
5691 return disas_cp15_insn (env
, s
, insn
);
5694 /* Unknown coprocessor. See if the board has hooked it. */
5695 return disas_cp_insn (env
, s
, insn
);
5700 /* Store a 64-bit value to a register pair. Clobbers val. */
5701 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
5705 tcg_gen_trunc_i64_i32(tmp
, val
);
5706 store_reg(s
, rlow
, tmp
);
5708 tcg_gen_shri_i64(val
, val
, 32);
5709 tcg_gen_trunc_i64_i32(tmp
, val
);
5710 store_reg(s
, rhigh
, tmp
);
5713 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5714 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
5719 /* Load value and extend to 64 bits. */
5720 tmp
= tcg_temp_new_i64();
5721 tmp2
= load_reg(s
, rlow
);
5722 tcg_gen_extu_i32_i64(tmp
, tmp2
);
5724 tcg_gen_add_i64(val
, val
, tmp
);
5725 tcg_temp_free_i64(tmp
);
5728 /* load and add a 64-bit value from a register pair. */
5729 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
5735 /* Load 64-bit value rd:rn. */
5736 tmpl
= load_reg(s
, rlow
);
5737 tmph
= load_reg(s
, rhigh
);
5738 tmp
= tcg_temp_new_i64();
5739 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
5742 tcg_gen_add_i64(val
, val
, tmp
);
5743 tcg_temp_free_i64(tmp
);
5746 /* Set N and Z flags from a 64-bit value. */
5747 static void gen_logicq_cc(TCGv_i64 val
)
5749 TCGv tmp
= new_tmp();
5750 gen_helper_logicq_cc(tmp
, val
);
5755 static void disas_arm_insn(CPUState
* env
, DisasContext
*s
)
5757 unsigned int cond
, insn
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
5764 insn
= ldl_code(s
->pc
);
5767 /* M variants do not implement ARM mode. */
5772 /* Unconditional instructions. */
5773 if (((insn
>> 25) & 7) == 1) {
5774 /* NEON Data processing. */
5775 if (!arm_feature(env
, ARM_FEATURE_NEON
))
5778 if (disas_neon_data_insn(env
, s
, insn
))
5782 if ((insn
& 0x0f100000) == 0x04000000) {
5783 /* NEON load/store. */
5784 if (!arm_feature(env
, ARM_FEATURE_NEON
))
5787 if (disas_neon_ls_insn(env
, s
, insn
))
5791 if ((insn
& 0x0d70f000) == 0x0550f000)
5793 else if ((insn
& 0x0ffffdff) == 0x01010000) {
5796 if (insn
& (1 << 9)) {
5797 /* BE8 mode not implemented. */
5801 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
5802 switch ((insn
>> 4) & 0xf) {
5805 gen_helper_clrex(cpu_env
);
5811 /* We don't emulate caches so these are a no-op. */
5816 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
5822 op1
= (insn
& 0x1f);
5823 if (op1
== (env
->uncached_cpsr
& CPSR_M
)) {
5824 addr
= load_reg(s
, 13);
5827 tmp
= tcg_const_i32(op1
);
5828 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
5829 tcg_temp_free_i32(tmp
);
5831 i
= (insn
>> 23) & 3;
5833 case 0: offset
= -4; break; /* DA */
5834 case 1: offset
= 0; break; /* IA */
5835 case 2: offset
= -8; break; /* DB */
5836 case 3: offset
= 4; break; /* IB */
5840 tcg_gen_addi_i32(addr
, addr
, offset
);
5841 tmp
= load_reg(s
, 14);
5842 gen_st32(tmp
, addr
, 0);
5843 tmp
= load_cpu_field(spsr
);
5844 tcg_gen_addi_i32(addr
, addr
, 4);
5845 gen_st32(tmp
, addr
, 0);
5846 if (insn
& (1 << 21)) {
5847 /* Base writeback. */
5849 case 0: offset
= -8; break;
5850 case 1: offset
= 4; break;
5851 case 2: offset
= -4; break;
5852 case 3: offset
= 0; break;
5856 tcg_gen_addi_i32(addr
, addr
, offset
);
5857 if (op1
== (env
->uncached_cpsr
& CPSR_M
)) {
5858 store_reg(s
, 13, addr
);
5860 tmp
= tcg_const_i32(op1
);
5861 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
5862 tcg_temp_free_i32(tmp
);
5868 } else if ((insn
& 0x0e5fffe0) == 0x081d0a00) {
5874 rn
= (insn
>> 16) & 0xf;
5875 addr
= load_reg(s
, rn
);
5876 i
= (insn
>> 23) & 3;
5878 case 0: offset
= -4; break; /* DA */
5879 case 1: offset
= 0; break; /* IA */
5880 case 2: offset
= -8; break; /* DB */
5881 case 3: offset
= 4; break; /* IB */
5885 tcg_gen_addi_i32(addr
, addr
, offset
);
5886 /* Load PC into tmp and CPSR into tmp2. */
5887 tmp
= gen_ld32(addr
, 0);
5888 tcg_gen_addi_i32(addr
, addr
, 4);
5889 tmp2
= gen_ld32(addr
, 0);
5890 if (insn
& (1 << 21)) {
5891 /* Base writeback. */
5893 case 0: offset
= -8; break;
5894 case 1: offset
= 4; break;
5895 case 2: offset
= -4; break;
5896 case 3: offset
= 0; break;
5900 tcg_gen_addi_i32(addr
, addr
, offset
);
5901 store_reg(s
, rn
, addr
);
5905 gen_rfe(s
, tmp
, tmp2
);
5907 } else if ((insn
& 0x0e000000) == 0x0a000000) {
5908 /* branch link and change to thumb (blx <offset>) */
5911 val
= (uint32_t)s
->pc
;
5913 tcg_gen_movi_i32(tmp
, val
);
5914 store_reg(s
, 14, tmp
);
5915 /* Sign-extend the 24-bit offset */
5916 offset
= (((int32_t)insn
) << 8) >> 8;
5917 /* offset * 4 + bit24 * 2 + (thumb bit) */
5918 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
5919 /* pipeline offset */
5923 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
5924 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
5925 /* iWMMXt register transfer. */
5926 if (env
->cp15
.c15_cpar
& (1 << 1))
5927 if (!disas_iwmmxt_insn(env
, s
, insn
))
5930 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
5931 /* Coprocessor double register transfer. */
5932 } else if ((insn
& 0x0f000010) == 0x0e000010) {
5933 /* Additional coprocessor register transfer. */
5934 } else if ((insn
& 0x0ff10020) == 0x01000000) {
5937 /* cps (privileged) */
5941 if (insn
& (1 << 19)) {
5942 if (insn
& (1 << 8))
5944 if (insn
& (1 << 7))
5946 if (insn
& (1 << 6))
5948 if (insn
& (1 << 18))
5951 if (insn
& (1 << 17)) {
5953 val
|= (insn
& 0x1f);
5956 gen_set_psr_im(s
, mask
, 0, val
);
5963 /* if not always execute, we generate a conditional jump to
5965 s
->condlabel
= gen_new_label();
5966 gen_test_cc(cond
^ 1, s
->condlabel
);
5969 if ((insn
& 0x0f900000) == 0x03000000) {
5970 if ((insn
& (1 << 21)) == 0) {
5972 rd
= (insn
>> 12) & 0xf;
5973 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
5974 if ((insn
& (1 << 22)) == 0) {
5977 tcg_gen_movi_i32(tmp
, val
);
5980 tmp
= load_reg(s
, rd
);
5981 tcg_gen_ext16u_i32(tmp
, tmp
);
5982 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
5984 store_reg(s
, rd
, tmp
);
5986 if (((insn
>> 12) & 0xf) != 0xf)
5988 if (((insn
>> 16) & 0xf) == 0) {
5989 gen_nop_hint(s
, insn
& 0xff);
5991 /* CPSR = immediate */
5993 shift
= ((insn
>> 8) & 0xf) * 2;
5995 val
= (val
>> shift
) | (val
<< (32 - shift
));
5996 i
= ((insn
& (1 << 22)) != 0);
5997 if (gen_set_psr_im(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, val
))
6001 } else if ((insn
& 0x0f900000) == 0x01000000
6002 && (insn
& 0x00000090) != 0x00000090) {
6003 /* miscellaneous instructions */
6004 op1
= (insn
>> 21) & 3;
6005 sh
= (insn
>> 4) & 0xf;
6008 case 0x0: /* move program status register */
6011 tmp
= load_reg(s
, rm
);
6012 i
= ((op1
& 2) != 0);
6013 if (gen_set_psr(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
6017 rd
= (insn
>> 12) & 0xf;
6021 tmp
= load_cpu_field(spsr
);
6024 gen_helper_cpsr_read(tmp
);
6026 store_reg(s
, rd
, tmp
);
6031 /* branch/exchange thumb (bx). */
6032 tmp
= load_reg(s
, rm
);
6034 } else if (op1
== 3) {
6036 rd
= (insn
>> 12) & 0xf;
6037 tmp
= load_reg(s
, rm
);
6038 gen_helper_clz(tmp
, tmp
);
6039 store_reg(s
, rd
, tmp
);
6047 /* Trivial implementation equivalent to bx. */
6048 tmp
= load_reg(s
, rm
);
6058 /* branch link/exchange thumb (blx) */
6059 tmp
= load_reg(s
, rm
);
6061 tcg_gen_movi_i32(tmp2
, s
->pc
);
6062 store_reg(s
, 14, tmp2
);
6065 case 0x5: /* saturating add/subtract */
6066 rd
= (insn
>> 12) & 0xf;
6067 rn
= (insn
>> 16) & 0xf;
6068 tmp
= load_reg(s
, rm
);
6069 tmp2
= load_reg(s
, rn
);
6071 gen_helper_double_saturate(tmp2
, tmp2
);
6073 gen_helper_sub_saturate(tmp
, tmp
, tmp2
);
6075 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
6077 store_reg(s
, rd
, tmp
);
6080 gen_set_condexec(s
);
6081 gen_set_pc_im(s
->pc
- 4);
6082 gen_exception(EXCP_BKPT
);
6083 s
->is_jmp
= DISAS_JUMP
;
6085 case 0x8: /* signed multiply */
6089 rs
= (insn
>> 8) & 0xf;
6090 rn
= (insn
>> 12) & 0xf;
6091 rd
= (insn
>> 16) & 0xf;
6093 /* (32 * 16) >> 16 */
6094 tmp
= load_reg(s
, rm
);
6095 tmp2
= load_reg(s
, rs
);
6097 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
6100 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6101 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
6103 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
6104 tcg_temp_free_i64(tmp64
);
6105 if ((sh
& 2) == 0) {
6106 tmp2
= load_reg(s
, rn
);
6107 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6110 store_reg(s
, rd
, tmp
);
6113 tmp
= load_reg(s
, rm
);
6114 tmp2
= load_reg(s
, rs
);
6115 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
6118 tmp64
= tcg_temp_new_i64();
6119 tcg_gen_ext_i32_i64(tmp64
, tmp
);
6121 gen_addq(s
, tmp64
, rn
, rd
);
6122 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6123 tcg_temp_free_i64(tmp64
);
6126 tmp2
= load_reg(s
, rn
);
6127 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6130 store_reg(s
, rd
, tmp
);
6137 } else if (((insn
& 0x0e000000) == 0 &&
6138 (insn
& 0x00000090) != 0x90) ||
6139 ((insn
& 0x0e000000) == (1 << 25))) {
6140 int set_cc
, logic_cc
, shiftop
;
6142 op1
= (insn
>> 21) & 0xf;
6143 set_cc
= (insn
>> 20) & 1;
6144 logic_cc
= table_logic_cc
[op1
] & set_cc
;
6146 /* data processing instruction */
6147 if (insn
& (1 << 25)) {
6148 /* immediate operand */
6150 shift
= ((insn
>> 8) & 0xf) * 2;
6152 val
= (val
>> shift
) | (val
<< (32 - shift
));
6155 tcg_gen_movi_i32(tmp2
, val
);
6156 if (logic_cc
&& shift
) {
6157 gen_set_CF_bit31(tmp2
);
6162 tmp2
= load_reg(s
, rm
);
6163 shiftop
= (insn
>> 5) & 3;
6164 if (!(insn
& (1 << 4))) {
6165 shift
= (insn
>> 7) & 0x1f;
6166 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
6168 rs
= (insn
>> 8) & 0xf;
6169 tmp
= load_reg(s
, rs
);
6170 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
6173 if (op1
!= 0x0f && op1
!= 0x0d) {
6174 rn
= (insn
>> 16) & 0xf;
6175 tmp
= load_reg(s
, rn
);
6179 rd
= (insn
>> 12) & 0xf;
6182 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6186 store_reg_bx(env
, s
, rd
, tmp
);
6189 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6193 store_reg_bx(env
, s
, rd
, tmp
);
6196 if (set_cc
&& rd
== 15) {
6197 /* SUBS r15, ... is used for exception return. */
6201 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6202 gen_exception_return(s
, tmp
);
6205 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6207 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
6209 store_reg_bx(env
, s
, rd
, tmp
);
6214 gen_helper_sub_cc(tmp
, tmp2
, tmp
);
6216 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
6218 store_reg_bx(env
, s
, rd
, tmp
);
6222 gen_helper_add_cc(tmp
, tmp
, tmp2
);
6224 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6226 store_reg_bx(env
, s
, rd
, tmp
);
6230 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
6232 gen_add_carry(tmp
, tmp
, tmp2
);
6234 store_reg_bx(env
, s
, rd
, tmp
);
6238 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
6240 gen_sub_carry(tmp
, tmp
, tmp2
);
6242 store_reg_bx(env
, s
, rd
, tmp
);
6246 gen_helper_sbc_cc(tmp
, tmp2
, tmp
);
6248 gen_sub_carry(tmp
, tmp2
, tmp
);
6250 store_reg_bx(env
, s
, rd
, tmp
);
6254 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6261 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6268 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6274 gen_helper_add_cc(tmp
, tmp
, tmp2
);
6279 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
6283 store_reg_bx(env
, s
, rd
, tmp
);
6286 if (logic_cc
&& rd
== 15) {
6287 /* MOVS r15, ... is used for exception return. */
6291 gen_exception_return(s
, tmp2
);
6296 store_reg_bx(env
, s
, rd
, tmp2
);
6300 tcg_gen_bic_i32(tmp
, tmp
, tmp2
);
6304 store_reg_bx(env
, s
, rd
, tmp
);
6308 tcg_gen_not_i32(tmp2
, tmp2
);
6312 store_reg_bx(env
, s
, rd
, tmp2
);
6315 if (op1
!= 0x0f && op1
!= 0x0d) {
6319 /* other instructions */
6320 op1
= (insn
>> 24) & 0xf;
6324 /* multiplies, extra load/stores */
6325 sh
= (insn
>> 5) & 3;
6328 rd
= (insn
>> 16) & 0xf;
6329 rn
= (insn
>> 12) & 0xf;
6330 rs
= (insn
>> 8) & 0xf;
6332 op1
= (insn
>> 20) & 0xf;
6334 case 0: case 1: case 2: case 3: case 6:
6336 tmp
= load_reg(s
, rs
);
6337 tmp2
= load_reg(s
, rm
);
6338 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
6340 if (insn
& (1 << 22)) {
6341 /* Subtract (mls) */
6343 tmp2
= load_reg(s
, rn
);
6344 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
6346 } else if (insn
& (1 << 21)) {
6348 tmp2
= load_reg(s
, rn
);
6349 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6352 if (insn
& (1 << 20))
6354 store_reg(s
, rd
, tmp
);
6358 tmp
= load_reg(s
, rs
);
6359 tmp2
= load_reg(s
, rm
);
6360 if (insn
& (1 << 22))
6361 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6363 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
6364 if (insn
& (1 << 21)) /* mult accumulate */
6365 gen_addq(s
, tmp64
, rn
, rd
);
6366 if (!(insn
& (1 << 23))) { /* double accumulate */
6368 gen_addq_lo(s
, tmp64
, rn
);
6369 gen_addq_lo(s
, tmp64
, rd
);
6371 if (insn
& (1 << 20))
6372 gen_logicq_cc(tmp64
);
6373 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6374 tcg_temp_free_i64(tmp64
);
6378 rn
= (insn
>> 16) & 0xf;
6379 rd
= (insn
>> 12) & 0xf;
6380 if (insn
& (1 << 23)) {
6381 /* load/store exclusive */
6382 op1
= (insn
>> 21) & 0x3;
6387 addr
= tcg_temp_local_new_i32();
6388 load_reg_var(s
, addr
, rn
);
6389 if (insn
& (1 << 20)) {
6390 gen_helper_mark_exclusive(cpu_env
, addr
);
6393 tmp
= gen_ld32(addr
, IS_USER(s
));
6395 case 1: /* ldrexd */
6396 tmp
= gen_ld32(addr
, IS_USER(s
));
6397 store_reg(s
, rd
, tmp
);
6398 tcg_gen_addi_i32(addr
, addr
, 4);
6399 tmp
= gen_ld32(addr
, IS_USER(s
));
6402 case 2: /* ldrexb */
6403 tmp
= gen_ld8u(addr
, IS_USER(s
));
6405 case 3: /* ldrexh */
6406 tmp
= gen_ld16u(addr
, IS_USER(s
));
6411 store_reg(s
, rd
, tmp
);
6413 int label
= gen_new_label();
6415 tmp2
= tcg_temp_local_new_i32();
6416 gen_helper_test_exclusive(tmp2
, cpu_env
, addr
);
6417 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp2
, 0, label
);
6418 tmp
= load_reg(s
,rm
);
6421 gen_st32(tmp
, addr
, IS_USER(s
));
6423 case 1: /* strexd */
6424 gen_st32(tmp
, addr
, IS_USER(s
));
6425 tcg_gen_addi_i32(addr
, addr
, 4);
6426 tmp
= load_reg(s
, rm
+ 1);
6427 gen_st32(tmp
, addr
, IS_USER(s
));
6429 case 2: /* strexb */
6430 gen_st8(tmp
, addr
, IS_USER(s
));
6432 case 3: /* strexh */
6433 gen_st16(tmp
, addr
, IS_USER(s
));
6438 gen_set_label(label
);
6439 tcg_gen_mov_i32(cpu_R
[rd
], tmp2
);
6440 tcg_temp_free(tmp2
);
6442 tcg_temp_free(addr
);
6444 /* SWP instruction */
6447 /* ??? This is not really atomic. However we know
6448 we never have multiple CPUs running in parallel,
6449 so it is good enough. */
6450 addr
= load_reg(s
, rn
);
6451 tmp
= load_reg(s
, rm
);
6452 if (insn
& (1 << 22)) {
6453 tmp2
= gen_ld8u(addr
, IS_USER(s
));
6454 gen_st8(tmp
, addr
, IS_USER(s
));
6456 tmp2
= gen_ld32(addr
, IS_USER(s
));
6457 gen_st32(tmp
, addr
, IS_USER(s
));
6460 store_reg(s
, rd
, tmp2
);
6466 /* Misc load/store */
6467 rn
= (insn
>> 16) & 0xf;
6468 rd
= (insn
>> 12) & 0xf;
6469 addr
= load_reg(s
, rn
);
6470 if (insn
& (1 << 24))
6471 gen_add_datah_offset(s
, insn
, 0, addr
);
6473 if (insn
& (1 << 20)) {
6477 tmp
= gen_ld16u(addr
, IS_USER(s
));
6480 tmp
= gen_ld8s(addr
, IS_USER(s
));
6484 tmp
= gen_ld16s(addr
, IS_USER(s
));
6488 } else if (sh
& 2) {
6492 tmp
= load_reg(s
, rd
);
6493 gen_st32(tmp
, addr
, IS_USER(s
));
6494 tcg_gen_addi_i32(addr
, addr
, 4);
6495 tmp
= load_reg(s
, rd
+ 1);
6496 gen_st32(tmp
, addr
, IS_USER(s
));
6500 tmp
= gen_ld32(addr
, IS_USER(s
));
6501 store_reg(s
, rd
, tmp
);
6502 tcg_gen_addi_i32(addr
, addr
, 4);
6503 tmp
= gen_ld32(addr
, IS_USER(s
));
6507 address_offset
= -4;
6510 tmp
= load_reg(s
, rd
);
6511 gen_st16(tmp
, addr
, IS_USER(s
));
6514 /* Perform base writeback before the loaded value to
6515 ensure correct behavior with overlapping index registers.
6516 ldrd with base writeback is is undefined if the
6517 destination and index registers overlap. */
6518 if (!(insn
& (1 << 24))) {
6519 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
6520 store_reg(s
, rn
, addr
);
6521 } else if (insn
& (1 << 21)) {
6523 tcg_gen_addi_i32(addr
, addr
, address_offset
);
6524 store_reg(s
, rn
, addr
);
6529 /* Complete the load. */
6530 store_reg(s
, rd
, tmp
);
6539 if (insn
& (1 << 4)) {
6541 /* Armv6 Media instructions. */
6543 rn
= (insn
>> 16) & 0xf;
6544 rd
= (insn
>> 12) & 0xf;
6545 rs
= (insn
>> 8) & 0xf;
6546 switch ((insn
>> 23) & 3) {
6547 case 0: /* Parallel add/subtract. */
6548 op1
= (insn
>> 20) & 7;
6549 tmp
= load_reg(s
, rn
);
6550 tmp2
= load_reg(s
, rm
);
6551 sh
= (insn
>> 5) & 7;
6552 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
6554 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
6556 store_reg(s
, rd
, tmp
);
6559 if ((insn
& 0x00700020) == 0) {
6560 /* Halfword pack. */
6561 tmp
= load_reg(s
, rn
);
6562 tmp2
= load_reg(s
, rm
);
6563 shift
= (insn
>> 7) & 0x1f;
6564 if (insn
& (1 << 6)) {
6568 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
6569 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
6570 tcg_gen_ext16u_i32(tmp2
, tmp2
);
6574 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
6575 tcg_gen_ext16u_i32(tmp
, tmp
);
6576 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
6578 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
6580 store_reg(s
, rd
, tmp
);
6581 } else if ((insn
& 0x00200020) == 0x00200000) {
6583 tmp
= load_reg(s
, rm
);
6584 shift
= (insn
>> 7) & 0x1f;
6585 if (insn
& (1 << 6)) {
6588 tcg_gen_sari_i32(tmp
, tmp
, shift
);
6590 tcg_gen_shli_i32(tmp
, tmp
, shift
);
6592 sh
= (insn
>> 16) & 0x1f;
6594 tmp2
= tcg_const_i32(sh
);
6595 if (insn
& (1 << 22))
6596 gen_helper_usat(tmp
, tmp
, tmp2
);
6598 gen_helper_ssat(tmp
, tmp
, tmp2
);
6599 tcg_temp_free_i32(tmp2
);
6601 store_reg(s
, rd
, tmp
);
6602 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
6604 tmp
= load_reg(s
, rm
);
6605 sh
= (insn
>> 16) & 0x1f;
6607 tmp2
= tcg_const_i32(sh
);
6608 if (insn
& (1 << 22))
6609 gen_helper_usat16(tmp
, tmp
, tmp2
);
6611 gen_helper_ssat16(tmp
, tmp
, tmp2
);
6612 tcg_temp_free_i32(tmp2
);
6614 store_reg(s
, rd
, tmp
);
6615 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
6617 tmp
= load_reg(s
, rn
);
6618 tmp2
= load_reg(s
, rm
);
6620 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
6621 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
6624 store_reg(s
, rd
, tmp
);
6625 } else if ((insn
& 0x000003e0) == 0x00000060) {
6626 tmp
= load_reg(s
, rm
);
6627 shift
= (insn
>> 10) & 3;
6628 /* ??? In many cases it's not neccessary to do a
6629 rotate, a shift is sufficient. */
6631 tcg_gen_rori_i32(tmp
, tmp
, shift
* 8);
6632 op1
= (insn
>> 20) & 7;
6634 case 0: gen_sxtb16(tmp
); break;
6635 case 2: gen_sxtb(tmp
); break;
6636 case 3: gen_sxth(tmp
); break;
6637 case 4: gen_uxtb16(tmp
); break;
6638 case 6: gen_uxtb(tmp
); break;
6639 case 7: gen_uxth(tmp
); break;
6640 default: goto illegal_op
;
6643 tmp2
= load_reg(s
, rn
);
6644 if ((op1
& 3) == 0) {
6645 gen_add16(tmp
, tmp2
);
6647 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6651 store_reg(s
, rd
, tmp
);
6652 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
6654 tmp
= load_reg(s
, rm
);
6655 if (insn
& (1 << 22)) {
6656 if (insn
& (1 << 7)) {
6660 gen_helper_rbit(tmp
, tmp
);
6663 if (insn
& (1 << 7))
6666 tcg_gen_bswap32_i32(tmp
, tmp
);
6668 store_reg(s
, rd
, tmp
);
6673 case 2: /* Multiplies (Type 3). */
6674 tmp
= load_reg(s
, rm
);
6675 tmp2
= load_reg(s
, rs
);
6676 if (insn
& (1 << 20)) {
6677 /* Signed multiply most significant [accumulate]. */
6678 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6679 if (insn
& (1 << 5))
6680 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
6681 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
6683 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
6684 tcg_temp_free_i64(tmp64
);
6686 tmp2
= load_reg(s
, rd
);
6687 if (insn
& (1 << 6)) {
6688 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
6690 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6694 store_reg(s
, rn
, tmp
);
6696 if (insn
& (1 << 5))
6697 gen_swap_half(tmp2
);
6698 gen_smul_dual(tmp
, tmp2
);
6699 /* This addition cannot overflow. */
6700 if (insn
& (1 << 6)) {
6701 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
6703 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6706 if (insn
& (1 << 22)) {
6707 /* smlald, smlsld */
6708 tmp64
= tcg_temp_new_i64();
6709 tcg_gen_ext_i32_i64(tmp64
, tmp
);
6711 gen_addq(s
, tmp64
, rd
, rn
);
6712 gen_storeq_reg(s
, rd
, rn
, tmp64
);
6713 tcg_temp_free_i64(tmp64
);
6715 /* smuad, smusd, smlad, smlsd */
6718 tmp2
= load_reg(s
, rd
);
6719 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6722 store_reg(s
, rn
, tmp
);
6727 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
6729 case 0: /* Unsigned sum of absolute differences. */
6731 tmp
= load_reg(s
, rm
);
6732 tmp2
= load_reg(s
, rs
);
6733 gen_helper_usad8(tmp
, tmp
, tmp2
);
6736 tmp2
= load_reg(s
, rd
);
6737 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6740 store_reg(s
, rn
, tmp
);
6742 case 0x20: case 0x24: case 0x28: case 0x2c:
6743 /* Bitfield insert/clear. */
6745 shift
= (insn
>> 7) & 0x1f;
6746 i
= (insn
>> 16) & 0x1f;
6750 tcg_gen_movi_i32(tmp
, 0);
6752 tmp
= load_reg(s
, rm
);
6755 tmp2
= load_reg(s
, rd
);
6756 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << i
) - 1);
6759 store_reg(s
, rd
, tmp
);
6761 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
6762 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
6764 tmp
= load_reg(s
, rm
);
6765 shift
= (insn
>> 7) & 0x1f;
6766 i
= ((insn
>> 16) & 0x1f) + 1;
6771 gen_ubfx(tmp
, shift
, (1u << i
) - 1);
6773 gen_sbfx(tmp
, shift
, i
);
6776 store_reg(s
, rd
, tmp
);
6786 /* Check for undefined extension instructions
6787 * per the ARM Bible IE:
6788 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
6790 sh
= (0xf << 20) | (0xf << 4);
6791 if (op1
== 0x7 && ((insn
& sh
) == sh
))
6795 /* load/store byte/word */
6796 rn
= (insn
>> 16) & 0xf;
6797 rd
= (insn
>> 12) & 0xf;
6798 tmp2
= load_reg(s
, rn
);
6799 i
= (IS_USER(s
) || (insn
& 0x01200000) == 0x00200000);
6800 if (insn
& (1 << 24))
6801 gen_add_data_offset(s
, insn
, tmp2
);
6802 if (insn
& (1 << 20)) {
6804 if (insn
& (1 << 22)) {
6805 tmp
= gen_ld8u(tmp2
, i
);
6807 tmp
= gen_ld32(tmp2
, i
);
6811 tmp
= load_reg(s
, rd
);
6812 if (insn
& (1 << 22))
6813 gen_st8(tmp
, tmp2
, i
);
6815 gen_st32(tmp
, tmp2
, i
);
6817 if (!(insn
& (1 << 24))) {
6818 gen_add_data_offset(s
, insn
, tmp2
);
6819 store_reg(s
, rn
, tmp2
);
6820 } else if (insn
& (1 << 21)) {
6821 store_reg(s
, rn
, tmp2
);
6825 if (insn
& (1 << 20)) {
6826 /* Complete the load. */
6830 store_reg(s
, rd
, tmp
);
6836 int j
, n
, user
, loaded_base
;
6838 /* load/store multiple words */
6839 /* XXX: store correct base if write back */
6841 if (insn
& (1 << 22)) {
6843 goto illegal_op
; /* only usable in supervisor mode */
6845 if ((insn
& (1 << 15)) == 0)
6848 rn
= (insn
>> 16) & 0xf;
6849 addr
= load_reg(s
, rn
);
6851 /* compute total size */
6853 TCGV_UNUSED(loaded_var
);
6856 if (insn
& (1 << i
))
6859 /* XXX: test invalid n == 0 case ? */
6860 if (insn
& (1 << 23)) {
6861 if (insn
& (1 << 24)) {
6863 tcg_gen_addi_i32(addr
, addr
, 4);
6865 /* post increment */
6868 if (insn
& (1 << 24)) {
6870 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
6872 /* post decrement */
6874 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
6879 if (insn
& (1 << i
)) {
6880 if (insn
& (1 << 20)) {
6882 tmp
= gen_ld32(addr
, IS_USER(s
));
6886 tmp2
= tcg_const_i32(i
);
6887 gen_helper_set_user_reg(tmp2
, tmp
);
6888 tcg_temp_free_i32(tmp2
);
6890 } else if (i
== rn
) {
6894 store_reg(s
, i
, tmp
);
6899 /* special case: r15 = PC + 8 */
6900 val
= (long)s
->pc
+ 4;
6902 tcg_gen_movi_i32(tmp
, val
);
6905 tmp2
= tcg_const_i32(i
);
6906 gen_helper_get_user_reg(tmp
, tmp2
);
6907 tcg_temp_free_i32(tmp2
);
6909 tmp
= load_reg(s
, i
);
6911 gen_st32(tmp
, addr
, IS_USER(s
));
6914 /* no need to add after the last transfer */
6916 tcg_gen_addi_i32(addr
, addr
, 4);
6919 if (insn
& (1 << 21)) {
6921 if (insn
& (1 << 23)) {
6922 if (insn
& (1 << 24)) {
6925 /* post increment */
6926 tcg_gen_addi_i32(addr
, addr
, 4);
6929 if (insn
& (1 << 24)) {
6932 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
6934 /* post decrement */
6935 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
6938 store_reg(s
, rn
, addr
);
6943 store_reg(s
, rn
, loaded_var
);
6945 if ((insn
& (1 << 22)) && !user
) {
6946 /* Restore CPSR from SPSR. */
6947 tmp
= load_cpu_field(spsr
);
6948 gen_set_cpsr(tmp
, 0xffffffff);
6950 s
->is_jmp
= DISAS_UPDATE
;
6959 /* branch (and link) */
6960 val
= (int32_t)s
->pc
;
6961 if (insn
& (1 << 24)) {
6963 tcg_gen_movi_i32(tmp
, val
);
6964 store_reg(s
, 14, tmp
);
6966 offset
= (((int32_t)insn
<< 8) >> 8);
6967 val
+= (offset
<< 2) + 4;
6975 if (disas_coproc_insn(env
, s
, insn
))
6980 gen_set_pc_im(s
->pc
);
6981 s
->is_jmp
= DISAS_SWI
;
6985 gen_set_condexec(s
);
6986 gen_set_pc_im(s
->pc
- 4);
6987 gen_exception(EXCP_UDEF
);
6988 s
->is_jmp
= DISAS_JUMP
;
6994 /* Return true if this is a Thumb-2 logical op. */
6996 thumb2_logic_op(int op
)
7001 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7002 then set condition code flags based on the result of the operation.
7003 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7004 to the high bit of T1.
7005 Returns zero if the opcode is valid. */
7008 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
, TCGv t0
, TCGv t1
)
7015 tcg_gen_and_i32(t0
, t0
, t1
);
7019 tcg_gen_bic_i32(t0
, t0
, t1
);
7023 tcg_gen_or_i32(t0
, t0
, t1
);
7027 tcg_gen_not_i32(t1
, t1
);
7028 tcg_gen_or_i32(t0
, t0
, t1
);
7032 tcg_gen_xor_i32(t0
, t0
, t1
);
7037 gen_helper_add_cc(t0
, t0
, t1
);
7039 tcg_gen_add_i32(t0
, t0
, t1
);
7043 gen_helper_adc_cc(t0
, t0
, t1
);
7049 gen_helper_sbc_cc(t0
, t0
, t1
);
7051 gen_sub_carry(t0
, t0
, t1
);
7055 gen_helper_sub_cc(t0
, t0
, t1
);
7057 tcg_gen_sub_i32(t0
, t0
, t1
);
7061 gen_helper_sub_cc(t0
, t1
, t0
);
7063 tcg_gen_sub_i32(t0
, t1
, t0
);
7065 default: /* 5, 6, 7, 9, 12, 15. */
7071 gen_set_CF_bit31(t1
);
7076 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7078 static int disas_thumb2_insn(CPUState
*env
, DisasContext
*s
, uint16_t insn_hw1
)
7080 uint32_t insn
, imm
, shift
, offset
;
7081 uint32_t rd
, rn
, rm
, rs
;
7092 if (!(arm_feature(env
, ARM_FEATURE_THUMB2
)
7093 || arm_feature (env
, ARM_FEATURE_M
))) {
7094 /* Thumb-1 cores may need to treat bl and blx as a pair of
7095 16-bit instructions to get correct prefetch abort behavior. */
7097 if ((insn
& (1 << 12)) == 0) {
7098 /* Second half of blx. */
7099 offset
= ((insn
& 0x7ff) << 1);
7100 tmp
= load_reg(s
, 14);
7101 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7102 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
7105 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7106 store_reg(s
, 14, tmp2
);
7110 if (insn
& (1 << 11)) {
7111 /* Second half of bl. */
7112 offset
= ((insn
& 0x7ff) << 1) | 1;
7113 tmp
= load_reg(s
, 14);
7114 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7117 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7118 store_reg(s
, 14, tmp2
);
7122 if ((s
->pc
& ~TARGET_PAGE_MASK
) == 0) {
7123 /* Instruction spans a page boundary. Implement it as two
7124 16-bit instructions in case the second half causes an
7126 offset
= ((int32_t)insn
<< 21) >> 9;
7127 tcg_gen_movi_i32(cpu_R
[14], s
->pc
+ 2 + offset
);
7130 /* Fall through to 32-bit decode. */
7133 insn
= lduw_code(s
->pc
);
7135 insn
|= (uint32_t)insn_hw1
<< 16;
7137 if ((insn
& 0xf800e800) != 0xf000e800) {
7141 rn
= (insn
>> 16) & 0xf;
7142 rs
= (insn
>> 12) & 0xf;
7143 rd
= (insn
>> 8) & 0xf;
7145 switch ((insn
>> 25) & 0xf) {
7146 case 0: case 1: case 2: case 3:
7147 /* 16-bit instructions. Should never happen. */
7150 if (insn
& (1 << 22)) {
7151 /* Other load/store, table branch. */
7152 if (insn
& 0x01200000) {
7153 /* Load/store doubleword. */
7156 tcg_gen_movi_i32(addr
, s
->pc
& ~3);
7158 addr
= load_reg(s
, rn
);
7160 offset
= (insn
& 0xff) * 4;
7161 if ((insn
& (1 << 23)) == 0)
7163 if (insn
& (1 << 24)) {
7164 tcg_gen_addi_i32(addr
, addr
, offset
);
7167 if (insn
& (1 << 20)) {
7169 tmp
= gen_ld32(addr
, IS_USER(s
));
7170 store_reg(s
, rs
, tmp
);
7171 tcg_gen_addi_i32(addr
, addr
, 4);
7172 tmp
= gen_ld32(addr
, IS_USER(s
));
7173 store_reg(s
, rd
, tmp
);
7176 tmp
= load_reg(s
, rs
);
7177 gen_st32(tmp
, addr
, IS_USER(s
));
7178 tcg_gen_addi_i32(addr
, addr
, 4);
7179 tmp
= load_reg(s
, rd
);
7180 gen_st32(tmp
, addr
, IS_USER(s
));
7182 if (insn
& (1 << 21)) {
7183 /* Base writeback. */
7186 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
7187 store_reg(s
, rn
, addr
);
7191 } else if ((insn
& (1 << 23)) == 0) {
7192 /* Load/store exclusive word. */
7193 addr
= tcg_temp_local_new();
7194 load_reg_var(s
, addr
, rn
);
7195 if (insn
& (1 << 20)) {
7196 gen_helper_mark_exclusive(cpu_env
, addr
);
7197 tmp
= gen_ld32(addr
, IS_USER(s
));
7198 store_reg(s
, rd
, tmp
);
7200 int label
= gen_new_label();
7201 tmp2
= tcg_temp_local_new();
7202 gen_helper_test_exclusive(tmp2
, cpu_env
, addr
);
7203 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp2
, 0, label
);
7204 tmp
= load_reg(s
, rs
);
7205 gen_st32(tmp
, addr
, IS_USER(s
));
7206 gen_set_label(label
);
7207 tcg_gen_mov_i32(cpu_R
[rd
], tmp2
);
7208 tcg_temp_free(tmp2
);
7210 tcg_temp_free(addr
);
7211 } else if ((insn
& (1 << 6)) == 0) {
7215 tcg_gen_movi_i32(addr
, s
->pc
);
7217 addr
= load_reg(s
, rn
);
7219 tmp
= load_reg(s
, rm
);
7220 tcg_gen_add_i32(addr
, addr
, tmp
);
7221 if (insn
& (1 << 4)) {
7223 tcg_gen_add_i32(addr
, addr
, tmp
);
7225 tmp
= gen_ld16u(addr
, IS_USER(s
));
7228 tmp
= gen_ld8u(addr
, IS_USER(s
));
7231 tcg_gen_shli_i32(tmp
, tmp
, 1);
7232 tcg_gen_addi_i32(tmp
, tmp
, s
->pc
);
7233 store_reg(s
, 15, tmp
);
7235 /* Load/store exclusive byte/halfword/doubleword. */
7236 /* ??? These are not really atomic. However we know
7237 we never have multiple CPUs running in parallel,
7238 so it is good enough. */
7239 op
= (insn
>> 4) & 0x3;
7240 addr
= tcg_temp_local_new();
7241 load_reg_var(s
, addr
, rn
);
7242 if (insn
& (1 << 20)) {
7243 gen_helper_mark_exclusive(cpu_env
, addr
);
7246 tmp
= gen_ld8u(addr
, IS_USER(s
));
7249 tmp
= gen_ld16u(addr
, IS_USER(s
));
7252 tmp
= gen_ld32(addr
, IS_USER(s
));
7253 tcg_gen_addi_i32(addr
, addr
, 4);
7254 tmp2
= gen_ld32(addr
, IS_USER(s
));
7255 store_reg(s
, rd
, tmp2
);
7260 store_reg(s
, rs
, tmp
);
7262 int label
= gen_new_label();
7263 tmp2
= tcg_temp_local_new();
7264 gen_helper_test_exclusive(tmp2
, cpu_env
, addr
);
7265 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp2
, 0, label
);
7266 tmp
= load_reg(s
, rs
);
7269 gen_st8(tmp
, addr
, IS_USER(s
));
7272 gen_st16(tmp
, addr
, IS_USER(s
));
7275 gen_st32(tmp
, addr
, IS_USER(s
));
7276 tcg_gen_addi_i32(addr
, addr
, 4);
7277 tmp
= load_reg(s
, rd
);
7278 gen_st32(tmp
, addr
, IS_USER(s
));
7283 gen_set_label(label
);
7284 tcg_gen_mov_i32(cpu_R
[rm
], tmp2
);
7285 tcg_temp_free(tmp2
);
7287 tcg_temp_free(addr
);
7290 /* Load/store multiple, RFE, SRS. */
7291 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
7292 /* Not available in user mode. */
7295 if (insn
& (1 << 20)) {
7297 addr
= load_reg(s
, rn
);
7298 if ((insn
& (1 << 24)) == 0)
7299 tcg_gen_addi_i32(addr
, addr
, -8);
7300 /* Load PC into tmp and CPSR into tmp2. */
7301 tmp
= gen_ld32(addr
, 0);
7302 tcg_gen_addi_i32(addr
, addr
, 4);
7303 tmp2
= gen_ld32(addr
, 0);
7304 if (insn
& (1 << 21)) {
7305 /* Base writeback. */
7306 if (insn
& (1 << 24)) {
7307 tcg_gen_addi_i32(addr
, addr
, 4);
7309 tcg_gen_addi_i32(addr
, addr
, -4);
7311 store_reg(s
, rn
, addr
);
7315 gen_rfe(s
, tmp
, tmp2
);
7319 if (op
== (env
->uncached_cpsr
& CPSR_M
)) {
7320 addr
= load_reg(s
, 13);
7323 tmp
= tcg_const_i32(op
);
7324 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7325 tcg_temp_free_i32(tmp
);
7327 if ((insn
& (1 << 24)) == 0) {
7328 tcg_gen_addi_i32(addr
, addr
, -8);
7330 tmp
= load_reg(s
, 14);
7331 gen_st32(tmp
, addr
, 0);
7332 tcg_gen_addi_i32(addr
, addr
, 4);
7334 gen_helper_cpsr_read(tmp
);
7335 gen_st32(tmp
, addr
, 0);
7336 if (insn
& (1 << 21)) {
7337 if ((insn
& (1 << 24)) == 0) {
7338 tcg_gen_addi_i32(addr
, addr
, -4);
7340 tcg_gen_addi_i32(addr
, addr
, 4);
7342 if (op
== (env
->uncached_cpsr
& CPSR_M
)) {
7343 store_reg(s
, 13, addr
);
7345 tmp
= tcg_const_i32(op
);
7346 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
7347 tcg_temp_free_i32(tmp
);
7355 /* Load/store multiple. */
7356 addr
= load_reg(s
, rn
);
7358 for (i
= 0; i
< 16; i
++) {
7359 if (insn
& (1 << i
))
7362 if (insn
& (1 << 24)) {
7363 tcg_gen_addi_i32(addr
, addr
, -offset
);
7366 for (i
= 0; i
< 16; i
++) {
7367 if ((insn
& (1 << i
)) == 0)
7369 if (insn
& (1 << 20)) {
7371 tmp
= gen_ld32(addr
, IS_USER(s
));
7375 store_reg(s
, i
, tmp
);
7379 tmp
= load_reg(s
, i
);
7380 gen_st32(tmp
, addr
, IS_USER(s
));
7382 tcg_gen_addi_i32(addr
, addr
, 4);
7384 if (insn
& (1 << 21)) {
7385 /* Base register writeback. */
7386 if (insn
& (1 << 24)) {
7387 tcg_gen_addi_i32(addr
, addr
, -offset
);
7389 /* Fault if writeback register is in register list. */
7390 if (insn
& (1 << rn
))
7392 store_reg(s
, rn
, addr
);
7399 case 5: /* Data processing register constant shift. */
7402 tcg_gen_movi_i32(tmp
, 0);
7404 tmp
= load_reg(s
, rn
);
7406 tmp2
= load_reg(s
, rm
);
7407 op
= (insn
>> 21) & 0xf;
7408 shiftop
= (insn
>> 4) & 3;
7409 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
7410 conds
= (insn
& (1 << 20)) != 0;
7411 logic_cc
= (conds
&& thumb2_logic_op(op
));
7412 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
7413 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
7417 store_reg(s
, rd
, tmp
);
7422 case 13: /* Misc data processing. */
7423 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
7424 if (op
< 4 && (insn
& 0xf000) != 0xf000)
7427 case 0: /* Register controlled shift. */
7428 tmp
= load_reg(s
, rn
);
7429 tmp2
= load_reg(s
, rm
);
7430 if ((insn
& 0x70) != 0)
7432 op
= (insn
>> 21) & 3;
7433 logic_cc
= (insn
& (1 << 20)) != 0;
7434 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
7437 store_reg_bx(env
, s
, rd
, tmp
);
7439 case 1: /* Sign/zero extend. */
7440 tmp
= load_reg(s
, rm
);
7441 shift
= (insn
>> 4) & 3;
7442 /* ??? In many cases it's not neccessary to do a
7443 rotate, a shift is sufficient. */
7445 tcg_gen_rori_i32(tmp
, tmp
, shift
* 8);
7446 op
= (insn
>> 20) & 7;
7448 case 0: gen_sxth(tmp
); break;
7449 case 1: gen_uxth(tmp
); break;
7450 case 2: gen_sxtb16(tmp
); break;
7451 case 3: gen_uxtb16(tmp
); break;
7452 case 4: gen_sxtb(tmp
); break;
7453 case 5: gen_uxtb(tmp
); break;
7454 default: goto illegal_op
;
7457 tmp2
= load_reg(s
, rn
);
7458 if ((op
>> 1) == 1) {
7459 gen_add16(tmp
, tmp2
);
7461 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7465 store_reg(s
, rd
, tmp
);
7467 case 2: /* SIMD add/subtract. */
7468 op
= (insn
>> 20) & 7;
7469 shift
= (insn
>> 4) & 7;
7470 if ((op
& 3) == 3 || (shift
& 3) == 3)
7472 tmp
= load_reg(s
, rn
);
7473 tmp2
= load_reg(s
, rm
);
7474 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
7476 store_reg(s
, rd
, tmp
);
7478 case 3: /* Other data processing. */
7479 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
7481 /* Saturating add/subtract. */
7482 tmp
= load_reg(s
, rn
);
7483 tmp2
= load_reg(s
, rm
);
7485 gen_helper_double_saturate(tmp
, tmp
);
7487 gen_helper_sub_saturate(tmp
, tmp2
, tmp
);
7489 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
7492 tmp
= load_reg(s
, rn
);
7494 case 0x0a: /* rbit */
7495 gen_helper_rbit(tmp
, tmp
);
7497 case 0x08: /* rev */
7498 tcg_gen_bswap32_i32(tmp
, tmp
);
7500 case 0x09: /* rev16 */
7503 case 0x0b: /* revsh */
7506 case 0x10: /* sel */
7507 tmp2
= load_reg(s
, rm
);
7509 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
7510 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
7514 case 0x18: /* clz */
7515 gen_helper_clz(tmp
, tmp
);
7521 store_reg(s
, rd
, tmp
);
7523 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7524 op
= (insn
>> 4) & 0xf;
7525 tmp
= load_reg(s
, rn
);
7526 tmp2
= load_reg(s
, rm
);
7527 switch ((insn
>> 20) & 7) {
7528 case 0: /* 32 x 32 -> 32 */
7529 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
7532 tmp2
= load_reg(s
, rs
);
7534 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
7536 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7540 case 1: /* 16 x 16 -> 32 */
7541 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
7544 tmp2
= load_reg(s
, rs
);
7545 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7549 case 2: /* Dual multiply add. */
7550 case 4: /* Dual multiply subtract. */
7552 gen_swap_half(tmp2
);
7553 gen_smul_dual(tmp
, tmp2
);
7554 /* This addition cannot overflow. */
7555 if (insn
& (1 << 22)) {
7556 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7558 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7563 tmp2
= load_reg(s
, rs
);
7564 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7568 case 3: /* 32 * 16 -> 32msb */
7570 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
7573 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7574 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
7576 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7577 tcg_temp_free_i64(tmp64
);
7580 tmp2
= load_reg(s
, rs
);
7581 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7585 case 5: case 6: /* 32 * 32 -> 32msb */
7586 gen_imull(tmp
, tmp2
);
7587 if (insn
& (1 << 5)) {
7588 gen_roundqd(tmp
, tmp2
);
7595 tmp2
= load_reg(s
, rs
);
7596 if (insn
& (1 << 21)) {
7597 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7599 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
7604 case 7: /* Unsigned sum of absolute differences. */
7605 gen_helper_usad8(tmp
, tmp
, tmp2
);
7608 tmp2
= load_reg(s
, rs
);
7609 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7614 store_reg(s
, rd
, tmp
);
7616 case 6: case 7: /* 64-bit multiply, Divide. */
7617 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
7618 tmp
= load_reg(s
, rn
);
7619 tmp2
= load_reg(s
, rm
);
7620 if ((op
& 0x50) == 0x10) {
7622 if (!arm_feature(env
, ARM_FEATURE_DIV
))
7625 gen_helper_udiv(tmp
, tmp
, tmp2
);
7627 gen_helper_sdiv(tmp
, tmp
, tmp2
);
7629 store_reg(s
, rd
, tmp
);
7630 } else if ((op
& 0xe) == 0xc) {
7631 /* Dual multiply accumulate long. */
7633 gen_swap_half(tmp2
);
7634 gen_smul_dual(tmp
, tmp2
);
7636 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7638 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7642 tmp64
= tcg_temp_new_i64();
7643 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7645 gen_addq(s
, tmp64
, rs
, rd
);
7646 gen_storeq_reg(s
, rs
, rd
, tmp64
);
7647 tcg_temp_free_i64(tmp64
);
7650 /* Unsigned 64-bit multiply */
7651 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
7655 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
7657 tmp64
= tcg_temp_new_i64();
7658 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7661 /* Signed 64-bit multiply */
7662 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7667 gen_addq_lo(s
, tmp64
, rs
);
7668 gen_addq_lo(s
, tmp64
, rd
);
7669 } else if (op
& 0x40) {
7670 /* 64-bit accumulate. */
7671 gen_addq(s
, tmp64
, rs
, rd
);
7673 gen_storeq_reg(s
, rs
, rd
, tmp64
);
7674 tcg_temp_free_i64(tmp64
);
7679 case 6: case 7: case 14: case 15:
7681 if (((insn
>> 24) & 3) == 3) {
7682 /* Translate into the equivalent ARM encoding. */
7683 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4);
7684 if (disas_neon_data_insn(env
, s
, insn
))
7687 if (insn
& (1 << 28))
7689 if (disas_coproc_insn (env
, s
, insn
))
7693 case 8: case 9: case 10: case 11:
7694 if (insn
& (1 << 15)) {
7695 /* Branches, misc control. */
7696 if (insn
& 0x5000) {
7697 /* Unconditional branch. */
7698 /* signextend(hw1[10:0]) -> offset[:12]. */
7699 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
7700 /* hw1[10:0] -> offset[11:1]. */
7701 offset
|= (insn
& 0x7ff) << 1;
7702 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7703 offset[24:22] already have the same value because of the
7704 sign extension above. */
7705 offset
^= ((~insn
) & (1 << 13)) << 10;
7706 offset
^= ((~insn
) & (1 << 11)) << 11;
7708 if (insn
& (1 << 14)) {
7709 /* Branch and link. */
7710 tcg_gen_movi_i32(cpu_R
[14], s
->pc
| 1);
7714 if (insn
& (1 << 12)) {
7719 offset
&= ~(uint32_t)2;
7720 gen_bx_im(s
, offset
);
7722 } else if (((insn
>> 23) & 7) == 7) {
7724 if (insn
& (1 << 13))
7727 if (insn
& (1 << 26)) {
7728 /* Secure monitor call (v6Z) */
7729 goto illegal_op
; /* not implemented. */
7731 op
= (insn
>> 20) & 7;
7733 case 0: /* msr cpsr. */
7735 tmp
= load_reg(s
, rn
);
7736 addr
= tcg_const_i32(insn
& 0xff);
7737 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
7738 tcg_temp_free_i32(addr
);
7744 case 1: /* msr spsr. */
7747 tmp
= load_reg(s
, rn
);
7749 msr_mask(env
, s
, (insn
>> 8) & 0xf, op
== 1),
7753 case 2: /* cps, nop-hint. */
7754 if (((insn
>> 8) & 7) == 0) {
7755 gen_nop_hint(s
, insn
& 0xff);
7757 /* Implemented as NOP in user mode. */
7762 if (insn
& (1 << 10)) {
7763 if (insn
& (1 << 7))
7765 if (insn
& (1 << 6))
7767 if (insn
& (1 << 5))
7769 if (insn
& (1 << 9))
7770 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
7772 if (insn
& (1 << 8)) {
7774 imm
|= (insn
& 0x1f);
7777 gen_set_psr_im(s
, offset
, 0, imm
);
7780 case 3: /* Special control operations. */
7781 op
= (insn
>> 4) & 0xf;
7784 gen_helper_clrex(cpu_env
);
7789 /* These execute as NOPs. */
7797 /* Trivial implementation equivalent to bx. */
7798 tmp
= load_reg(s
, rn
);
7801 case 5: /* Exception return. */
7802 /* Unpredictable in user mode. */
7804 case 6: /* mrs cpsr. */
7807 addr
= tcg_const_i32(insn
& 0xff);
7808 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
7809 tcg_temp_free_i32(addr
);
7811 gen_helper_cpsr_read(tmp
);
7813 store_reg(s
, rd
, tmp
);
7815 case 7: /* mrs spsr. */
7816 /* Not accessible in user mode. */
7817 if (IS_USER(s
) || IS_M(env
))
7819 tmp
= load_cpu_field(spsr
);
7820 store_reg(s
, rd
, tmp
);
7825 /* Conditional branch. */
7826 op
= (insn
>> 22) & 0xf;
7827 /* Generate a conditional jump to next instruction. */
7828 s
->condlabel
= gen_new_label();
7829 gen_test_cc(op
^ 1, s
->condlabel
);
7832 /* offset[11:1] = insn[10:0] */
7833 offset
= (insn
& 0x7ff) << 1;
7834 /* offset[17:12] = insn[21:16]. */
7835 offset
|= (insn
& 0x003f0000) >> 4;
7836 /* offset[31:20] = insn[26]. */
7837 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
7838 /* offset[18] = insn[13]. */
7839 offset
|= (insn
& (1 << 13)) << 5;
7840 /* offset[19] = insn[11]. */
7841 offset
|= (insn
& (1 << 11)) << 8;
7843 /* jump to the offset */
7844 gen_jmp(s
, s
->pc
+ offset
);
7847 /* Data processing immediate. */
7848 if (insn
& (1 << 25)) {
7849 if (insn
& (1 << 24)) {
7850 if (insn
& (1 << 20))
7852 /* Bitfield/Saturate. */
7853 op
= (insn
>> 21) & 7;
7855 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
7858 tcg_gen_movi_i32(tmp
, 0);
7860 tmp
= load_reg(s
, rn
);
7863 case 2: /* Signed bitfield extract. */
7865 if (shift
+ imm
> 32)
7868 gen_sbfx(tmp
, shift
, imm
);
7870 case 6: /* Unsigned bitfield extract. */
7872 if (shift
+ imm
> 32)
7875 gen_ubfx(tmp
, shift
, (1u << imm
) - 1);
7877 case 3: /* Bitfield insert/clear. */
7880 imm
= imm
+ 1 - shift
;
7882 tmp2
= load_reg(s
, rd
);
7883 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << imm
) - 1);
7889 default: /* Saturate. */
7892 tcg_gen_sari_i32(tmp
, tmp
, shift
);
7894 tcg_gen_shli_i32(tmp
, tmp
, shift
);
7896 tmp2
= tcg_const_i32(imm
);
7899 if ((op
& 1) && shift
== 0)
7900 gen_helper_usat16(tmp
, tmp
, tmp2
);
7902 gen_helper_usat(tmp
, tmp
, tmp2
);
7905 if ((op
& 1) && shift
== 0)
7906 gen_helper_ssat16(tmp
, tmp
, tmp2
);
7908 gen_helper_ssat(tmp
, tmp
, tmp2
);
7910 tcg_temp_free_i32(tmp2
);
7913 store_reg(s
, rd
, tmp
);
7915 imm
= ((insn
& 0x04000000) >> 15)
7916 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
7917 if (insn
& (1 << 22)) {
7918 /* 16-bit immediate. */
7919 imm
|= (insn
>> 4) & 0xf000;
7920 if (insn
& (1 << 23)) {
7922 tmp
= load_reg(s
, rd
);
7923 tcg_gen_ext16u_i32(tmp
, tmp
);
7924 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
7928 tcg_gen_movi_i32(tmp
, imm
);
7931 /* Add/sub 12-bit immediate. */
7933 offset
= s
->pc
& ~(uint32_t)3;
7934 if (insn
& (1 << 23))
7939 tcg_gen_movi_i32(tmp
, offset
);
7941 tmp
= load_reg(s
, rn
);
7942 if (insn
& (1 << 23))
7943 tcg_gen_subi_i32(tmp
, tmp
, imm
);
7945 tcg_gen_addi_i32(tmp
, tmp
, imm
);
7948 store_reg(s
, rd
, tmp
);
7951 int shifter_out
= 0;
7952 /* modified 12-bit immediate. */
7953 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
7954 imm
= (insn
& 0xff);
7957 /* Nothing to do. */
7959 case 1: /* 00XY00XY */
7962 case 2: /* XY00XY00 */
7966 case 3: /* XYXYXYXY */
7970 default: /* Rotated constant. */
7971 shift
= (shift
<< 1) | (imm
>> 7);
7973 imm
= imm
<< (32 - shift
);
7978 tcg_gen_movi_i32(tmp2
, imm
);
7979 rn
= (insn
>> 16) & 0xf;
7982 tcg_gen_movi_i32(tmp
, 0);
7984 tmp
= load_reg(s
, rn
);
7986 op
= (insn
>> 21) & 0xf;
7987 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
7988 shifter_out
, tmp
, tmp2
))
7991 rd
= (insn
>> 8) & 0xf;
7993 store_reg(s
, rd
, tmp
);
8000 case 12: /* Load/store single data item. */
8005 if ((insn
& 0x01100000) == 0x01000000) {
8006 if (disas_neon_ls_insn(env
, s
, insn
))
8014 /* s->pc has already been incremented by 4. */
8015 imm
= s
->pc
& 0xfffffffc;
8016 if (insn
& (1 << 23))
8017 imm
+= insn
& 0xfff;
8019 imm
-= insn
& 0xfff;
8020 tcg_gen_movi_i32(addr
, imm
);
8022 addr
= load_reg(s
, rn
);
8023 if (insn
& (1 << 23)) {
8024 /* Positive offset. */
8026 tcg_gen_addi_i32(addr
, addr
, imm
);
8028 op
= (insn
>> 8) & 7;
8031 case 0: case 8: /* Shifted Register. */
8032 shift
= (insn
>> 4) & 0xf;
8035 tmp
= load_reg(s
, rm
);
8037 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8038 tcg_gen_add_i32(addr
, addr
, tmp
);
8041 case 4: /* Negative offset. */
8042 tcg_gen_addi_i32(addr
, addr
, -imm
);
8044 case 6: /* User privilege. */
8045 tcg_gen_addi_i32(addr
, addr
, imm
);
8048 case 1: /* Post-decrement. */
8051 case 3: /* Post-increment. */
8055 case 5: /* Pre-decrement. */
8058 case 7: /* Pre-increment. */
8059 tcg_gen_addi_i32(addr
, addr
, imm
);
8067 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
8068 if (insn
& (1 << 20)) {
8070 if (rs
== 15 && op
!= 2) {
8073 /* Memory hint. Implemented as NOP. */
8076 case 0: tmp
= gen_ld8u(addr
, user
); break;
8077 case 4: tmp
= gen_ld8s(addr
, user
); break;
8078 case 1: tmp
= gen_ld16u(addr
, user
); break;
8079 case 5: tmp
= gen_ld16s(addr
, user
); break;
8080 case 2: tmp
= gen_ld32(addr
, user
); break;
8081 default: goto illegal_op
;
8086 store_reg(s
, rs
, tmp
);
8093 tmp
= load_reg(s
, rs
);
8095 case 0: gen_st8(tmp
, addr
, user
); break;
8096 case 1: gen_st16(tmp
, addr
, user
); break;
8097 case 2: gen_st32(tmp
, addr
, user
); break;
8098 default: goto illegal_op
;
8102 tcg_gen_addi_i32(addr
, addr
, imm
);
8104 store_reg(s
, rn
, addr
);
8118 static void disas_thumb_insn(CPUState
*env
, DisasContext
*s
)
8120 uint32_t val
, insn
, op
, rm
, rn
, rd
, shift
, cond
;
8127 if (s
->condexec_mask
) {
8128 cond
= s
->condexec_cond
;
8129 s
->condlabel
= gen_new_label();
8130 gen_test_cc(cond
^ 1, s
->condlabel
);
8134 insn
= lduw_code(s
->pc
);
8137 switch (insn
>> 12) {
8141 op
= (insn
>> 11) & 3;
8144 rn
= (insn
>> 3) & 7;
8145 tmp
= load_reg(s
, rn
);
8146 if (insn
& (1 << 10)) {
8149 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
8152 rm
= (insn
>> 6) & 7;
8153 tmp2
= load_reg(s
, rm
);
8155 if (insn
& (1 << 9)) {
8156 if (s
->condexec_mask
)
8157 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8159 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8161 if (s
->condexec_mask
)
8162 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8164 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8167 store_reg(s
, rd
, tmp
);
8169 /* shift immediate */
8170 rm
= (insn
>> 3) & 7;
8171 shift
= (insn
>> 6) & 0x1f;
8172 tmp
= load_reg(s
, rm
);
8173 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
8174 if (!s
->condexec_mask
)
8176 store_reg(s
, rd
, tmp
);
8180 /* arithmetic large immediate */
8181 op
= (insn
>> 11) & 3;
8182 rd
= (insn
>> 8) & 0x7;
8183 if (op
== 0) { /* mov */
8185 tcg_gen_movi_i32(tmp
, insn
& 0xff);
8186 if (!s
->condexec_mask
)
8188 store_reg(s
, rd
, tmp
);
8190 tmp
= load_reg(s
, rd
);
8192 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
8195 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8200 if (s
->condexec_mask
)
8201 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8203 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8205 store_reg(s
, rd
, tmp
);
8208 if (s
->condexec_mask
)
8209 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8211 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8213 store_reg(s
, rd
, tmp
);
8219 if (insn
& (1 << 11)) {
8220 rd
= (insn
>> 8) & 7;
8221 /* load pc-relative. Bit 1 of PC is ignored. */
8222 val
= s
->pc
+ 2 + ((insn
& 0xff) * 4);
8223 val
&= ~(uint32_t)2;
8225 tcg_gen_movi_i32(addr
, val
);
8226 tmp
= gen_ld32(addr
, IS_USER(s
));
8228 store_reg(s
, rd
, tmp
);
8231 if (insn
& (1 << 10)) {
8232 /* data processing extended or blx */
8233 rd
= (insn
& 7) | ((insn
>> 4) & 8);
8234 rm
= (insn
>> 3) & 0xf;
8235 op
= (insn
>> 8) & 3;
8238 tmp
= load_reg(s
, rd
);
8239 tmp2
= load_reg(s
, rm
);
8240 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8242 store_reg(s
, rd
, tmp
);
8245 tmp
= load_reg(s
, rd
);
8246 tmp2
= load_reg(s
, rm
);
8247 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8251 case 2: /* mov/cpy */
8252 tmp
= load_reg(s
, rm
);
8253 store_reg(s
, rd
, tmp
);
8255 case 3:/* branch [and link] exchange thumb register */
8256 tmp
= load_reg(s
, rm
);
8257 if (insn
& (1 << 7)) {
8258 val
= (uint32_t)s
->pc
| 1;
8260 tcg_gen_movi_i32(tmp2
, val
);
8261 store_reg(s
, 14, tmp2
);
8269 /* data processing register */
8271 rm
= (insn
>> 3) & 7;
8272 op
= (insn
>> 6) & 0xf;
8273 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
8274 /* the shift/rotate ops want the operands backwards */
8283 if (op
== 9) { /* neg */
8285 tcg_gen_movi_i32(tmp
, 0);
8286 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
8287 tmp
= load_reg(s
, rd
);
8292 tmp2
= load_reg(s
, rm
);
8295 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8296 if (!s
->condexec_mask
)
8300 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
8301 if (!s
->condexec_mask
)
8305 if (s
->condexec_mask
) {
8306 gen_helper_shl(tmp2
, tmp2
, tmp
);
8308 gen_helper_shl_cc(tmp2
, tmp2
, tmp
);
8313 if (s
->condexec_mask
) {
8314 gen_helper_shr(tmp2
, tmp2
, tmp
);
8316 gen_helper_shr_cc(tmp2
, tmp2
, tmp
);
8321 if (s
->condexec_mask
) {
8322 gen_helper_sar(tmp2
, tmp2
, tmp
);
8324 gen_helper_sar_cc(tmp2
, tmp2
, tmp
);
8329 if (s
->condexec_mask
)
8332 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
8335 if (s
->condexec_mask
)
8336 gen_sub_carry(tmp
, tmp
, tmp2
);
8338 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
8341 if (s
->condexec_mask
) {
8342 gen_helper_ror(tmp2
, tmp2
, tmp
);
8344 gen_helper_ror_cc(tmp2
, tmp2
, tmp
);
8349 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8354 if (s
->condexec_mask
)
8355 tcg_gen_neg_i32(tmp
, tmp2
);
8357 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8360 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8364 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8368 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
8369 if (!s
->condexec_mask
)
8373 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
8374 if (!s
->condexec_mask
)
8378 tcg_gen_bic_i32(tmp
, tmp
, tmp2
);
8379 if (!s
->condexec_mask
)
8383 tcg_gen_not_i32(tmp2
, tmp2
);
8384 if (!s
->condexec_mask
)
8392 store_reg(s
, rm
, tmp2
);
8396 store_reg(s
, rd
, tmp
);
8406 /* load/store register offset. */
8408 rn
= (insn
>> 3) & 7;
8409 rm
= (insn
>> 6) & 7;
8410 op
= (insn
>> 9) & 7;
8411 addr
= load_reg(s
, rn
);
8412 tmp
= load_reg(s
, rm
);
8413 tcg_gen_add_i32(addr
, addr
, tmp
);
8416 if (op
< 3) /* store */
8417 tmp
= load_reg(s
, rd
);
8421 gen_st32(tmp
, addr
, IS_USER(s
));
8424 gen_st16(tmp
, addr
, IS_USER(s
));
8427 gen_st8(tmp
, addr
, IS_USER(s
));
8430 tmp
= gen_ld8s(addr
, IS_USER(s
));
8433 tmp
= gen_ld32(addr
, IS_USER(s
));
8436 tmp
= gen_ld16u(addr
, IS_USER(s
));
8439 tmp
= gen_ld8u(addr
, IS_USER(s
));
8442 tmp
= gen_ld16s(addr
, IS_USER(s
));
8445 if (op
>= 3) /* load */
8446 store_reg(s
, rd
, tmp
);
8451 /* load/store word immediate offset */
8453 rn
= (insn
>> 3) & 7;
8454 addr
= load_reg(s
, rn
);
8455 val
= (insn
>> 4) & 0x7c;
8456 tcg_gen_addi_i32(addr
, addr
, val
);
8458 if (insn
& (1 << 11)) {
8460 tmp
= gen_ld32(addr
, IS_USER(s
));
8461 store_reg(s
, rd
, tmp
);
8464 tmp
= load_reg(s
, rd
);
8465 gen_st32(tmp
, addr
, IS_USER(s
));
8471 /* load/store byte immediate offset */
8473 rn
= (insn
>> 3) & 7;
8474 addr
= load_reg(s
, rn
);
8475 val
= (insn
>> 6) & 0x1f;
8476 tcg_gen_addi_i32(addr
, addr
, val
);
8478 if (insn
& (1 << 11)) {
8480 tmp
= gen_ld8u(addr
, IS_USER(s
));
8481 store_reg(s
, rd
, tmp
);
8484 tmp
= load_reg(s
, rd
);
8485 gen_st8(tmp
, addr
, IS_USER(s
));
8491 /* load/store halfword immediate offset */
8493 rn
= (insn
>> 3) & 7;
8494 addr
= load_reg(s
, rn
);
8495 val
= (insn
>> 5) & 0x3e;
8496 tcg_gen_addi_i32(addr
, addr
, val
);
8498 if (insn
& (1 << 11)) {
8500 tmp
= gen_ld16u(addr
, IS_USER(s
));
8501 store_reg(s
, rd
, tmp
);
8504 tmp
= load_reg(s
, rd
);
8505 gen_st16(tmp
, addr
, IS_USER(s
));
8511 /* load/store from stack */
8512 rd
= (insn
>> 8) & 7;
8513 addr
= load_reg(s
, 13);
8514 val
= (insn
& 0xff) * 4;
8515 tcg_gen_addi_i32(addr
, addr
, val
);
8517 if (insn
& (1 << 11)) {
8519 tmp
= gen_ld32(addr
, IS_USER(s
));
8520 store_reg(s
, rd
, tmp
);
8523 tmp
= load_reg(s
, rd
);
8524 gen_st32(tmp
, addr
, IS_USER(s
));
8530 /* add to high reg */
8531 rd
= (insn
>> 8) & 7;
8532 if (insn
& (1 << 11)) {
8534 tmp
= load_reg(s
, 13);
8536 /* PC. bit 1 is ignored. */
8538 tcg_gen_movi_i32(tmp
, (s
->pc
+ 2) & ~(uint32_t)2);
8540 val
= (insn
& 0xff) * 4;
8541 tcg_gen_addi_i32(tmp
, tmp
, val
);
8542 store_reg(s
, rd
, tmp
);
8547 op
= (insn
>> 8) & 0xf;
8550 /* adjust stack pointer */
8551 tmp
= load_reg(s
, 13);
8552 val
= (insn
& 0x7f) * 4;
8553 if (insn
& (1 << 7))
8554 val
= -(int32_t)val
;
8555 tcg_gen_addi_i32(tmp
, tmp
, val
);
8556 store_reg(s
, 13, tmp
);
8559 case 2: /* sign/zero extend. */
8562 rm
= (insn
>> 3) & 7;
8563 tmp
= load_reg(s
, rm
);
8564 switch ((insn
>> 6) & 3) {
8565 case 0: gen_sxth(tmp
); break;
8566 case 1: gen_sxtb(tmp
); break;
8567 case 2: gen_uxth(tmp
); break;
8568 case 3: gen_uxtb(tmp
); break;
8570 store_reg(s
, rd
, tmp
);
8572 case 4: case 5: case 0xc: case 0xd:
8574 addr
= load_reg(s
, 13);
8575 if (insn
& (1 << 8))
8579 for (i
= 0; i
< 8; i
++) {
8580 if (insn
& (1 << i
))
8583 if ((insn
& (1 << 11)) == 0) {
8584 tcg_gen_addi_i32(addr
, addr
, -offset
);
8586 for (i
= 0; i
< 8; i
++) {
8587 if (insn
& (1 << i
)) {
8588 if (insn
& (1 << 11)) {
8590 tmp
= gen_ld32(addr
, IS_USER(s
));
8591 store_reg(s
, i
, tmp
);
8594 tmp
= load_reg(s
, i
);
8595 gen_st32(tmp
, addr
, IS_USER(s
));
8597 /* advance to the next address. */
8598 tcg_gen_addi_i32(addr
, addr
, 4);
8602 if (insn
& (1 << 8)) {
8603 if (insn
& (1 << 11)) {
8605 tmp
= gen_ld32(addr
, IS_USER(s
));
8606 /* don't set the pc until the rest of the instruction
8610 tmp
= load_reg(s
, 14);
8611 gen_st32(tmp
, addr
, IS_USER(s
));
8613 tcg_gen_addi_i32(addr
, addr
, 4);
8615 if ((insn
& (1 << 11)) == 0) {
8616 tcg_gen_addi_i32(addr
, addr
, -offset
);
8618 /* write back the new stack pointer */
8619 store_reg(s
, 13, addr
);
8620 /* set the new PC value */
8621 if ((insn
& 0x0900) == 0x0900)
8625 case 1: case 3: case 9: case 11: /* czb */
8627 tmp
= load_reg(s
, rm
);
8628 s
->condlabel
= gen_new_label();
8630 if (insn
& (1 << 11))
8631 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
8633 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
8635 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
8636 val
= (uint32_t)s
->pc
+ 2;
8641 case 15: /* IT, nop-hint. */
8642 if ((insn
& 0xf) == 0) {
8643 gen_nop_hint(s
, (insn
>> 4) & 0xf);
8647 s
->condexec_cond
= (insn
>> 4) & 0xe;
8648 s
->condexec_mask
= insn
& 0x1f;
8649 /* No actual code generated for this insn, just setup state. */
8652 case 0xe: /* bkpt */
8653 gen_set_condexec(s
);
8654 gen_set_pc_im(s
->pc
- 2);
8655 gen_exception(EXCP_BKPT
);
8656 s
->is_jmp
= DISAS_JUMP
;
8661 rn
= (insn
>> 3) & 0x7;
8663 tmp
= load_reg(s
, rn
);
8664 switch ((insn
>> 6) & 3) {
8665 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
8666 case 1: gen_rev16(tmp
); break;
8667 case 3: gen_revsh(tmp
); break;
8668 default: goto illegal_op
;
8670 store_reg(s
, rd
, tmp
);
8678 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
8681 addr
= tcg_const_i32(16);
8682 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
8683 tcg_temp_free_i32(addr
);
8687 addr
= tcg_const_i32(17);
8688 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
8689 tcg_temp_free_i32(addr
);
8691 tcg_temp_free_i32(tmp
);
8694 if (insn
& (1 << 4))
8695 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
8698 gen_set_psr_im(s
, shift
, 0, ((insn
& 7) << 6) & shift
);
8708 /* load/store multiple */
8709 rn
= (insn
>> 8) & 0x7;
8710 addr
= load_reg(s
, rn
);
8711 for (i
= 0; i
< 8; i
++) {
8712 if (insn
& (1 << i
)) {
8713 if (insn
& (1 << 11)) {
8715 tmp
= gen_ld32(addr
, IS_USER(s
));
8716 store_reg(s
, i
, tmp
);
8719 tmp
= load_reg(s
, i
);
8720 gen_st32(tmp
, addr
, IS_USER(s
));
8722 /* advance to the next address */
8723 tcg_gen_addi_i32(addr
, addr
, 4);
8726 /* Base register writeback. */
8727 if ((insn
& (1 << rn
)) == 0) {
8728 store_reg(s
, rn
, addr
);
8735 /* conditional branch or swi */
8736 cond
= (insn
>> 8) & 0xf;
8742 gen_set_condexec(s
);
8743 gen_set_pc_im(s
->pc
);
8744 s
->is_jmp
= DISAS_SWI
;
8747 /* generate a conditional jump to next instruction */
8748 s
->condlabel
= gen_new_label();
8749 gen_test_cc(cond
^ 1, s
->condlabel
);
8752 /* jump to the offset */
8753 val
= (uint32_t)s
->pc
+ 2;
8754 offset
= ((int32_t)insn
<< 24) >> 24;
8760 if (insn
& (1 << 11)) {
8761 if (disas_thumb2_insn(env
, s
, insn
))
8765 /* unconditional branch */
8766 val
= (uint32_t)s
->pc
;
8767 offset
= ((int32_t)insn
<< 21) >> 21;
8768 val
+= (offset
<< 1) + 2;
8773 if (disas_thumb2_insn(env
, s
, insn
))
8779 gen_set_condexec(s
);
8780 gen_set_pc_im(s
->pc
- 4);
8781 gen_exception(EXCP_UDEF
);
8782 s
->is_jmp
= DISAS_JUMP
;
8786 gen_set_condexec(s
);
8787 gen_set_pc_im(s
->pc
- 2);
8788 gen_exception(EXCP_UDEF
);
8789 s
->is_jmp
= DISAS_JUMP
;
8792 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
8793 basic block 'tb'. If search_pc is TRUE, also generate PC
8794 information for each intermediate instruction. */
8795 static inline void gen_intermediate_code_internal(CPUState
*env
,
8796 TranslationBlock
*tb
,
8799 DisasContext dc1
, *dc
= &dc1
;
8801 uint16_t *gen_opc_end
;
8803 target_ulong pc_start
;
8804 uint32_t next_page_start
;
8808 /* generate intermediate code */
8815 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
8817 dc
->is_jmp
= DISAS_NEXT
;
8819 dc
->singlestep_enabled
= env
->singlestep_enabled
;
8821 dc
->thumb
= env
->thumb
;
8822 dc
->condexec_mask
= (env
->condexec_bits
& 0xf) << 1;
8823 dc
->condexec_cond
= env
->condexec_bits
>> 4;
8824 #if !defined(CONFIG_USER_ONLY)
8826 dc
->user
= ((env
->v7m
.exception
== 0) && (env
->v7m
.control
& 1));
8828 dc
->user
= (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_USR
;
8831 cpu_F0s
= tcg_temp_new_i32();
8832 cpu_F1s
= tcg_temp_new_i32();
8833 cpu_F0d
= tcg_temp_new_i64();
8834 cpu_F1d
= tcg_temp_new_i64();
8837 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
8838 cpu_M0
= tcg_temp_new_i64();
8839 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
8842 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8844 max_insns
= CF_COUNT_MASK
;
8847 /* Reset the conditional execution bits immediately. This avoids
8848 complications trying to do it at the end of the block. */
8849 if (env
->condexec_bits
)
8851 TCGv tmp
= new_tmp();
8852 tcg_gen_movi_i32(tmp
, 0);
8853 store_cpu_field(tmp
, condexec_bits
);
8856 #ifdef CONFIG_USER_ONLY
8857 /* Intercept jump to the magic kernel page. */
8858 if (dc
->pc
>= 0xffff0000) {
8859 /* We always get here via a jump, so know we are not in a
8860 conditional execution block. */
8861 gen_exception(EXCP_KERNEL_TRAP
);
8862 dc
->is_jmp
= DISAS_UPDATE
;
8866 if (dc
->pc
>= 0xfffffff0 && IS_M(env
)) {
8867 /* We always get here via a jump, so know we are not in a
8868 conditional execution block. */
8869 gen_exception(EXCP_EXCEPTION_EXIT
);
8870 dc
->is_jmp
= DISAS_UPDATE
;
8875 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
8876 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8877 if (bp
->pc
== dc
->pc
) {
8878 gen_set_condexec(dc
);
8879 gen_set_pc_im(dc
->pc
);
8880 gen_exception(EXCP_DEBUG
);
8881 dc
->is_jmp
= DISAS_JUMP
;
8882 /* Advance PC so that clearing the breakpoint will
8883 invalidate this TB. */
8885 goto done_generating
;
8891 j
= gen_opc_ptr
- gen_opc_buf
;
8895 gen_opc_instr_start
[lj
++] = 0;
8897 gen_opc_pc
[lj
] = dc
->pc
;
8898 gen_opc_instr_start
[lj
] = 1;
8899 gen_opc_icount
[lj
] = num_insns
;
8902 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8906 disas_thumb_insn(env
, dc
);
8907 if (dc
->condexec_mask
) {
8908 dc
->condexec_cond
= (dc
->condexec_cond
& 0xe)
8909 | ((dc
->condexec_mask
>> 4) & 1);
8910 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
8911 if (dc
->condexec_mask
== 0) {
8912 dc
->condexec_cond
= 0;
8916 disas_arm_insn(env
, dc
);
8919 fprintf(stderr
, "Internal resource leak before %08x\n", dc
->pc
);
8923 if (dc
->condjmp
&& !dc
->is_jmp
) {
8924 gen_set_label(dc
->condlabel
);
8927 /* Translation stops when a conditional branch is encountered.
8928 * Otherwise the subsequent code could get translated several times.
8929 * Also stop translation when a page boundary is reached. This
8930 * ensures prefetch aborts occur at the right place. */
8932 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
&&
8933 !env
->singlestep_enabled
&&
8935 dc
->pc
< next_page_start
&&
8936 num_insns
< max_insns
);
8938 if (tb
->cflags
& CF_LAST_IO
) {
8940 /* FIXME: This can theoretically happen with self-modifying
8942 cpu_abort(env
, "IO on conditional branch instruction");
8947 /* At this stage dc->condjmp will only be set when the skipped
8948 instruction was a conditional branch or trap, and the PC has
8949 already been written. */
8950 if (unlikely(env
->singlestep_enabled
)) {
8951 /* Make sure the pc is updated, and raise a debug exception. */
8953 gen_set_condexec(dc
);
8954 if (dc
->is_jmp
== DISAS_SWI
) {
8955 gen_exception(EXCP_SWI
);
8957 gen_exception(EXCP_DEBUG
);
8959 gen_set_label(dc
->condlabel
);
8961 if (dc
->condjmp
|| !dc
->is_jmp
) {
8962 gen_set_pc_im(dc
->pc
);
8965 gen_set_condexec(dc
);
8966 if (dc
->is_jmp
== DISAS_SWI
&& !dc
->condjmp
) {
8967 gen_exception(EXCP_SWI
);
8969 /* FIXME: Single stepping a WFI insn will not halt
8971 gen_exception(EXCP_DEBUG
);
8974 /* While branches must always occur at the end of an IT block,
8975 there are a few other things that can cause us to terminate
8976 the TB in the middel of an IT block:
8977 - Exception generating instructions (bkpt, swi, undefined).
8979 - Hardware watchpoints.
8980 Hardware breakpoints have already been handled and skip this code.
8982 gen_set_condexec(dc
);
8983 switch(dc
->is_jmp
) {
8985 gen_goto_tb(dc
, 1, dc
->pc
);
8990 /* indicate that the hash table must be used to find the next TB */
8994 /* nothing more to generate */
9000 gen_exception(EXCP_SWI
);
9004 gen_set_label(dc
->condlabel
);
9005 gen_set_condexec(dc
);
9006 gen_goto_tb(dc
, 1, dc
->pc
);
9012 gen_icount_end(tb
, num_insns
);
9013 *gen_opc_ptr
= INDEX_op_end
;
9016 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9017 qemu_log("----------------\n");
9018 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9019 log_target_disas(pc_start
, dc
->pc
- pc_start
, env
->thumb
);
9024 j
= gen_opc_ptr
- gen_opc_buf
;
9027 gen_opc_instr_start
[lj
++] = 0;
9029 tb
->size
= dc
->pc
- pc_start
;
9030 tb
->icount
= num_insns
;
9034 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
9036 gen_intermediate_code_internal(env
, tb
, 0);
9039 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
9041 gen_intermediate_code_internal(env
, tb
, 1);
9044 static const char *cpu_mode_names
[16] = {
9045 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9046 "???", "???", "???", "und", "???", "???", "???", "sys"
9049 void cpu_dump_state(CPUState
*env
, FILE *f
,
9050 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
9060 /* ??? This assumes float64 and double have the same layout.
9061 Oh well, it's only debug dumps. */
9070 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
9072 cpu_fprintf(f
, "\n");
9074 cpu_fprintf(f
, " ");
9076 psr
= cpsr_read(env
);
9077 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%d\n",
9079 psr
& (1 << 31) ? 'N' : '-',
9080 psr
& (1 << 30) ? 'Z' : '-',
9081 psr
& (1 << 29) ? 'C' : '-',
9082 psr
& (1 << 28) ? 'V' : '-',
9083 psr
& CPSR_T
? 'T' : 'A',
9084 cpu_mode_names
[psr
& 0xf], (psr
& 0x10) ? 32 : 26);
9087 for (i
= 0; i
< 16; i
++) {
9088 d
.d
= env
->vfp
.regs
[i
];
9092 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9093 i
* 2, (int)s0
.i
, s0
.s
,
9094 i
* 2 + 1, (int)s1
.i
, s1
.s
,
9095 i
, (int)(uint32_t)d
.l
.upper
, (int)(uint32_t)d
.l
.lower
,
9098 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->vfp
.xregs
[ARM_VFP_FPSCR
]);
9102 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
9103 unsigned long searched_pc
, int pc_pos
, void *puc
)
9105 env
->regs
[15] = gen_opc_pc
[pc_pos
];