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virtio-9p: Add P9_TWRITE support
[qemu.git] / hw / sun4m.c
blob9a79120b1df2a5ff48a5cdd137c2269d93f54a2b
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43
44 //#define DEBUG_IRQ
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #ifdef DEBUG_IRQ
75 #define DPRINTF(fmt, ...) \
76 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
77 #else
78 #define DPRINTF(fmt, ...)
79 #endif
80
81 #define KERNEL_LOAD_ADDR 0x00004000
82 #define CMDLINE_ADDR 0x007ff000
83 #define INITRD_LOAD_ADDR 0x00800000
84 #define PROM_SIZE_MAX (1024 * 1024)
85 #define PROM_VADDR 0xffd00000
86 #define PROM_FILENAME "openbios-sparc32"
87 #define CFG_ADDR 0xd00000510ULL
88 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
89
90 #define MAX_CPUS 16
91 #define MAX_PILS 16
92
93 #define ESCC_CLOCK 4915200
94
95 struct sun4m_hwdef {
96 target_phys_addr_t iommu_base, slavio_base;
97 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
98 target_phys_addr_t serial_base, fd_base;
99 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
100 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
101 target_phys_addr_t ecc_base;
102 uint32_t ecc_version;
103 uint8_t nvram_machine_id;
104 uint16_t machine_id;
105 uint32_t iommu_version;
106 uint64_t max_mem;
107 const char * const default_cpu_model;
108 };
109
110 #define MAX_IOUNITS 5
111
112 struct sun4d_hwdef {
113 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
114 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
115 target_phys_addr_t serial_base;
116 target_phys_addr_t espdma_base, esp_base;
117 target_phys_addr_t ledma_base, le_base;
118 target_phys_addr_t tcx_base;
119 target_phys_addr_t sbi_base;
120 uint8_t nvram_machine_id;
121 uint16_t machine_id;
122 uint32_t iounit_version;
123 uint64_t max_mem;
124 const char * const default_cpu_model;
125 };
126
127 struct sun4c_hwdef {
128 target_phys_addr_t iommu_base, slavio_base;
129 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
130 target_phys_addr_t serial_base, fd_base;
131 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
132 target_phys_addr_t tcx_base, aux1_base;
133 uint8_t nvram_machine_id;
134 uint16_t machine_id;
135 uint32_t iommu_version;
136 uint64_t max_mem;
137 const char * const default_cpu_model;
138 };
139
140 int DMA_get_channel_mode (int nchan)
141 {
142 return 0;
143 }
144 int DMA_read_memory (int nchan, void *buf, int pos, int size)
145 {
146 return 0;
147 }
148 int DMA_write_memory (int nchan, void *buf, int pos, int size)
149 {
150 return 0;
151 }
152 void DMA_hold_DREQ (int nchan) {}
153 void DMA_release_DREQ (int nchan) {}
154 void DMA_schedule(int nchan) {}
155 void DMA_init (int high_page_enable) {}
156 void DMA_register_channel (int nchan,
157 DMA_transfer_handler transfer_handler,
158 void *opaque)
159 {
160 }
161
162 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
163 {
164 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
165 return 0;
166 }
167
168 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
169 const char *cmdline, const char *boot_devices,
170 ram_addr_t RAM_size, uint32_t kernel_size,
171 int width, int height, int depth,
172 int nvram_machine_id, const char *arch)
173 {
174 unsigned int i;
175 uint32_t start, end;
176 uint8_t image[0x1ff0];
177 struct OpenBIOS_nvpart_v1 *part_header;
178
179 memset(image, '\0', sizeof(image));
180
181 start = 0;
182
183 // OpenBIOS nvram variables
184 // Variable partition
185 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
186 part_header->signature = OPENBIOS_PART_SYSTEM;
187 pstrcpy(part_header->name, sizeof(part_header->name), "system");
188
189 end = start + sizeof(struct OpenBIOS_nvpart_v1);
190 for (i = 0; i < nb_prom_envs; i++)
191 end = OpenBIOS_set_var(image, end, prom_envs[i]);
192
193 // End marker
194 image[end++] = '\0';
195
196 end = start + ((end - start + 15) & ~15);
197 OpenBIOS_finish_partition(part_header, end - start);
198
199 // free partition
200 start = end;
201 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
202 part_header->signature = OPENBIOS_PART_FREE;
203 pstrcpy(part_header->name, sizeof(part_header->name), "free");
204
205 end = 0x1fd0;
206 OpenBIOS_finish_partition(part_header, end - start);
207
208 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
209 nvram_machine_id);
210
211 for (i = 0; i < sizeof(image); i++)
212 m48t59_write(nvram, i, image[i]);
213 }
214
215 static DeviceState *slavio_intctl;
216
217 void pic_info(Monitor *mon)
218 {
219 if (slavio_intctl)
220 slavio_pic_info(mon, slavio_intctl);
221 }
222
223 void irq_info(Monitor *mon)
224 {
225 if (slavio_intctl)
226 slavio_irq_info(mon, slavio_intctl);
227 }
228
229 void cpu_check_irqs(CPUState *env)
230 {
231 if (env->pil_in && (env->interrupt_index == 0 ||
232 (env->interrupt_index & ~15) == TT_EXTINT)) {
233 unsigned int i;
234
235 for (i = 15; i > 0; i--) {
236 if (env->pil_in & (1 << i)) {
237 int old_interrupt = env->interrupt_index;
238
239 env->interrupt_index = TT_EXTINT | i;
240 if (old_interrupt != env->interrupt_index) {
241 DPRINTF("Set CPU IRQ %d\n", i);
242 cpu_interrupt(env, CPU_INTERRUPT_HARD);
243 }
244 break;
245 }
246 }
247 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
248 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
249 env->interrupt_index = 0;
250 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
251 }
252 }
253
254 static void cpu_set_irq(void *opaque, int irq, int level)
255 {
256 CPUState *env = opaque;
257
258 if (level) {
259 DPRINTF("Raise CPU IRQ %d\n", irq);
260 env->halted = 0;
261 env->pil_in |= 1 << irq;
262 cpu_check_irqs(env);
263 } else {
264 DPRINTF("Lower CPU IRQ %d\n", irq);
265 env->pil_in &= ~(1 << irq);
266 cpu_check_irqs(env);
267 }
268 }
269
270 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
271 {
272 }
273
274 static void main_cpu_reset(void *opaque)
275 {
276 CPUState *env = opaque;
277
278 cpu_reset(env);
279 env->halted = 0;
280 }
281
282 static void secondary_cpu_reset(void *opaque)
283 {
284 CPUState *env = opaque;
285
286 cpu_reset(env);
287 env->halted = 1;
288 }
289
290 static void cpu_halt_signal(void *opaque, int irq, int level)
291 {
292 if (level && cpu_single_env)
293 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
294 }
295
296 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
297 {
298 return addr - 0xf0000000ULL;
299 }
300
301 static unsigned long sun4m_load_kernel(const char *kernel_filename,
302 const char *initrd_filename,
303 ram_addr_t RAM_size)
304 {
305 int linux_boot;
306 unsigned int i;
307 long initrd_size, kernel_size;
308 uint8_t *ptr;
309
310 linux_boot = (kernel_filename != NULL);
311
312 kernel_size = 0;
313 if (linux_boot) {
314 int bswap_needed;
315
316 #ifdef BSWAP_NEEDED
317 bswap_needed = 1;
318 #else
319 bswap_needed = 0;
320 #endif
321 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
322 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
323 if (kernel_size < 0)
324 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
325 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
326 TARGET_PAGE_SIZE);
327 if (kernel_size < 0)
328 kernel_size = load_image_targphys(kernel_filename,
329 KERNEL_LOAD_ADDR,
330 RAM_size - KERNEL_LOAD_ADDR);
331 if (kernel_size < 0) {
332 fprintf(stderr, "qemu: could not load kernel '%s'\n",
333 kernel_filename);
334 exit(1);
335 }
336
337 /* load initrd */
338 initrd_size = 0;
339 if (initrd_filename) {
340 initrd_size = load_image_targphys(initrd_filename,
341 INITRD_LOAD_ADDR,
342 RAM_size - INITRD_LOAD_ADDR);
343 if (initrd_size < 0) {
344 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
345 initrd_filename);
346 exit(1);
347 }
348 }
349 if (initrd_size > 0) {
350 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
351 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
352 if (ldl_p(ptr) == 0x48647253) { // HdrS
353 stl_p(ptr + 16, INITRD_LOAD_ADDR);
354 stl_p(ptr + 20, initrd_size);
355 break;
356 }
357 }
358 }
359 }
360 return kernel_size;
361 }
362
363 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
364 {
365 DeviceState *dev;
366 SysBusDevice *s;
367
368 dev = qdev_create(NULL, "iommu");
369 qdev_prop_set_uint32(dev, "version", version);
370 qdev_init_nofail(dev);
371 s = sysbus_from_qdev(dev);
372 sysbus_connect_irq(s, 0, irq);
373 sysbus_mmio_map(s, 0, addr);
374
375 return s;
376 }
377
378 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
379 void *iommu, qemu_irq *dev_irq)
380 {
381 DeviceState *dev;
382 SysBusDevice *s;
383
384 dev = qdev_create(NULL, "sparc32_dma");
385 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
386 qdev_init_nofail(dev);
387 s = sysbus_from_qdev(dev);
388 sysbus_connect_irq(s, 0, parent_irq);
389 *dev_irq = qdev_get_gpio_in(dev, 0);
390 sysbus_mmio_map(s, 0, daddr);
391
392 return s;
393 }
394
395 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
396 void *dma_opaque, qemu_irq irq)
397 {
398 DeviceState *dev;
399 SysBusDevice *s;
400 qemu_irq reset;
401
402 qemu_check_nic_model(&nd_table[0], "lance");
403
404 dev = qdev_create(NULL, "lance");
405 qdev_set_nic_properties(dev, nd);
406 qdev_prop_set_ptr(dev, "dma", dma_opaque);
407 qdev_init_nofail(dev);
408 s = sysbus_from_qdev(dev);
409 sysbus_mmio_map(s, 0, leaddr);
410 sysbus_connect_irq(s, 0, irq);
411 reset = qdev_get_gpio_in(dev, 0);
412 qdev_connect_gpio_out(dma_opaque, 0, reset);
413 }
414
415 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
416 target_phys_addr_t addrg,
417 qemu_irq **parent_irq)
418 {
419 DeviceState *dev;
420 SysBusDevice *s;
421 unsigned int i, j;
422
423 dev = qdev_create(NULL, "slavio_intctl");
424 qdev_init_nofail(dev);
425
426 s = sysbus_from_qdev(dev);
427
428 for (i = 0; i < MAX_CPUS; i++) {
429 for (j = 0; j < MAX_PILS; j++) {
430 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
431 }
432 }
433 sysbus_mmio_map(s, 0, addrg);
434 for (i = 0; i < MAX_CPUS; i++) {
435 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
436 }
437
438 return dev;
439 }
440
441 #define SYS_TIMER_OFFSET 0x10000ULL
442 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
443
444 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
445 qemu_irq *cpu_irqs, unsigned int num_cpus)
446 {
447 DeviceState *dev;
448 SysBusDevice *s;
449 unsigned int i;
450
451 dev = qdev_create(NULL, "slavio_timer");
452 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
453 qdev_init_nofail(dev);
454 s = sysbus_from_qdev(dev);
455 sysbus_connect_irq(s, 0, master_irq);
456 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
457
458 for (i = 0; i < MAX_CPUS; i++) {
459 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
460 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
461 }
462 }
463
464 #define MISC_LEDS 0x01600000
465 #define MISC_CFG 0x01800000
466 #define MISC_DIAG 0x01a00000
467 #define MISC_MDM 0x01b00000
468 #define MISC_SYS 0x01f00000
469
470 static void slavio_misc_init(target_phys_addr_t base,
471 target_phys_addr_t aux1_base,
472 target_phys_addr_t aux2_base, qemu_irq irq,
473 qemu_irq fdc_tc)
474 {
475 DeviceState *dev;
476 SysBusDevice *s;
477
478 dev = qdev_create(NULL, "slavio_misc");
479 qdev_init_nofail(dev);
480 s = sysbus_from_qdev(dev);
481 if (base) {
482 /* 8 bit registers */
483 /* Slavio control */
484 sysbus_mmio_map(s, 0, base + MISC_CFG);
485 /* Diagnostics */
486 sysbus_mmio_map(s, 1, base + MISC_DIAG);
487 /* Modem control */
488 sysbus_mmio_map(s, 2, base + MISC_MDM);
489 /* 16 bit registers */
490 /* ss600mp diag LEDs */
491 sysbus_mmio_map(s, 3, base + MISC_LEDS);
492 /* 32 bit registers */
493 /* System control */
494 sysbus_mmio_map(s, 4, base + MISC_SYS);
495 }
496 if (aux1_base) {
497 /* AUX 1 (Misc System Functions) */
498 sysbus_mmio_map(s, 5, aux1_base);
499 }
500 if (aux2_base) {
501 /* AUX 2 (Software Powerdown Control) */
502 sysbus_mmio_map(s, 6, aux2_base);
503 }
504 sysbus_connect_irq(s, 0, irq);
505 sysbus_connect_irq(s, 1, fdc_tc);
506 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
507 }
508
509 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
510 {
511 DeviceState *dev;
512 SysBusDevice *s;
513
514 dev = qdev_create(NULL, "eccmemctl");
515 qdev_prop_set_uint32(dev, "version", version);
516 qdev_init_nofail(dev);
517 s = sysbus_from_qdev(dev);
518 sysbus_connect_irq(s, 0, irq);
519 sysbus_mmio_map(s, 0, base);
520 if (version == 0) { // SS-600MP only
521 sysbus_mmio_map(s, 1, base + 0x1000);
522 }
523 }
524
525 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
526 {
527 DeviceState *dev;
528 SysBusDevice *s;
529
530 dev = qdev_create(NULL, "apc");
531 qdev_init_nofail(dev);
532 s = sysbus_from_qdev(dev);
533 /* Power management (APC) XXX: not a Slavio device */
534 sysbus_mmio_map(s, 0, power_base);
535 sysbus_connect_irq(s, 0, cpu_halt);
536 }
537
538 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
539 int height, int depth)
540 {
541 DeviceState *dev;
542 SysBusDevice *s;
543
544 dev = qdev_create(NULL, "SUNW,tcx");
545 qdev_prop_set_taddr(dev, "addr", addr);
546 qdev_prop_set_uint32(dev, "vram_size", vram_size);
547 qdev_prop_set_uint16(dev, "width", width);
548 qdev_prop_set_uint16(dev, "height", height);
549 qdev_prop_set_uint16(dev, "depth", depth);
550 qdev_init_nofail(dev);
551 s = sysbus_from_qdev(dev);
552 /* 8-bit plane */
553 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
554 /* DAC */
555 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
556 /* TEC (dummy) */
557 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
558 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
559 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
560 if (depth == 24) {
561 /* 24-bit plane */
562 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
563 /* Control plane */
564 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
565 } else {
566 /* THC 8 bit (dummy) */
567 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
568 }
569 }
570
571 /* NCR89C100/MACIO Internal ID register */
572 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
573
574 static void idreg_init(target_phys_addr_t addr)
575 {
576 DeviceState *dev;
577 SysBusDevice *s;
578
579 dev = qdev_create(NULL, "macio_idreg");
580 qdev_init_nofail(dev);
581 s = sysbus_from_qdev(dev);
582
583 sysbus_mmio_map(s, 0, addr);
584 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
585 }
586
587 static int idreg_init1(SysBusDevice *dev)
588 {
589 ram_addr_t idreg_offset;
590
591 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
592 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
593 return 0;
594 }
595
596 static SysBusDeviceInfo idreg_info = {
597 .init = idreg_init1,
598 .qdev.name = "macio_idreg",
599 .qdev.size = sizeof(SysBusDevice),
600 };
601
602 static void idreg_register_devices(void)
603 {
604 sysbus_register_withprop(&idreg_info);
605 }
606
607 device_init(idreg_register_devices);
608
609 /* SS-5 TCX AFX register */
610 static void afx_init(target_phys_addr_t addr)
611 {
612 DeviceState *dev;
613 SysBusDevice *s;
614
615 dev = qdev_create(NULL, "tcx_afx");
616 qdev_init_nofail(dev);
617 s = sysbus_from_qdev(dev);
618
619 sysbus_mmio_map(s, 0, addr);
620 }
621
622 static int afx_init1(SysBusDevice *dev)
623 {
624 ram_addr_t afx_offset;
625
626 afx_offset = qemu_ram_alloc(4);
627 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
628 return 0;
629 }
630
631 static SysBusDeviceInfo afx_info = {
632 .init = afx_init1,
633 .qdev.name = "tcx_afx",
634 .qdev.size = sizeof(SysBusDevice),
635 };
636
637 static void afx_register_devices(void)
638 {
639 sysbus_register_withprop(&afx_info);
640 }
641
642 device_init(afx_register_devices);
643
644 /* Boot PROM (OpenBIOS) */
645 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
646 {
647 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
648 return addr + *base_addr - PROM_VADDR;
649 }
650
651 static void prom_init(target_phys_addr_t addr, const char *bios_name)
652 {
653 DeviceState *dev;
654 SysBusDevice *s;
655 char *filename;
656 int ret;
657
658 dev = qdev_create(NULL, "openprom");
659 qdev_init_nofail(dev);
660 s = sysbus_from_qdev(dev);
661
662 sysbus_mmio_map(s, 0, addr);
663
664 /* load boot prom */
665 if (bios_name == NULL) {
666 bios_name = PROM_FILENAME;
667 }
668 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
669 if (filename) {
670 ret = load_elf(filename, translate_prom_address, &addr, NULL,
671 NULL, NULL, 1, ELF_MACHINE, 0);
672 if (ret < 0 || ret > PROM_SIZE_MAX) {
673 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
674 }
675 qemu_free(filename);
676 } else {
677 ret = -1;
678 }
679 if (ret < 0 || ret > PROM_SIZE_MAX) {
680 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
681 exit(1);
682 }
683 }
684
685 static int prom_init1(SysBusDevice *dev)
686 {
687 ram_addr_t prom_offset;
688
689 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
690 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
691 return 0;
692 }
693
694 static SysBusDeviceInfo prom_info = {
695 .init = prom_init1,
696 .qdev.name = "openprom",
697 .qdev.size = sizeof(SysBusDevice),
698 .qdev.props = (Property[]) {
699 {/* end of property list */}
700 }
701 };
702
703 static void prom_register_devices(void)
704 {
705 sysbus_register_withprop(&prom_info);
706 }
707
708 device_init(prom_register_devices);
709
710 typedef struct RamDevice
711 {
712 SysBusDevice busdev;
713 uint64_t size;
714 } RamDevice;
715
716 /* System RAM */
717 static int ram_init1(SysBusDevice *dev)
718 {
719 ram_addr_t RAM_size, ram_offset;
720 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
721
722 RAM_size = d->size;
723
724 ram_offset = qemu_ram_alloc(RAM_size);
725 sysbus_init_mmio(dev, RAM_size, ram_offset);
726 return 0;
727 }
728
729 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
730 uint64_t max_mem)
731 {
732 DeviceState *dev;
733 SysBusDevice *s;
734 RamDevice *d;
735
736 /* allocate RAM */
737 if ((uint64_t)RAM_size > max_mem) {
738 fprintf(stderr,
739 "qemu: Too much memory for this machine: %d, maximum %d\n",
740 (unsigned int)(RAM_size / (1024 * 1024)),
741 (unsigned int)(max_mem / (1024 * 1024)));
742 exit(1);
743 }
744 dev = qdev_create(NULL, "memory");
745 s = sysbus_from_qdev(dev);
746
747 d = FROM_SYSBUS(RamDevice, s);
748 d->size = RAM_size;
749 qdev_init_nofail(dev);
750
751 sysbus_mmio_map(s, 0, addr);
752 }
753
754 static SysBusDeviceInfo ram_info = {
755 .init = ram_init1,
756 .qdev.name = "memory",
757 .qdev.size = sizeof(RamDevice),
758 .qdev.props = (Property[]) {
759 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
760 DEFINE_PROP_END_OF_LIST(),
761 }
762 };
763
764 static void ram_register_devices(void)
765 {
766 sysbus_register_withprop(&ram_info);
767 }
768
769 device_init(ram_register_devices);
770
771 static void cpu_devinit(const char *cpu_model, unsigned int id,
772 uint64_t prom_addr, qemu_irq **cpu_irqs)
773 {
774 CPUState *env;
775
776 env = cpu_init(cpu_model);
777 if (!env) {
778 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
779 exit(1);
780 }
781
782 cpu_sparc_set_id(env, id);
783 if (id == 0) {
784 qemu_register_reset(main_cpu_reset, env);
785 } else {
786 qemu_register_reset(secondary_cpu_reset, env);
787 env->halted = 1;
788 }
789 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
790 env->prom_addr = prom_addr;
791 }
792
793 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
794 const char *boot_device,
795 const char *kernel_filename,
796 const char *kernel_cmdline,
797 const char *initrd_filename, const char *cpu_model)
798 {
799 unsigned int i;
800 void *iommu, *espdma, *ledma, *nvram;
801 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
802 espdma_irq, ledma_irq;
803 qemu_irq esp_reset;
804 qemu_irq fdc_tc;
805 qemu_irq *cpu_halt;
806 unsigned long kernel_size;
807 DriveInfo *fd[MAX_FD];
808 void *fw_cfg;
809
810 /* init CPUs */
811 if (!cpu_model)
812 cpu_model = hwdef->default_cpu_model;
813
814 for(i = 0; i < smp_cpus; i++) {
815 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
816 }
817
818 for (i = smp_cpus; i < MAX_CPUS; i++)
819 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
820
821
822 /* set up devices */
823 ram_init(0, RAM_size, hwdef->max_mem);
824 /* models without ECC don't trap when missing ram is accessed */
825 if (!hwdef->ecc_base) {
826 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
827 }
828
829 prom_init(hwdef->slavio_base, bios_name);
830
831 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
832 hwdef->intctl_base + 0x10000ULL,
833 cpu_irqs);
834
835 for (i = 0; i < 32; i++) {
836 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
837 }
838 for (i = 0; i < MAX_CPUS; i++) {
839 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
840 }
841
842 if (hwdef->idreg_base) {
843 idreg_init(hwdef->idreg_base);
844 }
845
846 if (hwdef->afx_base) {
847 afx_init(hwdef->afx_base);
848 }
849
850 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
851 slavio_irq[30]);
852
853 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
854 iommu, &espdma_irq);
855
856 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
857 slavio_irq[16], iommu, &ledma_irq);
858
859 if (graphic_depth != 8 && graphic_depth != 24) {
860 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
861 exit (1);
862 }
863 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
864 graphic_depth);
865
866 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
867
868 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
869
870 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
871
872 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
873 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
874 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
875 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
876 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
877 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
878
879 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
880 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
881 slavio_irq[30], fdc_tc);
882
883 if (hwdef->apc_base) {
884 apc_init(hwdef->apc_base, cpu_halt[0]);
885 }
886
887 if (hwdef->fd_base) {
888 /* there is zero or one floppy drive */
889 memset(fd, 0, sizeof(fd));
890 fd[0] = drive_get(IF_FLOPPY, 0, 0);
891 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
892 &fdc_tc);
893 }
894
895 if (drive_get_max_bus(IF_SCSI) > 0) {
896 fprintf(stderr, "qemu: too many SCSI bus\n");
897 exit(1);
898 }
899
900 esp_reset = qdev_get_gpio_in(espdma, 0);
901 esp_init(hwdef->esp_base, 2,
902 espdma_memory_read, espdma_memory_write,
903 espdma, espdma_irq, &esp_reset);
904
905
906 if (hwdef->cs_base) {
907 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
908 slavio_irq[5]);
909 }
910
911 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
912 RAM_size);
913
914 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
915 boot_device, RAM_size, kernel_size, graphic_width,
916 graphic_height, graphic_depth, hwdef->nvram_machine_id,
917 "Sun4m");
918
919 if (hwdef->ecc_base)
920 ecc_init(hwdef->ecc_base, slavio_irq[28],
921 hwdef->ecc_version);
922
923 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
924 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
925 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
926 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
927 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
928 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
929 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
930 if (kernel_cmdline) {
931 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
932 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
933 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
934 (uint8_t*)strdup(kernel_cmdline),
935 strlen(kernel_cmdline) + 1);
936 } else {
937 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
938 }
939 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
940 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
941 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
942 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
943 }
944
945 enum {
946 ss2_id = 0,
947 ss5_id = 32,
948 vger_id,
949 lx_id,
950 ss4_id,
951 scls_id,
952 sbook_id,
953 ss10_id = 64,
954 ss20_id,
955 ss600mp_id,
956 ss1000_id = 96,
957 ss2000_id,
958 };
959
960 static const struct sun4m_hwdef sun4m_hwdefs[] = {
961 /* SS-5 */
962 {
963 .iommu_base = 0x10000000,
964 .tcx_base = 0x50000000,
965 .cs_base = 0x6c000000,
966 .slavio_base = 0x70000000,
967 .ms_kb_base = 0x71000000,
968 .serial_base = 0x71100000,
969 .nvram_base = 0x71200000,
970 .fd_base = 0x71400000,
971 .counter_base = 0x71d00000,
972 .intctl_base = 0x71e00000,
973 .idreg_base = 0x78000000,
974 .dma_base = 0x78400000,
975 .esp_base = 0x78800000,
976 .le_base = 0x78c00000,
977 .apc_base = 0x6a000000,
978 .afx_base = 0x6e000000,
979 .aux1_base = 0x71900000,
980 .aux2_base = 0x71910000,
981 .nvram_machine_id = 0x80,
982 .machine_id = ss5_id,
983 .iommu_version = 0x05000000,
984 .max_mem = 0x10000000,
985 .default_cpu_model = "Fujitsu MB86904",
986 },
987 /* SS-10 */
988 {
989 .iommu_base = 0xfe0000000ULL,
990 .tcx_base = 0xe20000000ULL,
991 .slavio_base = 0xff0000000ULL,
992 .ms_kb_base = 0xff1000000ULL,
993 .serial_base = 0xff1100000ULL,
994 .nvram_base = 0xff1200000ULL,
995 .fd_base = 0xff1700000ULL,
996 .counter_base = 0xff1300000ULL,
997 .intctl_base = 0xff1400000ULL,
998 .idreg_base = 0xef0000000ULL,
999 .dma_base = 0xef0400000ULL,
1000 .esp_base = 0xef0800000ULL,
1001 .le_base = 0xef0c00000ULL,
1002 .apc_base = 0xefa000000ULL, // XXX should not exist
1003 .aux1_base = 0xff1800000ULL,
1004 .aux2_base = 0xff1a01000ULL,
1005 .ecc_base = 0xf00000000ULL,
1006 .ecc_version = 0x10000000, // version 0, implementation 1
1007 .nvram_machine_id = 0x72,
1008 .machine_id = ss10_id,
1009 .iommu_version = 0x03000000,
1010 .max_mem = 0xf00000000ULL,
1011 .default_cpu_model = "TI SuperSparc II",
1012 },
1013 /* SS-600MP */
1014 {
1015 .iommu_base = 0xfe0000000ULL,
1016 .tcx_base = 0xe20000000ULL,
1017 .slavio_base = 0xff0000000ULL,
1018 .ms_kb_base = 0xff1000000ULL,
1019 .serial_base = 0xff1100000ULL,
1020 .nvram_base = 0xff1200000ULL,
1021 .counter_base = 0xff1300000ULL,
1022 .intctl_base = 0xff1400000ULL,
1023 .dma_base = 0xef0081000ULL,
1024 .esp_base = 0xef0080000ULL,
1025 .le_base = 0xef0060000ULL,
1026 .apc_base = 0xefa000000ULL, // XXX should not exist
1027 .aux1_base = 0xff1800000ULL,
1028 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1029 .ecc_base = 0xf00000000ULL,
1030 .ecc_version = 0x00000000, // version 0, implementation 0
1031 .nvram_machine_id = 0x71,
1032 .machine_id = ss600mp_id,
1033 .iommu_version = 0x01000000,
1034 .max_mem = 0xf00000000ULL,
1035 .default_cpu_model = "TI SuperSparc II",
1036 },
1037 /* SS-20 */
1038 {
1039 .iommu_base = 0xfe0000000ULL,
1040 .tcx_base = 0xe20000000ULL,
1041 .slavio_base = 0xff0000000ULL,
1042 .ms_kb_base = 0xff1000000ULL,
1043 .serial_base = 0xff1100000ULL,
1044 .nvram_base = 0xff1200000ULL,
1045 .fd_base = 0xff1700000ULL,
1046 .counter_base = 0xff1300000ULL,
1047 .intctl_base = 0xff1400000ULL,
1048 .idreg_base = 0xef0000000ULL,
1049 .dma_base = 0xef0400000ULL,
1050 .esp_base = 0xef0800000ULL,
1051 .le_base = 0xef0c00000ULL,
1052 .apc_base = 0xefa000000ULL, // XXX should not exist
1053 .aux1_base = 0xff1800000ULL,
1054 .aux2_base = 0xff1a01000ULL,
1055 .ecc_base = 0xf00000000ULL,
1056 .ecc_version = 0x20000000, // version 0, implementation 2
1057 .nvram_machine_id = 0x72,
1058 .machine_id = ss20_id,
1059 .iommu_version = 0x13000000,
1060 .max_mem = 0xf00000000ULL,
1061 .default_cpu_model = "TI SuperSparc II",
1062 },
1063 /* Voyager */
1064 {
1065 .iommu_base = 0x10000000,
1066 .tcx_base = 0x50000000,
1067 .slavio_base = 0x70000000,
1068 .ms_kb_base = 0x71000000,
1069 .serial_base = 0x71100000,
1070 .nvram_base = 0x71200000,
1071 .fd_base = 0x71400000,
1072 .counter_base = 0x71d00000,
1073 .intctl_base = 0x71e00000,
1074 .idreg_base = 0x78000000,
1075 .dma_base = 0x78400000,
1076 .esp_base = 0x78800000,
1077 .le_base = 0x78c00000,
1078 .apc_base = 0x71300000, // pmc
1079 .aux1_base = 0x71900000,
1080 .aux2_base = 0x71910000,
1081 .nvram_machine_id = 0x80,
1082 .machine_id = vger_id,
1083 .iommu_version = 0x05000000,
1084 .max_mem = 0x10000000,
1085 .default_cpu_model = "Fujitsu MB86904",
1086 },
1087 /* LX */
1088 {
1089 .iommu_base = 0x10000000,
1090 .tcx_base = 0x50000000,
1091 .slavio_base = 0x70000000,
1092 .ms_kb_base = 0x71000000,
1093 .serial_base = 0x71100000,
1094 .nvram_base = 0x71200000,
1095 .fd_base = 0x71400000,
1096 .counter_base = 0x71d00000,
1097 .intctl_base = 0x71e00000,
1098 .idreg_base = 0x78000000,
1099 .dma_base = 0x78400000,
1100 .esp_base = 0x78800000,
1101 .le_base = 0x78c00000,
1102 .aux1_base = 0x71900000,
1103 .aux2_base = 0x71910000,
1104 .nvram_machine_id = 0x80,
1105 .machine_id = lx_id,
1106 .iommu_version = 0x04000000,
1107 .max_mem = 0x10000000,
1108 .default_cpu_model = "TI MicroSparc I",
1109 },
1110 /* SS-4 */
1111 {
1112 .iommu_base = 0x10000000,
1113 .tcx_base = 0x50000000,
1114 .cs_base = 0x6c000000,
1115 .slavio_base = 0x70000000,
1116 .ms_kb_base = 0x71000000,
1117 .serial_base = 0x71100000,
1118 .nvram_base = 0x71200000,
1119 .fd_base = 0x71400000,
1120 .counter_base = 0x71d00000,
1121 .intctl_base = 0x71e00000,
1122 .idreg_base = 0x78000000,
1123 .dma_base = 0x78400000,
1124 .esp_base = 0x78800000,
1125 .le_base = 0x78c00000,
1126 .apc_base = 0x6a000000,
1127 .aux1_base = 0x71900000,
1128 .aux2_base = 0x71910000,
1129 .nvram_machine_id = 0x80,
1130 .machine_id = ss4_id,
1131 .iommu_version = 0x05000000,
1132 .max_mem = 0x10000000,
1133 .default_cpu_model = "Fujitsu MB86904",
1134 },
1135 /* SPARCClassic */
1136 {
1137 .iommu_base = 0x10000000,
1138 .tcx_base = 0x50000000,
1139 .slavio_base = 0x70000000,
1140 .ms_kb_base = 0x71000000,
1141 .serial_base = 0x71100000,
1142 .nvram_base = 0x71200000,
1143 .fd_base = 0x71400000,
1144 .counter_base = 0x71d00000,
1145 .intctl_base = 0x71e00000,
1146 .idreg_base = 0x78000000,
1147 .dma_base = 0x78400000,
1148 .esp_base = 0x78800000,
1149 .le_base = 0x78c00000,
1150 .apc_base = 0x6a000000,
1151 .aux1_base = 0x71900000,
1152 .aux2_base = 0x71910000,
1153 .nvram_machine_id = 0x80,
1154 .machine_id = scls_id,
1155 .iommu_version = 0x05000000,
1156 .max_mem = 0x10000000,
1157 .default_cpu_model = "TI MicroSparc I",
1158 },
1159 /* SPARCbook */
1160 {
1161 .iommu_base = 0x10000000,
1162 .tcx_base = 0x50000000, // XXX
1163 .slavio_base = 0x70000000,
1164 .ms_kb_base = 0x71000000,
1165 .serial_base = 0x71100000,
1166 .nvram_base = 0x71200000,
1167 .fd_base = 0x71400000,
1168 .counter_base = 0x71d00000,
1169 .intctl_base = 0x71e00000,
1170 .idreg_base = 0x78000000,
1171 .dma_base = 0x78400000,
1172 .esp_base = 0x78800000,
1173 .le_base = 0x78c00000,
1174 .apc_base = 0x6a000000,
1175 .aux1_base = 0x71900000,
1176 .aux2_base = 0x71910000,
1177 .nvram_machine_id = 0x80,
1178 .machine_id = sbook_id,
1179 .iommu_version = 0x05000000,
1180 .max_mem = 0x10000000,
1181 .default_cpu_model = "TI MicroSparc I",
1182 },
1183 };
1184
1185 /* SPARCstation 5 hardware initialisation */
1186 static void ss5_init(ram_addr_t RAM_size,
1187 const char *boot_device,
1188 const char *kernel_filename, const char *kernel_cmdline,
1189 const char *initrd_filename, const char *cpu_model)
1190 {
1191 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1192 kernel_cmdline, initrd_filename, cpu_model);
1193 }
1194
1195 /* SPARCstation 10 hardware initialisation */
1196 static void ss10_init(ram_addr_t RAM_size,
1197 const char *boot_device,
1198 const char *kernel_filename, const char *kernel_cmdline,
1199 const char *initrd_filename, const char *cpu_model)
1200 {
1201 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1202 kernel_cmdline, initrd_filename, cpu_model);
1203 }
1204
1205 /* SPARCserver 600MP hardware initialisation */
1206 static void ss600mp_init(ram_addr_t RAM_size,
1207 const char *boot_device,
1208 const char *kernel_filename,
1209 const char *kernel_cmdline,
1210 const char *initrd_filename, const char *cpu_model)
1211 {
1212 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1213 kernel_cmdline, initrd_filename, cpu_model);
1214 }
1215
1216 /* SPARCstation 20 hardware initialisation */
1217 static void ss20_init(ram_addr_t RAM_size,
1218 const char *boot_device,
1219 const char *kernel_filename, const char *kernel_cmdline,
1220 const char *initrd_filename, const char *cpu_model)
1221 {
1222 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1223 kernel_cmdline, initrd_filename, cpu_model);
1224 }
1225
1226 /* SPARCstation Voyager hardware initialisation */
1227 static void vger_init(ram_addr_t RAM_size,
1228 const char *boot_device,
1229 const char *kernel_filename, const char *kernel_cmdline,
1230 const char *initrd_filename, const char *cpu_model)
1231 {
1232 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1233 kernel_cmdline, initrd_filename, cpu_model);
1234 }
1235
1236 /* SPARCstation LX hardware initialisation */
1237 static void ss_lx_init(ram_addr_t RAM_size,
1238 const char *boot_device,
1239 const char *kernel_filename, const char *kernel_cmdline,
1240 const char *initrd_filename, const char *cpu_model)
1241 {
1242 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1243 kernel_cmdline, initrd_filename, cpu_model);
1244 }
1245
1246 /* SPARCstation 4 hardware initialisation */
1247 static void ss4_init(ram_addr_t RAM_size,
1248 const char *boot_device,
1249 const char *kernel_filename, const char *kernel_cmdline,
1250 const char *initrd_filename, const char *cpu_model)
1251 {
1252 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1253 kernel_cmdline, initrd_filename, cpu_model);
1254 }
1255
1256 /* SPARCClassic hardware initialisation */
1257 static void scls_init(ram_addr_t RAM_size,
1258 const char *boot_device,
1259 const char *kernel_filename, const char *kernel_cmdline,
1260 const char *initrd_filename, const char *cpu_model)
1261 {
1262 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1263 kernel_cmdline, initrd_filename, cpu_model);
1264 }
1265
1266 /* SPARCbook hardware initialisation */
1267 static void sbook_init(ram_addr_t RAM_size,
1268 const char *boot_device,
1269 const char *kernel_filename, const char *kernel_cmdline,
1270 const char *initrd_filename, const char *cpu_model)
1271 {
1272 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1273 kernel_cmdline, initrd_filename, cpu_model);
1274 }
1275
1276 static QEMUMachine ss5_machine = {
1277 .name = "SS-5",
1278 .desc = "Sun4m platform, SPARCstation 5",
1279 .init = ss5_init,
1280 .use_scsi = 1,
1281 .is_default = 1,
1282 };
1283
1284 static QEMUMachine ss10_machine = {
1285 .name = "SS-10",
1286 .desc = "Sun4m platform, SPARCstation 10",
1287 .init = ss10_init,
1288 .use_scsi = 1,
1289 .max_cpus = 4,
1290 };
1291
1292 static QEMUMachine ss600mp_machine = {
1293 .name = "SS-600MP",
1294 .desc = "Sun4m platform, SPARCserver 600MP",
1295 .init = ss600mp_init,
1296 .use_scsi = 1,
1297 .max_cpus = 4,
1298 };
1299
1300 static QEMUMachine ss20_machine = {
1301 .name = "SS-20",
1302 .desc = "Sun4m platform, SPARCstation 20",
1303 .init = ss20_init,
1304 .use_scsi = 1,
1305 .max_cpus = 4,
1306 };
1307
1308 static QEMUMachine voyager_machine = {
1309 .name = "Voyager",
1310 .desc = "Sun4m platform, SPARCstation Voyager",
1311 .init = vger_init,
1312 .use_scsi = 1,
1313 };
1314
1315 static QEMUMachine ss_lx_machine = {
1316 .name = "LX",
1317 .desc = "Sun4m platform, SPARCstation LX",
1318 .init = ss_lx_init,
1319 .use_scsi = 1,
1320 };
1321
1322 static QEMUMachine ss4_machine = {
1323 .name = "SS-4",
1324 .desc = "Sun4m platform, SPARCstation 4",
1325 .init = ss4_init,
1326 .use_scsi = 1,
1327 };
1328
1329 static QEMUMachine scls_machine = {
1330 .name = "SPARCClassic",
1331 .desc = "Sun4m platform, SPARCClassic",
1332 .init = scls_init,
1333 .use_scsi = 1,
1334 };
1335
1336 static QEMUMachine sbook_machine = {
1337 .name = "SPARCbook",
1338 .desc = "Sun4m platform, SPARCbook",
1339 .init = sbook_init,
1340 .use_scsi = 1,
1341 };
1342
1343 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1344 /* SS-1000 */
1345 {
1346 .iounit_bases = {
1347 0xfe0200000ULL,
1348 0xfe1200000ULL,
1349 0xfe2200000ULL,
1350 0xfe3200000ULL,
1351 -1,
1352 },
1353 .tcx_base = 0x820000000ULL,
1354 .slavio_base = 0xf00000000ULL,
1355 .ms_kb_base = 0xf00240000ULL,
1356 .serial_base = 0xf00200000ULL,
1357 .nvram_base = 0xf00280000ULL,
1358 .counter_base = 0xf00300000ULL,
1359 .espdma_base = 0x800081000ULL,
1360 .esp_base = 0x800080000ULL,
1361 .ledma_base = 0x800040000ULL,
1362 .le_base = 0x800060000ULL,
1363 .sbi_base = 0xf02800000ULL,
1364 .nvram_machine_id = 0x80,
1365 .machine_id = ss1000_id,
1366 .iounit_version = 0x03000000,
1367 .max_mem = 0xf00000000ULL,
1368 .default_cpu_model = "TI SuperSparc II",
1369 },
1370 /* SS-2000 */
1371 {
1372 .iounit_bases = {
1373 0xfe0200000ULL,
1374 0xfe1200000ULL,
1375 0xfe2200000ULL,
1376 0xfe3200000ULL,
1377 0xfe4200000ULL,
1378 },
1379 .tcx_base = 0x820000000ULL,
1380 .slavio_base = 0xf00000000ULL,
1381 .ms_kb_base = 0xf00240000ULL,
1382 .serial_base = 0xf00200000ULL,
1383 .nvram_base = 0xf00280000ULL,
1384 .counter_base = 0xf00300000ULL,
1385 .espdma_base = 0x800081000ULL,
1386 .esp_base = 0x800080000ULL,
1387 .ledma_base = 0x800040000ULL,
1388 .le_base = 0x800060000ULL,
1389 .sbi_base = 0xf02800000ULL,
1390 .nvram_machine_id = 0x80,
1391 .machine_id = ss2000_id,
1392 .iounit_version = 0x03000000,
1393 .max_mem = 0xf00000000ULL,
1394 .default_cpu_model = "TI SuperSparc II",
1395 },
1396 };
1397
1398 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1399 {
1400 DeviceState *dev;
1401 SysBusDevice *s;
1402 unsigned int i;
1403
1404 dev = qdev_create(NULL, "sbi");
1405 qdev_init_nofail(dev);
1406
1407 s = sysbus_from_qdev(dev);
1408
1409 for (i = 0; i < MAX_CPUS; i++) {
1410 sysbus_connect_irq(s, i, *parent_irq[i]);
1411 }
1412
1413 sysbus_mmio_map(s, 0, addr);
1414
1415 return dev;
1416 }
1417
1418 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1419 const char *boot_device,
1420 const char *kernel_filename,
1421 const char *kernel_cmdline,
1422 const char *initrd_filename, const char *cpu_model)
1423 {
1424 unsigned int i;
1425 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1426 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1427 espdma_irq, ledma_irq;
1428 qemu_irq esp_reset;
1429 unsigned long kernel_size;
1430 void *fw_cfg;
1431 DeviceState *dev;
1432
1433 /* init CPUs */
1434 if (!cpu_model)
1435 cpu_model = hwdef->default_cpu_model;
1436
1437 for(i = 0; i < smp_cpus; i++) {
1438 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1439 }
1440
1441 for (i = smp_cpus; i < MAX_CPUS; i++)
1442 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1443
1444 /* set up devices */
1445 ram_init(0, RAM_size, hwdef->max_mem);
1446
1447 prom_init(hwdef->slavio_base, bios_name);
1448
1449 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1450
1451 for (i = 0; i < 32; i++) {
1452 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1453 }
1454 for (i = 0; i < MAX_CPUS; i++) {
1455 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1456 }
1457
1458 for (i = 0; i < MAX_IOUNITS; i++)
1459 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1460 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1461 hwdef->iounit_version,
1462 sbi_irq[0]);
1463
1464 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1465 iounits[0], &espdma_irq);
1466
1467 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1468 iounits[0], &ledma_irq);
1469
1470 if (graphic_depth != 8 && graphic_depth != 24) {
1471 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1472 exit (1);
1473 }
1474 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1475 graphic_depth);
1476
1477 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1478
1479 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1480
1481 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1482
1483 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1484 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1485 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1486 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1487 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1488 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1489
1490 if (drive_get_max_bus(IF_SCSI) > 0) {
1491 fprintf(stderr, "qemu: too many SCSI bus\n");
1492 exit(1);
1493 }
1494
1495 esp_reset = qdev_get_gpio_in(espdma, 0);
1496 esp_init(hwdef->esp_base, 2,
1497 espdma_memory_read, espdma_memory_write,
1498 espdma, espdma_irq, &esp_reset);
1499
1500 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1501 RAM_size);
1502
1503 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1504 boot_device, RAM_size, kernel_size, graphic_width,
1505 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1506 "Sun4d");
1507
1508 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1509 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1510 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1511 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1512 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1513 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1514 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1515 if (kernel_cmdline) {
1516 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1517 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1518 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1519 (uint8_t*)strdup(kernel_cmdline),
1520 strlen(kernel_cmdline) + 1);
1521 } else {
1522 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1523 }
1524 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1525 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1526 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1527 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1528 }
1529
1530 /* SPARCserver 1000 hardware initialisation */
1531 static void ss1000_init(ram_addr_t RAM_size,
1532 const char *boot_device,
1533 const char *kernel_filename, const char *kernel_cmdline,
1534 const char *initrd_filename, const char *cpu_model)
1535 {
1536 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1537 kernel_cmdline, initrd_filename, cpu_model);
1538 }
1539
1540 /* SPARCcenter 2000 hardware initialisation */
1541 static void ss2000_init(ram_addr_t RAM_size,
1542 const char *boot_device,
1543 const char *kernel_filename, const char *kernel_cmdline,
1544 const char *initrd_filename, const char *cpu_model)
1545 {
1546 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1547 kernel_cmdline, initrd_filename, cpu_model);
1548 }
1549
1550 static QEMUMachine ss1000_machine = {
1551 .name = "SS-1000",
1552 .desc = "Sun4d platform, SPARCserver 1000",
1553 .init = ss1000_init,
1554 .use_scsi = 1,
1555 .max_cpus = 8,
1556 };
1557
1558 static QEMUMachine ss2000_machine = {
1559 .name = "SS-2000",
1560 .desc = "Sun4d platform, SPARCcenter 2000",
1561 .init = ss2000_init,
1562 .use_scsi = 1,
1563 .max_cpus = 20,
1564 };
1565
1566 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1567 /* SS-2 */
1568 {
1569 .iommu_base = 0xf8000000,
1570 .tcx_base = 0xfe000000,
1571 .slavio_base = 0xf6000000,
1572 .intctl_base = 0xf5000000,
1573 .counter_base = 0xf3000000,
1574 .ms_kb_base = 0xf0000000,
1575 .serial_base = 0xf1000000,
1576 .nvram_base = 0xf2000000,
1577 .fd_base = 0xf7200000,
1578 .dma_base = 0xf8400000,
1579 .esp_base = 0xf8800000,
1580 .le_base = 0xf8c00000,
1581 .aux1_base = 0xf7400003,
1582 .nvram_machine_id = 0x55,
1583 .machine_id = ss2_id,
1584 .max_mem = 0x10000000,
1585 .default_cpu_model = "Cypress CY7C601",
1586 },
1587 };
1588
1589 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1590 qemu_irq *parent_irq)
1591 {
1592 DeviceState *dev;
1593 SysBusDevice *s;
1594 unsigned int i;
1595
1596 dev = qdev_create(NULL, "sun4c_intctl");
1597 qdev_init_nofail(dev);
1598
1599 s = sysbus_from_qdev(dev);
1600
1601 for (i = 0; i < MAX_PILS; i++) {
1602 sysbus_connect_irq(s, i, parent_irq[i]);
1603 }
1604 sysbus_mmio_map(s, 0, addr);
1605
1606 return dev;
1607 }
1608
1609 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1610 const char *boot_device,
1611 const char *kernel_filename,
1612 const char *kernel_cmdline,
1613 const char *initrd_filename, const char *cpu_model)
1614 {
1615 void *iommu, *espdma, *ledma, *nvram;
1616 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1617 qemu_irq esp_reset;
1618 qemu_irq fdc_tc;
1619 unsigned long kernel_size;
1620 DriveInfo *fd[MAX_FD];
1621 void *fw_cfg;
1622 DeviceState *dev;
1623 unsigned int i;
1624
1625 /* init CPU */
1626 if (!cpu_model)
1627 cpu_model = hwdef->default_cpu_model;
1628
1629 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1630
1631 /* set up devices */
1632 ram_init(0, RAM_size, hwdef->max_mem);
1633
1634 prom_init(hwdef->slavio_base, bios_name);
1635
1636 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1637
1638 for (i = 0; i < 8; i++) {
1639 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1640 }
1641
1642 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1643 slavio_irq[1]);
1644
1645 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1646 iommu, &espdma_irq);
1647
1648 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1649 slavio_irq[3], iommu, &ledma_irq);
1650
1651 if (graphic_depth != 8 && graphic_depth != 24) {
1652 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1653 exit (1);
1654 }
1655 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1656 graphic_depth);
1657
1658 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1659
1660 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1661
1662 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1663 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1664 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1665 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1666 escc_init(hwdef->serial_base, slavio_irq[1],
1667 slavio_irq[1], serial_hds[0], serial_hds[1],
1668 ESCC_CLOCK, 1);
1669
1670 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1671
1672 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1673 /* there is zero or one floppy drive */
1674 memset(fd, 0, sizeof(fd));
1675 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1676 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1677 &fdc_tc);
1678 }
1679
1680 if (drive_get_max_bus(IF_SCSI) > 0) {
1681 fprintf(stderr, "qemu: too many SCSI bus\n");
1682 exit(1);
1683 }
1684
1685 esp_reset = qdev_get_gpio_in(espdma, 0);
1686 esp_init(hwdef->esp_base, 2,
1687 espdma_memory_read, espdma_memory_write,
1688 espdma, espdma_irq, &esp_reset);
1689
1690 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1691 RAM_size);
1692
1693 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1694 boot_device, RAM_size, kernel_size, graphic_width,
1695 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1696 "Sun4c");
1697
1698 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1699 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1700 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1701 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1702 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1703 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1704 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1705 if (kernel_cmdline) {
1706 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1707 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1708 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1709 (uint8_t*)strdup(kernel_cmdline),
1710 strlen(kernel_cmdline) + 1);
1711 } else {
1712 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1713 }
1714 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1715 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1716 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1717 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1718 }
1719
1720 /* SPARCstation 2 hardware initialisation */
1721 static void ss2_init(ram_addr_t RAM_size,
1722 const char *boot_device,
1723 const char *kernel_filename, const char *kernel_cmdline,
1724 const char *initrd_filename, const char *cpu_model)
1725 {
1726 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1727 kernel_cmdline, initrd_filename, cpu_model);
1728 }
1729
1730 static QEMUMachine ss2_machine = {
1731 .name = "SS-2",
1732 .desc = "Sun4c platform, SPARCstation 2",
1733 .init = ss2_init,
1734 .use_scsi = 1,
1735 };
1736
1737 static void ss2_machine_init(void)
1738 {
1739 qemu_register_machine(&ss5_machine);
1740 qemu_register_machine(&ss10_machine);
1741 qemu_register_machine(&ss600mp_machine);
1742 qemu_register_machine(&ss20_machine);
1743 qemu_register_machine(&voyager_machine);
1744 qemu_register_machine(&ss_lx_machine);
1745 qemu_register_machine(&ss4_machine);
1746 qemu_register_machine(&scls_machine);
1747 qemu_register_machine(&sbook_machine);
1748 qemu_register_machine(&ss1000_machine);
1749 qemu_register_machine(&ss2000_machine);
1750 qemu_register_machine(&ss2_machine);
1751 }
1752
1753 machine_init(ss2_machine_init);
QEmu