virtio-9p: Add P9_TWRITE support
[qemu.git] / hw / ppc_mac.h
blob89f96bbc347b32491d4d64ad8a26d3bf03638724
1 /*
2 * QEMU PowerMac emulation shared definitions and prototypes
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
25 #if !defined(__PPC_MAC_H__)
26 #define __PPC_MAC_H__
28 /* SMP is not enabled, for now */
29 #define MAX_CPUS 1
31 #define BIOS_SIZE (1024 * 1024)
32 #define BIOS_FILENAME "ppc_rom.bin"
33 #define VGABIOS_FILENAME "video.x"
34 #define NVRAM_SIZE 0x2000
35 #define PROM_FILENAME "openbios-ppc"
36 #define PROM_ADDR 0xfff00000
38 #define KERNEL_LOAD_ADDR 0x01000000
39 #define CMDLINE_ADDR 0x027ff000
40 #define INITRD_LOAD_ADDR 0x02800000
42 #define ESCC_CLOCK 3686400
44 /* Cuda */
45 void cuda_init (int *cuda_mem_index, qemu_irq irq);
47 /* MacIO */
48 void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
49 int dbdma_mem_index, int cuda_mem_index, void *nvram,
50 int nb_ide, int *ide_mem_index, int escc_mem_index);
52 /* Heathrow PIC */
53 qemu_irq *heathrow_pic_init(int *pmem_index,
54 int nb_cpus, qemu_irq **irqs);
56 /* Grackle PCI */
57 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
59 /* UniNorth PCI */
60 PCIBus *pci_pmac_init(qemu_irq *pic);
61 PCIBus *pci_pmac_u3_init(qemu_irq *pic);
63 /* Mac NVRAM */
64 typedef struct MacIONVRAMState MacIONVRAMState;
66 MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
67 unsigned int it_shift);
68 void macio_nvram_map (void *opaque, target_phys_addr_t mem_base);
69 void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
70 uint32_t macio_nvram_read (void *opaque, uint32_t addr);
71 void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
73 /* adb.c */
75 #define MAX_ADB_DEVICES 16
77 #define ADB_MAX_OUT_LEN 16
79 typedef struct ADBDevice ADBDevice;
81 /* buf = NULL means polling */
82 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
83 const uint8_t *buf, int len);
84 typedef int ADBDeviceReset(ADBDevice *d);
86 struct ADBDevice {
87 struct ADBBusState *bus;
88 int devaddr;
89 int handler;
90 ADBDeviceRequest *devreq;
91 ADBDeviceReset *devreset;
92 void *opaque;
95 typedef struct ADBBusState {
96 ADBDevice devices[MAX_ADB_DEVICES];
97 int nb_devices;
98 int poll_index;
99 } ADBBusState;
101 int adb_request(ADBBusState *s, uint8_t *buf_out,
102 const uint8_t *buf, int len);
103 int adb_poll(ADBBusState *s, uint8_t *buf_out);
105 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
106 ADBDeviceRequest *devreq,
107 ADBDeviceReset *devreset,
108 void *opaque);
109 void adb_kbd_init(ADBBusState *bus);
110 void adb_mouse_init(ADBBusState *bus);
112 extern ADBBusState adb_bus;
114 #endif /* !defined(__PPC_MAC_H__) */