hw/mips_int.c

   1 /*
   2  * QEMU MIPS interrupt support
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include "hw.h"
  24 #include "mips_cpudevs.h"
  25 #include "cpu.h"
  26
  27 /* Raise IRQ to CPU if necessary. It must be called every time the active
  28    IRQ may change */
  29 void cpu_mips_update_irq(CPUState *env)
  30 {
  31     if ((env->CP0_Status & (1 << CP0St_IE)) &&
  32         !(env->CP0_Status & (1 << CP0St_EXL)) &&
  33         !(env->CP0_Status & (1 << CP0St_ERL)) &&
  34         !(env->hflags & MIPS_HFLAG_DM)) {
  35         if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
  36             !(env->interrupt_request & CPU_INTERRUPT_HARD)) {
  37             cpu_interrupt(env, CPU_INTERRUPT_HARD);
  38         }
  39     } else
  40         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  41 }
  42
  43 static void cpu_mips_irq_request(void *opaque, int irq, int level)
  44 {
  45     CPUState *env = (CPUState *)opaque;
  46
  47     if (irq < 0 || irq > 7)
  48         return;
  49
  50     if (level) {
  51         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
  52     } else {
  53         env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
  54     }
  55     cpu_mips_update_irq(env);
  56 }
  57
  58 void cpu_mips_irq_init_cpu(CPUState *env)
  59 {
  60     qemu_irq *qi;
  61     int i;
  62
  63     qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
  64     for (i = 0; i < 8; i++) {
  65         env->irq[i] = qi[i];
  66     }
  67 }