s390x/ccw: make sure all ccw devices are properly reset
[qemu.git] / target / riscv / gdbstub.c
blob4f919b6c3413dcda62b018e6d3863a9aed273828
1 /*
2 * RISC-V GDB Server Stub
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu-common.h"
21 #include "exec/gdbstub.h"
22 #include "cpu.h"
24 int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
26 RISCVCPU *cpu = RISCV_CPU(cs);
27 CPURISCVState *env = &cpu->env;
29 if (n < 32) {
30 return gdb_get_regl(mem_buf, env->gpr[n]);
31 } else if (n == 32) {
32 return gdb_get_regl(mem_buf, env->pc);
33 } else if (n < 65) {
34 return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
35 } else if (n < 4096 + 65) {
36 return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65));
38 return 0;
41 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
43 RISCVCPU *cpu = RISCV_CPU(cs);
44 CPURISCVState *env = &cpu->env;
46 if (n == 0) {
47 /* discard writes to x0 */
48 return sizeof(target_ulong);
49 } else if (n < 32) {
50 env->gpr[n] = ldtul_p(mem_buf);
51 return sizeof(target_ulong);
52 } else if (n == 32) {
53 env->pc = ldtul_p(mem_buf);
54 return sizeof(target_ulong);
55 } else if (n < 65) {
56 env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
57 return sizeof(uint64_t);
58 } else if (n < 4096 + 65) {
59 csr_write_helper(env, ldtul_p(mem_buf), n - 65);
61 return 0;