target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "exec/exec-all.h"
  25
  26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  27 {
  28     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  29
  30     cpu->env.pc = value;
  31 }
  32
  33 static bool openrisc_cpu_has_work(CPUState *cs)
  34 {
  35     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  36                                     CPU_INTERRUPT_TIMER);
  37 }
  38
  39 /* CPUClass::reset() */
  40 static void openrisc_cpu_reset(CPUState *s)
  41 {
  42     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  43     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  44
  45     occ->parent_reset(s);
  46
  47     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  48
  49     cpu->env.pc = 0x100;
  50     cpu->env.sr = SR_FO | SR_SM;
  51     cpu->env.lock_addr = -1;
  52     s->exception_index = -1;
  53
  54     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
  55                    UPR_PMP;
  56     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  57     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  58
  59 #ifndef CONFIG_USER_ONLY
  60     cpu->env.picmr = 0x00000000;
  61     cpu->env.picsr = 0x00000000;
  62
  63     cpu->env.ttmr = 0x00000000;
  64 #endif
  65 }
  66
  67 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  68 {
  69     CPUState *cs = CPU(dev);
  70     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  71     Error *local_err = NULL;
  72
  73     cpu_exec_realizefn(cs, &local_err);
  74     if (local_err != NULL) {
  75         error_propagate(errp, local_err);
  76         return;
  77     }
  78
  79     qemu_init_vcpu(cs);
  80     cpu_reset(cs);
  81
  82     occ->parent_realize(dev, errp);
  83 }
  84
  85 static void openrisc_cpu_initfn(Object *obj)
  86 {
  87     CPUState *cs = CPU(obj);
  88     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  89
  90     cs->env_ptr = &cpu->env;
  91
  92 #ifndef CONFIG_USER_ONLY
  93     cpu_openrisc_mmu_init(cpu);
  94 #endif
  95 }
  96
  97 /* CPU models */
  98
  99 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 100 {
 101     ObjectClass *oc;
 102     char *typename;
 103
 104     typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
 105     oc = object_class_by_name(typename);
 106     g_free(typename);
 107     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 108                        object_class_is_abstract(oc))) {
 109         return NULL;
 110     }
 111     return oc;
 112 }
 113
 114 static void or1200_initfn(Object *obj)
 115 {
 116     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 117
 118     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 119                        CPUCFGR_EVBARP;
 120 }
 121
 122 static void openrisc_any_initfn(Object *obj)
 123 {
 124     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 125
 126     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
 127 }
 128
 129 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 130 {
 131     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 132     CPUClass *cc = CPU_CLASS(occ);
 133     DeviceClass *dc = DEVICE_CLASS(oc);
 134
 135     device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
 136                                     &occ->parent_realize);
 137     occ->parent_reset = cc->reset;
 138     cc->reset = openrisc_cpu_reset;
 139
 140     cc->class_by_name = openrisc_cpu_class_by_name;
 141     cc->has_work = openrisc_cpu_has_work;
 142     cc->do_interrupt = openrisc_cpu_do_interrupt;
 143     cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
 144     cc->dump_state = openrisc_cpu_dump_state;
 145     cc->set_pc = openrisc_cpu_set_pc;
 146     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 147     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 148 #ifdef CONFIG_USER_ONLY
 149     cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
 150 #else
 151     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
 152     dc->vmsd = &vmstate_openrisc_cpu;
 153 #endif
 154     cc->gdb_num_core_regs = 32 + 3;
 155     cc->tcg_initialize = openrisc_translate_init;
 156 }
 157
 158 /* Sort alphabetically by type name, except for "any". */
 159 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 160 {
 161     ObjectClass *class_a = (ObjectClass *)a;
 162     ObjectClass *class_b = (ObjectClass *)b;
 163     const char *name_a, *name_b;
 164
 165     name_a = object_class_get_name(class_a);
 166     name_b = object_class_get_name(class_b);
 167     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 168         return 1;
 169     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 170         return -1;
 171     } else {
 172         return strcmp(name_a, name_b);
 173     }
 174 }
 175
 176 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 177 {
 178     ObjectClass *oc = data;
 179     CPUListState *s = user_data;
 180     const char *typename;
 181     char *name;
 182
 183     typename = object_class_get_name(oc);
 184     name = g_strndup(typename,
 185                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 186     (*s->cpu_fprintf)(s->file, "  %s\n",
 187                       name);
 188     g_free(name);
 189 }
 190
 191 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 192 {
 193     CPUListState s = {
 194         .file = f,
 195         .cpu_fprintf = cpu_fprintf,
 196     };
 197     GSList *list;
 198
 199     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 200     list = g_slist_sort(list, openrisc_cpu_list_compare);
 201     (*cpu_fprintf)(f, "Available CPUs:\n");
 202     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 203     g_slist_free(list);
 204 }
 205
 206 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
 207     {                                               \
 208         .parent = TYPE_OPENRISC_CPU,                \
 209         .instance_init = initfn,                    \
 210         .name = OPENRISC_CPU_TYPE_NAME(cpu_model),  \
 211     }
 212
 213 static const TypeInfo openrisc_cpus_type_infos[] = {
 214     { /* base class should be registered first */
 215         .name = TYPE_OPENRISC_CPU,
 216         .parent = TYPE_CPU,
 217         .instance_size = sizeof(OpenRISCCPU),
 218         .instance_init = openrisc_cpu_initfn,
 219         .abstract = true,
 220         .class_size = sizeof(OpenRISCCPUClass),
 221         .class_init = openrisc_cpu_class_init,
 222     },
 223     DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
 224     DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
 225 };
 226
 227 DEFINE_TYPES(openrisc_cpus_type_infos)