hw/pcie_aer.c

   1 /*
   2  * pcie_aer.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "sysemu.h"
  22 #include "pci_bridge.h"
  23 #include "pcie.h"
  24 #include "msix.h"
  25 #include "msi.h"
  26 #include "pci_internals.h"
  27 #include "pcie_regs.h"
  28
  29 //#define DEBUG_PCIE
  30 #ifdef DEBUG_PCIE
  31 # define PCIE_DPRINTF(fmt, ...)                                         \
  32     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  33 #else
  34 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  35 #endif
  36 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  37     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  38
  39 /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
  40 static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
  41 {
  42     switch (status) {
  43     case PCI_ERR_UNC_INTN:
  44     case PCI_ERR_UNC_DLP:
  45     case PCI_ERR_UNC_SDN:
  46     case PCI_ERR_UNC_RX_OVER:
  47     case PCI_ERR_UNC_FCP:
  48     case PCI_ERR_UNC_MALF_TLP:
  49         return PCI_ERR_ROOT_CMD_FATAL_EN;
  50     case PCI_ERR_UNC_POISON_TLP:
  51     case PCI_ERR_UNC_ECRC:
  52     case PCI_ERR_UNC_UNSUP:
  53     case PCI_ERR_UNC_COMP_TIME:
  54     case PCI_ERR_UNC_COMP_ABORT:
  55     case PCI_ERR_UNC_UNX_COMP:
  56     case PCI_ERR_UNC_ACSV:
  57     case PCI_ERR_UNC_MCBTLP:
  58     case PCI_ERR_UNC_ATOP_EBLOCKED:
  59     case PCI_ERR_UNC_TLP_PRF_BLOCKED:
  60         return PCI_ERR_ROOT_CMD_NONFATAL_EN;
  61     default:
  62         abort();
  63         break;
  64     }
  65     return PCI_ERR_ROOT_CMD_FATAL_EN;
  66 }
  67
  68 static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err)
  69 {
  70     if (aer_log->log_num == aer_log->log_max) {
  71         return -1;
  72     }
  73     memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err);
  74     aer_log->log_num++;
  75     return 0;
  76 }
  77
  78 static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err)
  79 {
  80     assert(aer_log->log_num);
  81     *err = aer_log->log[0];
  82     aer_log->log_num--;
  83     memmove(&aer_log->log[0], &aer_log->log[1],
  84             aer_log->log_num * sizeof *err);
  85 }
  86
  87 static void aer_log_clear_all_err(PCIEAERLog *aer_log)
  88 {
  89     aer_log->log_num = 0;
  90 }
  91
  92 int pcie_aer_init(PCIDevice *dev, uint16_t offset)
  93 {
  94     PCIExpressDevice *exp;
  95
  96     pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
  97                         offset, PCI_ERR_SIZEOF);
  98     exp = &dev->exp;
  99     exp->aer_cap = offset;
 100
 101     /* log_max is property */
 102     if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
 103         dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT;
 104     }
 105     /* clip down the value to avoid unreasobale memory usage */
 106     if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
 107         return -EINVAL;
 108     }
 109     dev->exp.aer_log.log = qemu_mallocz(sizeof dev->exp.aer_log.log[0] *
 110                                         dev->exp.aer_log.log_max);
 111
 112     pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
 113                  PCI_ERR_UNC_SUPPORTED);
 114
 115     pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
 116                  PCI_ERR_UNC_SEVERITY_DEFAULT);
 117     pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER,
 118                  PCI_ERR_UNC_SUPPORTED);
 119
 120     pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS,
 121                                PCI_ERR_COR_STATUS);
 122
 123     pci_set_long(dev->config + offset + PCI_ERR_COR_MASK,
 124                  PCI_ERR_COR_MASK_DEFAULT);
 125     pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK,
 126                  PCI_ERR_COR_SUPPORTED);
 127
 128     /* capabilities and control. multiple header logging is supported */
 129     if (dev->exp.aer_log.log_max > 0) {
 130         pci_set_long(dev->config + offset + PCI_ERR_CAP,
 131                      PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC |
 132                      PCI_ERR_CAP_MHRC);
 133         pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
 134                      PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE |
 135                      PCI_ERR_CAP_MHRE);
 136     } else {
 137         pci_set_long(dev->config + offset + PCI_ERR_CAP,
 138                      PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC);
 139         pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
 140                      PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
 141     }
 142
 143     switch (pcie_cap_get_type(dev)) {
 144     case PCI_EXP_TYPE_ROOT_PORT:
 145         /* this case will be set by pcie_aer_root_init() */
 146         /* fallthrough */
 147     case PCI_EXP_TYPE_DOWNSTREAM:
 148     case PCI_EXP_TYPE_UPSTREAM:
 149         pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL,
 150                                    PCI_BRIDGE_CTL_SERR);
 151         pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS,
 152                                    PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
 153         break;
 154     default:
 155         /* nothing */
 156         break;
 157     }
 158     return 0;
 159 }
 160
 161 void pcie_aer_exit(PCIDevice *dev)
 162 {
 163     qemu_free(dev->exp.aer_log.log);
 164 }
 165
 166 static void pcie_aer_update_uncor_status(PCIDevice *dev)
 167 {
 168     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 169     PCIEAERLog *aer_log = &dev->exp.aer_log;
 170
 171     uint16_t i;
 172     for (i = 0; i < aer_log->log_num; i++) {
 173         pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS,
 174                                    dev->exp.aer_log.log[i].status);
 175     }
 176 }
 177
 178 /*
 179  * return value:
 180  * true: error message needs to be sent up
 181  * false: error message is masked
 182  *
 183  * 6.2.6 Error Message Control
 184  * Figure 6-3
 185  * all pci express devices part
 186  */
 187 static bool
 188 pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
 189 {
 190     if (!(pcie_aer_msg_is_uncor(msg) &&
 191           (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
 192         return false;
 193     }
 194
 195     /* Signaled System Error
 196      *
 197      * 7.5.1.1 Command register
 198      * Bit 8 SERR# Enable
 199      *
 200      * When Set, this bit enables reporting of Non-fatal and Fatal
 201      * errors detected by the Function to the Root Complex. Note that
 202      * errors are reported if enabled either through this bit or through
 203      * the PCI Express specific bits in the Device Control register (see
 204      * Section 7.8.4).
 205      */
 206     pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 207                                PCI_STATUS_SIG_SYSTEM_ERROR);
 208
 209     if (!(msg->severity &
 210           pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) {
 211         return false;
 212     }
 213
 214     /* send up error message */
 215     return true;
 216 }
 217
 218 /*
 219  * return value:
 220  * true: error message is sent up
 221  * false: error message is masked
 222  *
 223  * 6.2.6 Error Message Control
 224  * Figure 6-3
 225  * virtual pci bridge part
 226  */
 227 static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg)
 228 {
 229     uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL);
 230
 231     if (pcie_aer_msg_is_uncor(msg)) {
 232         /* Received System Error */
 233         pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS,
 234                                    PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
 235     }
 236
 237     if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) {
 238         return false;
 239     }
 240     return true;
 241 }
 242
 243 void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector)
 244 {
 245     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 246     assert(vector < PCI_ERR_ROOT_IRQ_MAX);
 247     pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS,
 248                                  PCI_ERR_ROOT_IRQ);
 249     pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS,
 250                                vector << PCI_ERR_ROOT_IRQ_SHIFT);
 251 }
 252
 253 static unsigned int pcie_aer_root_get_vector(PCIDevice *dev)
 254 {
 255     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 256     uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
 257     return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT;
 258 }
 259
 260 /* Given a status register, get corresponding bits in the command register */
 261 static uint32_t pcie_aer_status_to_cmd(uint32_t status)
 262 {
 263     uint32_t cmd = 0;
 264     if (status & PCI_ERR_ROOT_COR_RCV) {
 265         cmd |= PCI_ERR_ROOT_CMD_COR_EN;
 266     }
 267     if (status & PCI_ERR_ROOT_NONFATAL_RCV) {
 268         cmd |= PCI_ERR_ROOT_CMD_NONFATAL_EN;
 269     }
 270     if (status & PCI_ERR_ROOT_FATAL_RCV) {
 271         cmd |= PCI_ERR_ROOT_CMD_FATAL_EN;
 272     }
 273     return cmd;
 274 }
 275
 276 static void pcie_aer_root_notify(PCIDevice *dev)
 277 {
 278     if (msix_enabled(dev)) {
 279         msix_notify(dev, pcie_aer_root_get_vector(dev));
 280     } else if (msi_enabled(dev)) {
 281         msi_notify(dev, pcie_aer_root_get_vector(dev));
 282     } else {
 283         qemu_set_irq(dev->irq[dev->exp.aer_intx], 1);
 284     }
 285 }
 286
 287 /*
 288  * 6.2.6 Error Message Control
 289  * Figure 6-3
 290  * root port part
 291  */
 292 static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
 293 {
 294     uint16_t cmd;
 295     uint8_t *aer_cap;
 296     uint32_t root_cmd;
 297     uint32_t root_status, prev_status;
 298
 299     cmd = pci_get_word(dev->config + PCI_COMMAND);
 300     aer_cap = dev->config + dev->exp.aer_cap;
 301     root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
 302     prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
 303
 304     if (cmd & PCI_COMMAND_SERR) {
 305         /* System Error.
 306          *
 307          * The way to report System Error is platform specific and
 308          * it isn't implemented in qemu right now.
 309          * So just discard the error for now.
 310          * OS which cares of aer would receive errors via
 311          * native aer mechanims, so this wouldn't matter.
 312          */
 313     }
 314
 315     /* Errro Message Received: Root Error Status register */
 316     switch (msg->severity) {
 317     case PCI_ERR_ROOT_CMD_COR_EN:
 318         if (root_status & PCI_ERR_ROOT_COR_RCV) {
 319             root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
 320         } else {
 321             pci_set_word(aer_cap + PCI_ERR_ROOT_COR_SRC, msg->source_id);
 322         }
 323         root_status |= PCI_ERR_ROOT_COR_RCV;
 324         break;
 325     case PCI_ERR_ROOT_CMD_NONFATAL_EN:
 326         root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
 327         break;
 328     case PCI_ERR_ROOT_CMD_FATAL_EN:
 329         if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) {
 330             root_status |= PCI_ERR_ROOT_FIRST_FATAL;
 331         }
 332         root_status |= PCI_ERR_ROOT_FATAL_RCV;
 333         break;
 334     default:
 335         abort();
 336         break;
 337     }
 338     if (pcie_aer_msg_is_uncor(msg)) {
 339         if (root_status & PCI_ERR_ROOT_UNCOR_RCV) {
 340             root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
 341         } else {
 342             pci_set_word(aer_cap + PCI_ERR_ROOT_SRC, msg->source_id);
 343         }
 344         root_status |= PCI_ERR_ROOT_UNCOR_RCV;
 345     }
 346     pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status);
 347
 348     /* 6.2.4.1.2 Interrupt Generation */
 349     /* All the above did was set some bits in the status register.
 350      * Specifically these that match message severity.
 351      * The below code relies on this fact. */
 352     if (!(root_cmd & msg->severity) ||
 353         (pcie_aer_status_to_cmd(prev_status) & root_cmd)) {
 354         /* Condition is not being set or was already true so nothing to do. */
 355         return;
 356     }
 357
 358     pcie_aer_root_notify(dev);
 359 }
 360
 361 /*
 362  * 6.2.6 Error Message Control Figure 6-3
 363  *
 364  * Walk up the bus tree from the device, propagate the error message.
 365  */
 366 static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg)
 367 {
 368     uint8_t type;
 369
 370     while (dev) {
 371         if (!pci_is_express(dev)) {
 372             /* just ignore it */
 373             /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR?
 374              * Consider e.g. a PCI bridge above a PCI Express device. */
 375             return;
 376         }
 377
 378         type = pcie_cap_get_type(dev);
 379         if ((type == PCI_EXP_TYPE_ROOT_PORT ||
 380             type == PCI_EXP_TYPE_UPSTREAM ||
 381             type == PCI_EXP_TYPE_DOWNSTREAM) &&
 382             !pcie_aer_msg_vbridge(dev, msg)) {
 383                 return;
 384         }
 385         if (!pcie_aer_msg_alldev(dev, msg)) {
 386             return;
 387         }
 388         if (type == PCI_EXP_TYPE_ROOT_PORT) {
 389             pcie_aer_msg_root_port(dev, msg);
 390             /* Root port can notify system itself,
 391                or send the error message to root complex event collector. */
 392             /*
 393              * if root port is associated with an event collector,
 394              * return the root complex event collector here.
 395              * For now root complex event collector isn't supported.
 396              */
 397             return;
 398         }
 399         dev = pci_bridge_get_device(dev->bus);
 400     }
 401 }
 402
 403 static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err)
 404 {
 405     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 406     uint8_t first_bit = ffs(err->status) - 1;
 407     uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
 408     int i;
 409
 410     assert(err->status);
 411     assert(err->status & (err->status - 1));
 412
 413     errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
 414     errcap |= PCI_ERR_CAP_FEP(first_bit);
 415
 416     if (err->flags & PCIE_AER_ERR_HEADER_VALID) {
 417         for (i = 0; i < ARRAY_SIZE(err->header); ++i) {
 418             /* 7.10.8 Header Log Register */
 419             uint8_t *header_log =
 420                 aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0];
 421             cpu_to_be32wu((uint32_t*)header_log, err->header[i]);
 422         }
 423     } else {
 424         assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT));
 425         memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
 426     }
 427
 428     if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) &&
 429         (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 430          PCI_EXP_DEVCAP2_EETLPP)) {
 431         for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) {
 432             /* 7.10.12 tlp prefix log register */
 433             uint8_t *prefix_log =
 434                 aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0];
 435             cpu_to_be32wu((uint32_t*)prefix_log, err->prefix[i]);
 436         }
 437         errcap |= PCI_ERR_CAP_TLP;
 438     } else {
 439         memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0,
 440                PCI_ERR_TLP_PREFIX_LOG_SIZE);
 441     }
 442     pci_set_long(aer_cap + PCI_ERR_CAP, errcap);
 443 }
 444
 445 static void pcie_aer_clear_log(PCIDevice *dev)
 446 {
 447     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 448
 449     pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP,
 450                                  PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
 451
 452     memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
 453     memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE);
 454 }
 455
 456 static void pcie_aer_clear_error(PCIDevice *dev)
 457 {
 458     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 459     uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
 460     PCIEAERLog *aer_log = &dev->exp.aer_log;
 461     PCIEAERErr err;
 462
 463     if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) {
 464         pcie_aer_clear_log(dev);
 465         return;
 466     }
 467
 468     /*
 469      * If more errors are queued, set corresponding bits in uncorrectable
 470      * error status.
 471      * We emulate uncorrectable error status register as W1CS.
 472      * So set bit in uncorrectable error status here again for multiple
 473      * error recording support.
 474      *
 475      * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability)
 476      */
 477     pcie_aer_update_uncor_status(dev);
 478
 479     aer_log_del_err(aer_log, &err);
 480     pcie_aer_update_log(dev, &err);
 481 }
 482
 483 static int pcie_aer_record_error(PCIDevice *dev,
 484                                  const PCIEAERErr *err)
 485 {
 486     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 487     uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
 488     int fep = PCI_ERR_CAP_FEP(errcap);
 489
 490     assert(err->status);
 491     assert(err->status & (err->status - 1));
 492
 493     if (errcap & PCI_ERR_CAP_MHRE &&
 494         (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) {
 495         /*  Not first error. queue error */
 496         if (aer_log_add_err(&dev->exp.aer_log, err) < 0) {
 497             /* overflow */
 498             return -1;
 499         }
 500         return 0;
 501     }
 502
 503     pcie_aer_update_log(dev, err);
 504     return 0;
 505 }
 506
 507 typedef struct PCIEAERInject {
 508     PCIDevice *dev;
 509     uint8_t *aer_cap;
 510     const PCIEAERErr *err;
 511     uint16_t devctl;
 512     uint16_t devsta;
 513     uint32_t error_status;
 514     bool unsupported_request;
 515     bool log_overflow;
 516     PCIEAERMsg msg;
 517 } PCIEAERInject;
 518
 519 static bool pcie_aer_inject_cor_error(PCIEAERInject *inj,
 520                                       uint32_t uncor_status,
 521                                       bool is_advisory_nonfatal)
 522 {
 523     PCIDevice *dev = inj->dev;
 524
 525     inj->devsta |= PCI_EXP_DEVSTA_CED;
 526     if (inj->unsupported_request) {
 527         inj->devsta |= PCI_EXP_DEVSTA_URD;
 528     }
 529     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
 530
 531     if (inj->aer_cap) {
 532         uint32_t mask;
 533         pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS,
 534                                    inj->error_status);
 535         mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK);
 536         if (mask & inj->error_status) {
 537             return false;
 538         }
 539         if (is_advisory_nonfatal) {
 540             uint32_t uncor_mask =
 541                 pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
 542             if (!(uncor_mask & uncor_status)) {
 543                 inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
 544             }
 545             pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
 546                                        uncor_status);
 547         }
 548     }
 549
 550     if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) {
 551         return false;
 552     }
 553     if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) {
 554         return false;
 555     }
 556
 557     inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN;
 558     return true;
 559 }
 560
 561 static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal)
 562 {
 563     PCIDevice *dev = inj->dev;
 564     uint16_t cmd;
 565
 566     if (is_fatal) {
 567         inj->devsta |= PCI_EXP_DEVSTA_FED;
 568     } else {
 569         inj->devsta |= PCI_EXP_DEVSTA_NFED;
 570     }
 571     if (inj->unsupported_request) {
 572         inj->devsta |= PCI_EXP_DEVSTA_URD;
 573     }
 574     pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
 575
 576     if (inj->aer_cap) {
 577         uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
 578         if (mask & inj->error_status) {
 579             pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
 580                                        inj->error_status);
 581             return false;
 582         }
 583
 584         inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
 585         pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
 586                                    inj->error_status);
 587     }
 588
 589     cmd = pci_get_word(dev->config + PCI_COMMAND);
 590     if (inj->unsupported_request &&
 591         !(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) {
 592         return false;
 593     }
 594     if (is_fatal) {
 595         if (!((cmd & PCI_COMMAND_SERR) ||
 596               (inj->devctl & PCI_EXP_DEVCTL_FERE))) {
 597             return false;
 598         }
 599         inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN;
 600     } else {
 601         if (!((cmd & PCI_COMMAND_SERR) ||
 602               (inj->devctl & PCI_EXP_DEVCTL_NFERE))) {
 603             return false;
 604         }
 605         inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN;
 606     }
 607     return true;
 608 }
 609
 610 /*
 611  * non-Function specific error must be recorded in all functions.
 612  * It is the responsibility of the caller of this function.
 613  * It is also caller's responsiblity to determine which function should
 614  * report the rerror.
 615  *
 616  * 6.2.4 Error Logging
 617  * 6.2.5 Sqeunce of Device Error Signaling and Logging Operations
 618  * table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging
 619  *            Operations
 620  */
 621 int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err)
 622 {
 623     uint8_t *aer_cap = NULL;
 624     uint16_t devctl = 0;
 625     uint16_t devsta = 0;
 626     uint32_t error_status = err->status;
 627     PCIEAERInject inj;
 628
 629     if (!pci_is_express(dev)) {
 630         return -ENOSYS;
 631     }
 632
 633     if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
 634         error_status &= PCI_ERR_COR_SUPPORTED;
 635     } else {
 636         error_status &= PCI_ERR_UNC_SUPPORTED;
 637     }
 638
 639     /* invalid status bit. one and only one bit must be set */
 640     if (!error_status || (error_status & (error_status - 1))) {
 641         return -EINVAL;
 642     }
 643
 644     if (dev->exp.aer_cap) {
 645         uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 646         aer_cap = dev->config + dev->exp.aer_cap;
 647         devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL);
 648         devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA);
 649     }
 650
 651     inj.dev = dev;
 652     inj.aer_cap = aer_cap;
 653     inj.err = err;
 654     inj.devctl = devctl;
 655     inj.devsta = devsta;
 656     inj.error_status = error_status;
 657     inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) &&
 658         err->status == PCI_ERR_UNC_UNSUP;
 659     inj.log_overflow = false;
 660
 661     if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
 662         if (!pcie_aer_inject_cor_error(&inj, 0, false)) {
 663             return 0;
 664         }
 665     } else {
 666         bool is_fatal =
 667             pcie_aer_uncor_default_severity(error_status) ==
 668             PCI_ERR_ROOT_CMD_FATAL_EN;
 669         if (aer_cap) {
 670             is_fatal =
 671                 error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER);
 672         }
 673         if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) {
 674             inj.error_status = PCI_ERR_COR_ADV_NONFATAL;
 675             if (!pcie_aer_inject_cor_error(&inj, error_status, true)) {
 676                 return 0;
 677             }
 678         } else {
 679             if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) {
 680                 return 0;
 681             }
 682         }
 683     }
 684
 685     /* send up error message */
 686     inj.msg.source_id = err->source_id;
 687     pcie_aer_msg(dev, &inj.msg);
 688
 689     if (inj.log_overflow) {
 690         PCIEAERErr header_log_overflow = {
 691             .status = PCI_ERR_COR_HL_OVERFLOW,
 692             .flags = PCIE_AER_ERR_IS_CORRECTABLE,
 693         };
 694         int ret = pcie_aer_inject_error(dev, &header_log_overflow);
 695         assert(!ret);
 696     }
 697     return 0;
 698 }
 699
 700 void pcie_aer_write_config(PCIDevice *dev,
 701                            uint32_t addr, uint32_t val, int len)
 702 {
 703     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 704     uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
 705     uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap);
 706     uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS);
 707
 708     /* uncorrectable error */
 709     if (!(uncorsta & first_error)) {
 710         /* the bit that corresponds to the first error is cleared */
 711         pcie_aer_clear_error(dev);
 712     } else if (errcap & PCI_ERR_CAP_MHRE) {
 713         /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared
 714          * nothing should happen. So we have to revert the modification to
 715          * the register.
 716          */
 717         pcie_aer_update_uncor_status(dev);
 718     } else {
 719         /* capability & control
 720          * PCI_ERR_CAP_MHRE might be cleared, so clear of header log.
 721          */
 722         aer_log_clear_all_err(&dev->exp.aer_log);
 723     }
 724 }
 725
 726 void pcie_aer_root_init(PCIDevice *dev)
 727 {
 728     uint16_t pos = dev->exp.aer_cap;
 729
 730     pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND,
 731                  PCI_ERR_ROOT_CMD_EN_MASK);
 732     pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS,
 733                  PCI_ERR_ROOT_STATUS_REPORT_MASK);
 734 }
 735
 736 void pcie_aer_root_reset(PCIDevice *dev)
 737 {
 738     uint8_t* aer_cap = dev->config + dev->exp.aer_cap;
 739
 740     pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0);
 741
 742     /*
 743      * Advanced Error Interrupt Message Number in Root Error Status Register
 744      * must be updated by chip dependent code because it's chip dependent
 745      * which number is used.
 746      */
 747 }
 748
 749 void pcie_aer_root_write_config(PCIDevice *dev,
 750                                 uint32_t addr, uint32_t val, int len,
 751                                 uint32_t root_cmd_prev)
 752 {
 753     uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
 754     uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
 755     uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status);
 756     uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
 757     /* 6.2.4.1.2 Interrupt Generation */
 758     if (!msix_enabled(dev) && !msi_enabled(dev)) {
 759         qemu_set_irq(dev->irq[dev->exp.aer_intx], !!(root_cmd & enabled_cmd));
 760         return;
 761     }
 762
 763     if ((root_cmd_prev & enabled_cmd) || !(root_cmd & enabled_cmd)) {
 764         /* Send MSI on transition from false to true. */
 765         return;
 766     }
 767
 768     pcie_aer_root_notify(dev);
 769 }
 770
 771 static const VMStateDescription vmstate_pcie_aer_err = {
 772     .name = "PCIE_AER_ERROR",
 773     .version_id = 1,
 774     .minimum_version_id = 1,
 775     .minimum_version_id_old = 1,
 776     .fields     = (VMStateField[]) {
 777         VMSTATE_UINT32(status, PCIEAERErr),
 778         VMSTATE_UINT16(source_id, PCIEAERErr),
 779         VMSTATE_UINT16(flags, PCIEAERErr),
 780         VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4),
 781         VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4),
 782         VMSTATE_END_OF_LIST()
 783     }
 784 };
 785
 786 #define VMSTATE_PCIE_AER_ERRS(_field, _state, _field_num, _vmsd, _type) { \
 787     .name       = (stringify(_field)),                                    \
 788     .version_id = 0,                                                      \
 789     .num_offset = vmstate_offset_value(_state, _field_num, uint16_t),     \
 790     .size       = sizeof(_type),                                          \
 791     .vmsd       = &(_vmsd),                                               \
 792     .flags      = VMS_POINTER | VMS_VARRAY_UINT16 | VMS_STRUCT,           \
 793     .offset     = vmstate_offset_pointer(_state, _field, _type),          \
 794 }
 795
 796 const VMStateDescription vmstate_pcie_aer_log = {
 797     .name = "PCIE_AER_ERROR_LOG",
 798     .version_id = 1,
 799     .minimum_version_id = 1,
 800     .minimum_version_id_old = 1,
 801     .fields     = (VMStateField[]) {
 802         VMSTATE_UINT16(log_num, PCIEAERLog),
 803         VMSTATE_UINT16(log_max, PCIEAERLog),
 804         VMSTATE_PCIE_AER_ERRS(log, PCIEAERLog, log_num,
 805                               vmstate_pcie_aer_err, PCIEAERErr),
 806         VMSTATE_END_OF_LIST()
 807     }
 808 };