hw/arm_sysctl.c

   1 /*
   2  * Status and system control registers for ARM RealView/Versatile boards.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "hw.h"
  11 #include "qemu-timer.h"
  12 #include "sysbus.h"
  13 #include "primecell.h"
  14 #include "sysemu.h"
  15
  16 #define LOCK_VALUE 0xa05f
  17
  18 typedef struct {
  19     SysBusDevice busdev;
  20     uint32_t sys_id;
  21     uint32_t leds;
  22     uint16_t lockval;
  23     uint32_t cfgdata1;
  24     uint32_t cfgdata2;
  25     uint32_t flags;
  26     uint32_t nvflags;
  27     uint32_t resetlevel;
  28     uint32_t proc_id;
  29 } arm_sysctl_state;
  30
  31 static void arm_sysctl_reset(DeviceState *d)
  32 {
  33     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
  34
  35     s->leds = 0;
  36     s->lockval = 0;
  37     s->cfgdata1 = 0;
  38     s->cfgdata2 = 0;
  39     s->flags = 0;
  40     s->resetlevel = 0;
  41 }
  42
  43 static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
  44 {
  45     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
  46
  47     switch (offset) {
  48     case 0x00: /* ID */
  49         return s->sys_id;
  50     case 0x04: /* SW */
  51         /* General purpose hardware switches.
  52            We don't have a useful way of exposing these to the user.  */
  53         return 0;
  54     case 0x08: /* LED */
  55         return s->leds;
  56     case 0x20: /* LOCK */
  57         return s->lockval;
  58     case 0x0c: /* OSC0 */
  59     case 0x10: /* OSC1 */
  60     case 0x14: /* OSC2 */
  61     case 0x18: /* OSC3 */
  62     case 0x1c: /* OSC4 */
  63     case 0x24: /* 100HZ */
  64         /* ??? Implement these.  */
  65         return 0;
  66     case 0x28: /* CFGDATA1 */
  67         return s->cfgdata1;
  68     case 0x2c: /* CFGDATA2 */
  69         return s->cfgdata2;
  70     case 0x30: /* FLAGS */
  71         return s->flags;
  72     case 0x38: /* NVFLAGS */
  73         return s->nvflags;
  74     case 0x40: /* RESETCTL */
  75         return s->resetlevel;
  76     case 0x44: /* PCICTL */
  77         return 1;
  78     case 0x48: /* MCI */
  79         return 0;
  80     case 0x4c: /* FLASH */
  81         return 0;
  82     case 0x50: /* CLCD */
  83         return 0x1000;
  84     case 0x54: /* CLCDSER */
  85         return 0;
  86     case 0x58: /* BOOTCS */
  87         return 0;
  88     case 0x5c: /* 24MHz */
  89         return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec());
  90     case 0x60: /* MISC */
  91         return 0;
  92     case 0x84: /* PROCID0 */
  93         return s->proc_id;
  94     case 0x88: /* PROCID1 */
  95         return 0xff000000;
  96     case 0x64: /* DMAPSR0 */
  97     case 0x68: /* DMAPSR1 */
  98     case 0x6c: /* DMAPSR2 */
  99     case 0x70: /* IOSEL */
 100     case 0x74: /* PLDCTL */
 101     case 0x80: /* BUSID */
 102     case 0x8c: /* OSCRESET0 */
 103     case 0x90: /* OSCRESET1 */
 104     case 0x94: /* OSCRESET2 */
 105     case 0x98: /* OSCRESET3 */
 106     case 0x9c: /* OSCRESET4 */
 107     case 0xc0: /* SYS_TEST_OSC0 */
 108     case 0xc4: /* SYS_TEST_OSC1 */
 109     case 0xc8: /* SYS_TEST_OSC2 */
 110     case 0xcc: /* SYS_TEST_OSC3 */
 111     case 0xd0: /* SYS_TEST_OSC4 */
 112         return 0;
 113     default:
 114         printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
 115         return 0;
 116     }
 117 }
 118
 119 static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
 120                           uint32_t val)
 121 {
 122     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 123
 124     switch (offset) {
 125     case 0x08: /* LED */
 126         s->leds = val;
 127     case 0x0c: /* OSC0 */
 128     case 0x10: /* OSC1 */
 129     case 0x14: /* OSC2 */
 130     case 0x18: /* OSC3 */
 131     case 0x1c: /* OSC4 */
 132         /* ??? */
 133         break;
 134     case 0x20: /* LOCK */
 135         if (val == LOCK_VALUE)
 136             s->lockval = val;
 137         else
 138             s->lockval = val & 0x7fff;
 139         break;
 140     case 0x28: /* CFGDATA1 */
 141         /* ??? Need to implement this.  */
 142         s->cfgdata1 = val;
 143         break;
 144     case 0x2c: /* CFGDATA2 */
 145         /* ??? Need to implement this.  */
 146         s->cfgdata2 = val;
 147         break;
 148     case 0x30: /* FLAGSSET */
 149         s->flags |= val;
 150         break;
 151     case 0x34: /* FLAGSCLR */
 152         s->flags &= ~val;
 153         break;
 154     case 0x38: /* NVFLAGSSET */
 155         s->nvflags |= val;
 156         break;
 157     case 0x3c: /* NVFLAGSCLR */
 158         s->nvflags &= ~val;
 159         break;
 160     case 0x40: /* RESETCTL */
 161         if (s->lockval == LOCK_VALUE) {
 162             s->resetlevel = val;
 163             if (val & 0x100)
 164                 qemu_system_reset_request ();
 165         }
 166         break;
 167     case 0x44: /* PCICTL */
 168         /* nothing to do.  */
 169         break;
 170     case 0x4c: /* FLASH */
 171     case 0x50: /* CLCD */
 172     case 0x54: /* CLCDSER */
 173     case 0x64: /* DMAPSR0 */
 174     case 0x68: /* DMAPSR1 */
 175     case 0x6c: /* DMAPSR2 */
 176     case 0x70: /* IOSEL */
 177     case 0x74: /* PLDCTL */
 178     case 0x80: /* BUSID */
 179     case 0x84: /* PROCID0 */
 180     case 0x88: /* PROCID1 */
 181     case 0x8c: /* OSCRESET0 */
 182     case 0x90: /* OSCRESET1 */
 183     case 0x94: /* OSCRESET2 */
 184     case 0x98: /* OSCRESET3 */
 185     case 0x9c: /* OSCRESET4 */
 186         break;
 187     default:
 188         printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
 189         return;
 190     }
 191 }
 192
 193 static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
 194    arm_sysctl_read,
 195    arm_sysctl_read,
 196    arm_sysctl_read
 197 };
 198
 199 static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
 200    arm_sysctl_write,
 201    arm_sysctl_write,
 202    arm_sysctl_write
 203 };
 204
 205 static int arm_sysctl_init1(SysBusDevice *dev)
 206 {
 207     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
 208     int iomemtype;
 209
 210     iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
 211                                        arm_sysctl_writefn, s,
 212                                        DEVICE_NATIVE_ENDIAN);
 213     sysbus_init_mmio(dev, 0x1000, iomemtype);
 214     /* ??? Save/restore.  */
 215     return 0;
 216 }
 217
 218 /* Legacy helper function.  */
 219 void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
 220 {
 221     DeviceState *dev;
 222
 223     dev = qdev_create(NULL, "realview_sysctl");
 224     qdev_prop_set_uint32(dev, "sys_id", sys_id);
 225     qdev_init_nofail(dev);
 226     qdev_prop_set_uint32(dev, "proc_id", proc_id);
 227     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
 228 }
 229
 230 static SysBusDeviceInfo arm_sysctl_info = {
 231     .init = arm_sysctl_init1,
 232     .qdev.name  = "realview_sysctl",
 233     .qdev.size  = sizeof(arm_sysctl_state),
 234     .qdev.reset = arm_sysctl_reset,
 235     .qdev.props = (Property[]) {
 236         DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 237         DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 238         DEFINE_PROP_END_OF_LIST(),
 239     }
 240 };
 241
 242 static void arm_sysctl_register_devices(void)
 243 {
 244     sysbus_register_withprop(&arm_sysctl_info);
 245 }
 246
 247 device_init(arm_sysctl_register_devices)