hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "i2c.h"
  21
  22 #define MP_MISC_BASE            0x80002000
  23 #define MP_MISC_SIZE            0x00001000
  24
  25 #define MP_ETH_BASE             0x80008000
  26 #define MP_ETH_SIZE             0x00001000
  27
  28 #define MP_WLAN_BASE            0x8000C000
  29 #define MP_WLAN_SIZE            0x00000800
  30
  31 #define MP_UART1_BASE           0x8000C840
  32 #define MP_UART2_BASE           0x8000C940
  33
  34 #define MP_GPIO_BASE            0x8000D000
  35 #define MP_GPIO_SIZE            0x00001000
  36
  37 #define MP_FLASHCFG_BASE        0x90006000
  38 #define MP_FLASHCFG_SIZE        0x00001000
  39
  40 #define MP_AUDIO_BASE           0x90007000
  41
  42 #define MP_PIC_BASE             0x90008000
  43 #define MP_PIC_SIZE             0x00001000
  44
  45 #define MP_PIT_BASE             0x90009000
  46 #define MP_PIT_SIZE             0x00001000
  47
  48 #define MP_LCD_BASE             0x9000c000
  49 #define MP_LCD_SIZE             0x00001000
  50
  51 #define MP_SRAM_BASE            0xC0000000
  52 #define MP_SRAM_SIZE            0x00020000
  53
  54 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  55 #define MP_FLASH_SIZE_MAX       32*1024*1024
  56
  57 #define MP_TIMER1_IRQ           4
  58 #define MP_TIMER2_IRQ           5
  59 #define MP_TIMER3_IRQ           6
  60 #define MP_TIMER4_IRQ           7
  61 #define MP_EHCI_IRQ             8
  62 #define MP_ETH_IRQ              9
  63 #define MP_UART1_IRQ            11
  64 #define MP_UART2_IRQ            11
  65 #define MP_GPIO_IRQ             12
  66 #define MP_RTC_IRQ              28
  67 #define MP_AUDIO_IRQ            30
  68
  69 /* Wolfson 8750 I2C address */
  70 #define MP_WM_ADDR              0x34
  71
  72 /* Ethernet register offsets */
  73 #define MP_ETH_SMIR             0x010
  74 #define MP_ETH_PCXR             0x408
  75 #define MP_ETH_SDCMR            0x448
  76 #define MP_ETH_ICR              0x450
  77 #define MP_ETH_IMR              0x458
  78 #define MP_ETH_FRDP0            0x480
  79 #define MP_ETH_FRDP1            0x484
  80 #define MP_ETH_FRDP2            0x488
  81 #define MP_ETH_FRDP3            0x48C
  82 #define MP_ETH_CRDP0            0x4A0
  83 #define MP_ETH_CRDP1            0x4A4
  84 #define MP_ETH_CRDP2            0x4A8
  85 #define MP_ETH_CRDP3            0x4AC
  86 #define MP_ETH_CTDP0            0x4E0
  87 #define MP_ETH_CTDP1            0x4E4
  88 #define MP_ETH_CTDP2            0x4E8
  89 #define MP_ETH_CTDP3            0x4EC
  90
  91 /* MII PHY access */
  92 #define MP_ETH_SMIR_DATA        0x0000FFFF
  93 #define MP_ETH_SMIR_ADDR        0x03FF0000
  94 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
  95 #define MP_ETH_SMIR_RDVALID     (1 << 27)
  96
  97 /* PHY registers */
  98 #define MP_ETH_PHY1_BMSR        0x00210000
  99 #define MP_ETH_PHY1_PHYSID1     0x00410000
 100 #define MP_ETH_PHY1_PHYSID2     0x00610000
 101
 102 #define MP_PHY_BMSR_LINK        0x0004
 103 #define MP_PHY_BMSR_AUTONEG     0x0008
 104
 105 #define MP_PHY_88E3015          0x01410E20
 106
 107 /* TX descriptor status */
 108 #define MP_ETH_TX_OWN           (1 << 31)
 109
 110 /* RX descriptor status */
 111 #define MP_ETH_RX_OWN           (1 << 31)
 112
 113 /* Interrupt cause/mask bits */
 114 #define MP_ETH_IRQ_RX_BIT       0
 115 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 116 #define MP_ETH_IRQ_TXHI_BIT     2
 117 #define MP_ETH_IRQ_TXLO_BIT     3
 118
 119 /* Port config bits */
 120 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 121
 122 /* SDMA command bits */
 123 #define MP_ETH_CMD_TXHI         (1 << 23)
 124 #define MP_ETH_CMD_TXLO         (1 << 22)
 125
 126 typedef struct mv88w8618_tx_desc {
 127     uint32_t cmdstat;
 128     uint16_t res;
 129     uint16_t bytes;
 130     uint32_t buffer;
 131     uint32_t next;
 132 } mv88w8618_tx_desc;
 133
 134 typedef struct mv88w8618_rx_desc {
 135     uint32_t cmdstat;
 136     uint16_t bytes;
 137     uint16_t buffer_size;
 138     uint32_t buffer;
 139     uint32_t next;
 140 } mv88w8618_rx_desc;
 141
 142 typedef struct mv88w8618_eth_state {
 143     SysBusDevice busdev;
 144     qemu_irq irq;
 145     uint32_t smir;
 146     uint32_t icr;
 147     uint32_t imr;
 148     int mmio_index;
 149     int vlan_header;
 150     uint32_t tx_queue[2];
 151     uint32_t rx_queue[4];
 152     uint32_t frx_queue[4];
 153     uint32_t cur_rx[4];
 154     VLANClientState *vc;
 155 } mv88w8618_eth_state;
 156
 157 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 158 {
 159     cpu_to_le32s(&desc->cmdstat);
 160     cpu_to_le16s(&desc->bytes);
 161     cpu_to_le16s(&desc->buffer_size);
 162     cpu_to_le32s(&desc->buffer);
 163     cpu_to_le32s(&desc->next);
 164     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 165 }
 166
 167 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 168 {
 169     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 170     le32_to_cpus(&desc->cmdstat);
 171     le16_to_cpus(&desc->bytes);
 172     le16_to_cpus(&desc->buffer_size);
 173     le32_to_cpus(&desc->buffer);
 174     le32_to_cpus(&desc->next);
 175 }
 176
 177 static int eth_can_receive(VLANClientState *vc)
 178 {
 179     return 1;
 180 }
 181
 182 static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
 183 {
 184     mv88w8618_eth_state *s = vc->opaque;
 185     uint32_t desc_addr;
 186     mv88w8618_rx_desc desc;
 187     int i;
 188
 189     for (i = 0; i < 4; i++) {
 190         desc_addr = s->cur_rx[i];
 191         if (!desc_addr)
 192             continue;
 193         do {
 194             eth_rx_desc_get(desc_addr, &desc);
 195             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 196                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 197                                           buf, size);
 198                 desc.bytes = size + s->vlan_header;
 199                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 200                 s->cur_rx[i] = desc.next;
 201
 202                 s->icr |= MP_ETH_IRQ_RX;
 203                 if (s->icr & s->imr)
 204                     qemu_irq_raise(s->irq);
 205                 eth_rx_desc_put(desc_addr, &desc);
 206                 return size;
 207             }
 208             desc_addr = desc.next;
 209         } while (desc_addr != s->rx_queue[i]);
 210     }
 211     return size;
 212 }
 213
 214 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 215 {
 216     cpu_to_le32s(&desc->cmdstat);
 217     cpu_to_le16s(&desc->res);
 218     cpu_to_le16s(&desc->bytes);
 219     cpu_to_le32s(&desc->buffer);
 220     cpu_to_le32s(&desc->next);
 221     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 222 }
 223
 224 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 225 {
 226     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 227     le32_to_cpus(&desc->cmdstat);
 228     le16_to_cpus(&desc->res);
 229     le16_to_cpus(&desc->bytes);
 230     le32_to_cpus(&desc->buffer);
 231     le32_to_cpus(&desc->next);
 232 }
 233
 234 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 235 {
 236     uint32_t desc_addr = s->tx_queue[queue_index];
 237     mv88w8618_tx_desc desc;
 238     uint8_t buf[2048];
 239     int len;
 240
 241
 242     do {
 243         eth_tx_desc_get(desc_addr, &desc);
 244         if (desc.cmdstat & MP_ETH_TX_OWN) {
 245             len = desc.bytes;
 246             if (len < 2048) {
 247                 cpu_physical_memory_read(desc.buffer, buf, len);
 248                 qemu_send_packet(s->vc, buf, len);
 249             }
 250             desc.cmdstat &= ~MP_ETH_TX_OWN;
 251             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 252             eth_tx_desc_put(desc_addr, &desc);
 253         }
 254         desc_addr = desc.next;
 255     } while (desc_addr != s->tx_queue[queue_index]);
 256 }
 257
 258 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 259 {
 260     mv88w8618_eth_state *s = opaque;
 261
 262     switch (offset) {
 263     case MP_ETH_SMIR:
 264         if (s->smir & MP_ETH_SMIR_OPCODE) {
 265             switch (s->smir & MP_ETH_SMIR_ADDR) {
 266             case MP_ETH_PHY1_BMSR:
 267                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 268                        MP_ETH_SMIR_RDVALID;
 269             case MP_ETH_PHY1_PHYSID1:
 270                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 271             case MP_ETH_PHY1_PHYSID2:
 272                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 273             default:
 274                 return MP_ETH_SMIR_RDVALID;
 275             }
 276         }
 277         return 0;
 278
 279     case MP_ETH_ICR:
 280         return s->icr;
 281
 282     case MP_ETH_IMR:
 283         return s->imr;
 284
 285     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 286         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 287
 288     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 289         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 290
 291     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 292         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 293
 294     default:
 295         return 0;
 296     }
 297 }
 298
 299 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 300                                 uint32_t value)
 301 {
 302     mv88w8618_eth_state *s = opaque;
 303
 304     switch (offset) {
 305     case MP_ETH_SMIR:
 306         s->smir = value;
 307         break;
 308
 309     case MP_ETH_PCXR:
 310         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 311         break;
 312
 313     case MP_ETH_SDCMR:
 314         if (value & MP_ETH_CMD_TXHI)
 315             eth_send(s, 1);
 316         if (value & MP_ETH_CMD_TXLO)
 317             eth_send(s, 0);
 318         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 319             qemu_irq_raise(s->irq);
 320         break;
 321
 322     case MP_ETH_ICR:
 323         s->icr &= value;
 324         break;
 325
 326     case MP_ETH_IMR:
 327         s->imr = value;
 328         if (s->icr & s->imr)
 329             qemu_irq_raise(s->irq);
 330         break;
 331
 332     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 333         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 334         break;
 335
 336     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 337         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 338             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 339         break;
 340
 341     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 342         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 343         break;
 344     }
 345 }
 346
 347 static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
 348     mv88w8618_eth_read,
 349     mv88w8618_eth_read,
 350     mv88w8618_eth_read
 351 };
 352
 353 static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
 354     mv88w8618_eth_write,
 355     mv88w8618_eth_write,
 356     mv88w8618_eth_write
 357 };
 358
 359 static void eth_cleanup(VLANClientState *vc)
 360 {
 361     mv88w8618_eth_state *s = vc->opaque;
 362
 363     cpu_unregister_io_memory(s->mmio_index);
 364
 365     qemu_free(s);
 366 }
 367
 368 static int mv88w8618_eth_init(SysBusDevice *dev)
 369 {
 370     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 371
 372     sysbus_init_irq(dev, &s->irq);
 373     s->vc = qdev_get_vlan_client(&dev->qdev,
 374                                  eth_can_receive, eth_receive, NULL,
 375                                  eth_cleanup, s);
 376     s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
 377                                            mv88w8618_eth_writefn, s);
 378     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 379     return 0;
 380 }
 381
 382 /* LCD register offsets */
 383 #define MP_LCD_IRQCTRL          0x180
 384 #define MP_LCD_IRQSTAT          0x184
 385 #define MP_LCD_SPICTRL          0x1ac
 386 #define MP_LCD_INST             0x1bc
 387 #define MP_LCD_DATA             0x1c0
 388
 389 /* Mode magics */
 390 #define MP_LCD_SPI_DATA         0x00100011
 391 #define MP_LCD_SPI_CMD          0x00104011
 392 #define MP_LCD_SPI_INVALID      0x00000000
 393
 394 /* Commmands */
 395 #define MP_LCD_INST_SETPAGE0    0xB0
 396 /* ... */
 397 #define MP_LCD_INST_SETPAGE7    0xB7
 398
 399 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 400
 401 typedef struct musicpal_lcd_state {
 402     SysBusDevice busdev;
 403     uint32_t brightness;
 404     uint32_t mode;
 405     uint32_t irqctrl;
 406     int page;
 407     int page_off;
 408     DisplayState *ds;
 409     uint8_t video_ram[128*64/8];
 410 } musicpal_lcd_state;
 411
 412 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 413 {
 414     switch (s->brightness) {
 415     case 7:
 416         return col;
 417     case 0:
 418         return 0;
 419     default:
 420         return (col * s->brightness) / 7;
 421     }
 422 }
 423
 424 #define SET_LCD_PIXEL(depth, type) \
 425 static inline void glue(set_lcd_pixel, depth) \
 426         (musicpal_lcd_state *s, int x, int y, type col) \
 427 { \
 428     int dx, dy; \
 429     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 430 \
 431     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 432         for (dx = 0; dx < 3; dx++, pixel++) \
 433             *pixel = col; \
 434 }
 435 SET_LCD_PIXEL(8, uint8_t)
 436 SET_LCD_PIXEL(16, uint16_t)
 437 SET_LCD_PIXEL(32, uint32_t)
 438
 439 #include "pixel_ops.h"
 440
 441 static void lcd_refresh(void *opaque)
 442 {
 443     musicpal_lcd_state *s = opaque;
 444     int x, y, col;
 445
 446     switch (ds_get_bits_per_pixel(s->ds)) {
 447     case 0:
 448         return;
 449 #define LCD_REFRESH(depth, func) \
 450     case depth: \
 451         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 452                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 453                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 454         for (x = 0; x < 128; x++) \
 455             for (y = 0; y < 64; y++) \
 456                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 457                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 458                 else \
 459                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 460         break;
 461     LCD_REFRESH(8, rgb_to_pixel8)
 462     LCD_REFRESH(16, rgb_to_pixel16)
 463     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 464                      rgb_to_pixel32bgr : rgb_to_pixel32))
 465     default:
 466         hw_error("unsupported colour depth %i\n",
 467                   ds_get_bits_per_pixel(s->ds));
 468     }
 469
 470     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 471 }
 472
 473 static void lcd_invalidate(void *opaque)
 474 {
 475 }
 476
 477 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 478 {
 479     musicpal_lcd_state *s = (musicpal_lcd_state *) opaque;
 480     s->brightness &= ~(1 << irq);
 481     s->brightness |= level << irq;
 482 }
 483
 484 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 485 {
 486     musicpal_lcd_state *s = opaque;
 487
 488     switch (offset) {
 489     case MP_LCD_IRQCTRL:
 490         return s->irqctrl;
 491
 492     default:
 493         return 0;
 494     }
 495 }
 496
 497 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 498                                uint32_t value)
 499 {
 500     musicpal_lcd_state *s = opaque;
 501
 502     switch (offset) {
 503     case MP_LCD_IRQCTRL:
 504         s->irqctrl = value;
 505         break;
 506
 507     case MP_LCD_SPICTRL:
 508         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 509             s->mode = value;
 510         else
 511             s->mode = MP_LCD_SPI_INVALID;
 512         break;
 513
 514     case MP_LCD_INST:
 515         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 516             s->page = value - MP_LCD_INST_SETPAGE0;
 517             s->page_off = 0;
 518         }
 519         break;
 520
 521     case MP_LCD_DATA:
 522         if (s->mode == MP_LCD_SPI_CMD) {
 523             if (value >= MP_LCD_INST_SETPAGE0 &&
 524                 value <= MP_LCD_INST_SETPAGE7) {
 525                 s->page = value - MP_LCD_INST_SETPAGE0;
 526                 s->page_off = 0;
 527             }
 528         } else if (s->mode == MP_LCD_SPI_DATA) {
 529             s->video_ram[s->page*128 + s->page_off] = value;
 530             s->page_off = (s->page_off + 1) & 127;
 531         }
 532         break;
 533     }
 534 }
 535
 536 static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
 537     musicpal_lcd_read,
 538     musicpal_lcd_read,
 539     musicpal_lcd_read
 540 };
 541
 542 static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
 543     musicpal_lcd_write,
 544     musicpal_lcd_write,
 545     musicpal_lcd_write
 546 };
 547
 548 static int musicpal_lcd_init(SysBusDevice *dev)
 549 {
 550     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 551     int iomemtype;
 552
 553     s->brightness = 7;
 554
 555     iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
 556                                        musicpal_lcd_writefn, s);
 557     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 558
 559     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 560                                  NULL, NULL, s);
 561     qemu_console_resize(s->ds, 128*3, 64*3);
 562
 563     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 564
 565     return 0;
 566 }
 567
 568 /* PIC register offsets */
 569 #define MP_PIC_STATUS           0x00
 570 #define MP_PIC_ENABLE_SET       0x08
 571 #define MP_PIC_ENABLE_CLR       0x0C
 572
 573 typedef struct mv88w8618_pic_state
 574 {
 575     SysBusDevice busdev;
 576     uint32_t level;
 577     uint32_t enabled;
 578     qemu_irq parent_irq;
 579 } mv88w8618_pic_state;
 580
 581 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 582 {
 583     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 584 }
 585
 586 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 587 {
 588     mv88w8618_pic_state *s = opaque;
 589
 590     if (level)
 591         s->level |= 1 << irq;
 592     else
 593         s->level &= ~(1 << irq);
 594     mv88w8618_pic_update(s);
 595 }
 596
 597 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 598 {
 599     mv88w8618_pic_state *s = opaque;
 600
 601     switch (offset) {
 602     case MP_PIC_STATUS:
 603         return s->level & s->enabled;
 604
 605     default:
 606         return 0;
 607     }
 608 }
 609
 610 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 611                                 uint32_t value)
 612 {
 613     mv88w8618_pic_state *s = opaque;
 614
 615     switch (offset) {
 616     case MP_PIC_ENABLE_SET:
 617         s->enabled |= value;
 618         break;
 619
 620     case MP_PIC_ENABLE_CLR:
 621         s->enabled &= ~value;
 622         s->level &= ~value;
 623         break;
 624     }
 625     mv88w8618_pic_update(s);
 626 }
 627
 628 static void mv88w8618_pic_reset(void *opaque)
 629 {
 630     mv88w8618_pic_state *s = opaque;
 631
 632     s->level = 0;
 633     s->enabled = 0;
 634 }
 635
 636 static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
 637     mv88w8618_pic_read,
 638     mv88w8618_pic_read,
 639     mv88w8618_pic_read
 640 };
 641
 642 static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
 643     mv88w8618_pic_write,
 644     mv88w8618_pic_write,
 645     mv88w8618_pic_write
 646 };
 647
 648 static int mv88w8618_pic_init(SysBusDevice *dev)
 649 {
 650     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 651     int iomemtype;
 652
 653     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 654     sysbus_init_irq(dev, &s->parent_irq);
 655     iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
 656                                        mv88w8618_pic_writefn, s);
 657     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
 658
 659     qemu_register_reset(mv88w8618_pic_reset, s);
 660     return 0;
 661 }
 662
 663 /* PIT register offsets */
 664 #define MP_PIT_TIMER1_LENGTH    0x00
 665 /* ... */
 666 #define MP_PIT_TIMER4_LENGTH    0x0C
 667 #define MP_PIT_CONTROL          0x10
 668 #define MP_PIT_TIMER1_VALUE     0x14
 669 /* ... */
 670 #define MP_PIT_TIMER4_VALUE     0x20
 671 #define MP_BOARD_RESET          0x34
 672
 673 /* Magic board reset value (probably some watchdog behind it) */
 674 #define MP_BOARD_RESET_MAGIC    0x10000
 675
 676 typedef struct mv88w8618_timer_state {
 677     ptimer_state *ptimer;
 678     uint32_t limit;
 679     int freq;
 680     qemu_irq irq;
 681 } mv88w8618_timer_state;
 682
 683 typedef struct mv88w8618_pit_state {
 684     SysBusDevice busdev;
 685     mv88w8618_timer_state timer[4];
 686     uint32_t control;
 687 } mv88w8618_pit_state;
 688
 689 static void mv88w8618_timer_tick(void *opaque)
 690 {
 691     mv88w8618_timer_state *s = opaque;
 692
 693     qemu_irq_raise(s->irq);
 694 }
 695
 696 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 697                                  uint32_t freq)
 698 {
 699     QEMUBH *bh;
 700
 701     sysbus_init_irq(dev, &s->irq);
 702     s->freq = freq;
 703
 704     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 705     s->ptimer = ptimer_init(bh);
 706 }
 707
 708 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
 709 {
 710     mv88w8618_pit_state *s = opaque;
 711     mv88w8618_timer_state *t;
 712
 713     switch (offset) {
 714     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 715         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 716         return ptimer_get_count(t->ptimer);
 717
 718     default:
 719         return 0;
 720     }
 721 }
 722
 723 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 724                                 uint32_t value)
 725 {
 726     mv88w8618_pit_state *s = opaque;
 727     mv88w8618_timer_state *t;
 728     int i;
 729
 730     switch (offset) {
 731     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 732         t = &s->timer[offset >> 2];
 733         t->limit = value;
 734         ptimer_set_limit(t->ptimer, t->limit, 1);
 735         break;
 736
 737     case MP_PIT_CONTROL:
 738         for (i = 0; i < 4; i++) {
 739             if (value & 0xf) {
 740                 t = &s->timer[i];
 741                 ptimer_set_limit(t->ptimer, t->limit, 0);
 742                 ptimer_set_freq(t->ptimer, t->freq);
 743                 ptimer_run(t->ptimer, 0);
 744             }
 745             value >>= 4;
 746         }
 747         break;
 748
 749     case MP_BOARD_RESET:
 750         if (value == MP_BOARD_RESET_MAGIC)
 751             qemu_system_reset_request();
 752         break;
 753     }
 754 }
 755
 756 static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
 757     mv88w8618_pit_read,
 758     mv88w8618_pit_read,
 759     mv88w8618_pit_read
 760 };
 761
 762 static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
 763     mv88w8618_pit_write,
 764     mv88w8618_pit_write,
 765     mv88w8618_pit_write
 766 };
 767
 768 static int mv88w8618_pit_init(SysBusDevice *dev)
 769 {
 770     int iomemtype;
 771     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 772     int i;
 773
 774     /* Letting them all run at 1 MHz is likely just a pragmatic
 775      * simplification. */
 776     for (i = 0; i < 4; i++) {
 777         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 778     }
 779
 780     iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
 781                                        mv88w8618_pit_writefn, s);
 782     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
 783     return 0;
 784 }
 785
 786 /* Flash config register offsets */
 787 #define MP_FLASHCFG_CFGR0    0x04
 788
 789 typedef struct mv88w8618_flashcfg_state {
 790     SysBusDevice busdev;
 791     uint32_t cfgr0;
 792 } mv88w8618_flashcfg_state;
 793
 794 static uint32_t mv88w8618_flashcfg_read(void *opaque,
 795                                         target_phys_addr_t offset)
 796 {
 797     mv88w8618_flashcfg_state *s = opaque;
 798
 799     switch (offset) {
 800     case MP_FLASHCFG_CFGR0:
 801         return s->cfgr0;
 802
 803     default:
 804         return 0;
 805     }
 806 }
 807
 808 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 809                                      uint32_t value)
 810 {
 811     mv88w8618_flashcfg_state *s = opaque;
 812
 813     switch (offset) {
 814     case MP_FLASHCFG_CFGR0:
 815         s->cfgr0 = value;
 816         break;
 817     }
 818 }
 819
 820 static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
 821     mv88w8618_flashcfg_read,
 822     mv88w8618_flashcfg_read,
 823     mv88w8618_flashcfg_read
 824 };
 825
 826 static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
 827     mv88w8618_flashcfg_write,
 828     mv88w8618_flashcfg_write,
 829     mv88w8618_flashcfg_write
 830 };
 831
 832 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 833 {
 834     int iomemtype;
 835     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 836
 837     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 838     iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
 839                        mv88w8618_flashcfg_writefn, s);
 840     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
 841     return 0;
 842 }
 843
 844 /* Misc register offsets */
 845 #define MP_MISC_BOARD_REVISION  0x18
 846
 847 #define MP_BOARD_REVISION       0x31
 848
 849 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
 850 {
 851     switch (offset) {
 852     case MP_MISC_BOARD_REVISION:
 853         return MP_BOARD_REVISION;
 854
 855     default:
 856         return 0;
 857     }
 858 }
 859
 860 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
 861                                 uint32_t value)
 862 {
 863 }
 864
 865 static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
 866     musicpal_misc_read,
 867     musicpal_misc_read,
 868     musicpal_misc_read,
 869 };
 870
 871 static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
 872     musicpal_misc_write,
 873     musicpal_misc_write,
 874     musicpal_misc_write,
 875 };
 876
 877 static void musicpal_misc_init(void)
 878 {
 879     int iomemtype;
 880
 881     iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
 882                                        musicpal_misc_writefn, NULL);
 883     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
 884 }
 885
 886 /* WLAN register offsets */
 887 #define MP_WLAN_MAGIC1          0x11c
 888 #define MP_WLAN_MAGIC2          0x124
 889
 890 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
 891 {
 892     switch (offset) {
 893     /* Workaround to allow loading the binary-only wlandrv.ko crap
 894      * from the original Freecom firmware. */
 895     case MP_WLAN_MAGIC1:
 896         return ~3;
 897     case MP_WLAN_MAGIC2:
 898         return -1;
 899
 900     default:
 901         return 0;
 902     }
 903 }
 904
 905 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
 906                                  uint32_t value)
 907 {
 908 }
 909
 910 static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
 911     mv88w8618_wlan_read,
 912     mv88w8618_wlan_read,
 913     mv88w8618_wlan_read,
 914 };
 915
 916 static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
 917     mv88w8618_wlan_write,
 918     mv88w8618_wlan_write,
 919     mv88w8618_wlan_write,
 920 };
 921
 922 static int mv88w8618_wlan_init(SysBusDevice *dev)
 923 {
 924     int iomemtype;
 925
 926     iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
 927                                        mv88w8618_wlan_writefn, NULL);
 928     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
 929     return 0;
 930 }
 931
 932 /* GPIO register offsets */
 933 #define MP_GPIO_OE_LO           0x008
 934 #define MP_GPIO_OUT_LO          0x00c
 935 #define MP_GPIO_IN_LO           0x010
 936 #define MP_GPIO_ISR_LO          0x020
 937 #define MP_GPIO_OE_HI           0x508
 938 #define MP_GPIO_OUT_HI          0x50c
 939 #define MP_GPIO_IN_HI           0x510
 940 #define MP_GPIO_ISR_HI          0x520
 941
 942 /* GPIO bits & masks */
 943 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
 944 #define MP_GPIO_I2C_DATA_BIT    29
 945 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
 946 #define MP_GPIO_I2C_CLOCK_BIT   30
 947
 948 /* LCD brightness bits in GPIO_OE_HI */
 949 #define MP_OE_LCD_BRIGHTNESS    0x0007
 950
 951 typedef struct musicpal_gpio_state {
 952     SysBusDevice busdev;
 953     uint32_t lcd_brightness;
 954     uint32_t out_state;
 955     uint32_t in_state;
 956     uint32_t isr;
 957     uint32_t i2c_read_data;
 958     uint32_t key_released;
 959     uint32_t keys_event;    /* store the received key event */
 960     qemu_irq irq;
 961     qemu_irq out[5];
 962 } musicpal_gpio_state;
 963
 964 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
 965     int i;
 966     uint32_t brightness;
 967
 968     /* compute brightness ratio */
 969     switch (s->lcd_brightness) {
 970     case 0x00000007:
 971         brightness = 0;
 972         break;
 973
 974     case 0x00020000:
 975         brightness = 1;
 976         break;
 977
 978     case 0x00020001:
 979         brightness = 2;
 980         break;
 981
 982     case 0x00040000:
 983         brightness = 3;
 984         break;
 985
 986     case 0x00010006:
 987         brightness = 4;
 988         break;
 989
 990     case 0x00020005:
 991         brightness = 5;
 992         break;
 993
 994     case 0x00040003:
 995         brightness = 6;
 996         break;
 997
 998     case 0x00030004:
 999     default:
1000         brightness = 7;
1001     }
1002
1003     /* set lcd brightness GPIOs  */
1004     for (i = 0; i <= 2; i++)
1005         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1006 }
1007
1008 static void musicpal_gpio_keys_update(musicpal_gpio_state *s)
1009 {
1010         int gpio_mask = 0;
1011
1012         /* transform the key state for GPIO usage */
1013         gpio_mask |= (s->keys_event & 15) << 8;
1014         gpio_mask |= ((s->keys_event >> 4) & 15) << 19;
1015
1016         /* update GPIO state */
1017         if (s->key_released) {
1018             s->in_state |= gpio_mask;
1019         } else {
1020             s->in_state &= ~gpio_mask;
1021             s->isr = gpio_mask;
1022             qemu_irq_raise(s->irq);
1023         }
1024 }
1025
1026 static void musicpal_gpio_irq(void *opaque, int irq, int level)
1027 {
1028     musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
1029
1030     if (irq == 10) {
1031         s->i2c_read_data = level;
1032     }
1033
1034     /* receives keys bits */
1035     if (irq <= 7) {
1036         s->keys_event &= ~(1 << irq);
1037         s->keys_event |= level << irq;
1038         return;
1039     }
1040
1041     /* receives key press/release */
1042     if (irq == 8) {
1043         s->key_released = level;
1044         return;
1045     }
1046
1047     /* a key has been transmited */
1048     if (irq == 9 && level == 1)
1049         musicpal_gpio_keys_update(s);
1050 }
1051
1052 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1053 {
1054     musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
1055
1056     switch (offset) {
1057     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1058         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1059
1060     case MP_GPIO_OUT_LO:
1061         return s->out_state & 0xFFFF;
1062     case MP_GPIO_OUT_HI:
1063         return s->out_state >> 16;
1064
1065     case MP_GPIO_IN_LO:
1066         return s->in_state & 0xFFFF;
1067     case MP_GPIO_IN_HI:
1068         /* Update received I2C data */
1069         s->in_state = (s->in_state & ~MP_GPIO_I2C_DATA) |
1070                         (s->i2c_read_data << MP_GPIO_I2C_DATA_BIT);
1071         return s->in_state >> 16;
1072
1073     case MP_GPIO_ISR_LO:
1074         return s->isr & 0xFFFF;
1075     case MP_GPIO_ISR_HI:
1076         return s->isr >> 16;
1077
1078     default:
1079         return 0;
1080     }
1081 }
1082
1083 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1084                                 uint32_t value)
1085 {
1086     musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
1087     switch (offset) {
1088     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1089         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1090                          (value & MP_OE_LCD_BRIGHTNESS);
1091         musicpal_gpio_brightness_update(s);
1092         break;
1093
1094     case MP_GPIO_OUT_LO:
1095         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1096         break;
1097     case MP_GPIO_OUT_HI:
1098         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1099         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1100                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1101         musicpal_gpio_brightness_update(s);
1102         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1103         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1104         break;
1105
1106     }
1107 }
1108
1109 static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
1110     musicpal_gpio_read,
1111     musicpal_gpio_read,
1112     musicpal_gpio_read,
1113 };
1114
1115 static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
1116     musicpal_gpio_write,
1117     musicpal_gpio_write,
1118     musicpal_gpio_write,
1119 };
1120
1121 static void musicpal_gpio_reset(musicpal_gpio_state *s)
1122 {
1123     s->in_state = 0xffffffff;
1124     s->i2c_read_data = 1;
1125     s->key_released = 0;
1126     s->keys_event = 0;
1127     s->isr = 0;
1128 }
1129
1130 static int musicpal_gpio_init(SysBusDevice *dev)
1131 {
1132     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1133     int iomemtype;
1134
1135     sysbus_init_irq(dev, &s->irq);
1136
1137     iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
1138                                        musicpal_gpio_writefn, s);
1139     sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
1140
1141     musicpal_gpio_reset(s);
1142
1143     /* 3 brightness out + 2 lcd (data and clock ) */
1144     qdev_init_gpio_out(&dev->qdev, s->out, 5);
1145     /* 10 gpio button input + 1 I2C data input */
1146     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_irq, 11);
1147
1148     return 0;
1149 }
1150
1151 /* Keyboard codes & masks */
1152 #define KEY_RELEASED            0x80
1153 #define KEY_CODE                0x7f
1154
1155 #define KEYCODE_TAB             0x0f
1156 #define KEYCODE_ENTER           0x1c
1157 #define KEYCODE_F               0x21
1158 #define KEYCODE_M               0x32
1159
1160 #define KEYCODE_EXTENDED        0xe0
1161 #define KEYCODE_UP              0x48
1162 #define KEYCODE_DOWN            0x50
1163 #define KEYCODE_LEFT            0x4b
1164 #define KEYCODE_RIGHT           0x4d
1165
1166 #define MP_KEY_WHEEL_VOL       (1)
1167 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1168 #define MP_KEY_WHEEL_NAV       (1 << 2)
1169 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1170 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1171 #define MP_KEY_BTN_MENU        (1 << 5)
1172 #define MP_KEY_BTN_VOLUME      (1 << 6)
1173 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1174
1175 typedef struct musicpal_key_state {
1176     SysBusDevice busdev;
1177     uint32_t kbd_extended;
1178     uint32_t keys_state;
1179     qemu_irq out[10];
1180 } musicpal_key_state;
1181
1182 static void musicpal_key_event(void *opaque, int keycode)
1183 {
1184     musicpal_key_state *s = (musicpal_key_state *) opaque;
1185     uint32_t event = 0;
1186     int i;
1187
1188     if (keycode == KEYCODE_EXTENDED) {
1189         s->kbd_extended = 1;
1190         return;
1191     }
1192
1193     if (s->kbd_extended)
1194         switch (keycode & KEY_CODE) {
1195         case KEYCODE_UP:
1196             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1197             break;
1198
1199         case KEYCODE_DOWN:
1200             event = MP_KEY_WHEEL_NAV;
1201             break;
1202
1203         case KEYCODE_LEFT:
1204             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1205             break;
1206
1207         case KEYCODE_RIGHT:
1208             event = MP_KEY_WHEEL_VOL;
1209             break;
1210         }
1211     else {
1212         switch (keycode & KEY_CODE) {
1213         case KEYCODE_F:
1214             event = MP_KEY_BTN_FAVORITS;
1215             break;
1216
1217         case KEYCODE_TAB:
1218             event = MP_KEY_BTN_VOLUME;
1219             break;
1220
1221         case KEYCODE_ENTER:
1222             event = MP_KEY_BTN_NAVIGATION;
1223             break;
1224
1225         case KEYCODE_M:
1226             event = MP_KEY_BTN_MENU;
1227             break;
1228         }
1229         /* Do not repeat already pressed buttons */
1230         if (!(keycode & KEY_RELEASED) && !(s->keys_state & event))
1231             event = 0;
1232     }
1233
1234     if (event) {
1235
1236         /* transmit key event on GPIOS */
1237         for (i = 0; i <= 7; i++)
1238             qemu_set_irq(s->out[i], (event >> i) & 1);
1239
1240         /* handle key press/release */
1241         if (keycode & KEY_RELEASED) {
1242             s->keys_state |= event;
1243             qemu_irq_raise(s->out[8]);
1244         } else {
1245             s->keys_state &= ~event;
1246             qemu_irq_lower(s->out[8]);
1247         }
1248
1249         /* signal that a key event occured */
1250         qemu_irq_pulse(s->out[9]);
1251     }
1252
1253     s->kbd_extended = 0;
1254 }
1255
1256 static int musicpal_key_init(SysBusDevice *dev)
1257 {
1258     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1259
1260     sysbus_init_mmio(dev, 0x0, 0);
1261
1262     s->kbd_extended = 0;
1263     s->keys_state = 0;
1264
1265     /* 8 key event GPIO + 1 key press/release + 1 strobe */
1266     qdev_init_gpio_out(&dev->qdev, s->out, 10);
1267
1268     qemu_add_kbd_event_handler(musicpal_key_event, s);
1269
1270     return 0;
1271 }
1272
1273 static struct arm_boot_info musicpal_binfo = {
1274     .loader_start = 0x0,
1275     .board_id = 0x20e,
1276 };
1277
1278 static void musicpal_init(ram_addr_t ram_size,
1279                const char *boot_device,
1280                const char *kernel_filename, const char *kernel_cmdline,
1281                const char *initrd_filename, const char *cpu_model)
1282 {
1283     CPUState *env;
1284     qemu_irq *cpu_pic;
1285     qemu_irq pic[32];
1286     DeviceState *dev;
1287     DeviceState *i2c_dev;
1288     DeviceState *lcd_dev;
1289     DeviceState *key_dev;
1290 #ifdef HAS_AUDIO
1291     DeviceState *wm8750_dev;
1292     SysBusDevice *s;
1293 #endif
1294     i2c_bus *i2c;
1295     int i;
1296     unsigned long flash_size;
1297     DriveInfo *dinfo;
1298     ram_addr_t sram_off;
1299
1300     if (!cpu_model)
1301         cpu_model = "arm926";
1302
1303     env = cpu_init(cpu_model);
1304     if (!env) {
1305         fprintf(stderr, "Unable to find CPU definition\n");
1306         exit(1);
1307     }
1308     cpu_pic = arm_pic_init_cpu(env);
1309
1310     /* For now we use a fixed - the original - RAM size */
1311     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1312                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1313
1314     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1315     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1316
1317     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1318                                cpu_pic[ARM_PIC_CPU_IRQ]);
1319     for (i = 0; i < 32; i++) {
1320         pic[i] = qdev_get_gpio_in(dev, i);
1321     }
1322     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1323                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1324                           pic[MP_TIMER4_IRQ], NULL);
1325
1326     if (serial_hds[0])
1327         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1328                    serial_hds[0], 1);
1329     if (serial_hds[1])
1330         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1331                    serial_hds[1], 1);
1332
1333     /* Register flash */
1334     dinfo = drive_get(IF_PFLASH, 0, 0);
1335     if (dinfo) {
1336         flash_size = bdrv_getlength(dinfo->bdrv);
1337         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1338             flash_size != 32*1024*1024) {
1339             fprintf(stderr, "Invalid flash image size\n");
1340             exit(1);
1341         }
1342
1343         /*
1344          * The original U-Boot accesses the flash at 0xFE000000 instead of
1345          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1346          * image is smaller than 32 MB.
1347          */
1348         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1349                               dinfo->bdrv, 0x10000,
1350                               (flash_size + 0xffff) >> 16,
1351                               MP_FLASH_SIZE_MAX / flash_size,
1352                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1353                               0x5555, 0x2AAA);
1354     }
1355     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1356
1357     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1358     dev = qdev_create(NULL, "mv88w8618_eth");
1359     dev->nd = &nd_table[0];
1360     qdev_init(dev);
1361     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1362     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1363
1364     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1365
1366     musicpal_misc_init();
1367
1368     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1369     i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL);
1370     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1371
1372     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1373     key_dev = sysbus_create_simple("musicpal_key", 0, NULL);
1374
1375     /* I2C read data */
1376     qdev_connect_gpio_out(i2c_dev, 0, qdev_get_gpio_in(dev, 10));
1377     /* I2C data */
1378     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1379     /* I2C clock */
1380     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1381
1382     for (i = 0; i < 3; i++)
1383         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1384
1385     for (i = 0; i < 10; i++)
1386         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i));
1387
1388 #ifdef HAS_AUDIO
1389     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1390     dev = qdev_create(NULL, "mv88w8618_audio");
1391     s = sysbus_from_qdev(dev);
1392     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1393     qdev_init(dev);
1394     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1395     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1396 #endif
1397
1398     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1399     musicpal_binfo.kernel_filename = kernel_filename;
1400     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1401     musicpal_binfo.initrd_filename = initrd_filename;
1402     arm_load_kernel(env, &musicpal_binfo);
1403 }
1404
1405 static QEMUMachine musicpal_machine = {
1406     .name = "musicpal",
1407     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1408     .init = musicpal_init,
1409 };
1410
1411 static void musicpal_machine_init(void)
1412 {
1413     qemu_register_machine(&musicpal_machine);
1414 }
1415
1416 machine_init(musicpal_machine_init);
1417
1418 static void musicpal_register_devices(void)
1419 {
1420     sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state),
1421                         mv88w8618_pic_init);
1422     sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state),
1423                         mv88w8618_pit_init);
1424     sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state),
1425                         mv88w8618_flashcfg_init);
1426     sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state),
1427                         mv88w8618_eth_init);
1428     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1429                         mv88w8618_wlan_init);
1430     sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state),
1431                         musicpal_lcd_init);
1432     sysbus_register_dev("musicpal_gpio", sizeof(musicpal_gpio_state),
1433                         musicpal_gpio_init);
1434     sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state),
1435                         musicpal_key_init);
1436 }
1437
1438 device_init(musicpal_register_devices)