Merge remote branch 'qemu-kvm/uq/master' into staging-tmp
[qemu.git] / hw / sparc32_dma.c
blob6e991e073424090d6a8242b35dbda8e5da1fc243
1 /*
2 * QEMU Sparc32 DMA controller emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "hw.h"
26 #include "sparc32_dma.h"
27 #include "sun4m.h"
28 #include "sysbus.h"
30 /* debug DMA */
31 //#define DEBUG_DMA
34 * This is the DMA controller part of chip STP2000 (Master I/O), also
35 * produced as NCR89C100. See
36 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
37 * and
38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
41 #ifdef DEBUG_DMA
42 #define DPRINTF(fmt, ...) \
43 do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
44 #else
45 #define DPRINTF(fmt, ...)
46 #endif
48 #define DMA_REGS 4
49 #define DMA_SIZE (4 * sizeof(uint32_t))
50 /* We need the mask, because one instance of the device is not page
51 aligned (ledma, start address 0x0010) */
52 #define DMA_MASK (DMA_SIZE - 1)
54 #define DMA_VER 0xa0000000
55 #define DMA_INTR 1
56 #define DMA_INTREN 0x10
57 #define DMA_WRITE_MEM 0x100
58 #define DMA_LOADED 0x04000000
59 #define DMA_DRAIN_FIFO 0x40
60 #define DMA_RESET 0x80
62 typedef struct DMAState DMAState;
64 struct DMAState {
65 SysBusDevice busdev;
66 uint32_t dmaregs[DMA_REGS];
67 qemu_irq irq;
68 void *iommu;
69 qemu_irq dev_reset;
72 /* Note: on sparc, the lance 16 bit bus is swapped */
73 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
74 uint8_t *buf, int len, int do_bswap)
76 DMAState *s = opaque;
77 int i;
79 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
80 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
81 addr |= s->dmaregs[3];
82 if (do_bswap) {
83 sparc_iommu_memory_read(s->iommu, addr, buf, len);
84 } else {
85 addr &= ~1;
86 len &= ~1;
87 sparc_iommu_memory_read(s->iommu, addr, buf, len);
88 for(i = 0; i < len; i += 2) {
89 bswap16s((uint16_t *)(buf + i));
94 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
95 uint8_t *buf, int len, int do_bswap)
97 DMAState *s = opaque;
98 int l, i;
99 uint16_t tmp_buf[32];
101 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
102 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
103 addr |= s->dmaregs[3];
104 if (do_bswap) {
105 sparc_iommu_memory_write(s->iommu, addr, buf, len);
106 } else {
107 addr &= ~1;
108 len &= ~1;
109 while (len > 0) {
110 l = len;
111 if (l > sizeof(tmp_buf))
112 l = sizeof(tmp_buf);
113 for(i = 0; i < l; i += 2) {
114 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
116 sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
117 len -= l;
118 buf += l;
119 addr += l;
124 static void dma_set_irq(void *opaque, int irq, int level)
126 DMAState *s = opaque;
127 if (level) {
128 DPRINTF("Raise IRQ\n");
129 s->dmaregs[0] |= DMA_INTR;
130 qemu_irq_raise(s->irq);
131 } else {
132 s->dmaregs[0] &= ~DMA_INTR;
133 DPRINTF("Lower IRQ\n");
134 qemu_irq_lower(s->irq);
138 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
140 DMAState *s = opaque;
142 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
143 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
144 sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
145 DPRINTF("Raise IRQ\n");
146 s->dmaregs[0] |= DMA_INTR;
147 s->dmaregs[1] += len;
150 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
152 DMAState *s = opaque;
154 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
155 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
156 sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
157 DPRINTF("Raise IRQ\n");
158 s->dmaregs[0] |= DMA_INTR;
159 s->dmaregs[1] += len;
162 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
164 DMAState *s = opaque;
165 uint32_t saddr;
167 saddr = (addr & DMA_MASK) >> 2;
168 DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
169 s->dmaregs[saddr]);
171 return s->dmaregs[saddr];
174 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
176 DMAState *s = opaque;
177 uint32_t saddr;
179 saddr = (addr & DMA_MASK) >> 2;
180 DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
181 s->dmaregs[saddr], val);
182 switch (saddr) {
183 case 0:
184 if (!(val & DMA_INTREN)) {
185 DPRINTF("Lower IRQ\n");
186 qemu_irq_lower(s->irq);
188 if (val & DMA_RESET) {
189 qemu_irq_raise(s->dev_reset);
190 qemu_irq_lower(s->dev_reset);
191 } else if (val & DMA_DRAIN_FIFO) {
192 val &= ~DMA_DRAIN_FIFO;
193 } else if (val == 0)
194 val = DMA_DRAIN_FIFO;
195 val &= 0x0fffffff;
196 val |= DMA_VER;
197 break;
198 case 1:
199 s->dmaregs[0] |= DMA_LOADED;
200 break;
201 default:
202 break;
204 s->dmaregs[saddr] = val;
207 static CPUReadMemoryFunc * const dma_mem_read[3] = {
208 NULL,
209 NULL,
210 dma_mem_readl,
213 static CPUWriteMemoryFunc * const dma_mem_write[3] = {
214 NULL,
215 NULL,
216 dma_mem_writel,
219 static void dma_reset(DeviceState *d)
221 DMAState *s = container_of(d, DMAState, busdev.qdev);
223 memset(s->dmaregs, 0, DMA_SIZE);
224 s->dmaregs[0] = DMA_VER;
227 static const VMStateDescription vmstate_dma = {
228 .name ="sparc32_dma",
229 .version_id = 2,
230 .minimum_version_id = 2,
231 .minimum_version_id_old = 2,
232 .fields = (VMStateField []) {
233 VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS),
234 VMSTATE_END_OF_LIST()
238 static int sparc32_dma_init1(SysBusDevice *dev)
240 DMAState *s = FROM_SYSBUS(DMAState, dev);
241 int dma_io_memory;
243 sysbus_init_irq(dev, &s->irq);
245 dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
246 sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
248 qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
249 qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1);
251 return 0;
254 static SysBusDeviceInfo sparc32_dma_info = {
255 .init = sparc32_dma_init1,
256 .qdev.name = "sparc32_dma",
257 .qdev.size = sizeof(DMAState),
258 .qdev.vmsd = &vmstate_dma,
259 .qdev.reset = dma_reset,
260 .qdev.props = (Property[]) {
261 DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
262 DEFINE_PROP_END_OF_LIST(),
266 static void sparc32_dma_register_devices(void)
268 sysbus_register_withprop(&sparc32_dma_info);
271 device_init(sparc32_dma_register_devices)