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net/cadence_gem: Don't rx packets when no rx buffer available
[qemu.git] / target-xtensa / translate.c
blob2d2df33115f57afe2098d9e638069e712a6d1f80
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg-op.h"
37 #include "qemu/log.h"
38 #include "sysemu/sysemu.h"
39
40 #include "helper.h"
41 #define GEN_HELPER 1
42 #include "helper.h"
43
44 typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
49 int cring;
50 int ring;
51 uint32_t lbeg;
52 uint32_t lend;
53 TCGv_i32 litbase;
54 int is_jmp;
55 int singlestep_enabled;
56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
61
62 uint32_t ccount_delta;
63 unsigned used_window;
64
65 bool debug;
66 bool icount;
67 TCGv_i32 next_icount;
68
69 unsigned cpenable;
70 } DisasContext;
71
72 static TCGv_ptr cpu_env;
73 static TCGv_i32 cpu_pc;
74 static TCGv_i32 cpu_R[16];
75 static TCGv_i32 cpu_FR[16];
76 static TCGv_i32 cpu_SR[256];
77 static TCGv_i32 cpu_UR[256];
78
79 #include "exec/gen-icount.h"
80
81 typedef struct XtensaReg {
82 const char *name;
83 uint64_t opt_bits;
84 enum {
85 SR_R = 1,
86 SR_W = 2,
87 SR_X = 4,
88 SR_RW = 3,
89 SR_RWX = 7,
90 } access;
91 } XtensaReg;
92
93 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
94 .name = (regname), \
95 .opt_bits = XTENSA_OPTION_BIT(opt), \
96 .access = (acc), \
97 }
98
99 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
100
101 #define XTENSA_REG_BITS(regname, opt) { \
102 .name = (regname), \
103 .opt_bits = (opt), \
104 .access = SR_RWX, \
105 }
106
107 static const XtensaReg sregnames[256] = {
108 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
109 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
110 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
111 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
112 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
113 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
114 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
115 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
116 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
117 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
118 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
119 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
120 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
121 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
122 [WINDOW_START] = XTENSA_REG("WINDOW_START",
123 XTENSA_OPTION_WINDOWED_REGISTER),
124 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
125 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
126 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
127 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
128 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
129 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
130 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
131 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
132 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
133 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
134 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
135 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
136 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
137 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
138 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
139 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
140 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
141 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
142 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
143 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
144 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
145 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
146 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
152 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
153 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
155 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
157 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
159 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
160 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
161 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
162 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
163 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
164 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
165 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
166 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
167 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
168 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
169 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
170 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
171 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
172 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
173 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
174 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
175 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
176 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
177 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
178 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
179 XTENSA_OPTION_TIMER_INTERRUPT),
180 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
181 XTENSA_OPTION_TIMER_INTERRUPT),
182 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
183 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
184 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
185 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
186 };
187
188 static const XtensaReg uregnames[256] = {
189 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
190 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
191 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
192 };
193
194 void xtensa_translate_init(void)
195 {
196 static const char * const regnames[] = {
197 "ar0", "ar1", "ar2", "ar3",
198 "ar4", "ar5", "ar6", "ar7",
199 "ar8", "ar9", "ar10", "ar11",
200 "ar12", "ar13", "ar14", "ar15",
201 };
202 static const char * const fregnames[] = {
203 "f0", "f1", "f2", "f3",
204 "f4", "f5", "f6", "f7",
205 "f8", "f9", "f10", "f11",
206 "f12", "f13", "f14", "f15",
207 };
208 int i;
209
210 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
211 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
212 offsetof(CPUXtensaState, pc), "pc");
213
214 for (i = 0; i < 16; i++) {
215 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
216 offsetof(CPUXtensaState, regs[i]),
217 regnames[i]);
218 }
219
220 for (i = 0; i < 16; i++) {
221 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
222 offsetof(CPUXtensaState, fregs[i]),
223 fregnames[i]);
224 }
225
226 for (i = 0; i < 256; ++i) {
227 if (sregnames[i].name) {
228 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
229 offsetof(CPUXtensaState, sregs[i]),
230 sregnames[i].name);
231 }
232 }
233
234 for (i = 0; i < 256; ++i) {
235 if (uregnames[i].name) {
236 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
237 offsetof(CPUXtensaState, uregs[i]),
238 uregnames[i].name);
239 }
240 }
241 }
242
243 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
244 {
245 return xtensa_option_bits_enabled(dc->config, opt);
246 }
247
248 static inline bool option_enabled(DisasContext *dc, int opt)
249 {
250 return xtensa_option_enabled(dc->config, opt);
251 }
252
253 static void init_litbase(DisasContext *dc)
254 {
255 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
256 dc->litbase = tcg_temp_local_new_i32();
257 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
258 }
259 }
260
261 static void reset_litbase(DisasContext *dc)
262 {
263 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
264 tcg_temp_free(dc->litbase);
265 }
266 }
267
268 static void init_sar_tracker(DisasContext *dc)
269 {
270 dc->sar_5bit = false;
271 dc->sar_m32_5bit = false;
272 dc->sar_m32_allocated = false;
273 }
274
275 static void reset_sar_tracker(DisasContext *dc)
276 {
277 if (dc->sar_m32_allocated) {
278 tcg_temp_free(dc->sar_m32);
279 }
280 }
281
282 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
283 {
284 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
285 if (dc->sar_m32_5bit) {
286 tcg_gen_discard_i32(dc->sar_m32);
287 }
288 dc->sar_5bit = true;
289 dc->sar_m32_5bit = false;
290 }
291
292 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
293 {
294 TCGv_i32 tmp = tcg_const_i32(32);
295 if (!dc->sar_m32_allocated) {
296 dc->sar_m32 = tcg_temp_local_new_i32();
297 dc->sar_m32_allocated = true;
298 }
299 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
300 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
301 dc->sar_5bit = false;
302 dc->sar_m32_5bit = true;
303 tcg_temp_free(tmp);
304 }
305
306 static void gen_advance_ccount_cond(DisasContext *dc)
307 {
308 if (dc->ccount_delta > 0) {
309 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
310 gen_helper_advance_ccount(cpu_env, tmp);
311 tcg_temp_free(tmp);
312 }
313 }
314
315 static void gen_advance_ccount(DisasContext *dc)
316 {
317 gen_advance_ccount_cond(dc);
318 dc->ccount_delta = 0;
319 }
320
321 static void reset_used_window(DisasContext *dc)
322 {
323 dc->used_window = 0;
324 }
325
326 static void gen_exception(DisasContext *dc, int excp)
327 {
328 TCGv_i32 tmp = tcg_const_i32(excp);
329 gen_advance_ccount(dc);
330 gen_helper_exception(cpu_env, tmp);
331 tcg_temp_free(tmp);
332 }
333
334 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
335 {
336 TCGv_i32 tpc = tcg_const_i32(dc->pc);
337 TCGv_i32 tcause = tcg_const_i32(cause);
338 gen_advance_ccount(dc);
339 gen_helper_exception_cause(cpu_env, tpc, tcause);
340 tcg_temp_free(tpc);
341 tcg_temp_free(tcause);
342 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
343 cause == SYSCALL_CAUSE) {
344 dc->is_jmp = DISAS_UPDATE;
345 }
346 }
347
348 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
349 TCGv_i32 vaddr)
350 {
351 TCGv_i32 tpc = tcg_const_i32(dc->pc);
352 TCGv_i32 tcause = tcg_const_i32(cause);
353 gen_advance_ccount(dc);
354 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
355 tcg_temp_free(tpc);
356 tcg_temp_free(tcause);
357 }
358
359 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
360 {
361 TCGv_i32 tpc = tcg_const_i32(dc->pc);
362 TCGv_i32 tcause = tcg_const_i32(cause);
363 gen_advance_ccount(dc);
364 gen_helper_debug_exception(cpu_env, tpc, tcause);
365 tcg_temp_free(tpc);
366 tcg_temp_free(tcause);
367 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
368 dc->is_jmp = DISAS_UPDATE;
369 }
370 }
371
372 static void gen_check_privilege(DisasContext *dc)
373 {
374 if (dc->cring) {
375 gen_exception_cause(dc, PRIVILEGED_CAUSE);
376 dc->is_jmp = DISAS_UPDATE;
377 }
378 }
379
380 static void gen_check_cpenable(DisasContext *dc, unsigned cp)
381 {
382 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
383 !(dc->cpenable & (1 << cp))) {
384 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
385 dc->is_jmp = DISAS_UPDATE;
386 }
387 }
388
389 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
390 {
391 tcg_gen_mov_i32(cpu_pc, dest);
392 gen_advance_ccount(dc);
393 if (dc->icount) {
394 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
395 }
396 if (dc->singlestep_enabled) {
397 gen_exception(dc, EXCP_DEBUG);
398 } else {
399 if (slot >= 0) {
400 tcg_gen_goto_tb(slot);
401 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
402 } else {
403 tcg_gen_exit_tb(0);
404 }
405 }
406 dc->is_jmp = DISAS_UPDATE;
407 }
408
409 static void gen_jump(DisasContext *dc, TCGv dest)
410 {
411 gen_jump_slot(dc, dest, -1);
412 }
413
414 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
415 {
416 TCGv_i32 tmp = tcg_const_i32(dest);
417 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
418 slot = -1;
419 }
420 gen_jump_slot(dc, tmp, slot);
421 tcg_temp_free(tmp);
422 }
423
424 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
425 int slot)
426 {
427 TCGv_i32 tcallinc = tcg_const_i32(callinc);
428
429 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
430 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
431 tcg_temp_free(tcallinc);
432 tcg_gen_movi_i32(cpu_R[callinc << 2],
433 (callinc << 30) | (dc->next_pc & 0x3fffffff));
434 gen_jump_slot(dc, dest, slot);
435 }
436
437 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
438 {
439 gen_callw_slot(dc, callinc, dest, -1);
440 }
441
442 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
443 {
444 TCGv_i32 tmp = tcg_const_i32(dest);
445 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
446 slot = -1;
447 }
448 gen_callw_slot(dc, callinc, tmp, slot);
449 tcg_temp_free(tmp);
450 }
451
452 static bool gen_check_loop_end(DisasContext *dc, int slot)
453 {
454 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
455 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
456 dc->next_pc == dc->lend) {
457 int label = gen_new_label();
458
459 gen_advance_ccount(dc);
460 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
461 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
462 gen_jumpi(dc, dc->lbeg, slot);
463 gen_set_label(label);
464 gen_jumpi(dc, dc->next_pc, -1);
465 return true;
466 }
467 return false;
468 }
469
470 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
471 {
472 if (!gen_check_loop_end(dc, slot)) {
473 gen_jumpi(dc, dc->next_pc, slot);
474 }
475 }
476
477 static void gen_brcond(DisasContext *dc, TCGCond cond,
478 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
479 {
480 int label = gen_new_label();
481
482 gen_advance_ccount(dc);
483 tcg_gen_brcond_i32(cond, t0, t1, label);
484 gen_jumpi_check_loop_end(dc, 0);
485 gen_set_label(label);
486 gen_jumpi(dc, dc->pc + offset, 1);
487 }
488
489 static void gen_brcondi(DisasContext *dc, TCGCond cond,
490 TCGv_i32 t0, uint32_t t1, uint32_t offset)
491 {
492 TCGv_i32 tmp = tcg_const_i32(t1);
493 gen_brcond(dc, cond, t0, tmp, offset);
494 tcg_temp_free(tmp);
495 }
496
497 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
498 {
499 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
500 if (sregnames[sr].name) {
501 qemu_log("SR %s is not configured\n", sregnames[sr].name);
502 } else {
503 qemu_log("SR %d is not implemented\n", sr);
504 }
505 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
506 return false;
507 } else if (!(sregnames[sr].access & access)) {
508 static const char * const access_text[] = {
509 [SR_R] = "rsr",
510 [SR_W] = "wsr",
511 [SR_X] = "xsr",
512 };
513 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
514 qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
515 access_text[access]);
516 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
517 return false;
518 }
519 return true;
520 }
521
522 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
523 {
524 gen_advance_ccount(dc);
525 tcg_gen_mov_i32(d, cpu_SR[sr]);
526 }
527
528 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
529 {
530 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
531 tcg_gen_or_i32(d, d, cpu_SR[sr]);
532 tcg_gen_andi_i32(d, d, 0xfffffffc);
533 }
534
535 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
536 {
537 static void (* const rsr_handler[256])(DisasContext *dc,
538 TCGv_i32 d, uint32_t sr) = {
539 [CCOUNT] = gen_rsr_ccount,
540 [PTEVADDR] = gen_rsr_ptevaddr,
541 };
542
543 if (rsr_handler[sr]) {
544 rsr_handler[sr](dc, d, sr);
545 } else {
546 tcg_gen_mov_i32(d, cpu_SR[sr]);
547 }
548 }
549
550 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
551 {
552 gen_helper_wsr_lbeg(cpu_env, s);
553 gen_jumpi_check_loop_end(dc, 0);
554 }
555
556 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
557 {
558 gen_helper_wsr_lend(cpu_env, s);
559 gen_jumpi_check_loop_end(dc, 0);
560 }
561
562 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
563 {
564 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
565 if (dc->sar_m32_5bit) {
566 tcg_gen_discard_i32(dc->sar_m32);
567 }
568 dc->sar_5bit = false;
569 dc->sar_m32_5bit = false;
570 }
571
572 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
573 {
574 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
575 }
576
577 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
578 {
579 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
580 /* This can change tb->flags, so exit tb */
581 gen_jumpi_check_loop_end(dc, -1);
582 }
583
584 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
585 {
586 tcg_gen_ext8s_i32(cpu_SR[sr], s);
587 }
588
589 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
590 {
591 gen_helper_wsr_windowbase(cpu_env, v);
592 reset_used_window(dc);
593 }
594
595 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
596 {
597 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
598 reset_used_window(dc);
599 }
600
601 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
602 {
603 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
604 }
605
606 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
607 {
608 gen_helper_wsr_rasid(cpu_env, v);
609 /* This can change tb->flags, so exit tb */
610 gen_jumpi_check_loop_end(dc, -1);
611 }
612
613 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
614 {
615 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
616 }
617
618 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
619 {
620 gen_helper_wsr_ibreakenable(cpu_env, v);
621 gen_jumpi_check_loop_end(dc, 0);
622 }
623
624 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
625 {
626 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
627 }
628
629 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
630 {
631 unsigned id = sr - IBREAKA;
632
633 if (id < dc->config->nibreak) {
634 TCGv_i32 tmp = tcg_const_i32(id);
635 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
636 tcg_temp_free(tmp);
637 gen_jumpi_check_loop_end(dc, 0);
638 }
639 }
640
641 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
642 {
643 unsigned id = sr - DBREAKA;
644
645 if (id < dc->config->ndbreak) {
646 TCGv_i32 tmp = tcg_const_i32(id);
647 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
648 tcg_temp_free(tmp);
649 }
650 }
651
652 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
653 {
654 unsigned id = sr - DBREAKC;
655
656 if (id < dc->config->ndbreak) {
657 TCGv_i32 tmp = tcg_const_i32(id);
658 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
659 tcg_temp_free(tmp);
660 }
661 }
662
663 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
664 {
665 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
666 /* This can change tb->flags, so exit tb */
667 gen_jumpi_check_loop_end(dc, -1);
668 }
669
670 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
671 {
672 tcg_gen_andi_i32(cpu_SR[sr], v,
673 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
674 gen_helper_check_interrupts(cpu_env);
675 gen_jumpi_check_loop_end(dc, 0);
676 }
677
678 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
679 {
680 TCGv_i32 tmp = tcg_temp_new_i32();
681
682 tcg_gen_andi_i32(tmp, v,
683 dc->config->inttype_mask[INTTYPE_EDGE] |
684 dc->config->inttype_mask[INTTYPE_NMI] |
685 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
686 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
687 tcg_temp_free(tmp);
688 gen_helper_check_interrupts(cpu_env);
689 }
690
691 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
692 {
693 tcg_gen_mov_i32(cpu_SR[sr], v);
694 gen_helper_check_interrupts(cpu_env);
695 gen_jumpi_check_loop_end(dc, 0);
696 }
697
698 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
699 {
700 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
701 PS_UM | PS_EXCM | PS_INTLEVEL;
702
703 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
704 mask |= PS_RING;
705 }
706 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
707 reset_used_window(dc);
708 gen_helper_check_interrupts(cpu_env);
709 /* This can change mmu index and tb->flags, so exit tb */
710 gen_jumpi_check_loop_end(dc, -1);
711 }
712
713 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
714 {
715 if (dc->icount) {
716 tcg_gen_mov_i32(dc->next_icount, v);
717 } else {
718 tcg_gen_mov_i32(cpu_SR[sr], v);
719 }
720 }
721
722 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
723 {
724 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
725 /* This can change tb->flags, so exit tb */
726 gen_jumpi_check_loop_end(dc, -1);
727 }
728
729 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
730 {
731 uint32_t id = sr - CCOMPARE;
732 if (id < dc->config->nccompare) {
733 uint32_t int_bit = 1 << dc->config->timerint[id];
734 gen_advance_ccount(dc);
735 tcg_gen_mov_i32(cpu_SR[sr], v);
736 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
737 gen_helper_check_interrupts(cpu_env);
738 }
739 }
740
741 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
742 {
743 static void (* const wsr_handler[256])(DisasContext *dc,
744 uint32_t sr, TCGv_i32 v) = {
745 [LBEG] = gen_wsr_lbeg,
746 [LEND] = gen_wsr_lend,
747 [SAR] = gen_wsr_sar,
748 [BR] = gen_wsr_br,
749 [LITBASE] = gen_wsr_litbase,
750 [ACCHI] = gen_wsr_acchi,
751 [WINDOW_BASE] = gen_wsr_windowbase,
752 [WINDOW_START] = gen_wsr_windowstart,
753 [PTEVADDR] = gen_wsr_ptevaddr,
754 [RASID] = gen_wsr_rasid,
755 [ITLBCFG] = gen_wsr_tlbcfg,
756 [DTLBCFG] = gen_wsr_tlbcfg,
757 [IBREAKENABLE] = gen_wsr_ibreakenable,
758 [ATOMCTL] = gen_wsr_atomctl,
759 [IBREAKA] = gen_wsr_ibreaka,
760 [IBREAKA + 1] = gen_wsr_ibreaka,
761 [DBREAKA] = gen_wsr_dbreaka,
762 [DBREAKA + 1] = gen_wsr_dbreaka,
763 [DBREAKC] = gen_wsr_dbreakc,
764 [DBREAKC + 1] = gen_wsr_dbreakc,
765 [CPENABLE] = gen_wsr_cpenable,
766 [INTSET] = gen_wsr_intset,
767 [INTCLEAR] = gen_wsr_intclear,
768 [INTENABLE] = gen_wsr_intenable,
769 [PS] = gen_wsr_ps,
770 [ICOUNT] = gen_wsr_icount,
771 [ICOUNTLEVEL] = gen_wsr_icountlevel,
772 [CCOMPARE] = gen_wsr_ccompare,
773 [CCOMPARE + 1] = gen_wsr_ccompare,
774 [CCOMPARE + 2] = gen_wsr_ccompare,
775 };
776
777 if (wsr_handler[sr]) {
778 wsr_handler[sr](dc, sr, s);
779 } else {
780 tcg_gen_mov_i32(cpu_SR[sr], s);
781 }
782 }
783
784 static void gen_wur(uint32_t ur, TCGv_i32 s)
785 {
786 switch (ur) {
787 case FCR:
788 gen_helper_wur_fcr(cpu_env, s);
789 break;
790
791 case FSR:
792 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
793 break;
794
795 default:
796 tcg_gen_mov_i32(cpu_UR[ur], s);
797 break;
798 }
799 }
800
801 static void gen_load_store_alignment(DisasContext *dc, int shift,
802 TCGv_i32 addr, bool no_hw_alignment)
803 {
804 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
805 tcg_gen_andi_i32(addr, addr, ~0 << shift);
806 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
807 no_hw_alignment) {
808 int label = gen_new_label();
809 TCGv_i32 tmp = tcg_temp_new_i32();
810 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
811 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
812 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
813 gen_set_label(label);
814 tcg_temp_free(tmp);
815 }
816 }
817
818 static void gen_waiti(DisasContext *dc, uint32_t imm4)
819 {
820 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
821 TCGv_i32 intlevel = tcg_const_i32(imm4);
822 gen_advance_ccount(dc);
823 gen_helper_waiti(cpu_env, pc, intlevel);
824 tcg_temp_free(pc);
825 tcg_temp_free(intlevel);
826 }
827
828 static void gen_window_check1(DisasContext *dc, unsigned r1)
829 {
830 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
831 return;
832 }
833 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
834 r1 / 4 > dc->used_window) {
835 int label = gen_new_label();
836 TCGv_i32 ws = tcg_temp_new_i32();
837
838 dc->used_window = r1 / 4;
839 tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START],
840 dc->config->nareg / 4, dc->config->nareg / 4);
841 tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]);
842 tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2);
843 tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label);
844 {
845 TCGv_i32 pc = tcg_const_i32(dc->pc);
846 TCGv_i32 w = tcg_const_i32(r1 / 4);
847
848 gen_advance_ccount_cond(dc);
849 gen_helper_window_check(cpu_env, pc, w);
850
851 tcg_temp_free(w);
852 tcg_temp_free(pc);
853 }
854 gen_set_label(label);
855 tcg_temp_free(ws);
856 }
857 }
858
859 static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
860 {
861 gen_window_check1(dc, r1 > r2 ? r1 : r2);
862 }
863
864 static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
865 unsigned r3)
866 {
867 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
868 }
869
870 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
871 {
872 TCGv_i32 m = tcg_temp_new_i32();
873
874 if (hi) {
875 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
876 } else {
877 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
878 }
879 return m;
880 }
881
882 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
883 {
884 #define HAS_OPTION_BITS(opt) do { \
885 if (!option_bits_enabled(dc, opt)) { \
886 qemu_log("Option is not enabled %s:%d\n", \
887 __FILE__, __LINE__); \
888 goto invalid_opcode; \
889 } \
890 } while (0)
891
892 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
893
894 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
895 #define RESERVED() do { \
896 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
897 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
898 goto invalid_opcode; \
899 } while (0)
900
901
902 #ifdef TARGET_WORDS_BIGENDIAN
903 #define OP0 (((b0) & 0xf0) >> 4)
904 #define OP1 (((b2) & 0xf0) >> 4)
905 #define OP2 ((b2) & 0xf)
906 #define RRR_R ((b1) & 0xf)
907 #define RRR_S (((b1) & 0xf0) >> 4)
908 #define RRR_T ((b0) & 0xf)
909 #else
910 #define OP0 (((b0) & 0xf))
911 #define OP1 (((b2) & 0xf))
912 #define OP2 (((b2) & 0xf0) >> 4)
913 #define RRR_R (((b1) & 0xf0) >> 4)
914 #define RRR_S (((b1) & 0xf))
915 #define RRR_T (((b0) & 0xf0) >> 4)
916 #endif
917 #define RRR_X ((RRR_R & 0x4) >> 2)
918 #define RRR_Y ((RRR_T & 0x4) >> 2)
919 #define RRR_W (RRR_R & 0x3)
920
921 #define RRRN_R RRR_R
922 #define RRRN_S RRR_S
923 #define RRRN_T RRR_T
924
925 #define RRI8_R RRR_R
926 #define RRI8_S RRR_S
927 #define RRI8_T RRR_T
928 #define RRI8_IMM8 (b2)
929 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
930
931 #ifdef TARGET_WORDS_BIGENDIAN
932 #define RI16_IMM16 (((b1) << 8) | (b2))
933 #else
934 #define RI16_IMM16 (((b2) << 8) | (b1))
935 #endif
936
937 #ifdef TARGET_WORDS_BIGENDIAN
938 #define CALL_N (((b0) & 0xc) >> 2)
939 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
940 #else
941 #define CALL_N (((b0) & 0x30) >> 4)
942 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
943 #endif
944 #define CALL_OFFSET_SE \
945 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
946
947 #define CALLX_N CALL_N
948 #ifdef TARGET_WORDS_BIGENDIAN
949 #define CALLX_M ((b0) & 0x3)
950 #else
951 #define CALLX_M (((b0) & 0xc0) >> 6)
952 #endif
953 #define CALLX_S RRR_S
954
955 #define BRI12_M CALLX_M
956 #define BRI12_S RRR_S
957 #ifdef TARGET_WORDS_BIGENDIAN
958 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
959 #else
960 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
961 #endif
962 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
963
964 #define BRI8_M BRI12_M
965 #define BRI8_R RRI8_R
966 #define BRI8_S RRI8_S
967 #define BRI8_IMM8 RRI8_IMM8
968 #define BRI8_IMM8_SE RRI8_IMM8_SE
969
970 #define RSR_SR (b1)
971
972 uint8_t b0 = cpu_ldub_code(env, dc->pc);
973 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
974 uint8_t b2 = 0;
975
976 static const uint32_t B4CONST[] = {
977 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
978 };
979
980 static const uint32_t B4CONSTU[] = {
981 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
982 };
983
984 if (OP0 >= 8) {
985 dc->next_pc = dc->pc + 2;
986 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
987 } else {
988 dc->next_pc = dc->pc + 3;
989 b2 = cpu_ldub_code(env, dc->pc + 2);
990 }
991
992 switch (OP0) {
993 case 0: /*QRST*/
994 switch (OP1) {
995 case 0: /*RST0*/
996 switch (OP2) {
997 case 0: /*ST0*/
998 if ((RRR_R & 0xc) == 0x8) {
999 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1000 }
1001
1002 switch (RRR_R) {
1003 case 0: /*SNM0*/
1004 switch (CALLX_M) {
1005 case 0: /*ILL*/
1006 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1007 break;
1008
1009 case 1: /*reserved*/
1010 RESERVED();
1011 break;
1012
1013 case 2: /*JR*/
1014 switch (CALLX_N) {
1015 case 0: /*RET*/
1016 case 2: /*JX*/
1017 gen_window_check1(dc, CALLX_S);
1018 gen_jump(dc, cpu_R[CALLX_S]);
1019 break;
1020
1021 case 1: /*RETWw*/
1022 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1023 {
1024 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1025 gen_advance_ccount(dc);
1026 gen_helper_retw(tmp, cpu_env, tmp);
1027 gen_jump(dc, tmp);
1028 tcg_temp_free(tmp);
1029 }
1030 break;
1031
1032 case 3: /*reserved*/
1033 RESERVED();
1034 break;
1035 }
1036 break;
1037
1038 case 3: /*CALLX*/
1039 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
1040 switch (CALLX_N) {
1041 case 0: /*CALLX0*/
1042 {
1043 TCGv_i32 tmp = tcg_temp_new_i32();
1044 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1045 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1046 gen_jump(dc, tmp);
1047 tcg_temp_free(tmp);
1048 }
1049 break;
1050
1051 case 1: /*CALLX4w*/
1052 case 2: /*CALLX8w*/
1053 case 3: /*CALLX12w*/
1054 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1055 {
1056 TCGv_i32 tmp = tcg_temp_new_i32();
1057
1058 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1059 gen_callw(dc, CALLX_N, tmp);
1060 tcg_temp_free(tmp);
1061 }
1062 break;
1063 }
1064 break;
1065 }
1066 break;
1067
1068 case 1: /*MOVSPw*/
1069 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1070 gen_window_check2(dc, RRR_T, RRR_S);
1071 {
1072 TCGv_i32 pc = tcg_const_i32(dc->pc);
1073 gen_advance_ccount(dc);
1074 gen_helper_movsp(cpu_env, pc);
1075 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1076 tcg_temp_free(pc);
1077 }
1078 break;
1079
1080 case 2: /*SYNC*/
1081 switch (RRR_T) {
1082 case 0: /*ISYNC*/
1083 break;
1084
1085 case 1: /*RSYNC*/
1086 break;
1087
1088 case 2: /*ESYNC*/
1089 break;
1090
1091 case 3: /*DSYNC*/
1092 break;
1093
1094 case 8: /*EXCW*/
1095 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1096 break;
1097
1098 case 12: /*MEMW*/
1099 break;
1100
1101 case 13: /*EXTW*/
1102 break;
1103
1104 case 15: /*NOP*/
1105 break;
1106
1107 default: /*reserved*/
1108 RESERVED();
1109 break;
1110 }
1111 break;
1112
1113 case 3: /*RFEIx*/
1114 switch (RRR_T) {
1115 case 0: /*RFETx*/
1116 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1117 switch (RRR_S) {
1118 case 0: /*RFEx*/
1119 gen_check_privilege(dc);
1120 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1121 gen_helper_check_interrupts(cpu_env);
1122 gen_jump(dc, cpu_SR[EPC1]);
1123 break;
1124
1125 case 1: /*RFUEx*/
1126 RESERVED();
1127 break;
1128
1129 case 2: /*RFDEx*/
1130 gen_check_privilege(dc);
1131 gen_jump(dc, cpu_SR[
1132 dc->config->ndepc ? DEPC : EPC1]);
1133 break;
1134
1135 case 4: /*RFWOw*/
1136 case 5: /*RFWUw*/
1137 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1138 gen_check_privilege(dc);
1139 {
1140 TCGv_i32 tmp = tcg_const_i32(1);
1141
1142 tcg_gen_andi_i32(
1143 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1144 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1145
1146 if (RRR_S == 4) {
1147 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1148 cpu_SR[WINDOW_START], tmp);
1149 } else {
1150 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1151 cpu_SR[WINDOW_START], tmp);
1152 }
1153
1154 gen_helper_restore_owb(cpu_env);
1155 gen_helper_check_interrupts(cpu_env);
1156 gen_jump(dc, cpu_SR[EPC1]);
1157
1158 tcg_temp_free(tmp);
1159 }
1160 break;
1161
1162 default: /*reserved*/
1163 RESERVED();
1164 break;
1165 }
1166 break;
1167
1168 case 1: /*RFIx*/
1169 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1170 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1171 gen_check_privilege(dc);
1172 tcg_gen_mov_i32(cpu_SR[PS],
1173 cpu_SR[EPS2 + RRR_S - 2]);
1174 gen_helper_check_interrupts(cpu_env);
1175 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1176 } else {
1177 qemu_log("RFI %d is illegal\n", RRR_S);
1178 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1179 }
1180 break;
1181
1182 case 2: /*RFME*/
1183 TBD();
1184 break;
1185
1186 default: /*reserved*/
1187 RESERVED();
1188 break;
1189
1190 }
1191 break;
1192
1193 case 4: /*BREAKx*/
1194 HAS_OPTION(XTENSA_OPTION_DEBUG);
1195 if (dc->debug) {
1196 gen_debug_exception(dc, DEBUGCAUSE_BI);
1197 }
1198 break;
1199
1200 case 5: /*SYSCALLx*/
1201 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1202 switch (RRR_S) {
1203 case 0: /*SYSCALLx*/
1204 gen_exception_cause(dc, SYSCALL_CAUSE);
1205 break;
1206
1207 case 1: /*SIMCALL*/
1208 if (semihosting_enabled) {
1209 gen_check_privilege(dc);
1210 gen_helper_simcall(cpu_env);
1211 } else {
1212 qemu_log("SIMCALL but semihosting is disabled\n");
1213 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1214 }
1215 break;
1216
1217 default:
1218 RESERVED();
1219 break;
1220 }
1221 break;
1222
1223 case 6: /*RSILx*/
1224 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1225 gen_check_privilege(dc);
1226 gen_window_check1(dc, RRR_T);
1227 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1228 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1229 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1230 gen_helper_check_interrupts(cpu_env);
1231 gen_jumpi_check_loop_end(dc, 0);
1232 break;
1233
1234 case 7: /*WAITIx*/
1235 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1236 gen_check_privilege(dc);
1237 gen_waiti(dc, RRR_S);
1238 break;
1239
1240 case 8: /*ANY4p*/
1241 case 9: /*ALL4p*/
1242 case 10: /*ANY8p*/
1243 case 11: /*ALL8p*/
1244 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1245 {
1246 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1247 TCGv_i32 mask = tcg_const_i32(
1248 ((1 << shift) - 1) << RRR_S);
1249 TCGv_i32 tmp = tcg_temp_new_i32();
1250
1251 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1252 if (RRR_R & 1) { /*ALL*/
1253 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1254 } else { /*ANY*/
1255 tcg_gen_add_i32(tmp, tmp, mask);
1256 }
1257 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1258 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1259 tmp, RRR_T, 1);
1260 tcg_temp_free(mask);
1261 tcg_temp_free(tmp);
1262 }
1263 break;
1264
1265 default: /*reserved*/
1266 RESERVED();
1267 break;
1268
1269 }
1270 break;
1271
1272 case 1: /*AND*/
1273 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1274 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1275 break;
1276
1277 case 2: /*OR*/
1278 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1279 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1280 break;
1281
1282 case 3: /*XOR*/
1283 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1284 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1285 break;
1286
1287 case 4: /*ST1*/
1288 switch (RRR_R) {
1289 case 0: /*SSR*/
1290 gen_window_check1(dc, RRR_S);
1291 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1292 break;
1293
1294 case 1: /*SSL*/
1295 gen_window_check1(dc, RRR_S);
1296 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1297 break;
1298
1299 case 2: /*SSA8L*/
1300 gen_window_check1(dc, RRR_S);
1301 {
1302 TCGv_i32 tmp = tcg_temp_new_i32();
1303 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1304 gen_right_shift_sar(dc, tmp);
1305 tcg_temp_free(tmp);
1306 }
1307 break;
1308
1309 case 3: /*SSA8B*/
1310 gen_window_check1(dc, RRR_S);
1311 {
1312 TCGv_i32 tmp = tcg_temp_new_i32();
1313 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1314 gen_left_shift_sar(dc, tmp);
1315 tcg_temp_free(tmp);
1316 }
1317 break;
1318
1319 case 4: /*SSAI*/
1320 {
1321 TCGv_i32 tmp = tcg_const_i32(
1322 RRR_S | ((RRR_T & 1) << 4));
1323 gen_right_shift_sar(dc, tmp);
1324 tcg_temp_free(tmp);
1325 }
1326 break;
1327
1328 case 6: /*RER*/
1329 TBD();
1330 break;
1331
1332 case 7: /*WER*/
1333 TBD();
1334 break;
1335
1336 case 8: /*ROTWw*/
1337 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1338 gen_check_privilege(dc);
1339 {
1340 TCGv_i32 tmp = tcg_const_i32(
1341 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1342 gen_helper_rotw(cpu_env, tmp);
1343 tcg_temp_free(tmp);
1344 reset_used_window(dc);
1345 }
1346 break;
1347
1348 case 14: /*NSAu*/
1349 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1350 gen_window_check2(dc, RRR_S, RRR_T);
1351 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1352 break;
1353
1354 case 15: /*NSAUu*/
1355 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1356 gen_window_check2(dc, RRR_S, RRR_T);
1357 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1358 break;
1359
1360 default: /*reserved*/
1361 RESERVED();
1362 break;
1363 }
1364 break;
1365
1366 case 5: /*TLB*/
1367 HAS_OPTION_BITS(
1368 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1369 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1370 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1371 gen_check_privilege(dc);
1372 gen_window_check2(dc, RRR_S, RRR_T);
1373 {
1374 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1375
1376 switch (RRR_R & 7) {
1377 case 3: /*RITLB0*/ /*RDTLB0*/
1378 gen_helper_rtlb0(cpu_R[RRR_T],
1379 cpu_env, cpu_R[RRR_S], dtlb);
1380 break;
1381
1382 case 4: /*IITLB*/ /*IDTLB*/
1383 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1384 /* This could change memory mapping, so exit tb */
1385 gen_jumpi_check_loop_end(dc, -1);
1386 break;
1387
1388 case 5: /*PITLB*/ /*PDTLB*/
1389 tcg_gen_movi_i32(cpu_pc, dc->pc);
1390 gen_helper_ptlb(cpu_R[RRR_T],
1391 cpu_env, cpu_R[RRR_S], dtlb);
1392 break;
1393
1394 case 6: /*WITLB*/ /*WDTLB*/
1395 gen_helper_wtlb(
1396 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1397 /* This could change memory mapping, so exit tb */
1398 gen_jumpi_check_loop_end(dc, -1);
1399 break;
1400
1401 case 7: /*RITLB1*/ /*RDTLB1*/
1402 gen_helper_rtlb1(cpu_R[RRR_T],
1403 cpu_env, cpu_R[RRR_S], dtlb);
1404 break;
1405
1406 default:
1407 tcg_temp_free(dtlb);
1408 RESERVED();
1409 break;
1410 }
1411 tcg_temp_free(dtlb);
1412 }
1413 break;
1414
1415 case 6: /*RT0*/
1416 gen_window_check2(dc, RRR_R, RRR_T);
1417 switch (RRR_S) {
1418 case 0: /*NEG*/
1419 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1420 break;
1421
1422 case 1: /*ABS*/
1423 {
1424 TCGv_i32 zero = tcg_const_i32(0);
1425 TCGv_i32 neg = tcg_temp_new_i32();
1426
1427 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1428 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1429 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1430 tcg_temp_free(neg);
1431 tcg_temp_free(zero);
1432 }
1433 break;
1434
1435 default: /*reserved*/
1436 RESERVED();
1437 break;
1438 }
1439 break;
1440
1441 case 7: /*reserved*/
1442 RESERVED();
1443 break;
1444
1445 case 8: /*ADD*/
1446 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1447 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1448 break;
1449
1450 case 9: /*ADD**/
1451 case 10:
1452 case 11:
1453 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1454 {
1455 TCGv_i32 tmp = tcg_temp_new_i32();
1456 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1457 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1458 tcg_temp_free(tmp);
1459 }
1460 break;
1461
1462 case 12: /*SUB*/
1463 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1464 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1465 break;
1466
1467 case 13: /*SUB**/
1468 case 14:
1469 case 15:
1470 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1471 {
1472 TCGv_i32 tmp = tcg_temp_new_i32();
1473 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1474 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1475 tcg_temp_free(tmp);
1476 }
1477 break;
1478 }
1479 break;
1480
1481 case 1: /*RST1*/
1482 switch (OP2) {
1483 case 0: /*SLLI*/
1484 case 1:
1485 gen_window_check2(dc, RRR_R, RRR_S);
1486 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1487 32 - (RRR_T | ((OP2 & 1) << 4)));
1488 break;
1489
1490 case 2: /*SRAI*/
1491 case 3:
1492 gen_window_check2(dc, RRR_R, RRR_T);
1493 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1494 RRR_S | ((OP2 & 1) << 4));
1495 break;
1496
1497 case 4: /*SRLI*/
1498 gen_window_check2(dc, RRR_R, RRR_T);
1499 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1500 break;
1501
1502 case 6: /*XSR*/
1503 if (gen_check_sr(dc, RSR_SR, SR_X)) {
1504 TCGv_i32 tmp = tcg_temp_new_i32();
1505
1506 if (RSR_SR >= 64) {
1507 gen_check_privilege(dc);
1508 }
1509 gen_window_check1(dc, RRR_T);
1510 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1511 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1512 gen_wsr(dc, RSR_SR, tmp);
1513 tcg_temp_free(tmp);
1514 }
1515 break;
1516
1517 /*
1518 * Note: 64 bit ops are used here solely because SAR values
1519 * have range 0..63
1520 */
1521 #define gen_shift_reg(cmd, reg) do { \
1522 TCGv_i64 tmp = tcg_temp_new_i64(); \
1523 tcg_gen_extu_i32_i64(tmp, reg); \
1524 tcg_gen_##cmd##_i64(v, v, tmp); \
1525 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1526 tcg_temp_free_i64(v); \
1527 tcg_temp_free_i64(tmp); \
1528 } while (0)
1529
1530 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1531
1532 case 8: /*SRC*/
1533 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1534 {
1535 TCGv_i64 v = tcg_temp_new_i64();
1536 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1537 gen_shift(shr);
1538 }
1539 break;
1540
1541 case 9: /*SRL*/
1542 gen_window_check2(dc, RRR_R, RRR_T);
1543 if (dc->sar_5bit) {
1544 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1545 } else {
1546 TCGv_i64 v = tcg_temp_new_i64();
1547 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1548 gen_shift(shr);
1549 }
1550 break;
1551
1552 case 10: /*SLL*/
1553 gen_window_check2(dc, RRR_R, RRR_S);
1554 if (dc->sar_m32_5bit) {
1555 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1556 } else {
1557 TCGv_i64 v = tcg_temp_new_i64();
1558 TCGv_i32 s = tcg_const_i32(32);
1559 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1560 tcg_gen_andi_i32(s, s, 0x3f);
1561 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1562 gen_shift_reg(shl, s);
1563 tcg_temp_free(s);
1564 }
1565 break;
1566
1567 case 11: /*SRA*/
1568 gen_window_check2(dc, RRR_R, RRR_T);
1569 if (dc->sar_5bit) {
1570 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1571 } else {
1572 TCGv_i64 v = tcg_temp_new_i64();
1573 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1574 gen_shift(sar);
1575 }
1576 break;
1577 #undef gen_shift
1578 #undef gen_shift_reg
1579
1580 case 12: /*MUL16U*/
1581 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1582 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1583 {
1584 TCGv_i32 v1 = tcg_temp_new_i32();
1585 TCGv_i32 v2 = tcg_temp_new_i32();
1586 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1587 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1588 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1589 tcg_temp_free(v2);
1590 tcg_temp_free(v1);
1591 }
1592 break;
1593
1594 case 13: /*MUL16S*/
1595 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1596 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1597 {
1598 TCGv_i32 v1 = tcg_temp_new_i32();
1599 TCGv_i32 v2 = tcg_temp_new_i32();
1600 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1601 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1602 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1603 tcg_temp_free(v2);
1604 tcg_temp_free(v1);
1605 }
1606 break;
1607
1608 default: /*reserved*/
1609 RESERVED();
1610 break;
1611 }
1612 break;
1613
1614 case 2: /*RST2*/
1615 if (OP2 >= 8) {
1616 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1617 }
1618
1619 if (OP2 >= 12) {
1620 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1621 int label = gen_new_label();
1622 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1623 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1624 gen_set_label(label);
1625 }
1626
1627 switch (OP2) {
1628 #define BOOLEAN_LOGIC(fn, r, s, t) \
1629 do { \
1630 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1631 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1632 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1633 \
1634 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1635 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1636 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1637 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1638 tcg_temp_free(tmp1); \
1639 tcg_temp_free(tmp2); \
1640 } while (0)
1641
1642 case 0: /*ANDBp*/
1643 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1644 break;
1645
1646 case 1: /*ANDBCp*/
1647 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1648 break;
1649
1650 case 2: /*ORBp*/
1651 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1652 break;
1653
1654 case 3: /*ORBCp*/
1655 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1656 break;
1657
1658 case 4: /*XORBp*/
1659 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1660 break;
1661
1662 #undef BOOLEAN_LOGIC
1663
1664 case 8: /*MULLi*/
1665 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1666 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1667 break;
1668
1669 case 10: /*MULUHi*/
1670 case 11: /*MULSHi*/
1671 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1672 {
1673 TCGv lo = tcg_temp_new();
1674
1675 if (OP2 == 10) {
1676 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1677 cpu_R[RRR_S], cpu_R[RRR_T]);
1678 } else {
1679 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1680 cpu_R[RRR_S], cpu_R[RRR_T]);
1681 }
1682 tcg_temp_free(lo);
1683 }
1684 break;
1685
1686 case 12: /*QUOUi*/
1687 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1688 break;
1689
1690 case 13: /*QUOSi*/
1691 case 15: /*REMSi*/
1692 {
1693 int label1 = gen_new_label();
1694 int label2 = gen_new_label();
1695
1696 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1697 label1);
1698 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1699 label1);
1700 tcg_gen_movi_i32(cpu_R[RRR_R],
1701 OP2 == 13 ? 0x80000000 : 0);
1702 tcg_gen_br(label2);
1703 gen_set_label(label1);
1704 if (OP2 == 13) {
1705 tcg_gen_div_i32(cpu_R[RRR_R],
1706 cpu_R[RRR_S], cpu_R[RRR_T]);
1707 } else {
1708 tcg_gen_rem_i32(cpu_R[RRR_R],
1709 cpu_R[RRR_S], cpu_R[RRR_T]);
1710 }
1711 gen_set_label(label2);
1712 }
1713 break;
1714
1715 case 14: /*REMUi*/
1716 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1717 break;
1718
1719 default: /*reserved*/
1720 RESERVED();
1721 break;
1722 }
1723 break;
1724
1725 case 3: /*RST3*/
1726 switch (OP2) {
1727 case 0: /*RSR*/
1728 if (gen_check_sr(dc, RSR_SR, SR_R)) {
1729 if (RSR_SR >= 64) {
1730 gen_check_privilege(dc);
1731 }
1732 gen_window_check1(dc, RRR_T);
1733 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1734 }
1735 break;
1736
1737 case 1: /*WSR*/
1738 if (gen_check_sr(dc, RSR_SR, SR_W)) {
1739 if (RSR_SR >= 64) {
1740 gen_check_privilege(dc);
1741 }
1742 gen_window_check1(dc, RRR_T);
1743 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1744 }
1745 break;
1746
1747 case 2: /*SEXTu*/
1748 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1749 gen_window_check2(dc, RRR_R, RRR_S);
1750 {
1751 int shift = 24 - RRR_T;
1752
1753 if (shift == 24) {
1754 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1755 } else if (shift == 16) {
1756 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1757 } else {
1758 TCGv_i32 tmp = tcg_temp_new_i32();
1759 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1760 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1761 tcg_temp_free(tmp);
1762 }
1763 }
1764 break;
1765
1766 case 3: /*CLAMPSu*/
1767 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1768 gen_window_check2(dc, RRR_R, RRR_S);
1769 {
1770 TCGv_i32 tmp1 = tcg_temp_new_i32();
1771 TCGv_i32 tmp2 = tcg_temp_new_i32();
1772 TCGv_i32 zero = tcg_const_i32(0);
1773
1774 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1775 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1776 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1777
1778 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1779 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1780
1781 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1782 cpu_R[RRR_S], tmp1);
1783 tcg_temp_free(tmp1);
1784 tcg_temp_free(tmp2);
1785 tcg_temp_free(zero);
1786 }
1787 break;
1788
1789 case 4: /*MINu*/
1790 case 5: /*MAXu*/
1791 case 6: /*MINUu*/
1792 case 7: /*MAXUu*/
1793 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1794 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1795 {
1796 static const TCGCond cond[] = {
1797 TCG_COND_LE,
1798 TCG_COND_GE,
1799 TCG_COND_LEU,
1800 TCG_COND_GEU
1801 };
1802 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1803 cpu_R[RRR_S], cpu_R[RRR_T],
1804 cpu_R[RRR_S], cpu_R[RRR_T]);
1805 }
1806 break;
1807
1808 case 8: /*MOVEQZ*/
1809 case 9: /*MOVNEZ*/
1810 case 10: /*MOVLTZ*/
1811 case 11: /*MOVGEZ*/
1812 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1813 {
1814 static const TCGCond cond[] = {
1815 TCG_COND_EQ,
1816 TCG_COND_NE,
1817 TCG_COND_LT,
1818 TCG_COND_GE,
1819 };
1820 TCGv_i32 zero = tcg_const_i32(0);
1821
1822 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1823 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1824 tcg_temp_free(zero);
1825 }
1826 break;
1827
1828 case 12: /*MOVFp*/
1829 case 13: /*MOVTp*/
1830 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1831 gen_window_check2(dc, RRR_R, RRR_S);
1832 {
1833 TCGv_i32 zero = tcg_const_i32(0);
1834 TCGv_i32 tmp = tcg_temp_new_i32();
1835
1836 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1837 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1838 cpu_R[RRR_R], tmp, zero,
1839 cpu_R[RRR_S], cpu_R[RRR_R]);
1840
1841 tcg_temp_free(tmp);
1842 tcg_temp_free(zero);
1843 }
1844 break;
1845
1846 case 14: /*RUR*/
1847 gen_window_check1(dc, RRR_R);
1848 {
1849 int st = (RRR_S << 4) + RRR_T;
1850 if (uregnames[st].name) {
1851 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1852 } else {
1853 qemu_log("RUR %d not implemented, ", st);
1854 TBD();
1855 }
1856 }
1857 break;
1858
1859 case 15: /*WUR*/
1860 gen_window_check1(dc, RRR_T);
1861 if (uregnames[RSR_SR].name) {
1862 gen_wur(RSR_SR, cpu_R[RRR_T]);
1863 } else {
1864 qemu_log("WUR %d not implemented, ", RSR_SR);
1865 TBD();
1866 }
1867 break;
1868
1869 }
1870 break;
1871
1872 case 4: /*EXTUI*/
1873 case 5:
1874 gen_window_check2(dc, RRR_R, RRR_T);
1875 {
1876 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1877 int maskimm = (1 << (OP2 + 1)) - 1;
1878
1879 TCGv_i32 tmp = tcg_temp_new_i32();
1880 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1881 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1882 tcg_temp_free(tmp);
1883 }
1884 break;
1885
1886 case 6: /*CUST0*/
1887 RESERVED();
1888 break;
1889
1890 case 7: /*CUST1*/
1891 RESERVED();
1892 break;
1893
1894 case 8: /*LSCXp*/
1895 switch (OP2) {
1896 case 0: /*LSXf*/
1897 case 1: /*LSXUf*/
1898 case 4: /*SSXf*/
1899 case 5: /*SSXUf*/
1900 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1901 gen_window_check2(dc, RRR_S, RRR_T);
1902 gen_check_cpenable(dc, 0);
1903 {
1904 TCGv_i32 addr = tcg_temp_new_i32();
1905 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1906 gen_load_store_alignment(dc, 2, addr, false);
1907 if (OP2 & 0x4) {
1908 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1909 } else {
1910 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1911 }
1912 if (OP2 & 0x1) {
1913 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1914 }
1915 tcg_temp_free(addr);
1916 }
1917 break;
1918
1919 default: /*reserved*/
1920 RESERVED();
1921 break;
1922 }
1923 break;
1924
1925 case 9: /*LSC4*/
1926 gen_window_check2(dc, RRR_S, RRR_T);
1927 switch (OP2) {
1928 case 0: /*L32E*/
1929 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1930 gen_check_privilege(dc);
1931 {
1932 TCGv_i32 addr = tcg_temp_new_i32();
1933 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1934 (0xffffffc0 | (RRR_R << 2)));
1935 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1936 tcg_temp_free(addr);
1937 }
1938 break;
1939
1940 case 4: /*S32E*/
1941 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1942 gen_check_privilege(dc);
1943 {
1944 TCGv_i32 addr = tcg_temp_new_i32();
1945 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1946 (0xffffffc0 | (RRR_R << 2)));
1947 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1948 tcg_temp_free(addr);
1949 }
1950 break;
1951
1952 default:
1953 RESERVED();
1954 break;
1955 }
1956 break;
1957
1958 case 10: /*FP0*/
1959 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1960 switch (OP2) {
1961 case 0: /*ADD.Sf*/
1962 gen_check_cpenable(dc, 0);
1963 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1964 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1965 break;
1966
1967 case 1: /*SUB.Sf*/
1968 gen_check_cpenable(dc, 0);
1969 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1970 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1971 break;
1972
1973 case 2: /*MUL.Sf*/
1974 gen_check_cpenable(dc, 0);
1975 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
1976 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1977 break;
1978
1979 case 4: /*MADD.Sf*/
1980 gen_check_cpenable(dc, 0);
1981 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
1982 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1983 break;
1984
1985 case 5: /*MSUB.Sf*/
1986 gen_check_cpenable(dc, 0);
1987 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
1988 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1989 break;
1990
1991 case 8: /*ROUND.Sf*/
1992 case 9: /*TRUNC.Sf*/
1993 case 10: /*FLOOR.Sf*/
1994 case 11: /*CEIL.Sf*/
1995 case 14: /*UTRUNC.Sf*/
1996 gen_window_check1(dc, RRR_R);
1997 gen_check_cpenable(dc, 0);
1998 {
1999 static const unsigned rounding_mode_const[] = {
2000 float_round_nearest_even,
2001 float_round_to_zero,
2002 float_round_down,
2003 float_round_up,
2004 [6] = float_round_to_zero,
2005 };
2006 TCGv_i32 rounding_mode = tcg_const_i32(
2007 rounding_mode_const[OP2 & 7]);
2008 TCGv_i32 scale = tcg_const_i32(RRR_T);
2009
2010 if (OP2 == 14) {
2011 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2012 rounding_mode, scale);
2013 } else {
2014 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2015 rounding_mode, scale);
2016 }
2017
2018 tcg_temp_free(rounding_mode);
2019 tcg_temp_free(scale);
2020 }
2021 break;
2022
2023 case 12: /*FLOAT.Sf*/
2024 case 13: /*UFLOAT.Sf*/
2025 gen_window_check1(dc, RRR_S);
2026 gen_check_cpenable(dc, 0);
2027 {
2028 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2029
2030 if (OP2 == 13) {
2031 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2032 cpu_R[RRR_S], scale);
2033 } else {
2034 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2035 cpu_R[RRR_S], scale);
2036 }
2037 tcg_temp_free(scale);
2038 }
2039 break;
2040
2041 case 15: /*FP1OP*/
2042 switch (RRR_T) {
2043 case 0: /*MOV.Sf*/
2044 gen_check_cpenable(dc, 0);
2045 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2046 break;
2047
2048 case 1: /*ABS.Sf*/
2049 gen_check_cpenable(dc, 0);
2050 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2051 break;
2052
2053 case 4: /*RFRf*/
2054 gen_window_check1(dc, RRR_R);
2055 gen_check_cpenable(dc, 0);
2056 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2057 break;
2058
2059 case 5: /*WFRf*/
2060 gen_window_check1(dc, RRR_S);
2061 gen_check_cpenable(dc, 0);
2062 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2063 break;
2064
2065 case 6: /*NEG.Sf*/
2066 gen_check_cpenable(dc, 0);
2067 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2068 break;
2069
2070 default: /*reserved*/
2071 RESERVED();
2072 break;
2073 }
2074 break;
2075
2076 default: /*reserved*/
2077 RESERVED();
2078 break;
2079 }
2080 break;
2081
2082 case 11: /*FP1*/
2083 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2084
2085 #define gen_compare(rel, br, a, b) \
2086 do { \
2087 TCGv_i32 bit = tcg_const_i32(1 << br); \
2088 \
2089 gen_check_cpenable(dc, 0); \
2090 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2091 tcg_temp_free(bit); \
2092 } while (0)
2093
2094 switch (OP2) {
2095 case 1: /*UN.Sf*/
2096 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2097 break;
2098
2099 case 2: /*OEQ.Sf*/
2100 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2101 break;
2102
2103 case 3: /*UEQ.Sf*/
2104 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2105 break;
2106
2107 case 4: /*OLT.Sf*/
2108 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2109 break;
2110
2111 case 5: /*ULT.Sf*/
2112 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2113 break;
2114
2115 case 6: /*OLE.Sf*/
2116 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2117 break;
2118
2119 case 7: /*ULE.Sf*/
2120 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2121 break;
2122
2123 #undef gen_compare
2124
2125 case 8: /*MOVEQZ.Sf*/
2126 case 9: /*MOVNEZ.Sf*/
2127 case 10: /*MOVLTZ.Sf*/
2128 case 11: /*MOVGEZ.Sf*/
2129 gen_window_check1(dc, RRR_T);
2130 gen_check_cpenable(dc, 0);
2131 {
2132 static const TCGCond cond[] = {
2133 TCG_COND_EQ,
2134 TCG_COND_NE,
2135 TCG_COND_LT,
2136 TCG_COND_GE,
2137 };
2138 TCGv_i32 zero = tcg_const_i32(0);
2139
2140 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2141 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2142 tcg_temp_free(zero);
2143 }
2144 break;
2145
2146 case 12: /*MOVF.Sf*/
2147 case 13: /*MOVT.Sf*/
2148 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2149 gen_check_cpenable(dc, 0);
2150 {
2151 TCGv_i32 zero = tcg_const_i32(0);
2152 TCGv_i32 tmp = tcg_temp_new_i32();
2153
2154 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2155 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2156 cpu_FR[RRR_R], tmp, zero,
2157 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2158
2159 tcg_temp_free(tmp);
2160 tcg_temp_free(zero);
2161 }
2162 break;
2163
2164 default: /*reserved*/
2165 RESERVED();
2166 break;
2167 }
2168 break;
2169
2170 default: /*reserved*/
2171 RESERVED();
2172 break;
2173 }
2174 break;
2175
2176 case 1: /*L32R*/
2177 gen_window_check1(dc, RRR_T);
2178 {
2179 TCGv_i32 tmp = tcg_const_i32(
2180 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2181 0 : ((dc->pc + 3) & ~3)) +
2182 (0xfffc0000 | (RI16_IMM16 << 2)));
2183
2184 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2185 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2186 }
2187 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2188 tcg_temp_free(tmp);
2189 }
2190 break;
2191
2192 case 2: /*LSAI*/
2193 #define gen_load_store(type, shift) do { \
2194 TCGv_i32 addr = tcg_temp_new_i32(); \
2195 gen_window_check2(dc, RRI8_S, RRI8_T); \
2196 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2197 if (shift) { \
2198 gen_load_store_alignment(dc, shift, addr, false); \
2199 } \
2200 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2201 tcg_temp_free(addr); \
2202 } while (0)
2203
2204 switch (RRI8_R) {
2205 case 0: /*L8UI*/
2206 gen_load_store(ld8u, 0);
2207 break;
2208
2209 case 1: /*L16UI*/
2210 gen_load_store(ld16u, 1);
2211 break;
2212
2213 case 2: /*L32I*/
2214 gen_load_store(ld32u, 2);
2215 break;
2216
2217 case 4: /*S8I*/
2218 gen_load_store(st8, 0);
2219 break;
2220
2221 case 5: /*S16I*/
2222 gen_load_store(st16, 1);
2223 break;
2224
2225 case 6: /*S32I*/
2226 gen_load_store(st32, 2);
2227 break;
2228
2229 case 7: /*CACHEc*/
2230 if (RRI8_T < 8) {
2231 HAS_OPTION(XTENSA_OPTION_DCACHE);
2232 }
2233
2234 switch (RRI8_T) {
2235 case 0: /*DPFRc*/
2236 break;
2237
2238 case 1: /*DPFWc*/
2239 break;
2240
2241 case 2: /*DPFROc*/
2242 break;
2243
2244 case 3: /*DPFWOc*/
2245 break;
2246
2247 case 4: /*DHWBc*/
2248 break;
2249
2250 case 5: /*DHWBIc*/
2251 break;
2252
2253 case 6: /*DHIc*/
2254 break;
2255
2256 case 7: /*DIIc*/
2257 break;
2258
2259 case 8: /*DCEc*/
2260 switch (OP1) {
2261 case 0: /*DPFLl*/
2262 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2263 break;
2264
2265 case 2: /*DHUl*/
2266 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2267 break;
2268
2269 case 3: /*DIUl*/
2270 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2271 break;
2272
2273 case 4: /*DIWBc*/
2274 HAS_OPTION(XTENSA_OPTION_DCACHE);
2275 break;
2276
2277 case 5: /*DIWBIc*/
2278 HAS_OPTION(XTENSA_OPTION_DCACHE);
2279 break;
2280
2281 default: /*reserved*/
2282 RESERVED();
2283 break;
2284
2285 }
2286 break;
2287
2288 case 12: /*IPFc*/
2289 HAS_OPTION(XTENSA_OPTION_ICACHE);
2290 break;
2291
2292 case 13: /*ICEc*/
2293 switch (OP1) {
2294 case 0: /*IPFLl*/
2295 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2296 break;
2297
2298 case 2: /*IHUl*/
2299 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2300 break;
2301
2302 case 3: /*IIUl*/
2303 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2304 break;
2305
2306 default: /*reserved*/
2307 RESERVED();
2308 break;
2309 }
2310 break;
2311
2312 case 14: /*IHIc*/
2313 HAS_OPTION(XTENSA_OPTION_ICACHE);
2314 break;
2315
2316 case 15: /*IIIc*/
2317 HAS_OPTION(XTENSA_OPTION_ICACHE);
2318 break;
2319
2320 default: /*reserved*/
2321 RESERVED();
2322 break;
2323 }
2324 break;
2325
2326 case 9: /*L16SI*/
2327 gen_load_store(ld16s, 1);
2328 break;
2329 #undef gen_load_store
2330
2331 case 10: /*MOVI*/
2332 gen_window_check1(dc, RRI8_T);
2333 tcg_gen_movi_i32(cpu_R[RRI8_T],
2334 RRI8_IMM8 | (RRI8_S << 8) |
2335 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2336 break;
2337
2338 #define gen_load_store_no_hw_align(type) do { \
2339 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2340 gen_window_check2(dc, RRI8_S, RRI8_T); \
2341 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2342 gen_load_store_alignment(dc, 2, addr, true); \
2343 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2344 tcg_temp_free(addr); \
2345 } while (0)
2346
2347 case 11: /*L32AIy*/
2348 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2349 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2350 break;
2351
2352 case 12: /*ADDI*/
2353 gen_window_check2(dc, RRI8_S, RRI8_T);
2354 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2355 break;
2356
2357 case 13: /*ADDMI*/
2358 gen_window_check2(dc, RRI8_S, RRI8_T);
2359 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2360 break;
2361
2362 case 14: /*S32C1Iy*/
2363 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2364 gen_window_check2(dc, RRI8_S, RRI8_T);
2365 {
2366 int label = gen_new_label();
2367 TCGv_i32 tmp = tcg_temp_local_new_i32();
2368 TCGv_i32 addr = tcg_temp_local_new_i32();
2369 TCGv_i32 tpc;
2370
2371 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2372 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2373 gen_load_store_alignment(dc, 2, addr, true);
2374
2375 gen_advance_ccount(dc);
2376 tpc = tcg_const_i32(dc->pc);
2377 gen_helper_check_atomctl(cpu_env, tpc, addr);
2378 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2379 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2380 cpu_SR[SCOMPARE1], label);
2381
2382 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2383
2384 gen_set_label(label);
2385 tcg_temp_free(tpc);
2386 tcg_temp_free(addr);
2387 tcg_temp_free(tmp);
2388 }
2389 break;
2390
2391 case 15: /*S32RIy*/
2392 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2393 gen_load_store_no_hw_align(st32); /*TODO release?*/
2394 break;
2395 #undef gen_load_store_no_hw_align
2396
2397 default: /*reserved*/
2398 RESERVED();
2399 break;
2400 }
2401 break;
2402
2403 case 3: /*LSCIp*/
2404 switch (RRI8_R) {
2405 case 0: /*LSIf*/
2406 case 4: /*SSIf*/
2407 case 8: /*LSIUf*/
2408 case 12: /*SSIUf*/
2409 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2410 gen_window_check1(dc, RRI8_S);
2411 gen_check_cpenable(dc, 0);
2412 {
2413 TCGv_i32 addr = tcg_temp_new_i32();
2414 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2415 gen_load_store_alignment(dc, 2, addr, false);
2416 if (RRI8_R & 0x4) {
2417 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2418 } else {
2419 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2420 }
2421 if (RRI8_R & 0x8) {
2422 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2423 }
2424 tcg_temp_free(addr);
2425 }
2426 break;
2427
2428 default: /*reserved*/
2429 RESERVED();
2430 break;
2431 }
2432 break;
2433
2434 case 4: /*MAC16d*/
2435 HAS_OPTION(XTENSA_OPTION_MAC16);
2436 {
2437 enum {
2438 MAC16_UMUL = 0x0,
2439 MAC16_MUL = 0x4,
2440 MAC16_MULA = 0x8,
2441 MAC16_MULS = 0xc,
2442 MAC16_NONE = 0xf,
2443 } op = OP1 & 0xc;
2444 bool is_m1_sr = (OP2 & 0x3) == 2;
2445 bool is_m2_sr = (OP2 & 0xc) == 0;
2446 uint32_t ld_offset = 0;
2447
2448 if (OP2 > 9) {
2449 RESERVED();
2450 }
2451
2452 switch (OP2 & 2) {
2453 case 0: /*MACI?/MACC?*/
2454 is_m1_sr = true;
2455 ld_offset = (OP2 & 1) ? -4 : 4;
2456
2457 if (OP2 >= 8) { /*MACI/MACC*/
2458 if (OP1 == 0) { /*LDINC/LDDEC*/
2459 op = MAC16_NONE;
2460 } else {
2461 RESERVED();
2462 }
2463 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2464 RESERVED();
2465 }
2466 break;
2467
2468 case 2: /*MACD?/MACA?*/
2469 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2470 RESERVED();
2471 }
2472 break;
2473 }
2474
2475 if (op != MAC16_NONE) {
2476 if (!is_m1_sr) {
2477 gen_window_check1(dc, RRR_S);
2478 }
2479 if (!is_m2_sr) {
2480 gen_window_check1(dc, RRR_T);
2481 }
2482 }
2483
2484 {
2485 TCGv_i32 vaddr = tcg_temp_new_i32();
2486 TCGv_i32 mem32 = tcg_temp_new_i32();
2487
2488 if (ld_offset) {
2489 gen_window_check1(dc, RRR_S);
2490 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2491 gen_load_store_alignment(dc, 2, vaddr, false);
2492 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2493 }
2494 if (op != MAC16_NONE) {
2495 TCGv_i32 m1 = gen_mac16_m(
2496 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2497 OP1 & 1, op == MAC16_UMUL);
2498 TCGv_i32 m2 = gen_mac16_m(
2499 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2500 OP1 & 2, op == MAC16_UMUL);
2501
2502 if (op == MAC16_MUL || op == MAC16_UMUL) {
2503 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2504 if (op == MAC16_UMUL) {
2505 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2506 } else {
2507 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2508 }
2509 } else {
2510 TCGv_i32 lo = tcg_temp_new_i32();
2511 TCGv_i32 hi = tcg_temp_new_i32();
2512
2513 tcg_gen_mul_i32(lo, m1, m2);
2514 tcg_gen_sari_i32(hi, lo, 31);
2515 if (op == MAC16_MULA) {
2516 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2517 cpu_SR[ACCLO], cpu_SR[ACCHI],
2518 lo, hi);
2519 } else {
2520 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2521 cpu_SR[ACCLO], cpu_SR[ACCHI],
2522 lo, hi);
2523 }
2524 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2525
2526 tcg_temp_free_i32(lo);
2527 tcg_temp_free_i32(hi);
2528 }
2529 tcg_temp_free(m1);
2530 tcg_temp_free(m2);
2531 }
2532 if (ld_offset) {
2533 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2534 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2535 }
2536 tcg_temp_free(vaddr);
2537 tcg_temp_free(mem32);
2538 }
2539 }
2540 break;
2541
2542 case 5: /*CALLN*/
2543 switch (CALL_N) {
2544 case 0: /*CALL0*/
2545 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2546 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2547 break;
2548
2549 case 1: /*CALL4w*/
2550 case 2: /*CALL8w*/
2551 case 3: /*CALL12w*/
2552 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2553 gen_window_check1(dc, CALL_N << 2);
2554 gen_callwi(dc, CALL_N,
2555 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2556 break;
2557 }
2558 break;
2559
2560 case 6: /*SI*/
2561 switch (CALL_N) {
2562 case 0: /*J*/
2563 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2564 break;
2565
2566 case 1: /*BZ*/
2567 gen_window_check1(dc, BRI12_S);
2568 {
2569 static const TCGCond cond[] = {
2570 TCG_COND_EQ, /*BEQZ*/
2571 TCG_COND_NE, /*BNEZ*/
2572 TCG_COND_LT, /*BLTZ*/
2573 TCG_COND_GE, /*BGEZ*/
2574 };
2575
2576 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2577 4 + BRI12_IMM12_SE);
2578 }
2579 break;
2580
2581 case 2: /*BI0*/
2582 gen_window_check1(dc, BRI8_S);
2583 {
2584 static const TCGCond cond[] = {
2585 TCG_COND_EQ, /*BEQI*/
2586 TCG_COND_NE, /*BNEI*/
2587 TCG_COND_LT, /*BLTI*/
2588 TCG_COND_GE, /*BGEI*/
2589 };
2590
2591 gen_brcondi(dc, cond[BRI8_M & 3],
2592 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2593 }
2594 break;
2595
2596 case 3: /*BI1*/
2597 switch (BRI8_M) {
2598 case 0: /*ENTRYw*/
2599 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2600 {
2601 TCGv_i32 pc = tcg_const_i32(dc->pc);
2602 TCGv_i32 s = tcg_const_i32(BRI12_S);
2603 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2604 gen_advance_ccount(dc);
2605 gen_helper_entry(cpu_env, pc, s, imm);
2606 tcg_temp_free(imm);
2607 tcg_temp_free(s);
2608 tcg_temp_free(pc);
2609 reset_used_window(dc);
2610 }
2611 break;
2612
2613 case 1: /*B1*/
2614 switch (BRI8_R) {
2615 case 0: /*BFp*/
2616 case 1: /*BTp*/
2617 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2618 {
2619 TCGv_i32 tmp = tcg_temp_new_i32();
2620 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2621 gen_brcondi(dc,
2622 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2623 tmp, 0, 4 + RRI8_IMM8_SE);
2624 tcg_temp_free(tmp);
2625 }
2626 break;
2627
2628 case 8: /*LOOP*/
2629 case 9: /*LOOPNEZ*/
2630 case 10: /*LOOPGTZ*/
2631 HAS_OPTION(XTENSA_OPTION_LOOP);
2632 gen_window_check1(dc, RRI8_S);
2633 {
2634 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2635 TCGv_i32 tmp = tcg_const_i32(lend);
2636
2637 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2638 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2639 gen_helper_wsr_lend(cpu_env, tmp);
2640 tcg_temp_free(tmp);
2641
2642 if (BRI8_R > 8) {
2643 int label = gen_new_label();
2644 tcg_gen_brcondi_i32(
2645 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2646 cpu_R[RRI8_S], 0, label);
2647 gen_jumpi(dc, lend, 1);
2648 gen_set_label(label);
2649 }
2650
2651 gen_jumpi(dc, dc->next_pc, 0);
2652 }
2653 break;
2654
2655 default: /*reserved*/
2656 RESERVED();
2657 break;
2658
2659 }
2660 break;
2661
2662 case 2: /*BLTUI*/
2663 case 3: /*BGEUI*/
2664 gen_window_check1(dc, BRI8_S);
2665 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2666 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2667 break;
2668 }
2669 break;
2670
2671 }
2672 break;
2673
2674 case 7: /*B*/
2675 {
2676 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2677
2678 switch (RRI8_R & 7) {
2679 case 0: /*BNONE*/ /*BANY*/
2680 gen_window_check2(dc, RRI8_S, RRI8_T);
2681 {
2682 TCGv_i32 tmp = tcg_temp_new_i32();
2683 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2684 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2685 tcg_temp_free(tmp);
2686 }
2687 break;
2688
2689 case 1: /*BEQ*/ /*BNE*/
2690 case 2: /*BLT*/ /*BGE*/
2691 case 3: /*BLTU*/ /*BGEU*/
2692 gen_window_check2(dc, RRI8_S, RRI8_T);
2693 {
2694 static const TCGCond cond[] = {
2695 [1] = TCG_COND_EQ,
2696 [2] = TCG_COND_LT,
2697 [3] = TCG_COND_LTU,
2698 [9] = TCG_COND_NE,
2699 [10] = TCG_COND_GE,
2700 [11] = TCG_COND_GEU,
2701 };
2702 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2703 4 + RRI8_IMM8_SE);
2704 }
2705 break;
2706
2707 case 4: /*BALL*/ /*BNALL*/
2708 gen_window_check2(dc, RRI8_S, RRI8_T);
2709 {
2710 TCGv_i32 tmp = tcg_temp_new_i32();
2711 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2712 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2713 4 + RRI8_IMM8_SE);
2714 tcg_temp_free(tmp);
2715 }
2716 break;
2717
2718 case 5: /*BBC*/ /*BBS*/
2719 gen_window_check2(dc, RRI8_S, RRI8_T);
2720 {
2721 #ifdef TARGET_WORDS_BIGENDIAN
2722 TCGv_i32 bit = tcg_const_i32(0x80000000);
2723 #else
2724 TCGv_i32 bit = tcg_const_i32(0x00000001);
2725 #endif
2726 TCGv_i32 tmp = tcg_temp_new_i32();
2727 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2728 #ifdef TARGET_WORDS_BIGENDIAN
2729 tcg_gen_shr_i32(bit, bit, tmp);
2730 #else
2731 tcg_gen_shl_i32(bit, bit, tmp);
2732 #endif
2733 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2734 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2735 tcg_temp_free(tmp);
2736 tcg_temp_free(bit);
2737 }
2738 break;
2739
2740 case 6: /*BBCI*/ /*BBSI*/
2741 case 7:
2742 gen_window_check1(dc, RRI8_S);
2743 {
2744 TCGv_i32 tmp = tcg_temp_new_i32();
2745 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2746 #ifdef TARGET_WORDS_BIGENDIAN
2747 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2748 #else
2749 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2750 #endif
2751 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2752 tcg_temp_free(tmp);
2753 }
2754 break;
2755
2756 }
2757 }
2758 break;
2759
2760 #define gen_narrow_load_store(type) do { \
2761 TCGv_i32 addr = tcg_temp_new_i32(); \
2762 gen_window_check2(dc, RRRN_S, RRRN_T); \
2763 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2764 gen_load_store_alignment(dc, 2, addr, false); \
2765 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2766 tcg_temp_free(addr); \
2767 } while (0)
2768
2769 case 8: /*L32I.Nn*/
2770 gen_narrow_load_store(ld32u);
2771 break;
2772
2773 case 9: /*S32I.Nn*/
2774 gen_narrow_load_store(st32);
2775 break;
2776 #undef gen_narrow_load_store
2777
2778 case 10: /*ADD.Nn*/
2779 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
2780 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2781 break;
2782
2783 case 11: /*ADDI.Nn*/
2784 gen_window_check2(dc, RRRN_R, RRRN_S);
2785 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
2786 break;
2787
2788 case 12: /*ST2n*/
2789 gen_window_check1(dc, RRRN_S);
2790 if (RRRN_T < 8) { /*MOVI.Nn*/
2791 tcg_gen_movi_i32(cpu_R[RRRN_S],
2792 RRRN_R | (RRRN_T << 4) |
2793 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2794 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2795 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2796
2797 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2798 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2799 }
2800 break;
2801
2802 case 13: /*ST3n*/
2803 switch (RRRN_R) {
2804 case 0: /*MOV.Nn*/
2805 gen_window_check2(dc, RRRN_S, RRRN_T);
2806 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2807 break;
2808
2809 case 15: /*S3*/
2810 switch (RRRN_T) {
2811 case 0: /*RET.Nn*/
2812 gen_jump(dc, cpu_R[0]);
2813 break;
2814
2815 case 1: /*RETW.Nn*/
2816 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2817 {
2818 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2819 gen_advance_ccount(dc);
2820 gen_helper_retw(tmp, cpu_env, tmp);
2821 gen_jump(dc, tmp);
2822 tcg_temp_free(tmp);
2823 }
2824 break;
2825
2826 case 2: /*BREAK.Nn*/
2827 HAS_OPTION(XTENSA_OPTION_DEBUG);
2828 if (dc->debug) {
2829 gen_debug_exception(dc, DEBUGCAUSE_BN);
2830 }
2831 break;
2832
2833 case 3: /*NOP.Nn*/
2834 break;
2835
2836 case 6: /*ILL.Nn*/
2837 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2838 break;
2839
2840 default: /*reserved*/
2841 RESERVED();
2842 break;
2843 }
2844 break;
2845
2846 default: /*reserved*/
2847 RESERVED();
2848 break;
2849 }
2850 break;
2851
2852 default: /*reserved*/
2853 RESERVED();
2854 break;
2855 }
2856
2857 if (dc->is_jmp == DISAS_NEXT) {
2858 gen_check_loop_end(dc, 0);
2859 }
2860 dc->pc = dc->next_pc;
2861
2862 return;
2863
2864 invalid_opcode:
2865 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2866 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2867 #undef HAS_OPTION
2868 }
2869
2870 static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
2871 {
2872 CPUBreakpoint *bp;
2873
2874 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2875 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2876 if (bp->pc == dc->pc) {
2877 tcg_gen_movi_i32(cpu_pc, dc->pc);
2878 gen_exception(dc, EXCP_DEBUG);
2879 dc->is_jmp = DISAS_UPDATE;
2880 }
2881 }
2882 }
2883 }
2884
2885 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
2886 {
2887 unsigned i;
2888
2889 for (i = 0; i < dc->config->nibreak; ++i) {
2890 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2891 env->sregs[IBREAKA + i] == dc->pc) {
2892 gen_debug_exception(dc, DEBUGCAUSE_IB);
2893 break;
2894 }
2895 }
2896 }
2897
2898 static inline
2899 void gen_intermediate_code_internal(XtensaCPU *cpu,
2900 TranslationBlock *tb, bool search_pc)
2901 {
2902 CPUState *cs = CPU(cpu);
2903 CPUXtensaState *env = &cpu->env;
2904 DisasContext dc;
2905 int insn_count = 0;
2906 int j, lj = -1;
2907 uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
2908 int max_insns = tb->cflags & CF_COUNT_MASK;
2909 uint32_t pc_start = tb->pc;
2910 uint32_t next_page_start =
2911 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2912
2913 if (max_insns == 0) {
2914 max_insns = CF_COUNT_MASK;
2915 }
2916
2917 dc.config = env->config;
2918 dc.singlestep_enabled = cs->singlestep_enabled;
2919 dc.tb = tb;
2920 dc.pc = pc_start;
2921 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2922 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
2923 dc.lbeg = env->sregs[LBEG];
2924 dc.lend = env->sregs[LEND];
2925 dc.is_jmp = DISAS_NEXT;
2926 dc.ccount_delta = 0;
2927 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
2928 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
2929 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
2930 XTENSA_TBFLAG_CPENABLE_SHIFT;
2931
2932 init_litbase(&dc);
2933 init_sar_tracker(&dc);
2934 reset_used_window(&dc);
2935 if (dc.icount) {
2936 dc.next_icount = tcg_temp_local_new_i32();
2937 }
2938
2939 gen_tb_start();
2940
2941 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
2942 tcg_gen_movi_i32(cpu_pc, dc.pc);
2943 gen_exception(&dc, EXCP_DEBUG);
2944 }
2945
2946 do {
2947 check_breakpoint(env, &dc);
2948
2949 if (search_pc) {
2950 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
2951 if (lj < j) {
2952 lj++;
2953 while (lj < j) {
2954 tcg_ctx.gen_opc_instr_start[lj++] = 0;
2955 }
2956 }
2957 tcg_ctx.gen_opc_pc[lj] = dc.pc;
2958 tcg_ctx.gen_opc_instr_start[lj] = 1;
2959 tcg_ctx.gen_opc_icount[lj] = insn_count;
2960 }
2961
2962 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
2963 tcg_gen_debug_insn_start(dc.pc);
2964 }
2965
2966 ++dc.ccount_delta;
2967
2968 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2969 gen_io_start();
2970 }
2971
2972 if (dc.icount) {
2973 int label = gen_new_label();
2974
2975 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
2976 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
2977 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
2978 if (dc.debug) {
2979 gen_debug_exception(&dc, DEBUGCAUSE_IC);
2980 }
2981 gen_set_label(label);
2982 }
2983
2984 if (dc.debug) {
2985 gen_ibreak_check(env, &dc);
2986 }
2987
2988 disas_xtensa_insn(env, &dc);
2989 ++insn_count;
2990 if (dc.icount) {
2991 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
2992 }
2993 if (cs->singlestep_enabled) {
2994 tcg_gen_movi_i32(cpu_pc, dc.pc);
2995 gen_exception(&dc, EXCP_DEBUG);
2996 break;
2997 }
2998 } while (dc.is_jmp == DISAS_NEXT &&
2999 insn_count < max_insns &&
3000 dc.pc < next_page_start &&
3001 tcg_ctx.gen_opc_ptr < gen_opc_end);
3002
3003 reset_litbase(&dc);
3004 reset_sar_tracker(&dc);
3005 if (dc.icount) {
3006 tcg_temp_free(dc.next_icount);
3007 }
3008
3009 if (tb->cflags & CF_LAST_IO) {
3010 gen_io_end();
3011 }
3012
3013 if (dc.is_jmp == DISAS_NEXT) {
3014 gen_jumpi(&dc, dc.pc, 0);
3015 }
3016 gen_tb_end(tb, insn_count);
3017 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3018
3019 #ifdef DEBUG_DISAS
3020 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3021 qemu_log("----------------\n");
3022 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3023 log_target_disas(env, pc_start, dc.pc - pc_start, 0);
3024 qemu_log("\n");
3025 }
3026 #endif
3027 if (search_pc) {
3028 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3029 memset(tcg_ctx.gen_opc_instr_start + lj + 1, 0,
3030 (j - lj) * sizeof(tcg_ctx.gen_opc_instr_start[0]));
3031 } else {
3032 tb->size = dc.pc - pc_start;
3033 tb->icount = insn_count;
3034 }
3035 }
3036
3037 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3038 {
3039 gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, false);
3040 }
3041
3042 void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
3043 {
3044 gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, true);
3045 }
3046
3047 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3048 fprintf_function cpu_fprintf, int flags)
3049 {
3050 XtensaCPU *cpu = XTENSA_CPU(cs);
3051 CPUXtensaState *env = &cpu->env;
3052 int i, j;
3053
3054 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3055
3056 for (i = j = 0; i < 256; ++i) {
3057 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3058 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3059 (j++ % 4) == 3 ? '\n' : ' ');
3060 }
3061 }
3062
3063 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3064
3065 for (i = j = 0; i < 256; ++i) {
3066 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3067 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
3068 (j++ % 4) == 3 ? '\n' : ' ');
3069 }
3070 }
3071
3072 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3073
3074 for (i = 0; i < 16; ++i) {
3075 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
3076 (i % 4) == 3 ? '\n' : ' ');
3077 }
3078
3079 cpu_fprintf(f, "\n");
3080
3081 for (i = 0; i < env->config->nareg; ++i) {
3082 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3083 (i % 4) == 3 ? '\n' : ' ');
3084 }
3085
3086 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3087 cpu_fprintf(f, "\n");
3088
3089 for (i = 0; i < 16; ++i) {
3090 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3091 float32_val(env->fregs[i]),
3092 *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
3093 }
3094 }
3095 }
3096
3097 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
3098 {
3099 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3100 }
QEmu