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linux-user: rlimit conversion between host and target.
[qemu.git] / linux-user / main.c
blob99a7cde559ca03132ed93d2e1cca9e3141e49c62
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "cache-utils.h"
32 /* For tb_lock */
33 #include "exec-all.h"
34
35 #include "qemu-timer.h"
36 #include "envlist.h"
37
38 #define DEBUG_LOGFILE "/tmp/qemu.log"
39
40 char *exec_path;
41
42 int singlestep;
43 unsigned long mmap_min_addr;
44 #if defined(CONFIG_USE_GUEST_BASE)
45 unsigned long guest_base;
46 int have_guest_base;
47 #endif
48
49 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
50 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
51
52 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
53 we allocate a bigger stack. Need a better solution, for example
54 by remapping the process stack directly at the right place */
55 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
56
57 void gemu_log(const char *fmt, ...)
58 {
59 va_list ap;
60
61 va_start(ap, fmt);
62 vfprintf(stderr, fmt, ap);
63 va_end(ap);
64 }
65
66 #if defined(TARGET_I386)
67 int cpu_get_pic_interrupt(CPUState *env)
68 {
69 return -1;
70 }
71 #endif
72
73 /* timers for rdtsc */
74
75 #if 0
76
77 static uint64_t emu_time;
78
79 int64_t cpu_get_real_ticks(void)
80 {
81 return emu_time++;
82 }
83
84 #endif
85
86 #if defined(CONFIG_USE_NPTL)
87 /***********************************************************/
88 /* Helper routines for implementing atomic operations. */
89
90 /* To implement exclusive operations we force all cpus to syncronise.
91 We don't require a full sync, only that no cpus are executing guest code.
92 The alternative is to map target atomic ops onto host equivalents,
93 which requires quite a lot of per host/target work. */
94 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
95 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
96 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
97 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
98 static int pending_cpus;
99
100 /* Make sure everything is in a consistent state for calling fork(). */
101 void fork_start(void)
102 {
103 pthread_mutex_lock(&tb_lock);
104 pthread_mutex_lock(&exclusive_lock);
105 mmap_fork_start();
106 }
107
108 void fork_end(int child)
109 {
110 mmap_fork_end(child);
111 if (child) {
112 /* Child processes created by fork() only have a single thread.
113 Discard information about the parent threads. */
114 first_cpu = thread_env;
115 thread_env->next_cpu = NULL;
116 pending_cpus = 0;
117 pthread_mutex_init(&exclusive_lock, NULL);
118 pthread_mutex_init(&cpu_list_mutex, NULL);
119 pthread_cond_init(&exclusive_cond, NULL);
120 pthread_cond_init(&exclusive_resume, NULL);
121 pthread_mutex_init(&tb_lock, NULL);
122 gdbserver_fork(thread_env);
123 } else {
124 pthread_mutex_unlock(&exclusive_lock);
125 pthread_mutex_unlock(&tb_lock);
126 }
127 }
128
129 /* Wait for pending exclusive operations to complete. The exclusive lock
130 must be held. */
131 static inline void exclusive_idle(void)
132 {
133 while (pending_cpus) {
134 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
135 }
136 }
137
138 /* Start an exclusive operation.
139 Must only be called from outside cpu_arm_exec. */
140 static inline void start_exclusive(void)
141 {
142 CPUState *other;
143 pthread_mutex_lock(&exclusive_lock);
144 exclusive_idle();
145
146 pending_cpus = 1;
147 /* Make all other cpus stop executing. */
148 for (other = first_cpu; other; other = other->next_cpu) {
149 if (other->running) {
150 pending_cpus++;
151 cpu_exit(other);
152 }
153 }
154 if (pending_cpus > 1) {
155 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
156 }
157 }
158
159 /* Finish an exclusive operation. */
160 static inline void end_exclusive(void)
161 {
162 pending_cpus = 0;
163 pthread_cond_broadcast(&exclusive_resume);
164 pthread_mutex_unlock(&exclusive_lock);
165 }
166
167 /* Wait for exclusive ops to finish, and begin cpu execution. */
168 static inline void cpu_exec_start(CPUState *env)
169 {
170 pthread_mutex_lock(&exclusive_lock);
171 exclusive_idle();
172 env->running = 1;
173 pthread_mutex_unlock(&exclusive_lock);
174 }
175
176 /* Mark cpu as not executing, and release pending exclusive ops. */
177 static inline void cpu_exec_end(CPUState *env)
178 {
179 pthread_mutex_lock(&exclusive_lock);
180 env->running = 0;
181 if (pending_cpus > 1) {
182 pending_cpus--;
183 if (pending_cpus == 1) {
184 pthread_cond_signal(&exclusive_cond);
185 }
186 }
187 exclusive_idle();
188 pthread_mutex_unlock(&exclusive_lock);
189 }
190
191 void cpu_list_lock(void)
192 {
193 pthread_mutex_lock(&cpu_list_mutex);
194 }
195
196 void cpu_list_unlock(void)
197 {
198 pthread_mutex_unlock(&cpu_list_mutex);
199 }
200 #else /* if !CONFIG_USE_NPTL */
201 /* These are no-ops because we are not threadsafe. */
202 static inline void cpu_exec_start(CPUState *env)
203 {
204 }
205
206 static inline void cpu_exec_end(CPUState *env)
207 {
208 }
209
210 static inline void start_exclusive(void)
211 {
212 }
213
214 static inline void end_exclusive(void)
215 {
216 }
217
218 void fork_start(void)
219 {
220 }
221
222 void fork_end(int child)
223 {
224 if (child) {
225 gdbserver_fork(thread_env);
226 }
227 }
228
229 void cpu_list_lock(void)
230 {
231 }
232
233 void cpu_list_unlock(void)
234 {
235 }
236 #endif
237
238
239 #ifdef TARGET_I386
240 /***********************************************************/
241 /* CPUX86 core interface */
242
243 void cpu_smm_update(CPUState *env)
244 {
245 }
246
247 uint64_t cpu_get_tsc(CPUX86State *env)
248 {
249 return cpu_get_real_ticks();
250 }
251
252 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
253 int flags)
254 {
255 unsigned int e1, e2;
256 uint32_t *p;
257 e1 = (addr << 16) | (limit & 0xffff);
258 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
259 e2 |= flags;
260 p = ptr;
261 p[0] = tswap32(e1);
262 p[1] = tswap32(e2);
263 }
264
265 static uint64_t *idt_table;
266 #ifdef TARGET_X86_64
267 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
268 uint64_t addr, unsigned int sel)
269 {
270 uint32_t *p, e1, e2;
271 e1 = (addr & 0xffff) | (sel << 16);
272 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
273 p = ptr;
274 p[0] = tswap32(e1);
275 p[1] = tswap32(e2);
276 p[2] = tswap32(addr >> 32);
277 p[3] = 0;
278 }
279 /* only dpl matters as we do only user space emulation */
280 static void set_idt(int n, unsigned int dpl)
281 {
282 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
283 }
284 #else
285 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
286 uint32_t addr, unsigned int sel)
287 {
288 uint32_t *p, e1, e2;
289 e1 = (addr & 0xffff) | (sel << 16);
290 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
291 p = ptr;
292 p[0] = tswap32(e1);
293 p[1] = tswap32(e2);
294 }
295
296 /* only dpl matters as we do only user space emulation */
297 static void set_idt(int n, unsigned int dpl)
298 {
299 set_gate(idt_table + n, 0, dpl, 0, 0);
300 }
301 #endif
302
303 void cpu_loop(CPUX86State *env)
304 {
305 int trapnr;
306 abi_ulong pc;
307 target_siginfo_t info;
308
309 for(;;) {
310 trapnr = cpu_x86_exec(env);
311 switch(trapnr) {
312 case 0x80:
313 /* linux syscall from int $0x80 */
314 env->regs[R_EAX] = do_syscall(env,
315 env->regs[R_EAX],
316 env->regs[R_EBX],
317 env->regs[R_ECX],
318 env->regs[R_EDX],
319 env->regs[R_ESI],
320 env->regs[R_EDI],
321 env->regs[R_EBP]);
322 break;
323 #ifndef TARGET_ABI32
324 case EXCP_SYSCALL:
325 /* linux syscall from syscall intruction */
326 env->regs[R_EAX] = do_syscall(env,
327 env->regs[R_EAX],
328 env->regs[R_EDI],
329 env->regs[R_ESI],
330 env->regs[R_EDX],
331 env->regs[10],
332 env->regs[8],
333 env->regs[9]);
334 env->eip = env->exception_next_eip;
335 break;
336 #endif
337 case EXCP0B_NOSEG:
338 case EXCP0C_STACK:
339 info.si_signo = SIGBUS;
340 info.si_errno = 0;
341 info.si_code = TARGET_SI_KERNEL;
342 info._sifields._sigfault._addr = 0;
343 queue_signal(env, info.si_signo, &info);
344 break;
345 case EXCP0D_GPF:
346 /* XXX: potential problem if ABI32 */
347 #ifndef TARGET_X86_64
348 if (env->eflags & VM_MASK) {
349 handle_vm86_fault(env);
350 } else
351 #endif
352 {
353 info.si_signo = SIGSEGV;
354 info.si_errno = 0;
355 info.si_code = TARGET_SI_KERNEL;
356 info._sifields._sigfault._addr = 0;
357 queue_signal(env, info.si_signo, &info);
358 }
359 break;
360 case EXCP0E_PAGE:
361 info.si_signo = SIGSEGV;
362 info.si_errno = 0;
363 if (!(env->error_code & 1))
364 info.si_code = TARGET_SEGV_MAPERR;
365 else
366 info.si_code = TARGET_SEGV_ACCERR;
367 info._sifields._sigfault._addr = env->cr[2];
368 queue_signal(env, info.si_signo, &info);
369 break;
370 case EXCP00_DIVZ:
371 #ifndef TARGET_X86_64
372 if (env->eflags & VM_MASK) {
373 handle_vm86_trap(env, trapnr);
374 } else
375 #endif
376 {
377 /* division by zero */
378 info.si_signo = SIGFPE;
379 info.si_errno = 0;
380 info.si_code = TARGET_FPE_INTDIV;
381 info._sifields._sigfault._addr = env->eip;
382 queue_signal(env, info.si_signo, &info);
383 }
384 break;
385 case EXCP01_DB:
386 case EXCP03_INT3:
387 #ifndef TARGET_X86_64
388 if (env->eflags & VM_MASK) {
389 handle_vm86_trap(env, trapnr);
390 } else
391 #endif
392 {
393 info.si_signo = SIGTRAP;
394 info.si_errno = 0;
395 if (trapnr == EXCP01_DB) {
396 info.si_code = TARGET_TRAP_BRKPT;
397 info._sifields._sigfault._addr = env->eip;
398 } else {
399 info.si_code = TARGET_SI_KERNEL;
400 info._sifields._sigfault._addr = 0;
401 }
402 queue_signal(env, info.si_signo, &info);
403 }
404 break;
405 case EXCP04_INTO:
406 case EXCP05_BOUND:
407 #ifndef TARGET_X86_64
408 if (env->eflags & VM_MASK) {
409 handle_vm86_trap(env, trapnr);
410 } else
411 #endif
412 {
413 info.si_signo = SIGSEGV;
414 info.si_errno = 0;
415 info.si_code = TARGET_SI_KERNEL;
416 info._sifields._sigfault._addr = 0;
417 queue_signal(env, info.si_signo, &info);
418 }
419 break;
420 case EXCP06_ILLOP:
421 info.si_signo = SIGILL;
422 info.si_errno = 0;
423 info.si_code = TARGET_ILL_ILLOPN;
424 info._sifields._sigfault._addr = env->eip;
425 queue_signal(env, info.si_signo, &info);
426 break;
427 case EXCP_INTERRUPT:
428 /* just indicate that signals should be handled asap */
429 break;
430 case EXCP_DEBUG:
431 {
432 int sig;
433
434 sig = gdb_handlesig (env, TARGET_SIGTRAP);
435 if (sig)
436 {
437 info.si_signo = sig;
438 info.si_errno = 0;
439 info.si_code = TARGET_TRAP_BRKPT;
440 queue_signal(env, info.si_signo, &info);
441 }
442 }
443 break;
444 default:
445 pc = env->segs[R_CS].base + env->eip;
446 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
447 (long)pc, trapnr);
448 abort();
449 }
450 process_pending_signals(env);
451 }
452 }
453 #endif
454
455 #ifdef TARGET_ARM
456
457 static void arm_cache_flush(abi_ulong start, abi_ulong last)
458 {
459 abi_ulong addr, last1;
460
461 if (last < start)
462 return;
463 addr = start;
464 for(;;) {
465 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
466 if (last1 > last)
467 last1 = last;
468 tb_invalidate_page_range(addr, last1 + 1);
469 if (last1 == last)
470 break;
471 addr = last1 + 1;
472 }
473 }
474
475 /* Handle a jump to the kernel code page. */
476 static int
477 do_kernel_trap(CPUARMState *env)
478 {
479 uint32_t addr;
480 uint32_t cpsr;
481 uint32_t val;
482
483 switch (env->regs[15]) {
484 case 0xffff0fa0: /* __kernel_memory_barrier */
485 /* ??? No-op. Will need to do better for SMP. */
486 break;
487 case 0xffff0fc0: /* __kernel_cmpxchg */
488 /* XXX: This only works between threads, not between processes.
489 It's probably possible to implement this with native host
490 operations. However things like ldrex/strex are much harder so
491 there's not much point trying. */
492 start_exclusive();
493 cpsr = cpsr_read(env);
494 addr = env->regs[2];
495 /* FIXME: This should SEGV if the access fails. */
496 if (get_user_u32(val, addr))
497 val = ~env->regs[0];
498 if (val == env->regs[0]) {
499 val = env->regs[1];
500 /* FIXME: Check for segfaults. */
501 put_user_u32(val, addr);
502 env->regs[0] = 0;
503 cpsr |= CPSR_C;
504 } else {
505 env->regs[0] = -1;
506 cpsr &= ~CPSR_C;
507 }
508 cpsr_write(env, cpsr, CPSR_C);
509 end_exclusive();
510 break;
511 case 0xffff0fe0: /* __kernel_get_tls */
512 env->regs[0] = env->cp15.c13_tls2;
513 break;
514 default:
515 return 1;
516 }
517 /* Jump back to the caller. */
518 addr = env->regs[14];
519 if (addr & 1) {
520 env->thumb = 1;
521 addr &= ~1;
522 }
523 env->regs[15] = addr;
524
525 return 0;
526 }
527
528 static int do_strex(CPUARMState *env)
529 {
530 uint32_t val;
531 int size;
532 int rc = 1;
533 int segv = 0;
534 uint32_t addr;
535 start_exclusive();
536 addr = env->exclusive_addr;
537 if (addr != env->exclusive_test) {
538 goto fail;
539 }
540 size = env->exclusive_info & 0xf;
541 switch (size) {
542 case 0:
543 segv = get_user_u8(val, addr);
544 break;
545 case 1:
546 segv = get_user_u16(val, addr);
547 break;
548 case 2:
549 case 3:
550 segv = get_user_u32(val, addr);
551 break;
552 default:
553 abort();
554 }
555 if (segv) {
556 env->cp15.c6_data = addr;
557 goto done;
558 }
559 if (val != env->exclusive_val) {
560 goto fail;
561 }
562 if (size == 3) {
563 segv = get_user_u32(val, addr + 4);
564 if (segv) {
565 env->cp15.c6_data = addr + 4;
566 goto done;
567 }
568 if (val != env->exclusive_high) {
569 goto fail;
570 }
571 }
572 val = env->regs[(env->exclusive_info >> 8) & 0xf];
573 switch (size) {
574 case 0:
575 segv = put_user_u8(val, addr);
576 break;
577 case 1:
578 segv = put_user_u16(val, addr);
579 break;
580 case 2:
581 case 3:
582 segv = put_user_u32(val, addr);
583 break;
584 }
585 if (segv) {
586 env->cp15.c6_data = addr;
587 goto done;
588 }
589 if (size == 3) {
590 val = env->regs[(env->exclusive_info >> 12) & 0xf];
591 segv = put_user_u32(val, addr);
592 if (segv) {
593 env->cp15.c6_data = addr + 4;
594 goto done;
595 }
596 }
597 rc = 0;
598 fail:
599 env->regs[15] += 4;
600 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
601 done:
602 end_exclusive();
603 return segv;
604 }
605
606 void cpu_loop(CPUARMState *env)
607 {
608 int trapnr;
609 unsigned int n, insn;
610 target_siginfo_t info;
611 uint32_t addr;
612
613 for(;;) {
614 cpu_exec_start(env);
615 trapnr = cpu_arm_exec(env);
616 cpu_exec_end(env);
617 switch(trapnr) {
618 case EXCP_UDEF:
619 {
620 TaskState *ts = env->opaque;
621 uint32_t opcode;
622 int rc;
623
624 /* we handle the FPU emulation here, as Linux */
625 /* we get the opcode */
626 /* FIXME - what to do if get_user() fails? */
627 get_user_u32(opcode, env->regs[15]);
628
629 rc = EmulateAll(opcode, &ts->fpa, env);
630 if (rc == 0) { /* illegal instruction */
631 info.si_signo = SIGILL;
632 info.si_errno = 0;
633 info.si_code = TARGET_ILL_ILLOPN;
634 info._sifields._sigfault._addr = env->regs[15];
635 queue_signal(env, info.si_signo, &info);
636 } else if (rc < 0) { /* FP exception */
637 int arm_fpe=0;
638
639 /* translate softfloat flags to FPSR flags */
640 if (-rc & float_flag_invalid)
641 arm_fpe |= BIT_IOC;
642 if (-rc & float_flag_divbyzero)
643 arm_fpe |= BIT_DZC;
644 if (-rc & float_flag_overflow)
645 arm_fpe |= BIT_OFC;
646 if (-rc & float_flag_underflow)
647 arm_fpe |= BIT_UFC;
648 if (-rc & float_flag_inexact)
649 arm_fpe |= BIT_IXC;
650
651 FPSR fpsr = ts->fpa.fpsr;
652 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
653
654 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
655 info.si_signo = SIGFPE;
656 info.si_errno = 0;
657
658 /* ordered by priority, least first */
659 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
660 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
661 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
662 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
663 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
664
665 info._sifields._sigfault._addr = env->regs[15];
666 queue_signal(env, info.si_signo, &info);
667 } else {
668 env->regs[15] += 4;
669 }
670
671 /* accumulate unenabled exceptions */
672 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
673 fpsr |= BIT_IXC;
674 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
675 fpsr |= BIT_UFC;
676 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
677 fpsr |= BIT_OFC;
678 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
679 fpsr |= BIT_DZC;
680 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
681 fpsr |= BIT_IOC;
682 ts->fpa.fpsr=fpsr;
683 } else { /* everything OK */
684 /* increment PC */
685 env->regs[15] += 4;
686 }
687 }
688 break;
689 case EXCP_SWI:
690 case EXCP_BKPT:
691 {
692 env->eabi = 1;
693 /* system call */
694 if (trapnr == EXCP_BKPT) {
695 if (env->thumb) {
696 /* FIXME - what to do if get_user() fails? */
697 get_user_u16(insn, env->regs[15]);
698 n = insn & 0xff;
699 env->regs[15] += 2;
700 } else {
701 /* FIXME - what to do if get_user() fails? */
702 get_user_u32(insn, env->regs[15]);
703 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
704 env->regs[15] += 4;
705 }
706 } else {
707 if (env->thumb) {
708 /* FIXME - what to do if get_user() fails? */
709 get_user_u16(insn, env->regs[15] - 2);
710 n = insn & 0xff;
711 } else {
712 /* FIXME - what to do if get_user() fails? */
713 get_user_u32(insn, env->regs[15] - 4);
714 n = insn & 0xffffff;
715 }
716 }
717
718 if (n == ARM_NR_cacheflush) {
719 arm_cache_flush(env->regs[0], env->regs[1]);
720 } else if (n == ARM_NR_semihosting
721 || n == ARM_NR_thumb_semihosting) {
722 env->regs[0] = do_arm_semihosting (env);
723 } else if (n == 0 || n >= ARM_SYSCALL_BASE
724 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
725 /* linux syscall */
726 if (env->thumb || n == 0) {
727 n = env->regs[7];
728 } else {
729 n -= ARM_SYSCALL_BASE;
730 env->eabi = 0;
731 }
732 if ( n > ARM_NR_BASE) {
733 switch (n) {
734 case ARM_NR_cacheflush:
735 arm_cache_flush(env->regs[0], env->regs[1]);
736 break;
737 case ARM_NR_set_tls:
738 cpu_set_tls(env, env->regs[0]);
739 env->regs[0] = 0;
740 break;
741 default:
742 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
743 n);
744 env->regs[0] = -TARGET_ENOSYS;
745 break;
746 }
747 } else {
748 env->regs[0] = do_syscall(env,
749 n,
750 env->regs[0],
751 env->regs[1],
752 env->regs[2],
753 env->regs[3],
754 env->regs[4],
755 env->regs[5]);
756 }
757 } else {
758 goto error;
759 }
760 }
761 break;
762 case EXCP_INTERRUPT:
763 /* just indicate that signals should be handled asap */
764 break;
765 case EXCP_PREFETCH_ABORT:
766 addr = env->cp15.c6_insn;
767 goto do_segv;
768 case EXCP_DATA_ABORT:
769 addr = env->cp15.c6_data;
770 goto do_segv;
771 do_segv:
772 {
773 info.si_signo = SIGSEGV;
774 info.si_errno = 0;
775 /* XXX: check env->error_code */
776 info.si_code = TARGET_SEGV_MAPERR;
777 info._sifields._sigfault._addr = addr;
778 queue_signal(env, info.si_signo, &info);
779 }
780 break;
781 case EXCP_DEBUG:
782 {
783 int sig;
784
785 sig = gdb_handlesig (env, TARGET_SIGTRAP);
786 if (sig)
787 {
788 info.si_signo = sig;
789 info.si_errno = 0;
790 info.si_code = TARGET_TRAP_BRKPT;
791 queue_signal(env, info.si_signo, &info);
792 }
793 }
794 break;
795 case EXCP_KERNEL_TRAP:
796 if (do_kernel_trap(env))
797 goto error;
798 break;
799 case EXCP_STREX:
800 if (do_strex(env)) {
801 addr = env->cp15.c6_data;
802 goto do_segv;
803 }
804 break;
805 default:
806 error:
807 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
808 trapnr);
809 cpu_dump_state(env, stderr, fprintf, 0);
810 abort();
811 }
812 process_pending_signals(env);
813 }
814 }
815
816 #endif
817
818 #ifdef TARGET_SPARC
819 #define SPARC64_STACK_BIAS 2047
820
821 //#define DEBUG_WIN
822
823 /* WARNING: dealing with register windows _is_ complicated. More info
824 can be found at http://www.sics.se/~psm/sparcstack.html */
825 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
826 {
827 index = (index + cwp * 16) % (16 * env->nwindows);
828 /* wrap handling : if cwp is on the last window, then we use the
829 registers 'after' the end */
830 if (index < 8 && env->cwp == env->nwindows - 1)
831 index += 16 * env->nwindows;
832 return index;
833 }
834
835 /* save the register window 'cwp1' */
836 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
837 {
838 unsigned int i;
839 abi_ulong sp_ptr;
840
841 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
842 #ifdef TARGET_SPARC64
843 if (sp_ptr & 3)
844 sp_ptr += SPARC64_STACK_BIAS;
845 #endif
846 #if defined(DEBUG_WIN)
847 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
848 sp_ptr, cwp1);
849 #endif
850 for(i = 0; i < 16; i++) {
851 /* FIXME - what to do if put_user() fails? */
852 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
853 sp_ptr += sizeof(abi_ulong);
854 }
855 }
856
857 static void save_window(CPUSPARCState *env)
858 {
859 #ifndef TARGET_SPARC64
860 unsigned int new_wim;
861 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
862 ((1LL << env->nwindows) - 1);
863 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
864 env->wim = new_wim;
865 #else
866 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
867 env->cansave++;
868 env->canrestore--;
869 #endif
870 }
871
872 static void restore_window(CPUSPARCState *env)
873 {
874 #ifndef TARGET_SPARC64
875 unsigned int new_wim;
876 #endif
877 unsigned int i, cwp1;
878 abi_ulong sp_ptr;
879
880 #ifndef TARGET_SPARC64
881 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
882 ((1LL << env->nwindows) - 1);
883 #endif
884
885 /* restore the invalid window */
886 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
887 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
888 #ifdef TARGET_SPARC64
889 if (sp_ptr & 3)
890 sp_ptr += SPARC64_STACK_BIAS;
891 #endif
892 #if defined(DEBUG_WIN)
893 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
894 sp_ptr, cwp1);
895 #endif
896 for(i = 0; i < 16; i++) {
897 /* FIXME - what to do if get_user() fails? */
898 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
899 sp_ptr += sizeof(abi_ulong);
900 }
901 #ifdef TARGET_SPARC64
902 env->canrestore++;
903 if (env->cleanwin < env->nwindows - 1)
904 env->cleanwin++;
905 env->cansave--;
906 #else
907 env->wim = new_wim;
908 #endif
909 }
910
911 static void flush_windows(CPUSPARCState *env)
912 {
913 int offset, cwp1;
914
915 offset = 1;
916 for(;;) {
917 /* if restore would invoke restore_window(), then we can stop */
918 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
919 #ifndef TARGET_SPARC64
920 if (env->wim & (1 << cwp1))
921 break;
922 #else
923 if (env->canrestore == 0)
924 break;
925 env->cansave++;
926 env->canrestore--;
927 #endif
928 save_window_offset(env, cwp1);
929 offset++;
930 }
931 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
932 #ifndef TARGET_SPARC64
933 /* set wim so that restore will reload the registers */
934 env->wim = 1 << cwp1;
935 #endif
936 #if defined(DEBUG_WIN)
937 printf("flush_windows: nb=%d\n", offset - 1);
938 #endif
939 }
940
941 void cpu_loop (CPUSPARCState *env)
942 {
943 int trapnr;
944 abi_long ret;
945 target_siginfo_t info;
946
947 while (1) {
948 trapnr = cpu_sparc_exec (env);
949
950 switch (trapnr) {
951 #ifndef TARGET_SPARC64
952 case 0x88:
953 case 0x90:
954 #else
955 case 0x110:
956 case 0x16d:
957 #endif
958 ret = do_syscall (env, env->gregs[1],
959 env->regwptr[0], env->regwptr[1],
960 env->regwptr[2], env->regwptr[3],
961 env->regwptr[4], env->regwptr[5]);
962 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
963 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
964 env->xcc |= PSR_CARRY;
965 #else
966 env->psr |= PSR_CARRY;
967 #endif
968 ret = -ret;
969 } else {
970 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
971 env->xcc &= ~PSR_CARRY;
972 #else
973 env->psr &= ~PSR_CARRY;
974 #endif
975 }
976 env->regwptr[0] = ret;
977 /* next instruction */
978 env->pc = env->npc;
979 env->npc = env->npc + 4;
980 break;
981 case 0x83: /* flush windows */
982 #ifdef TARGET_ABI32
983 case 0x103:
984 #endif
985 flush_windows(env);
986 /* next instruction */
987 env->pc = env->npc;
988 env->npc = env->npc + 4;
989 break;
990 #ifndef TARGET_SPARC64
991 case TT_WIN_OVF: /* window overflow */
992 save_window(env);
993 break;
994 case TT_WIN_UNF: /* window underflow */
995 restore_window(env);
996 break;
997 case TT_TFAULT:
998 case TT_DFAULT:
999 {
1000 info.si_signo = SIGSEGV;
1001 info.si_errno = 0;
1002 /* XXX: check env->error_code */
1003 info.si_code = TARGET_SEGV_MAPERR;
1004 info._sifields._sigfault._addr = env->mmuregs[4];
1005 queue_signal(env, info.si_signo, &info);
1006 }
1007 break;
1008 #else
1009 case TT_SPILL: /* window overflow */
1010 save_window(env);
1011 break;
1012 case TT_FILL: /* window underflow */
1013 restore_window(env);
1014 break;
1015 case TT_TFAULT:
1016 case TT_DFAULT:
1017 {
1018 info.si_signo = SIGSEGV;
1019 info.si_errno = 0;
1020 /* XXX: check env->error_code */
1021 info.si_code = TARGET_SEGV_MAPERR;
1022 if (trapnr == TT_DFAULT)
1023 info._sifields._sigfault._addr = env->dmmuregs[4];
1024 else
1025 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1026 queue_signal(env, info.si_signo, &info);
1027 }
1028 break;
1029 #ifndef TARGET_ABI32
1030 case 0x16e:
1031 flush_windows(env);
1032 sparc64_get_context(env);
1033 break;
1034 case 0x16f:
1035 flush_windows(env);
1036 sparc64_set_context(env);
1037 break;
1038 #endif
1039 #endif
1040 case EXCP_INTERRUPT:
1041 /* just indicate that signals should be handled asap */
1042 break;
1043 case EXCP_DEBUG:
1044 {
1045 int sig;
1046
1047 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1048 if (sig)
1049 {
1050 info.si_signo = sig;
1051 info.si_errno = 0;
1052 info.si_code = TARGET_TRAP_BRKPT;
1053 queue_signal(env, info.si_signo, &info);
1054 }
1055 }
1056 break;
1057 default:
1058 printf ("Unhandled trap: 0x%x\n", trapnr);
1059 cpu_dump_state(env, stderr, fprintf, 0);
1060 exit (1);
1061 }
1062 process_pending_signals (env);
1063 }
1064 }
1065
1066 #endif
1067
1068 #ifdef TARGET_PPC
1069 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1070 {
1071 /* TO FIX */
1072 return 0;
1073 }
1074
1075 uint64_t cpu_ppc_load_tbl (CPUState *env)
1076 {
1077 return cpu_ppc_get_tb(env);
1078 }
1079
1080 uint32_t cpu_ppc_load_tbu (CPUState *env)
1081 {
1082 return cpu_ppc_get_tb(env) >> 32;
1083 }
1084
1085 uint64_t cpu_ppc_load_atbl (CPUState *env)
1086 {
1087 return cpu_ppc_get_tb(env);
1088 }
1089
1090 uint32_t cpu_ppc_load_atbu (CPUState *env)
1091 {
1092 return cpu_ppc_get_tb(env) >> 32;
1093 }
1094
1095 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1096 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1097
1098 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1099 {
1100 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1101 }
1102
1103 /* XXX: to be fixed */
1104 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1105 {
1106 return -1;
1107 }
1108
1109 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1110 {
1111 return -1;
1112 }
1113
1114 #define EXCP_DUMP(env, fmt, ...) \
1115 do { \
1116 fprintf(stderr, fmt , ## __VA_ARGS__); \
1117 cpu_dump_state(env, stderr, fprintf, 0); \
1118 qemu_log(fmt, ## __VA_ARGS__); \
1119 if (logfile) \
1120 log_cpu_state(env, 0); \
1121 } while (0)
1122
1123 static int do_store_exclusive(CPUPPCState *env)
1124 {
1125 target_ulong addr;
1126 target_ulong page_addr;
1127 target_ulong val;
1128 int flags;
1129 int segv = 0;
1130
1131 addr = env->reserve_ea;
1132 page_addr = addr & TARGET_PAGE_MASK;
1133 start_exclusive();
1134 mmap_lock();
1135 flags = page_get_flags(page_addr);
1136 if ((flags & PAGE_READ) == 0) {
1137 segv = 1;
1138 } else {
1139 int reg = env->reserve_info & 0x1f;
1140 int size = (env->reserve_info >> 5) & 0xf;
1141 int stored = 0;
1142
1143 if (addr == env->reserve_addr) {
1144 switch (size) {
1145 case 1: segv = get_user_u8(val, addr); break;
1146 case 2: segv = get_user_u16(val, addr); break;
1147 case 4: segv = get_user_u32(val, addr); break;
1148 #if defined(TARGET_PPC64)
1149 case 8: segv = get_user_u64(val, addr); break;
1150 #endif
1151 default: abort();
1152 }
1153 if (!segv && val == env->reserve_val) {
1154 val = env->gpr[reg];
1155 switch (size) {
1156 case 1: segv = put_user_u8(val, addr); break;
1157 case 2: segv = put_user_u16(val, addr); break;
1158 case 4: segv = put_user_u32(val, addr); break;
1159 #if defined(TARGET_PPC64)
1160 case 8: segv = put_user_u64(val, addr); break;
1161 #endif
1162 default: abort();
1163 }
1164 if (!segv) {
1165 stored = 1;
1166 }
1167 }
1168 }
1169 env->crf[0] = (stored << 1) | xer_so;
1170 env->reserve_addr = (target_ulong)-1;
1171 }
1172 if (!segv) {
1173 env->nip += 4;
1174 }
1175 mmap_unlock();
1176 end_exclusive();
1177 return segv;
1178 }
1179
1180 void cpu_loop(CPUPPCState *env)
1181 {
1182 target_siginfo_t info;
1183 int trapnr;
1184 uint32_t ret;
1185
1186 for(;;) {
1187 cpu_exec_start(env);
1188 trapnr = cpu_ppc_exec(env);
1189 cpu_exec_end(env);
1190 switch(trapnr) {
1191 case POWERPC_EXCP_NONE:
1192 /* Just go on */
1193 break;
1194 case POWERPC_EXCP_CRITICAL: /* Critical input */
1195 cpu_abort(env, "Critical interrupt while in user mode. "
1196 "Aborting\n");
1197 break;
1198 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1199 cpu_abort(env, "Machine check exception while in user mode. "
1200 "Aborting\n");
1201 break;
1202 case POWERPC_EXCP_DSI: /* Data storage exception */
1203 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1204 env->spr[SPR_DAR]);
1205 /* XXX: check this. Seems bugged */
1206 switch (env->error_code & 0xFF000000) {
1207 case 0x40000000:
1208 info.si_signo = TARGET_SIGSEGV;
1209 info.si_errno = 0;
1210 info.si_code = TARGET_SEGV_MAPERR;
1211 break;
1212 case 0x04000000:
1213 info.si_signo = TARGET_SIGILL;
1214 info.si_errno = 0;
1215 info.si_code = TARGET_ILL_ILLADR;
1216 break;
1217 case 0x08000000:
1218 info.si_signo = TARGET_SIGSEGV;
1219 info.si_errno = 0;
1220 info.si_code = TARGET_SEGV_ACCERR;
1221 break;
1222 default:
1223 /* Let's send a regular segfault... */
1224 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1225 env->error_code);
1226 info.si_signo = TARGET_SIGSEGV;
1227 info.si_errno = 0;
1228 info.si_code = TARGET_SEGV_MAPERR;
1229 break;
1230 }
1231 info._sifields._sigfault._addr = env->nip;
1232 queue_signal(env, info.si_signo, &info);
1233 break;
1234 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1235 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1236 "\n", env->spr[SPR_SRR0]);
1237 /* XXX: check this */
1238 switch (env->error_code & 0xFF000000) {
1239 case 0x40000000:
1240 info.si_signo = TARGET_SIGSEGV;
1241 info.si_errno = 0;
1242 info.si_code = TARGET_SEGV_MAPERR;
1243 break;
1244 case 0x10000000:
1245 case 0x08000000:
1246 info.si_signo = TARGET_SIGSEGV;
1247 info.si_errno = 0;
1248 info.si_code = TARGET_SEGV_ACCERR;
1249 break;
1250 default:
1251 /* Let's send a regular segfault... */
1252 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1253 env->error_code);
1254 info.si_signo = TARGET_SIGSEGV;
1255 info.si_errno = 0;
1256 info.si_code = TARGET_SEGV_MAPERR;
1257 break;
1258 }
1259 info._sifields._sigfault._addr = env->nip - 4;
1260 queue_signal(env, info.si_signo, &info);
1261 break;
1262 case POWERPC_EXCP_EXTERNAL: /* External input */
1263 cpu_abort(env, "External interrupt while in user mode. "
1264 "Aborting\n");
1265 break;
1266 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1267 EXCP_DUMP(env, "Unaligned memory access\n");
1268 /* XXX: check this */
1269 info.si_signo = TARGET_SIGBUS;
1270 info.si_errno = 0;
1271 info.si_code = TARGET_BUS_ADRALN;
1272 info._sifields._sigfault._addr = env->nip - 4;
1273 queue_signal(env, info.si_signo, &info);
1274 break;
1275 case POWERPC_EXCP_PROGRAM: /* Program exception */
1276 /* XXX: check this */
1277 switch (env->error_code & ~0xF) {
1278 case POWERPC_EXCP_FP:
1279 EXCP_DUMP(env, "Floating point program exception\n");
1280 info.si_signo = TARGET_SIGFPE;
1281 info.si_errno = 0;
1282 switch (env->error_code & 0xF) {
1283 case POWERPC_EXCP_FP_OX:
1284 info.si_code = TARGET_FPE_FLTOVF;
1285 break;
1286 case POWERPC_EXCP_FP_UX:
1287 info.si_code = TARGET_FPE_FLTUND;
1288 break;
1289 case POWERPC_EXCP_FP_ZX:
1290 case POWERPC_EXCP_FP_VXZDZ:
1291 info.si_code = TARGET_FPE_FLTDIV;
1292 break;
1293 case POWERPC_EXCP_FP_XX:
1294 info.si_code = TARGET_FPE_FLTRES;
1295 break;
1296 case POWERPC_EXCP_FP_VXSOFT:
1297 info.si_code = TARGET_FPE_FLTINV;
1298 break;
1299 case POWERPC_EXCP_FP_VXSNAN:
1300 case POWERPC_EXCP_FP_VXISI:
1301 case POWERPC_EXCP_FP_VXIDI:
1302 case POWERPC_EXCP_FP_VXIMZ:
1303 case POWERPC_EXCP_FP_VXVC:
1304 case POWERPC_EXCP_FP_VXSQRT:
1305 case POWERPC_EXCP_FP_VXCVI:
1306 info.si_code = TARGET_FPE_FLTSUB;
1307 break;
1308 default:
1309 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1310 env->error_code);
1311 break;
1312 }
1313 break;
1314 case POWERPC_EXCP_INVAL:
1315 EXCP_DUMP(env, "Invalid instruction\n");
1316 info.si_signo = TARGET_SIGILL;
1317 info.si_errno = 0;
1318 switch (env->error_code & 0xF) {
1319 case POWERPC_EXCP_INVAL_INVAL:
1320 info.si_code = TARGET_ILL_ILLOPC;
1321 break;
1322 case POWERPC_EXCP_INVAL_LSWX:
1323 info.si_code = TARGET_ILL_ILLOPN;
1324 break;
1325 case POWERPC_EXCP_INVAL_SPR:
1326 info.si_code = TARGET_ILL_PRVREG;
1327 break;
1328 case POWERPC_EXCP_INVAL_FP:
1329 info.si_code = TARGET_ILL_COPROC;
1330 break;
1331 default:
1332 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1333 env->error_code & 0xF);
1334 info.si_code = TARGET_ILL_ILLADR;
1335 break;
1336 }
1337 break;
1338 case POWERPC_EXCP_PRIV:
1339 EXCP_DUMP(env, "Privilege violation\n");
1340 info.si_signo = TARGET_SIGILL;
1341 info.si_errno = 0;
1342 switch (env->error_code & 0xF) {
1343 case POWERPC_EXCP_PRIV_OPC:
1344 info.si_code = TARGET_ILL_PRVOPC;
1345 break;
1346 case POWERPC_EXCP_PRIV_REG:
1347 info.si_code = TARGET_ILL_PRVREG;
1348 break;
1349 default:
1350 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1351 env->error_code & 0xF);
1352 info.si_code = TARGET_ILL_PRVOPC;
1353 break;
1354 }
1355 break;
1356 case POWERPC_EXCP_TRAP:
1357 cpu_abort(env, "Tried to call a TRAP\n");
1358 break;
1359 default:
1360 /* Should not happen ! */
1361 cpu_abort(env, "Unknown program exception (%02x)\n",
1362 env->error_code);
1363 break;
1364 }
1365 info._sifields._sigfault._addr = env->nip - 4;
1366 queue_signal(env, info.si_signo, &info);
1367 break;
1368 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1369 EXCP_DUMP(env, "No floating point allowed\n");
1370 info.si_signo = TARGET_SIGILL;
1371 info.si_errno = 0;
1372 info.si_code = TARGET_ILL_COPROC;
1373 info._sifields._sigfault._addr = env->nip - 4;
1374 queue_signal(env, info.si_signo, &info);
1375 break;
1376 case POWERPC_EXCP_SYSCALL: /* System call exception */
1377 cpu_abort(env, "Syscall exception while in user mode. "
1378 "Aborting\n");
1379 break;
1380 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1381 EXCP_DUMP(env, "No APU instruction allowed\n");
1382 info.si_signo = TARGET_SIGILL;
1383 info.si_errno = 0;
1384 info.si_code = TARGET_ILL_COPROC;
1385 info._sifields._sigfault._addr = env->nip - 4;
1386 queue_signal(env, info.si_signo, &info);
1387 break;
1388 case POWERPC_EXCP_DECR: /* Decrementer exception */
1389 cpu_abort(env, "Decrementer interrupt while in user mode. "
1390 "Aborting\n");
1391 break;
1392 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1393 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1394 "Aborting\n");
1395 break;
1396 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1397 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1398 "Aborting\n");
1399 break;
1400 case POWERPC_EXCP_DTLB: /* Data TLB error */
1401 cpu_abort(env, "Data TLB exception while in user mode. "
1402 "Aborting\n");
1403 break;
1404 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1405 cpu_abort(env, "Instruction TLB exception while in user mode. "
1406 "Aborting\n");
1407 break;
1408 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1409 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1410 info.si_signo = TARGET_SIGILL;
1411 info.si_errno = 0;
1412 info.si_code = TARGET_ILL_COPROC;
1413 info._sifields._sigfault._addr = env->nip - 4;
1414 queue_signal(env, info.si_signo, &info);
1415 break;
1416 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1417 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1418 break;
1419 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1420 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1421 break;
1422 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1423 cpu_abort(env, "Performance monitor exception not handled\n");
1424 break;
1425 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1426 cpu_abort(env, "Doorbell interrupt while in user mode. "
1427 "Aborting\n");
1428 break;
1429 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1430 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1431 "Aborting\n");
1432 break;
1433 case POWERPC_EXCP_RESET: /* System reset exception */
1434 cpu_abort(env, "Reset interrupt while in user mode. "
1435 "Aborting\n");
1436 break;
1437 case POWERPC_EXCP_DSEG: /* Data segment exception */
1438 cpu_abort(env, "Data segment exception while in user mode. "
1439 "Aborting\n");
1440 break;
1441 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1442 cpu_abort(env, "Instruction segment exception "
1443 "while in user mode. Aborting\n");
1444 break;
1445 /* PowerPC 64 with hypervisor mode support */
1446 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1447 cpu_abort(env, "Hypervisor decrementer interrupt "
1448 "while in user mode. Aborting\n");
1449 break;
1450 case POWERPC_EXCP_TRACE: /* Trace exception */
1451 /* Nothing to do:
1452 * we use this exception to emulate step-by-step execution mode.
1453 */
1454 break;
1455 /* PowerPC 64 with hypervisor mode support */
1456 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1457 cpu_abort(env, "Hypervisor data storage exception "
1458 "while in user mode. Aborting\n");
1459 break;
1460 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1461 cpu_abort(env, "Hypervisor instruction storage exception "
1462 "while in user mode. Aborting\n");
1463 break;
1464 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1465 cpu_abort(env, "Hypervisor data segment exception "
1466 "while in user mode. Aborting\n");
1467 break;
1468 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1469 cpu_abort(env, "Hypervisor instruction segment exception "
1470 "while in user mode. Aborting\n");
1471 break;
1472 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1473 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1474 info.si_signo = TARGET_SIGILL;
1475 info.si_errno = 0;
1476 info.si_code = TARGET_ILL_COPROC;
1477 info._sifields._sigfault._addr = env->nip - 4;
1478 queue_signal(env, info.si_signo, &info);
1479 break;
1480 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1481 cpu_abort(env, "Programable interval timer interrupt "
1482 "while in user mode. Aborting\n");
1483 break;
1484 case POWERPC_EXCP_IO: /* IO error exception */
1485 cpu_abort(env, "IO error exception while in user mode. "
1486 "Aborting\n");
1487 break;
1488 case POWERPC_EXCP_RUNM: /* Run mode exception */
1489 cpu_abort(env, "Run mode exception while in user mode. "
1490 "Aborting\n");
1491 break;
1492 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1493 cpu_abort(env, "Emulation trap exception not handled\n");
1494 break;
1495 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1496 cpu_abort(env, "Instruction fetch TLB exception "
1497 "while in user-mode. Aborting");
1498 break;
1499 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1500 cpu_abort(env, "Data load TLB exception while in user-mode. "
1501 "Aborting");
1502 break;
1503 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1504 cpu_abort(env, "Data store TLB exception while in user-mode. "
1505 "Aborting");
1506 break;
1507 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1508 cpu_abort(env, "Floating-point assist exception not handled\n");
1509 break;
1510 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1511 cpu_abort(env, "Instruction address breakpoint exception "
1512 "not handled\n");
1513 break;
1514 case POWERPC_EXCP_SMI: /* System management interrupt */
1515 cpu_abort(env, "System management interrupt while in user mode. "
1516 "Aborting\n");
1517 break;
1518 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1519 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1520 "Aborting\n");
1521 break;
1522 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1523 cpu_abort(env, "Performance monitor exception not handled\n");
1524 break;
1525 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1526 cpu_abort(env, "Vector assist exception not handled\n");
1527 break;
1528 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1529 cpu_abort(env, "Soft patch exception not handled\n");
1530 break;
1531 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1532 cpu_abort(env, "Maintenance exception while in user mode. "
1533 "Aborting\n");
1534 break;
1535 case POWERPC_EXCP_STOP: /* stop translation */
1536 /* We did invalidate the instruction cache. Go on */
1537 break;
1538 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1539 /* We just stopped because of a branch. Go on */
1540 break;
1541 case POWERPC_EXCP_SYSCALL_USER:
1542 /* system call in user-mode emulation */
1543 /* WARNING:
1544 * PPC ABI uses overflow flag in cr0 to signal an error
1545 * in syscalls.
1546 */
1547 #if 0
1548 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1549 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1550 #endif
1551 env->crf[0] &= ~0x1;
1552 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1553 env->gpr[5], env->gpr[6], env->gpr[7],
1554 env->gpr[8]);
1555 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) {
1556 /* Returning from a successful sigreturn syscall.
1557 Avoid corrupting register state. */
1558 break;
1559 }
1560 if (ret > (uint32_t)(-515)) {
1561 env->crf[0] |= 0x1;
1562 ret = -ret;
1563 }
1564 env->gpr[3] = ret;
1565 #if 0
1566 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1567 #endif
1568 break;
1569 case POWERPC_EXCP_STCX:
1570 if (do_store_exclusive(env)) {
1571 info.si_signo = TARGET_SIGSEGV;
1572 info.si_errno = 0;
1573 info.si_code = TARGET_SEGV_MAPERR;
1574 info._sifields._sigfault._addr = env->nip;
1575 queue_signal(env, info.si_signo, &info);
1576 }
1577 break;
1578 case EXCP_DEBUG:
1579 {
1580 int sig;
1581
1582 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1583 if (sig) {
1584 info.si_signo = sig;
1585 info.si_errno = 0;
1586 info.si_code = TARGET_TRAP_BRKPT;
1587 queue_signal(env, info.si_signo, &info);
1588 }
1589 }
1590 break;
1591 case EXCP_INTERRUPT:
1592 /* just indicate that signals should be handled asap */
1593 break;
1594 default:
1595 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1596 break;
1597 }
1598 process_pending_signals(env);
1599 }
1600 }
1601 #endif
1602
1603 #ifdef TARGET_MIPS
1604
1605 #define MIPS_SYS(name, args) args,
1606
1607 static const uint8_t mips_syscall_args[] = {
1608 MIPS_SYS(sys_syscall , 0) /* 4000 */
1609 MIPS_SYS(sys_exit , 1)
1610 MIPS_SYS(sys_fork , 0)
1611 MIPS_SYS(sys_read , 3)
1612 MIPS_SYS(sys_write , 3)
1613 MIPS_SYS(sys_open , 3) /* 4005 */
1614 MIPS_SYS(sys_close , 1)
1615 MIPS_SYS(sys_waitpid , 3)
1616 MIPS_SYS(sys_creat , 2)
1617 MIPS_SYS(sys_link , 2)
1618 MIPS_SYS(sys_unlink , 1) /* 4010 */
1619 MIPS_SYS(sys_execve , 0)
1620 MIPS_SYS(sys_chdir , 1)
1621 MIPS_SYS(sys_time , 1)
1622 MIPS_SYS(sys_mknod , 3)
1623 MIPS_SYS(sys_chmod , 2) /* 4015 */
1624 MIPS_SYS(sys_lchown , 3)
1625 MIPS_SYS(sys_ni_syscall , 0)
1626 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1627 MIPS_SYS(sys_lseek , 3)
1628 MIPS_SYS(sys_getpid , 0) /* 4020 */
1629 MIPS_SYS(sys_mount , 5)
1630 MIPS_SYS(sys_oldumount , 1)
1631 MIPS_SYS(sys_setuid , 1)
1632 MIPS_SYS(sys_getuid , 0)
1633 MIPS_SYS(sys_stime , 1) /* 4025 */
1634 MIPS_SYS(sys_ptrace , 4)
1635 MIPS_SYS(sys_alarm , 1)
1636 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1637 MIPS_SYS(sys_pause , 0)
1638 MIPS_SYS(sys_utime , 2) /* 4030 */
1639 MIPS_SYS(sys_ni_syscall , 0)
1640 MIPS_SYS(sys_ni_syscall , 0)
1641 MIPS_SYS(sys_access , 2)
1642 MIPS_SYS(sys_nice , 1)
1643 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1644 MIPS_SYS(sys_sync , 0)
1645 MIPS_SYS(sys_kill , 2)
1646 MIPS_SYS(sys_rename , 2)
1647 MIPS_SYS(sys_mkdir , 2)
1648 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1649 MIPS_SYS(sys_dup , 1)
1650 MIPS_SYS(sys_pipe , 0)
1651 MIPS_SYS(sys_times , 1)
1652 MIPS_SYS(sys_ni_syscall , 0)
1653 MIPS_SYS(sys_brk , 1) /* 4045 */
1654 MIPS_SYS(sys_setgid , 1)
1655 MIPS_SYS(sys_getgid , 0)
1656 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1657 MIPS_SYS(sys_geteuid , 0)
1658 MIPS_SYS(sys_getegid , 0) /* 4050 */
1659 MIPS_SYS(sys_acct , 0)
1660 MIPS_SYS(sys_umount , 2)
1661 MIPS_SYS(sys_ni_syscall , 0)
1662 MIPS_SYS(sys_ioctl , 3)
1663 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1664 MIPS_SYS(sys_ni_syscall , 2)
1665 MIPS_SYS(sys_setpgid , 2)
1666 MIPS_SYS(sys_ni_syscall , 0)
1667 MIPS_SYS(sys_olduname , 1)
1668 MIPS_SYS(sys_umask , 1) /* 4060 */
1669 MIPS_SYS(sys_chroot , 1)
1670 MIPS_SYS(sys_ustat , 2)
1671 MIPS_SYS(sys_dup2 , 2)
1672 MIPS_SYS(sys_getppid , 0)
1673 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1674 MIPS_SYS(sys_setsid , 0)
1675 MIPS_SYS(sys_sigaction , 3)
1676 MIPS_SYS(sys_sgetmask , 0)
1677 MIPS_SYS(sys_ssetmask , 1)
1678 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1679 MIPS_SYS(sys_setregid , 2)
1680 MIPS_SYS(sys_sigsuspend , 0)
1681 MIPS_SYS(sys_sigpending , 1)
1682 MIPS_SYS(sys_sethostname , 2)
1683 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1684 MIPS_SYS(sys_getrlimit , 2)
1685 MIPS_SYS(sys_getrusage , 2)
1686 MIPS_SYS(sys_gettimeofday, 2)
1687 MIPS_SYS(sys_settimeofday, 2)
1688 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1689 MIPS_SYS(sys_setgroups , 2)
1690 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1691 MIPS_SYS(sys_symlink , 2)
1692 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1693 MIPS_SYS(sys_readlink , 3) /* 4085 */
1694 MIPS_SYS(sys_uselib , 1)
1695 MIPS_SYS(sys_swapon , 2)
1696 MIPS_SYS(sys_reboot , 3)
1697 MIPS_SYS(old_readdir , 3)
1698 MIPS_SYS(old_mmap , 6) /* 4090 */
1699 MIPS_SYS(sys_munmap , 2)
1700 MIPS_SYS(sys_truncate , 2)
1701 MIPS_SYS(sys_ftruncate , 2)
1702 MIPS_SYS(sys_fchmod , 2)
1703 MIPS_SYS(sys_fchown , 3) /* 4095 */
1704 MIPS_SYS(sys_getpriority , 2)
1705 MIPS_SYS(sys_setpriority , 3)
1706 MIPS_SYS(sys_ni_syscall , 0)
1707 MIPS_SYS(sys_statfs , 2)
1708 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1709 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1710 MIPS_SYS(sys_socketcall , 2)
1711 MIPS_SYS(sys_syslog , 3)
1712 MIPS_SYS(sys_setitimer , 3)
1713 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1714 MIPS_SYS(sys_newstat , 2)
1715 MIPS_SYS(sys_newlstat , 2)
1716 MIPS_SYS(sys_newfstat , 2)
1717 MIPS_SYS(sys_uname , 1)
1718 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1719 MIPS_SYS(sys_vhangup , 0)
1720 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1721 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1722 MIPS_SYS(sys_wait4 , 4)
1723 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1724 MIPS_SYS(sys_sysinfo , 1)
1725 MIPS_SYS(sys_ipc , 6)
1726 MIPS_SYS(sys_fsync , 1)
1727 MIPS_SYS(sys_sigreturn , 0)
1728 MIPS_SYS(sys_clone , 6) /* 4120 */
1729 MIPS_SYS(sys_setdomainname, 2)
1730 MIPS_SYS(sys_newuname , 1)
1731 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1732 MIPS_SYS(sys_adjtimex , 1)
1733 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1734 MIPS_SYS(sys_sigprocmask , 3)
1735 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1736 MIPS_SYS(sys_init_module , 5)
1737 MIPS_SYS(sys_delete_module, 1)
1738 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1739 MIPS_SYS(sys_quotactl , 0)
1740 MIPS_SYS(sys_getpgid , 1)
1741 MIPS_SYS(sys_fchdir , 1)
1742 MIPS_SYS(sys_bdflush , 2)
1743 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1744 MIPS_SYS(sys_personality , 1)
1745 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1746 MIPS_SYS(sys_setfsuid , 1)
1747 MIPS_SYS(sys_setfsgid , 1)
1748 MIPS_SYS(sys_llseek , 5) /* 4140 */
1749 MIPS_SYS(sys_getdents , 3)
1750 MIPS_SYS(sys_select , 5)
1751 MIPS_SYS(sys_flock , 2)
1752 MIPS_SYS(sys_msync , 3)
1753 MIPS_SYS(sys_readv , 3) /* 4145 */
1754 MIPS_SYS(sys_writev , 3)
1755 MIPS_SYS(sys_cacheflush , 3)
1756 MIPS_SYS(sys_cachectl , 3)
1757 MIPS_SYS(sys_sysmips , 4)
1758 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1759 MIPS_SYS(sys_getsid , 1)
1760 MIPS_SYS(sys_fdatasync , 0)
1761 MIPS_SYS(sys_sysctl , 1)
1762 MIPS_SYS(sys_mlock , 2)
1763 MIPS_SYS(sys_munlock , 2) /* 4155 */
1764 MIPS_SYS(sys_mlockall , 1)
1765 MIPS_SYS(sys_munlockall , 0)
1766 MIPS_SYS(sys_sched_setparam, 2)
1767 MIPS_SYS(sys_sched_getparam, 2)
1768 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1769 MIPS_SYS(sys_sched_getscheduler, 1)
1770 MIPS_SYS(sys_sched_yield , 0)
1771 MIPS_SYS(sys_sched_get_priority_max, 1)
1772 MIPS_SYS(sys_sched_get_priority_min, 1)
1773 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1774 MIPS_SYS(sys_nanosleep, 2)
1775 MIPS_SYS(sys_mremap , 4)
1776 MIPS_SYS(sys_accept , 3)
1777 MIPS_SYS(sys_bind , 3)
1778 MIPS_SYS(sys_connect , 3) /* 4170 */
1779 MIPS_SYS(sys_getpeername , 3)
1780 MIPS_SYS(sys_getsockname , 3)
1781 MIPS_SYS(sys_getsockopt , 5)
1782 MIPS_SYS(sys_listen , 2)
1783 MIPS_SYS(sys_recv , 4) /* 4175 */
1784 MIPS_SYS(sys_recvfrom , 6)
1785 MIPS_SYS(sys_recvmsg , 3)
1786 MIPS_SYS(sys_send , 4)
1787 MIPS_SYS(sys_sendmsg , 3)
1788 MIPS_SYS(sys_sendto , 6) /* 4180 */
1789 MIPS_SYS(sys_setsockopt , 5)
1790 MIPS_SYS(sys_shutdown , 2)
1791 MIPS_SYS(sys_socket , 3)
1792 MIPS_SYS(sys_socketpair , 4)
1793 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1794 MIPS_SYS(sys_getresuid , 3)
1795 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1796 MIPS_SYS(sys_poll , 3)
1797 MIPS_SYS(sys_nfsservctl , 3)
1798 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1799 MIPS_SYS(sys_getresgid , 3)
1800 MIPS_SYS(sys_prctl , 5)
1801 MIPS_SYS(sys_rt_sigreturn, 0)
1802 MIPS_SYS(sys_rt_sigaction, 4)
1803 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1804 MIPS_SYS(sys_rt_sigpending, 2)
1805 MIPS_SYS(sys_rt_sigtimedwait, 4)
1806 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1807 MIPS_SYS(sys_rt_sigsuspend, 0)
1808 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1809 MIPS_SYS(sys_pwrite64 , 6)
1810 MIPS_SYS(sys_chown , 3)
1811 MIPS_SYS(sys_getcwd , 2)
1812 MIPS_SYS(sys_capget , 2)
1813 MIPS_SYS(sys_capset , 2) /* 4205 */
1814 MIPS_SYS(sys_sigaltstack , 0)
1815 MIPS_SYS(sys_sendfile , 4)
1816 MIPS_SYS(sys_ni_syscall , 0)
1817 MIPS_SYS(sys_ni_syscall , 0)
1818 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1819 MIPS_SYS(sys_truncate64 , 4)
1820 MIPS_SYS(sys_ftruncate64 , 4)
1821 MIPS_SYS(sys_stat64 , 2)
1822 MIPS_SYS(sys_lstat64 , 2)
1823 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1824 MIPS_SYS(sys_pivot_root , 2)
1825 MIPS_SYS(sys_mincore , 3)
1826 MIPS_SYS(sys_madvise , 3)
1827 MIPS_SYS(sys_getdents64 , 3)
1828 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1829 MIPS_SYS(sys_ni_syscall , 0)
1830 MIPS_SYS(sys_gettid , 0)
1831 MIPS_SYS(sys_readahead , 5)
1832 MIPS_SYS(sys_setxattr , 5)
1833 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1834 MIPS_SYS(sys_fsetxattr , 5)
1835 MIPS_SYS(sys_getxattr , 4)
1836 MIPS_SYS(sys_lgetxattr , 4)
1837 MIPS_SYS(sys_fgetxattr , 4)
1838 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1839 MIPS_SYS(sys_llistxattr , 3)
1840 MIPS_SYS(sys_flistxattr , 3)
1841 MIPS_SYS(sys_removexattr , 2)
1842 MIPS_SYS(sys_lremovexattr, 2)
1843 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1844 MIPS_SYS(sys_tkill , 2)
1845 MIPS_SYS(sys_sendfile64 , 5)
1846 MIPS_SYS(sys_futex , 2)
1847 MIPS_SYS(sys_sched_setaffinity, 3)
1848 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1849 MIPS_SYS(sys_io_setup , 2)
1850 MIPS_SYS(sys_io_destroy , 1)
1851 MIPS_SYS(sys_io_getevents, 5)
1852 MIPS_SYS(sys_io_submit , 3)
1853 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1854 MIPS_SYS(sys_exit_group , 1)
1855 MIPS_SYS(sys_lookup_dcookie, 3)
1856 MIPS_SYS(sys_epoll_create, 1)
1857 MIPS_SYS(sys_epoll_ctl , 4)
1858 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1859 MIPS_SYS(sys_remap_file_pages, 5)
1860 MIPS_SYS(sys_set_tid_address, 1)
1861 MIPS_SYS(sys_restart_syscall, 0)
1862 MIPS_SYS(sys_fadvise64_64, 7)
1863 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1864 MIPS_SYS(sys_fstatfs64 , 2)
1865 MIPS_SYS(sys_timer_create, 3)
1866 MIPS_SYS(sys_timer_settime, 4)
1867 MIPS_SYS(sys_timer_gettime, 2)
1868 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1869 MIPS_SYS(sys_timer_delete, 1)
1870 MIPS_SYS(sys_clock_settime, 2)
1871 MIPS_SYS(sys_clock_gettime, 2)
1872 MIPS_SYS(sys_clock_getres, 2)
1873 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1874 MIPS_SYS(sys_tgkill , 3)
1875 MIPS_SYS(sys_utimes , 2)
1876 MIPS_SYS(sys_mbind , 4)
1877 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1878 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1879 MIPS_SYS(sys_mq_open , 4)
1880 MIPS_SYS(sys_mq_unlink , 1)
1881 MIPS_SYS(sys_mq_timedsend, 5)
1882 MIPS_SYS(sys_mq_timedreceive, 5)
1883 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1884 MIPS_SYS(sys_mq_getsetattr, 3)
1885 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1886 MIPS_SYS(sys_waitid , 4)
1887 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1888 MIPS_SYS(sys_add_key , 5)
1889 MIPS_SYS(sys_request_key, 4)
1890 MIPS_SYS(sys_keyctl , 5)
1891 MIPS_SYS(sys_set_thread_area, 1)
1892 MIPS_SYS(sys_inotify_init, 0)
1893 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1894 MIPS_SYS(sys_inotify_rm_watch, 2)
1895 MIPS_SYS(sys_migrate_pages, 4)
1896 MIPS_SYS(sys_openat, 4)
1897 MIPS_SYS(sys_mkdirat, 3)
1898 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1899 MIPS_SYS(sys_fchownat, 5)
1900 MIPS_SYS(sys_futimesat, 3)
1901 MIPS_SYS(sys_fstatat64, 4)
1902 MIPS_SYS(sys_unlinkat, 3)
1903 MIPS_SYS(sys_renameat, 4) /* 4295 */
1904 MIPS_SYS(sys_linkat, 5)
1905 MIPS_SYS(sys_symlinkat, 3)
1906 MIPS_SYS(sys_readlinkat, 4)
1907 MIPS_SYS(sys_fchmodat, 3)
1908 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1909 MIPS_SYS(sys_pselect6, 6)
1910 MIPS_SYS(sys_ppoll, 5)
1911 MIPS_SYS(sys_unshare, 1)
1912 MIPS_SYS(sys_splice, 4)
1913 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1914 MIPS_SYS(sys_tee, 4)
1915 MIPS_SYS(sys_vmsplice, 4)
1916 MIPS_SYS(sys_move_pages, 6)
1917 MIPS_SYS(sys_set_robust_list, 2)
1918 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1919 MIPS_SYS(sys_kexec_load, 4)
1920 MIPS_SYS(sys_getcpu, 3)
1921 MIPS_SYS(sys_epoll_pwait, 6)
1922 MIPS_SYS(sys_ioprio_set, 3)
1923 MIPS_SYS(sys_ioprio_get, 2)
1924 };
1925
1926 #undef MIPS_SYS
1927
1928 static int do_store_exclusive(CPUMIPSState *env)
1929 {
1930 target_ulong addr;
1931 target_ulong page_addr;
1932 target_ulong val;
1933 int flags;
1934 int segv = 0;
1935 int reg;
1936 int d;
1937
1938 addr = env->lladdr;
1939 page_addr = addr & TARGET_PAGE_MASK;
1940 start_exclusive();
1941 mmap_lock();
1942 flags = page_get_flags(page_addr);
1943 if ((flags & PAGE_READ) == 0) {
1944 segv = 1;
1945 } else {
1946 reg = env->llreg & 0x1f;
1947 d = (env->llreg & 0x20) != 0;
1948 if (d) {
1949 segv = get_user_s64(val, addr);
1950 } else {
1951 segv = get_user_s32(val, addr);
1952 }
1953 if (!segv) {
1954 if (val != env->llval) {
1955 env->active_tc.gpr[reg] = 0;
1956 } else {
1957 if (d) {
1958 segv = put_user_u64(env->llnewval, addr);
1959 } else {
1960 segv = put_user_u32(env->llnewval, addr);
1961 }
1962 if (!segv) {
1963 env->active_tc.gpr[reg] = 1;
1964 }
1965 }
1966 }
1967 }
1968 env->lladdr = -1;
1969 if (!segv) {
1970 env->active_tc.PC += 4;
1971 }
1972 mmap_unlock();
1973 end_exclusive();
1974 return segv;
1975 }
1976
1977 void cpu_loop(CPUMIPSState *env)
1978 {
1979 target_siginfo_t info;
1980 int trapnr, ret;
1981 unsigned int syscall_num;
1982
1983 for(;;) {
1984 cpu_exec_start(env);
1985 trapnr = cpu_mips_exec(env);
1986 cpu_exec_end(env);
1987 switch(trapnr) {
1988 case EXCP_SYSCALL:
1989 syscall_num = env->active_tc.gpr[2] - 4000;
1990 env->active_tc.PC += 4;
1991 if (syscall_num >= sizeof(mips_syscall_args)) {
1992 ret = -ENOSYS;
1993 } else {
1994 int nb_args;
1995 abi_ulong sp_reg;
1996 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1997
1998 nb_args = mips_syscall_args[syscall_num];
1999 sp_reg = env->active_tc.gpr[29];
2000 switch (nb_args) {
2001 /* these arguments are taken from the stack */
2002 /* FIXME - what to do if get_user() fails? */
2003 case 8: get_user_ual(arg8, sp_reg + 28);
2004 case 7: get_user_ual(arg7, sp_reg + 24);
2005 case 6: get_user_ual(arg6, sp_reg + 20);
2006 case 5: get_user_ual(arg5, sp_reg + 16);
2007 default:
2008 break;
2009 }
2010 ret = do_syscall(env, env->active_tc.gpr[2],
2011 env->active_tc.gpr[4],
2012 env->active_tc.gpr[5],
2013 env->active_tc.gpr[6],
2014 env->active_tc.gpr[7],
2015 arg5, arg6/*, arg7, arg8*/);
2016 }
2017 if (ret == -TARGET_QEMU_ESIGRETURN) {
2018 /* Returning from a successful sigreturn syscall.
2019 Avoid clobbering register state. */
2020 break;
2021 }
2022 if ((unsigned int)ret >= (unsigned int)(-1133)) {
2023 env->active_tc.gpr[7] = 1; /* error flag */
2024 ret = -ret;
2025 } else {
2026 env->active_tc.gpr[7] = 0; /* error flag */
2027 }
2028 env->active_tc.gpr[2] = ret;
2029 break;
2030 case EXCP_TLBL:
2031 case EXCP_TLBS:
2032 info.si_signo = TARGET_SIGSEGV;
2033 info.si_errno = 0;
2034 /* XXX: check env->error_code */
2035 info.si_code = TARGET_SEGV_MAPERR;
2036 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2037 queue_signal(env, info.si_signo, &info);
2038 break;
2039 case EXCP_CpU:
2040 case EXCP_RI:
2041 info.si_signo = TARGET_SIGILL;
2042 info.si_errno = 0;
2043 info.si_code = 0;
2044 queue_signal(env, info.si_signo, &info);
2045 break;
2046 case EXCP_INTERRUPT:
2047 /* just indicate that signals should be handled asap */
2048 break;
2049 case EXCP_DEBUG:
2050 {
2051 int sig;
2052
2053 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2054 if (sig)
2055 {
2056 info.si_signo = sig;
2057 info.si_errno = 0;
2058 info.si_code = TARGET_TRAP_BRKPT;
2059 queue_signal(env, info.si_signo, &info);
2060 }
2061 }
2062 break;
2063 case EXCP_SC:
2064 if (do_store_exclusive(env)) {
2065 info.si_signo = TARGET_SIGSEGV;
2066 info.si_errno = 0;
2067 info.si_code = TARGET_SEGV_MAPERR;
2068 info._sifields._sigfault._addr = env->active_tc.PC;
2069 queue_signal(env, info.si_signo, &info);
2070 }
2071 break;
2072 default:
2073 // error:
2074 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2075 trapnr);
2076 cpu_dump_state(env, stderr, fprintf, 0);
2077 abort();
2078 }
2079 process_pending_signals(env);
2080 }
2081 }
2082 #endif
2083
2084 #ifdef TARGET_SH4
2085 void cpu_loop (CPUState *env)
2086 {
2087 int trapnr, ret;
2088 target_siginfo_t info;
2089
2090 while (1) {
2091 trapnr = cpu_sh4_exec (env);
2092
2093 switch (trapnr) {
2094 case 0x160:
2095 env->pc += 2;
2096 ret = do_syscall(env,
2097 env->gregs[3],
2098 env->gregs[4],
2099 env->gregs[5],
2100 env->gregs[6],
2101 env->gregs[7],
2102 env->gregs[0],
2103 env->gregs[1]);
2104 env->gregs[0] = ret;
2105 break;
2106 case EXCP_INTERRUPT:
2107 /* just indicate that signals should be handled asap */
2108 break;
2109 case EXCP_DEBUG:
2110 {
2111 int sig;
2112
2113 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2114 if (sig)
2115 {
2116 info.si_signo = sig;
2117 info.si_errno = 0;
2118 info.si_code = TARGET_TRAP_BRKPT;
2119 queue_signal(env, info.si_signo, &info);
2120 }
2121 }
2122 break;
2123 case 0xa0:
2124 case 0xc0:
2125 info.si_signo = SIGSEGV;
2126 info.si_errno = 0;
2127 info.si_code = TARGET_SEGV_MAPERR;
2128 info._sifields._sigfault._addr = env->tea;
2129 queue_signal(env, info.si_signo, &info);
2130 break;
2131
2132 default:
2133 printf ("Unhandled trap: 0x%x\n", trapnr);
2134 cpu_dump_state(env, stderr, fprintf, 0);
2135 exit (1);
2136 }
2137 process_pending_signals (env);
2138 }
2139 }
2140 #endif
2141
2142 #ifdef TARGET_CRIS
2143 void cpu_loop (CPUState *env)
2144 {
2145 int trapnr, ret;
2146 target_siginfo_t info;
2147
2148 while (1) {
2149 trapnr = cpu_cris_exec (env);
2150 switch (trapnr) {
2151 case 0xaa:
2152 {
2153 info.si_signo = SIGSEGV;
2154 info.si_errno = 0;
2155 /* XXX: check env->error_code */
2156 info.si_code = TARGET_SEGV_MAPERR;
2157 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2158 queue_signal(env, info.si_signo, &info);
2159 }
2160 break;
2161 case EXCP_INTERRUPT:
2162 /* just indicate that signals should be handled asap */
2163 break;
2164 case EXCP_BREAK:
2165 ret = do_syscall(env,
2166 env->regs[9],
2167 env->regs[10],
2168 env->regs[11],
2169 env->regs[12],
2170 env->regs[13],
2171 env->pregs[7],
2172 env->pregs[11]);
2173 env->regs[10] = ret;
2174 break;
2175 case EXCP_DEBUG:
2176 {
2177 int sig;
2178
2179 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2180 if (sig)
2181 {
2182 info.si_signo = sig;
2183 info.si_errno = 0;
2184 info.si_code = TARGET_TRAP_BRKPT;
2185 queue_signal(env, info.si_signo, &info);
2186 }
2187 }
2188 break;
2189 default:
2190 printf ("Unhandled trap: 0x%x\n", trapnr);
2191 cpu_dump_state(env, stderr, fprintf, 0);
2192 exit (1);
2193 }
2194 process_pending_signals (env);
2195 }
2196 }
2197 #endif
2198
2199 #ifdef TARGET_MICROBLAZE
2200 void cpu_loop (CPUState *env)
2201 {
2202 int trapnr, ret;
2203 target_siginfo_t info;
2204
2205 while (1) {
2206 trapnr = cpu_mb_exec (env);
2207 switch (trapnr) {
2208 case 0xaa:
2209 {
2210 info.si_signo = SIGSEGV;
2211 info.si_errno = 0;
2212 /* XXX: check env->error_code */
2213 info.si_code = TARGET_SEGV_MAPERR;
2214 info._sifields._sigfault._addr = 0;
2215 queue_signal(env, info.si_signo, &info);
2216 }
2217 break;
2218 case EXCP_INTERRUPT:
2219 /* just indicate that signals should be handled asap */
2220 break;
2221 case EXCP_BREAK:
2222 /* Return address is 4 bytes after the call. */
2223 env->regs[14] += 4;
2224 ret = do_syscall(env,
2225 env->regs[12],
2226 env->regs[5],
2227 env->regs[6],
2228 env->regs[7],
2229 env->regs[8],
2230 env->regs[9],
2231 env->regs[10]);
2232 env->regs[3] = ret;
2233 env->sregs[SR_PC] = env->regs[14];
2234 break;
2235 case EXCP_DEBUG:
2236 {
2237 int sig;
2238
2239 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2240 if (sig)
2241 {
2242 info.si_signo = sig;
2243 info.si_errno = 0;
2244 info.si_code = TARGET_TRAP_BRKPT;
2245 queue_signal(env, info.si_signo, &info);
2246 }
2247 }
2248 break;
2249 default:
2250 printf ("Unhandled trap: 0x%x\n", trapnr);
2251 cpu_dump_state(env, stderr, fprintf, 0);
2252 exit (1);
2253 }
2254 process_pending_signals (env);
2255 }
2256 }
2257 #endif
2258
2259 #ifdef TARGET_M68K
2260
2261 void cpu_loop(CPUM68KState *env)
2262 {
2263 int trapnr;
2264 unsigned int n;
2265 target_siginfo_t info;
2266 TaskState *ts = env->opaque;
2267
2268 for(;;) {
2269 trapnr = cpu_m68k_exec(env);
2270 switch(trapnr) {
2271 case EXCP_ILLEGAL:
2272 {
2273 if (ts->sim_syscalls) {
2274 uint16_t nr;
2275 nr = lduw(env->pc + 2);
2276 env->pc += 4;
2277 do_m68k_simcall(env, nr);
2278 } else {
2279 goto do_sigill;
2280 }
2281 }
2282 break;
2283 case EXCP_HALT_INSN:
2284 /* Semihosing syscall. */
2285 env->pc += 4;
2286 do_m68k_semihosting(env, env->dregs[0]);
2287 break;
2288 case EXCP_LINEA:
2289 case EXCP_LINEF:
2290 case EXCP_UNSUPPORTED:
2291 do_sigill:
2292 info.si_signo = SIGILL;
2293 info.si_errno = 0;
2294 info.si_code = TARGET_ILL_ILLOPN;
2295 info._sifields._sigfault._addr = env->pc;
2296 queue_signal(env, info.si_signo, &info);
2297 break;
2298 case EXCP_TRAP0:
2299 {
2300 ts->sim_syscalls = 0;
2301 n = env->dregs[0];
2302 env->pc += 2;
2303 env->dregs[0] = do_syscall(env,
2304 n,
2305 env->dregs[1],
2306 env->dregs[2],
2307 env->dregs[3],
2308 env->dregs[4],
2309 env->dregs[5],
2310 env->aregs[0]);
2311 }
2312 break;
2313 case EXCP_INTERRUPT:
2314 /* just indicate that signals should be handled asap */
2315 break;
2316 case EXCP_ACCESS:
2317 {
2318 info.si_signo = SIGSEGV;
2319 info.si_errno = 0;
2320 /* XXX: check env->error_code */
2321 info.si_code = TARGET_SEGV_MAPERR;
2322 info._sifields._sigfault._addr = env->mmu.ar;
2323 queue_signal(env, info.si_signo, &info);
2324 }
2325 break;
2326 case EXCP_DEBUG:
2327 {
2328 int sig;
2329
2330 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2331 if (sig)
2332 {
2333 info.si_signo = sig;
2334 info.si_errno = 0;
2335 info.si_code = TARGET_TRAP_BRKPT;
2336 queue_signal(env, info.si_signo, &info);
2337 }
2338 }
2339 break;
2340 default:
2341 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2342 trapnr);
2343 cpu_dump_state(env, stderr, fprintf, 0);
2344 abort();
2345 }
2346 process_pending_signals(env);
2347 }
2348 }
2349 #endif /* TARGET_M68K */
2350
2351 #ifdef TARGET_ALPHA
2352 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2353 {
2354 target_ulong addr, val, tmp;
2355 target_siginfo_t info;
2356 int ret = 0;
2357
2358 addr = env->lock_addr;
2359 tmp = env->lock_st_addr;
2360 env->lock_addr = -1;
2361 env->lock_st_addr = 0;
2362
2363 start_exclusive();
2364 mmap_lock();
2365
2366 if (addr == tmp) {
2367 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2368 goto do_sigsegv;
2369 }
2370
2371 if (val == env->lock_value) {
2372 tmp = env->ir[reg];
2373 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2374 goto do_sigsegv;
2375 }
2376 ret = 1;
2377 }
2378 }
2379 env->ir[reg] = ret;
2380 env->pc += 4;
2381
2382 mmap_unlock();
2383 end_exclusive();
2384 return;
2385
2386 do_sigsegv:
2387 mmap_unlock();
2388 end_exclusive();
2389
2390 info.si_signo = TARGET_SIGSEGV;
2391 info.si_errno = 0;
2392 info.si_code = TARGET_SEGV_MAPERR;
2393 info._sifields._sigfault._addr = addr;
2394 queue_signal(env, TARGET_SIGSEGV, &info);
2395 }
2396
2397 void cpu_loop (CPUState *env)
2398 {
2399 int trapnr;
2400 target_siginfo_t info;
2401 abi_long sysret;
2402
2403 while (1) {
2404 trapnr = cpu_alpha_exec (env);
2405
2406 /* All of the traps imply a transition through PALcode, which
2407 implies an REI instruction has been executed. Which means
2408 that the intr_flag should be cleared. */
2409 env->intr_flag = 0;
2410
2411 switch (trapnr) {
2412 case EXCP_RESET:
2413 fprintf(stderr, "Reset requested. Exit\n");
2414 exit(1);
2415 break;
2416 case EXCP_MCHK:
2417 fprintf(stderr, "Machine check exception. Exit\n");
2418 exit(1);
2419 break;
2420 case EXCP_ARITH:
2421 env->lock_addr = -1;
2422 info.si_signo = TARGET_SIGFPE;
2423 info.si_errno = 0;
2424 info.si_code = TARGET_FPE_FLTINV;
2425 info._sifields._sigfault._addr = env->pc;
2426 queue_signal(env, info.si_signo, &info);
2427 break;
2428 case EXCP_HW_INTERRUPT:
2429 fprintf(stderr, "External interrupt. Exit\n");
2430 exit(1);
2431 break;
2432 case EXCP_DFAULT:
2433 env->lock_addr = -1;
2434 info.si_signo = TARGET_SIGSEGV;
2435 info.si_errno = 0;
2436 info.si_code = 0; /* ??? SEGV_MAPERR vs SEGV_ACCERR. */
2437 info._sifields._sigfault._addr = env->pc;
2438 queue_signal(env, info.si_signo, &info);
2439 break;
2440 case EXCP_DTB_MISS_PAL:
2441 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2442 exit(1);
2443 break;
2444 case EXCP_ITB_MISS:
2445 fprintf(stderr, "MMU instruction TLB miss\n");
2446 exit(1);
2447 break;
2448 case EXCP_ITB_ACV:
2449 fprintf(stderr, "MMU instruction access violation\n");
2450 exit(1);
2451 break;
2452 case EXCP_DTB_MISS_NATIVE:
2453 fprintf(stderr, "MMU data TLB miss\n");
2454 exit(1);
2455 break;
2456 case EXCP_UNALIGN:
2457 env->lock_addr = -1;
2458 info.si_signo = TARGET_SIGBUS;
2459 info.si_errno = 0;
2460 info.si_code = TARGET_BUS_ADRALN;
2461 info._sifields._sigfault._addr = env->pc;
2462 queue_signal(env, info.si_signo, &info);
2463 break;
2464 case EXCP_OPCDEC:
2465 do_sigill:
2466 env->lock_addr = -1;
2467 info.si_signo = TARGET_SIGILL;
2468 info.si_errno = 0;
2469 info.si_code = TARGET_ILL_ILLOPC;
2470 info._sifields._sigfault._addr = env->pc;
2471 queue_signal(env, info.si_signo, &info);
2472 break;
2473 case EXCP_FEN:
2474 /* No-op. Linux simply re-enables the FPU. */
2475 break;
2476 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2477 env->lock_addr = -1;
2478 switch ((trapnr >> 6) | 0x80) {
2479 case 0x80:
2480 /* BPT */
2481 info.si_signo = TARGET_SIGTRAP;
2482 info.si_errno = 0;
2483 info.si_code = TARGET_TRAP_BRKPT;
2484 info._sifields._sigfault._addr = env->pc;
2485 queue_signal(env, info.si_signo, &info);
2486 break;
2487 case 0x81:
2488 /* BUGCHK */
2489 info.si_signo = TARGET_SIGTRAP;
2490 info.si_errno = 0;
2491 info.si_code = 0;
2492 info._sifields._sigfault._addr = env->pc;
2493 queue_signal(env, info.si_signo, &info);
2494 break;
2495 case 0x83:
2496 /* CALLSYS */
2497 trapnr = env->ir[IR_V0];
2498 sysret = do_syscall(env, trapnr,
2499 env->ir[IR_A0], env->ir[IR_A1],
2500 env->ir[IR_A2], env->ir[IR_A3],
2501 env->ir[IR_A4], env->ir[IR_A5]);
2502 if (trapnr != TARGET_NR_sigreturn
2503 && trapnr != TARGET_NR_rt_sigreturn) {
2504 env->ir[IR_V0] = (sysret < 0 ? -sysret : sysret);
2505 env->ir[IR_A3] = (sysret < 0);
2506 }
2507 break;
2508 case 0x86:
2509 /* IMB */
2510 /* ??? We can probably elide the code using page_unprotect
2511 that is checking for self-modifying code. Instead we
2512 could simply call tb_flush here. Until we work out the
2513 changes required to turn off the extra write protection,
2514 this can be a no-op. */
2515 break;
2516 case 0x9E:
2517 /* RDUNIQUE */
2518 /* Handled in the translator for usermode. */
2519 abort();
2520 case 0x9F:
2521 /* WRUNIQUE */
2522 /* Handled in the translator for usermode. */
2523 abort();
2524 case 0xAA:
2525 /* GENTRAP */
2526 info.si_signo = TARGET_SIGFPE;
2527 switch (env->ir[IR_A0]) {
2528 case TARGET_GEN_INTOVF:
2529 info.si_code = TARGET_FPE_INTOVF;
2530 break;
2531 case TARGET_GEN_INTDIV:
2532 info.si_code = TARGET_FPE_INTDIV;
2533 break;
2534 case TARGET_GEN_FLTOVF:
2535 info.si_code = TARGET_FPE_FLTOVF;
2536 break;
2537 case TARGET_GEN_FLTUND:
2538 info.si_code = TARGET_FPE_FLTUND;
2539 break;
2540 case TARGET_GEN_FLTINV:
2541 info.si_code = TARGET_FPE_FLTINV;
2542 break;
2543 case TARGET_GEN_FLTINE:
2544 info.si_code = TARGET_FPE_FLTRES;
2545 break;
2546 case TARGET_GEN_ROPRAND:
2547 info.si_code = 0;
2548 break;
2549 default:
2550 info.si_signo = TARGET_SIGTRAP;
2551 info.si_code = 0;
2552 break;
2553 }
2554 info.si_errno = 0;
2555 info._sifields._sigfault._addr = env->pc;
2556 queue_signal(env, info.si_signo, &info);
2557 break;
2558 default:
2559 goto do_sigill;
2560 }
2561 break;
2562 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2563 goto do_sigill;
2564 case EXCP_DEBUG:
2565 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
2566 if (info.si_signo) {
2567 env->lock_addr = -1;
2568 info.si_errno = 0;
2569 info.si_code = TARGET_TRAP_BRKPT;
2570 queue_signal(env, info.si_signo, &info);
2571 }
2572 break;
2573 case EXCP_STL_C:
2574 case EXCP_STQ_C:
2575 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
2576 break;
2577 default:
2578 printf ("Unhandled trap: 0x%x\n", trapnr);
2579 cpu_dump_state(env, stderr, fprintf, 0);
2580 exit (1);
2581 }
2582 process_pending_signals (env);
2583 }
2584 }
2585 #endif /* TARGET_ALPHA */
2586
2587 static void usage(void)
2588 {
2589 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2590 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2591 "Linux CPU emulator (compiled for %s emulation)\n"
2592 "\n"
2593 "Standard options:\n"
2594 "-h print this help\n"
2595 "-g port wait gdb connection to port\n"
2596 "-L path set the elf interpreter prefix (default=%s)\n"
2597 "-s size set the stack size in bytes (default=%ld)\n"
2598 "-cpu model select CPU (-cpu ? for list)\n"
2599 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2600 "-E var=value sets/modifies targets environment variable(s)\n"
2601 "-U var unsets targets environment variable(s)\n"
2602 "-0 argv0 forces target process argv[0] to be argv0\n"
2603 #if defined(CONFIG_USE_GUEST_BASE)
2604 "-B address set guest_base address to address\n"
2605 #endif
2606 "\n"
2607 "Debug options:\n"
2608 "-d options activate log (logfile=%s)\n"
2609 "-p pagesize set the host page size to 'pagesize'\n"
2610 "-singlestep always run in singlestep mode\n"
2611 "-strace log system calls\n"
2612 "\n"
2613 "Environment variables:\n"
2614 "QEMU_STRACE Print system calls and arguments similar to the\n"
2615 " 'strace' program. Enable by setting to any value.\n"
2616 "You can use -E and -U options to set/unset environment variables\n"
2617 "for target process. It is possible to provide several variables\n"
2618 "by repeating the option. For example:\n"
2619 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2620 "Note that if you provide several changes to single variable\n"
2621 "last change will stay in effect.\n"
2622 ,
2623 TARGET_ARCH,
2624 interp_prefix,
2625 guest_stack_size,
2626 DEBUG_LOGFILE);
2627 exit(1);
2628 }
2629
2630 THREAD CPUState *thread_env;
2631
2632 void task_settid(TaskState *ts)
2633 {
2634 if (ts->ts_tid == 0) {
2635 #ifdef CONFIG_USE_NPTL
2636 ts->ts_tid = (pid_t)syscall(SYS_gettid);
2637 #else
2638 /* when no threads are used, tid becomes pid */
2639 ts->ts_tid = getpid();
2640 #endif
2641 }
2642 }
2643
2644 void stop_all_tasks(void)
2645 {
2646 /*
2647 * We trust that when using NPTL, start_exclusive()
2648 * handles thread stopping correctly.
2649 */
2650 start_exclusive();
2651 }
2652
2653 /* Assumes contents are already zeroed. */
2654 void init_task_state(TaskState *ts)
2655 {
2656 int i;
2657
2658 ts->used = 1;
2659 ts->first_free = ts->sigqueue_table;
2660 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2661 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2662 }
2663 ts->sigqueue_table[i].next = NULL;
2664 }
2665
2666 int main(int argc, char **argv, char **envp)
2667 {
2668 const char *filename;
2669 const char *cpu_model;
2670 struct target_pt_regs regs1, *regs = &regs1;
2671 struct image_info info1, *info = &info1;
2672 struct linux_binprm bprm;
2673 TaskState ts1, *ts = &ts1;
2674 CPUState *env;
2675 int optind;
2676 const char *r;
2677 int gdbstub_port = 0;
2678 char **target_environ, **wrk;
2679 char **target_argv;
2680 int target_argc;
2681 envlist_t *envlist = NULL;
2682 const char *argv0 = NULL;
2683 int i;
2684 int ret;
2685
2686 if (argc <= 1)
2687 usage();
2688
2689 qemu_cache_utils_init(envp);
2690
2691 /* init debug */
2692 cpu_set_log_filename(DEBUG_LOGFILE);
2693
2694 if ((envlist = envlist_create()) == NULL) {
2695 (void) fprintf(stderr, "Unable to allocate envlist\n");
2696 exit(1);
2697 }
2698
2699 /* add current environment into the list */
2700 for (wrk = environ; *wrk != NULL; wrk++) {
2701 (void) envlist_setenv(envlist, *wrk);
2702 }
2703
2704 /* Read the stack limit from the kernel. If it's "unlimited",
2705 then we can do little else besides use the default. */
2706 {
2707 struct rlimit lim;
2708 if (getrlimit(RLIMIT_STACK, &lim) == 0
2709 && lim.rlim_cur != RLIM_INFINITY
2710 && lim.rlim_cur == (target_long)lim.rlim_cur) {
2711 guest_stack_size = lim.rlim_cur;
2712 }
2713 }
2714
2715 cpu_model = NULL;
2716 #if defined(cpudef_setup)
2717 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
2718 #endif
2719
2720 optind = 1;
2721 for(;;) {
2722 if (optind >= argc)
2723 break;
2724 r = argv[optind];
2725 if (r[0] != '-')
2726 break;
2727 optind++;
2728 r++;
2729 if (!strcmp(r, "-")) {
2730 break;
2731 } else if (!strcmp(r, "d")) {
2732 int mask;
2733 const CPULogItem *item;
2734
2735 if (optind >= argc)
2736 break;
2737
2738 r = argv[optind++];
2739 mask = cpu_str_to_log_mask(r);
2740 if (!mask) {
2741 printf("Log items (comma separated):\n");
2742 for(item = cpu_log_items; item->mask != 0; item++) {
2743 printf("%-10s %s\n", item->name, item->help);
2744 }
2745 exit(1);
2746 }
2747 cpu_set_log(mask);
2748 } else if (!strcmp(r, "E")) {
2749 r = argv[optind++];
2750 if (envlist_setenv(envlist, r) != 0)
2751 usage();
2752 } else if (!strcmp(r, "U")) {
2753 r = argv[optind++];
2754 if (envlist_unsetenv(envlist, r) != 0)
2755 usage();
2756 } else if (!strcmp(r, "0")) {
2757 r = argv[optind++];
2758 argv0 = r;
2759 } else if (!strcmp(r, "s")) {
2760 if (optind >= argc)
2761 break;
2762 r = argv[optind++];
2763 guest_stack_size = strtoul(r, (char **)&r, 0);
2764 if (guest_stack_size == 0)
2765 usage();
2766 if (*r == 'M')
2767 guest_stack_size *= 1024 * 1024;
2768 else if (*r == 'k' || *r == 'K')
2769 guest_stack_size *= 1024;
2770 } else if (!strcmp(r, "L")) {
2771 interp_prefix = argv[optind++];
2772 } else if (!strcmp(r, "p")) {
2773 if (optind >= argc)
2774 break;
2775 qemu_host_page_size = atoi(argv[optind++]);
2776 if (qemu_host_page_size == 0 ||
2777 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2778 fprintf(stderr, "page size must be a power of two\n");
2779 exit(1);
2780 }
2781 } else if (!strcmp(r, "g")) {
2782 if (optind >= argc)
2783 break;
2784 gdbstub_port = atoi(argv[optind++]);
2785 } else if (!strcmp(r, "r")) {
2786 qemu_uname_release = argv[optind++];
2787 } else if (!strcmp(r, "cpu")) {
2788 cpu_model = argv[optind++];
2789 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
2790 /* XXX: implement xxx_cpu_list for targets that still miss it */
2791 #if defined(cpu_list_id)
2792 cpu_list_id(stdout, &fprintf, "");
2793 #endif
2794 exit(1);
2795 }
2796 #if defined(CONFIG_USE_GUEST_BASE)
2797 } else if (!strcmp(r, "B")) {
2798 guest_base = strtol(argv[optind++], NULL, 0);
2799 have_guest_base = 1;
2800 #endif
2801 } else if (!strcmp(r, "drop-ld-preload")) {
2802 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
2803 } else if (!strcmp(r, "singlestep")) {
2804 singlestep = 1;
2805 } else if (!strcmp(r, "strace")) {
2806 do_strace = 1;
2807 } else
2808 {
2809 usage();
2810 }
2811 }
2812 if (optind >= argc)
2813 usage();
2814 filename = argv[optind];
2815 exec_path = argv[optind];
2816
2817 /* Zero out regs */
2818 memset(regs, 0, sizeof(struct target_pt_regs));
2819
2820 /* Zero out image_info */
2821 memset(info, 0, sizeof(struct image_info));
2822
2823 memset(&bprm, 0, sizeof (bprm));
2824
2825 /* Scan interp_prefix dir for replacement files. */
2826 init_paths(interp_prefix);
2827
2828 if (cpu_model == NULL) {
2829 #if defined(TARGET_I386)
2830 #ifdef TARGET_X86_64
2831 cpu_model = "qemu64";
2832 #else
2833 cpu_model = "qemu32";
2834 #endif
2835 #elif defined(TARGET_ARM)
2836 cpu_model = "any";
2837 #elif defined(TARGET_M68K)
2838 cpu_model = "any";
2839 #elif defined(TARGET_SPARC)
2840 #ifdef TARGET_SPARC64
2841 cpu_model = "TI UltraSparc II";
2842 #else
2843 cpu_model = "Fujitsu MB86904";
2844 #endif
2845 #elif defined(TARGET_MIPS)
2846 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2847 cpu_model = "20Kc";
2848 #else
2849 cpu_model = "24Kf";
2850 #endif
2851 #elif defined(TARGET_PPC)
2852 #ifdef TARGET_PPC64
2853 cpu_model = "970fx";
2854 #else
2855 cpu_model = "750";
2856 #endif
2857 #else
2858 cpu_model = "any";
2859 #endif
2860 }
2861 cpu_exec_init_all(0);
2862 /* NOTE: we need to init the CPU at this stage to get
2863 qemu_host_page_size */
2864 env = cpu_init(cpu_model);
2865 if (!env) {
2866 fprintf(stderr, "Unable to find CPU definition\n");
2867 exit(1);
2868 }
2869 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
2870 cpu_reset(env);
2871 #endif
2872
2873 thread_env = env;
2874
2875 if (getenv("QEMU_STRACE")) {
2876 do_strace = 1;
2877 }
2878
2879 target_environ = envlist_to_environ(envlist, NULL);
2880 envlist_free(envlist);
2881
2882 #if defined(CONFIG_USE_GUEST_BASE)
2883 /*
2884 * Now that page sizes are configured in cpu_init() we can do
2885 * proper page alignment for guest_base.
2886 */
2887 guest_base = HOST_PAGE_ALIGN(guest_base);
2888 #endif /* CONFIG_USE_GUEST_BASE */
2889
2890 /*
2891 * Read in mmap_min_addr kernel parameter. This value is used
2892 * When loading the ELF image to determine whether guest_base
2893 * is needed. It is also used in mmap_find_vma.
2894 */
2895 {
2896 FILE *fp;
2897
2898 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
2899 unsigned long tmp;
2900 if (fscanf(fp, "%lu", &tmp) == 1) {
2901 mmap_min_addr = tmp;
2902 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
2903 }
2904 fclose(fp);
2905 }
2906 }
2907
2908 /*
2909 * Prepare copy of argv vector for target.
2910 */
2911 target_argc = argc - optind;
2912 target_argv = calloc(target_argc + 1, sizeof (char *));
2913 if (target_argv == NULL) {
2914 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
2915 exit(1);
2916 }
2917
2918 /*
2919 * If argv0 is specified (using '-0' switch) we replace
2920 * argv[0] pointer with the given one.
2921 */
2922 i = 0;
2923 if (argv0 != NULL) {
2924 target_argv[i++] = strdup(argv0);
2925 }
2926 for (; i < target_argc; i++) {
2927 target_argv[i] = strdup(argv[optind + i]);
2928 }
2929 target_argv[target_argc] = NULL;
2930
2931 memset(ts, 0, sizeof(TaskState));
2932 init_task_state(ts);
2933 /* build Task State */
2934 ts->info = info;
2935 ts->bprm = &bprm;
2936 env->opaque = ts;
2937 task_settid(ts);
2938
2939 ret = loader_exec(filename, target_argv, target_environ, regs,
2940 info, &bprm);
2941 if (ret != 0) {
2942 printf("Error %d while loading %s\n", ret, filename);
2943 _exit(1);
2944 }
2945
2946 for (i = 0; i < target_argc; i++) {
2947 free(target_argv[i]);
2948 }
2949 free(target_argv);
2950
2951 for (wrk = target_environ; *wrk; wrk++) {
2952 free(*wrk);
2953 }
2954
2955 free(target_environ);
2956
2957 if (qemu_log_enabled()) {
2958 #if defined(CONFIG_USE_GUEST_BASE)
2959 qemu_log("guest_base 0x%lx\n", guest_base);
2960 #endif
2961 log_page_dump();
2962
2963 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2964 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2965 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
2966 info->start_code);
2967 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
2968 info->start_data);
2969 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2970 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
2971 info->start_stack);
2972 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2973 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2974 }
2975
2976 target_set_brk(info->brk);
2977 syscall_init();
2978 signal_init();
2979
2980 #if defined(TARGET_I386)
2981 cpu_x86_set_cpl(env, 3);
2982
2983 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2984 env->hflags |= HF_PE_MASK;
2985 if (env->cpuid_features & CPUID_SSE) {
2986 env->cr[4] |= CR4_OSFXSR_MASK;
2987 env->hflags |= HF_OSFXSR_MASK;
2988 }
2989 #ifndef TARGET_ABI32
2990 /* enable 64 bit mode if possible */
2991 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2992 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2993 exit(1);
2994 }
2995 env->cr[4] |= CR4_PAE_MASK;
2996 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2997 env->hflags |= HF_LMA_MASK;
2998 #endif
2999
3000 /* flags setup : we activate the IRQs by default as in user mode */
3001 env->eflags |= IF_MASK;
3002
3003 /* linux register setup */
3004 #ifndef TARGET_ABI32
3005 env->regs[R_EAX] = regs->rax;
3006 env->regs[R_EBX] = regs->rbx;
3007 env->regs[R_ECX] = regs->rcx;
3008 env->regs[R_EDX] = regs->rdx;
3009 env->regs[R_ESI] = regs->rsi;
3010 env->regs[R_EDI] = regs->rdi;
3011 env->regs[R_EBP] = regs->rbp;
3012 env->regs[R_ESP] = regs->rsp;
3013 env->eip = regs->rip;
3014 #else
3015 env->regs[R_EAX] = regs->eax;
3016 env->regs[R_EBX] = regs->ebx;
3017 env->regs[R_ECX] = regs->ecx;
3018 env->regs[R_EDX] = regs->edx;
3019 env->regs[R_ESI] = regs->esi;
3020 env->regs[R_EDI] = regs->edi;
3021 env->regs[R_EBP] = regs->ebp;
3022 env->regs[R_ESP] = regs->esp;
3023 env->eip = regs->eip;
3024 #endif
3025
3026 /* linux interrupt setup */
3027 #ifndef TARGET_ABI32
3028 env->idt.limit = 511;
3029 #else
3030 env->idt.limit = 255;
3031 #endif
3032 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3033 PROT_READ|PROT_WRITE,
3034 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3035 idt_table = g2h(env->idt.base);
3036 set_idt(0, 0);
3037 set_idt(1, 0);
3038 set_idt(2, 0);
3039 set_idt(3, 3);
3040 set_idt(4, 3);
3041 set_idt(5, 0);
3042 set_idt(6, 0);
3043 set_idt(7, 0);
3044 set_idt(8, 0);
3045 set_idt(9, 0);
3046 set_idt(10, 0);
3047 set_idt(11, 0);
3048 set_idt(12, 0);
3049 set_idt(13, 0);
3050 set_idt(14, 0);
3051 set_idt(15, 0);
3052 set_idt(16, 0);
3053 set_idt(17, 0);
3054 set_idt(18, 0);
3055 set_idt(19, 0);
3056 set_idt(0x80, 3);
3057
3058 /* linux segment setup */
3059 {
3060 uint64_t *gdt_table;
3061 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3062 PROT_READ|PROT_WRITE,
3063 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3064 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
3065 gdt_table = g2h(env->gdt.base);
3066 #ifdef TARGET_ABI32
3067 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3068 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3069 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3070 #else
3071 /* 64 bit code segment */
3072 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3073 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3074 DESC_L_MASK |
3075 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3076 #endif
3077 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3078 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3079 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3080 }
3081 cpu_x86_load_seg(env, R_CS, __USER_CS);
3082 cpu_x86_load_seg(env, R_SS, __USER_DS);
3083 #ifdef TARGET_ABI32
3084 cpu_x86_load_seg(env, R_DS, __USER_DS);
3085 cpu_x86_load_seg(env, R_ES, __USER_DS);
3086 cpu_x86_load_seg(env, R_FS, __USER_DS);
3087 cpu_x86_load_seg(env, R_GS, __USER_DS);
3088 /* This hack makes Wine work... */
3089 env->segs[R_FS].selector = 0;
3090 #else
3091 cpu_x86_load_seg(env, R_DS, 0);
3092 cpu_x86_load_seg(env, R_ES, 0);
3093 cpu_x86_load_seg(env, R_FS, 0);
3094 cpu_x86_load_seg(env, R_GS, 0);
3095 #endif
3096 #elif defined(TARGET_ARM)
3097 {
3098 int i;
3099 cpsr_write(env, regs->uregs[16], 0xffffffff);
3100 for(i = 0; i < 16; i++) {
3101 env->regs[i] = regs->uregs[i];
3102 }
3103 }
3104 #elif defined(TARGET_SPARC)
3105 {
3106 int i;
3107 env->pc = regs->pc;
3108 env->npc = regs->npc;
3109 env->y = regs->y;
3110 for(i = 0; i < 8; i++)
3111 env->gregs[i] = regs->u_regs[i];
3112 for(i = 0; i < 8; i++)
3113 env->regwptr[i] = regs->u_regs[i + 8];
3114 }
3115 #elif defined(TARGET_PPC)
3116 {
3117 int i;
3118
3119 #if defined(TARGET_PPC64)
3120 #if defined(TARGET_ABI32)
3121 env->msr &= ~((target_ulong)1 << MSR_SF);
3122 #else
3123 env->msr |= (target_ulong)1 << MSR_SF;
3124 #endif
3125 #endif
3126 env->nip = regs->nip;
3127 for(i = 0; i < 32; i++) {
3128 env->gpr[i] = regs->gpr[i];
3129 }
3130 }
3131 #elif defined(TARGET_M68K)
3132 {
3133 env->pc = regs->pc;
3134 env->dregs[0] = regs->d0;
3135 env->dregs[1] = regs->d1;
3136 env->dregs[2] = regs->d2;
3137 env->dregs[3] = regs->d3;
3138 env->dregs[4] = regs->d4;
3139 env->dregs[5] = regs->d5;
3140 env->dregs[6] = regs->d6;
3141 env->dregs[7] = regs->d7;
3142 env->aregs[0] = regs->a0;
3143 env->aregs[1] = regs->a1;
3144 env->aregs[2] = regs->a2;
3145 env->aregs[3] = regs->a3;
3146 env->aregs[4] = regs->a4;
3147 env->aregs[5] = regs->a5;
3148 env->aregs[6] = regs->a6;
3149 env->aregs[7] = regs->usp;
3150 env->sr = regs->sr;
3151 ts->sim_syscalls = 1;
3152 }
3153 #elif defined(TARGET_MICROBLAZE)
3154 {
3155 env->regs[0] = regs->r0;
3156 env->regs[1] = regs->r1;
3157 env->regs[2] = regs->r2;
3158 env->regs[3] = regs->r3;
3159 env->regs[4] = regs->r4;
3160 env->regs[5] = regs->r5;
3161 env->regs[6] = regs->r6;
3162 env->regs[7] = regs->r7;
3163 env->regs[8] = regs->r8;
3164 env->regs[9] = regs->r9;
3165 env->regs[10] = regs->r10;
3166 env->regs[11] = regs->r11;
3167 env->regs[12] = regs->r12;
3168 env->regs[13] = regs->r13;
3169 env->regs[14] = regs->r14;
3170 env->regs[15] = regs->r15;
3171 env->regs[16] = regs->r16;
3172 env->regs[17] = regs->r17;
3173 env->regs[18] = regs->r18;
3174 env->regs[19] = regs->r19;
3175 env->regs[20] = regs->r20;
3176 env->regs[21] = regs->r21;
3177 env->regs[22] = regs->r22;
3178 env->regs[23] = regs->r23;
3179 env->regs[24] = regs->r24;
3180 env->regs[25] = regs->r25;
3181 env->regs[26] = regs->r26;
3182 env->regs[27] = regs->r27;
3183 env->regs[28] = regs->r28;
3184 env->regs[29] = regs->r29;
3185 env->regs[30] = regs->r30;
3186 env->regs[31] = regs->r31;
3187 env->sregs[SR_PC] = regs->pc;
3188 }
3189 #elif defined(TARGET_MIPS)
3190 {
3191 int i;
3192
3193 for(i = 0; i < 32; i++) {
3194 env->active_tc.gpr[i] = regs->regs[i];
3195 }
3196 env->active_tc.PC = regs->cp0_epc;
3197 }
3198 #elif defined(TARGET_SH4)
3199 {
3200 int i;
3201
3202 for(i = 0; i < 16; i++) {
3203 env->gregs[i] = regs->regs[i];
3204 }
3205 env->pc = regs->pc;
3206 }
3207 #elif defined(TARGET_ALPHA)
3208 {
3209 int i;
3210
3211 for(i = 0; i < 28; i++) {
3212 env->ir[i] = ((abi_ulong *)regs)[i];
3213 }
3214 env->ir[IR_SP] = regs->usp;
3215 env->pc = regs->pc;
3216 }
3217 #elif defined(TARGET_CRIS)
3218 {
3219 env->regs[0] = regs->r0;
3220 env->regs[1] = regs->r1;
3221 env->regs[2] = regs->r2;
3222 env->regs[3] = regs->r3;
3223 env->regs[4] = regs->r4;
3224 env->regs[5] = regs->r5;
3225 env->regs[6] = regs->r6;
3226 env->regs[7] = regs->r7;
3227 env->regs[8] = regs->r8;
3228 env->regs[9] = regs->r9;
3229 env->regs[10] = regs->r10;
3230 env->regs[11] = regs->r11;
3231 env->regs[12] = regs->r12;
3232 env->regs[13] = regs->r13;
3233 env->regs[14] = info->start_stack;
3234 env->regs[15] = regs->acr;
3235 env->pc = regs->erp;
3236 }
3237 #else
3238 #error unsupported target CPU
3239 #endif
3240
3241 #if defined(TARGET_ARM) || defined(TARGET_M68K)
3242 ts->stack_base = info->start_stack;
3243 ts->heap_base = info->brk;
3244 /* This will be filled in on the first SYS_HEAPINFO call. */
3245 ts->heap_limit = 0;
3246 #endif
3247
3248 if (gdbstub_port) {
3249 gdbserver_start (gdbstub_port);
3250 gdb_handlesig(env, 0);
3251 }
3252 cpu_loop(env);
3253 /* never exits */
3254 return 0;
3255 }
QEmu