hw/pci-host/apb.c

   1 /*
   2  * QEMU Ultrasparc APB PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2012,2013 Artyom Tarasenko
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 /* XXX This file and most of its contents are somewhat misnamed.  The
  27    Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
  28    the secondary PCI bridge.  */
  29
  30 #include "hw/sysbus.h"
  31 #include "hw/pci/pci.h"
  32 #include "hw/pci/pci_host.h"
  33 #include "hw/pci/pci_bridge.h"
  34 #include "hw/pci/pci_bus.h"
  35 #include "hw/pci-host/apb.h"
  36 #include "sysemu/sysemu.h"
  37 #include "exec/address-spaces.h"
  38
  39 /* debug APB */
  40 //#define DEBUG_APB
  41
  42 #ifdef DEBUG_APB
  43 #define APB_DPRINTF(fmt, ...) \
  44 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
  45 #else
  46 #define APB_DPRINTF(fmt, ...)
  47 #endif
  48
  49 /* debug IOMMU */
  50 //#define DEBUG_IOMMU
  51
  52 #ifdef DEBUG_IOMMU
  53 #define IOMMU_DPRINTF(fmt, ...) \
  54 do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
  55 #else
  56 #define IOMMU_DPRINTF(fmt, ...)
  57 #endif
  58
  59 /*
  60  * Chipset docs:
  61  * PBM: "UltraSPARC IIi User's Manual",
  62  * http://www.sun.com/processors/manuals/805-0087.pdf
  63  *
  64  * APB: "Advanced PCI Bridge (APB) User's Manual",
  65  * http://www.sun.com/processors/manuals/805-1251.pdf
  66  */
  67
  68 #define PBM_PCI_IMR_MASK    0x7fffffff
  69 #define PBM_PCI_IMR_ENABLED 0x80000000
  70
  71 #define POR          (1U << 31)
  72 #define SOFT_POR     (1U << 30)
  73 #define SOFT_XIR     (1U << 29)
  74 #define BTN_POR      (1U << 28)
  75 #define BTN_XIR      (1U << 27)
  76 #define RESET_MASK   0xf8000000
  77 #define RESET_WCMASK 0x98000000
  78 #define RESET_WMASK  0x60000000
  79
  80 #define MAX_IVEC 0x40
  81 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
  82
  83 #define IOMMU_PAGE_SIZE_8K      (1ULL << 13)
  84 #define IOMMU_PAGE_MASK_8K      (~(IOMMU_PAGE_SIZE_8K - 1))
  85 #define IOMMU_PAGE_SIZE_64K     (1ULL << 16)
  86 #define IOMMU_PAGE_MASK_64K     (~(IOMMU_PAGE_SIZE_64K - 1))
  87
  88 #define IOMMU_NREGS             3
  89
  90 #define IOMMU_CTRL              0x0
  91 #define IOMMU_CTRL_TBW_SIZE     (1ULL << 2)
  92 #define IOMMU_CTRL_MMU_EN       (1ULL)
  93
  94 #define IOMMU_CTRL_TSB_SHIFT    16
  95
  96 #define IOMMU_BASE              0x8
  97 #define IOMMU_FLUSH             0x10
  98
  99 #define IOMMU_TTE_DATA_V        (1ULL << 63)
 100 #define IOMMU_TTE_DATA_SIZE     (1ULL << 61)
 101 #define IOMMU_TTE_DATA_W        (1ULL << 1)
 102
 103 #define IOMMU_TTE_PHYS_MASK_8K  0x1ffffffe000ULL
 104 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
 105
 106 #define IOMMU_TSB_8K_OFFSET_MASK_8M    0x00000000007fe000ULL
 107 #define IOMMU_TSB_8K_OFFSET_MASK_16M   0x0000000000ffe000ULL
 108 #define IOMMU_TSB_8K_OFFSET_MASK_32M   0x0000000001ffe000ULL
 109 #define IOMMU_TSB_8K_OFFSET_MASK_64M   0x0000000003ffe000ULL
 110 #define IOMMU_TSB_8K_OFFSET_MASK_128M  0x0000000007ffe000ULL
 111 #define IOMMU_TSB_8K_OFFSET_MASK_256M  0x000000000fffe000ULL
 112 #define IOMMU_TSB_8K_OFFSET_MASK_512M  0x000000001fffe000ULL
 113 #define IOMMU_TSB_8K_OFFSET_MASK_1G    0x000000003fffe000ULL
 114
 115 #define IOMMU_TSB_64K_OFFSET_MASK_64M  0x0000000003ff0000ULL
 116 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
 117 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
 118 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
 119 #define IOMMU_TSB_64K_OFFSET_MASK_1G   0x000000003fff0000ULL
 120 #define IOMMU_TSB_64K_OFFSET_MASK_2G   0x000000007fff0000ULL
 121
 122 typedef struct IOMMUState {
 123     AddressSpace iommu_as;
 124     MemoryRegion iommu;
 125
 126     uint64_t regs[IOMMU_NREGS];
 127 } IOMMUState;
 128
 129 #define TYPE_APB "pbm"
 130
 131 #define APB_DEVICE(obj) \
 132     OBJECT_CHECK(APBState, (obj), TYPE_APB)
 133
 134 typedef struct APBState {
 135     PCIHostState parent_obj;
 136
 137     MemoryRegion apb_config;
 138     MemoryRegion pci_config;
 139     MemoryRegion pci_mmio;
 140     MemoryRegion pci_ioport;
 141     uint64_t pci_irq_in;
 142     IOMMUState iommu;
 143     uint32_t pci_control[16];
 144     uint32_t pci_irq_map[8];
 145     uint32_t pci_err_irq_map[4];
 146     uint32_t obio_irq_map[32];
 147     qemu_irq *pbm_irqs;
 148     qemu_irq *ivec_irqs;
 149     unsigned int irq_request;
 150     uint32_t reset_control;
 151     unsigned int nr_resets;
 152 } APBState;
 153
 154 static inline void pbm_set_request(APBState *s, unsigned int irq_num)
 155 {
 156     APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
 157
 158     s->irq_request = irq_num;
 159     qemu_set_irq(s->ivec_irqs[irq_num], 1);
 160 }
 161
 162 static inline void pbm_check_irqs(APBState *s)
 163 {
 164
 165     unsigned int i;
 166
 167     /* Previous request is not acknowledged, resubmit */
 168     if (s->irq_request != NO_IRQ_REQUEST) {
 169         pbm_set_request(s, s->irq_request);
 170         return;
 171     }
 172     /* no request pending */
 173     if (s->pci_irq_in == 0ULL) {
 174         return;
 175     }
 176     for (i = 0; i < 32; i++) {
 177         if (s->pci_irq_in & (1ULL << i)) {
 178             if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
 179                 pbm_set_request(s, i);
 180                 return;
 181             }
 182         }
 183     }
 184     for (i = 32; i < 64; i++) {
 185         if (s->pci_irq_in & (1ULL << i)) {
 186             if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
 187                 pbm_set_request(s, i);
 188                 break;
 189             }
 190         }
 191     }
 192 }
 193
 194 static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
 195 {
 196     APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
 197     qemu_set_irq(s->ivec_irqs[irq_num], 0);
 198     s->irq_request = NO_IRQ_REQUEST;
 199 }
 200
 201 static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 202 {
 203     IOMMUState *is = opaque;
 204
 205     return &is->iommu_as;
 206 }
 207
 208 static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr,
 209                                          bool is_write)
 210 {
 211     IOMMUState *is = container_of(iommu, IOMMUState, iommu);
 212     hwaddr baseaddr, offset;
 213     uint64_t tte;
 214     uint32_t tsbsize;
 215     IOMMUTLBEntry ret = {
 216         .target_as = &address_space_memory,
 217         .iova = 0,
 218         .translated_addr = 0,
 219         .addr_mask = ~(hwaddr)0,
 220         .perm = IOMMU_NONE,
 221     };
 222
 223     if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
 224         /* IOMMU disabled, passthrough using standard 8K page */
 225         ret.iova = addr & IOMMU_PAGE_MASK_8K;
 226         ret.translated_addr = addr;
 227         ret.addr_mask = IOMMU_PAGE_MASK_8K;
 228         ret.perm = IOMMU_RW;
 229
 230         return ret;
 231     }
 232
 233     baseaddr = is->regs[IOMMU_BASE >> 3];
 234     tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
 235
 236     if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
 237         /* 64K */
 238         switch (tsbsize) {
 239         case 0:
 240             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
 241             break;
 242         case 1:
 243             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
 244             break;
 245         case 2:
 246             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
 247             break;
 248         case 3:
 249             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
 250             break;
 251         case 4:
 252             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
 253             break;
 254         case 5:
 255             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
 256             break;
 257         default:
 258             /* Not implemented, error */
 259             return ret;
 260         }
 261     } else {
 262         /* 8K */
 263         switch (tsbsize) {
 264         case 0:
 265             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
 266             break;
 267         case 1:
 268             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
 269             break;
 270         case 2:
 271             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
 272             break;
 273         case 3:
 274             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
 275             break;
 276         case 4:
 277             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
 278             break;
 279         case 5:
 280             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
 281             break;
 282         case 6:
 283             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
 284             break;
 285         case 7:
 286             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
 287             break;
 288         }
 289     }
 290
 291     tte = ldq_be_phys(&address_space_memory, baseaddr + offset);
 292
 293     if (!(tte & IOMMU_TTE_DATA_V)) {
 294         /* Invalid mapping */
 295         return ret;
 296     }
 297
 298     if (tte & IOMMU_TTE_DATA_W) {
 299         /* Writeable */
 300         ret.perm = IOMMU_RW;
 301     } else {
 302         ret.perm = IOMMU_RO;
 303     }
 304
 305     /* Extract phys */
 306     if (tte & IOMMU_TTE_DATA_SIZE) {
 307         /* 64K */
 308         ret.iova = addr & IOMMU_PAGE_MASK_64K;
 309         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
 310         ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
 311     } else {
 312         /* 8K */
 313         ret.iova = addr & IOMMU_PAGE_MASK_8K;
 314         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
 315         ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
 316     }
 317
 318     return ret;
 319 }
 320
 321 static MemoryRegionIOMMUOps pbm_iommu_ops = {
 322     .translate = pbm_translate_iommu,
 323 };
 324
 325 static void iommu_config_write(void *opaque, hwaddr addr,
 326                                uint64_t val, unsigned size)
 327 {
 328     IOMMUState *is = opaque;
 329
 330     IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64
 331                   " size: %d\n", addr, val, size);
 332
 333     switch (addr) {
 334     case IOMMU_CTRL:
 335         if (size == 4) {
 336             is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
 337             is->regs[IOMMU_CTRL >> 3] |= val << 32;
 338         } else {
 339             is->regs[IOMMU_CTRL >> 3] = val;
 340         }
 341         break;
 342     case IOMMU_CTRL + 0x4:
 343         is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
 344         is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
 345         break;
 346     case IOMMU_BASE:
 347         if (size == 4) {
 348             is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
 349             is->regs[IOMMU_BASE >> 3] |= val << 32;
 350         } else {
 351             is->regs[IOMMU_BASE >> 3] = val;
 352         }
 353         break;
 354     case IOMMU_BASE + 0x4:
 355         is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
 356         is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
 357         break;
 358     case IOMMU_FLUSH:
 359     case IOMMU_FLUSH + 0x4:
 360         break;
 361     default:
 362         qemu_log_mask(LOG_UNIMP,
 363                   "apb iommu: Unimplemented register write "
 364                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
 365                   addr, size, val);
 366         break;
 367     }
 368 }
 369
 370 static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size)
 371 {
 372     IOMMUState *is = opaque;
 373     uint64_t val;
 374
 375     switch (addr) {
 376     case IOMMU_CTRL:
 377         if (size == 4) {
 378             val = is->regs[IOMMU_CTRL >> 3] >> 32;
 379         } else {
 380             val = is->regs[IOMMU_CTRL >> 3];
 381         }
 382         break;
 383     case IOMMU_CTRL + 0x4:
 384         val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
 385         break;
 386     case IOMMU_BASE:
 387         if (size == 4) {
 388             val = is->regs[IOMMU_BASE >> 3] >> 32;
 389         } else {
 390             val = is->regs[IOMMU_BASE >> 3];
 391         }
 392         break;
 393     case IOMMU_BASE + 0x4:
 394         val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
 395         break;
 396     case IOMMU_FLUSH:
 397     case IOMMU_FLUSH + 0x4:
 398         val = 0;
 399         break;
 400     default:
 401         qemu_log_mask(LOG_UNIMP,
 402                       "apb iommu: Unimplemented register read "
 403                       "reg 0x%" HWADDR_PRIx " size 0x%x\n",
 404                       addr, size);
 405         val = 0;
 406         break;
 407     }
 408
 409     IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64
 410                   " size: %d\n", addr, val, size);
 411
 412     return val;
 413 }
 414
 415 static void apb_config_writel (void *opaque, hwaddr addr,
 416                                uint64_t val, unsigned size)
 417 {
 418     APBState *s = opaque;
 419     IOMMUState *is = &s->iommu;
 420
 421     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 422
 423     switch (addr & 0xffff) {
 424     case 0x30 ... 0x4f: /* DMA error registers */
 425         /* XXX: not implemented yet */
 426         break;
 427     case 0x200 ... 0x217: /* IOMMU */
 428         iommu_config_write(is, (addr & 0x1f), val, size);
 429         break;
 430     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 431         if (addr & 4) {
 432             unsigned int ino = (addr & 0x3f) >> 3;
 433             s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
 434             s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 435             if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
 436                 pbm_clear_request(s, ino);
 437             }
 438             pbm_check_irqs(s);
 439         }
 440         break;
 441     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 442         if (addr & 4) {
 443             unsigned int ino = ((addr & 0xff) >> 3);
 444             s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
 445             s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 446             if ((s->irq_request == (ino | 0x20))
 447                  && !(val & ~PBM_PCI_IMR_MASK)) {
 448                 pbm_clear_request(s, ino | 0x20);
 449             }
 450             pbm_check_irqs(s);
 451         }
 452         break;
 453     case 0x1400 ... 0x14ff: /* PCI interrupt clear */
 454         if (addr & 4) {
 455             unsigned int ino = (addr & 0xff) >> 5;
 456             if ((s->irq_request / 4)  == ino) {
 457                 pbm_clear_request(s, s->irq_request);
 458                 pbm_check_irqs(s);
 459             }
 460         }
 461         break;
 462     case 0x1800 ... 0x1860: /* OBIO interrupt clear */
 463         if (addr & 4) {
 464             unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
 465             if (s->irq_request == ino) {
 466                 pbm_clear_request(s, ino);
 467                 pbm_check_irqs(s);
 468             }
 469         }
 470         break;
 471     case 0x2000 ... 0x202f: /* PCI control */
 472         s->pci_control[(addr & 0x3f) >> 2] = val;
 473         break;
 474     case 0xf020 ... 0xf027: /* Reset control */
 475         if (addr & 4) {
 476             val &= RESET_MASK;
 477             s->reset_control &= ~(val & RESET_WCMASK);
 478             s->reset_control |= val & RESET_WMASK;
 479             if (val & SOFT_POR) {
 480                 s->nr_resets = 0;
 481                 qemu_system_reset_request();
 482             } else if (val & SOFT_XIR) {
 483                 qemu_system_reset_request();
 484             }
 485         }
 486         break;
 487     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 488     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 489     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 490     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 491         /* we don't care */
 492     default:
 493         break;
 494     }
 495 }
 496
 497 static uint64_t apb_config_readl (void *opaque,
 498                                   hwaddr addr, unsigned size)
 499 {
 500     APBState *s = opaque;
 501     IOMMUState *is = &s->iommu;
 502     uint32_t val;
 503
 504     switch (addr & 0xffff) {
 505     case 0x30 ... 0x4f: /* DMA error registers */
 506         val = 0;
 507         /* XXX: not implemented yet */
 508         break;
 509     case 0x200 ... 0x217: /* IOMMU */
 510         val = iommu_config_read(is, (addr & 0x1f), size);
 511         break;
 512     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 513         if (addr & 4) {
 514             val = s->pci_irq_map[(addr & 0x3f) >> 3];
 515         } else {
 516             val = 0;
 517         }
 518         break;
 519     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 520         if (addr & 4) {
 521             val = s->obio_irq_map[(addr & 0xff) >> 3];
 522         } else {
 523             val = 0;
 524         }
 525         break;
 526     case 0x1080 ... 0x108f: /* PCI bus error */
 527         if (addr & 4) {
 528             val = s->pci_err_irq_map[(addr & 0xf) >> 3];
 529         } else {
 530             val = 0;
 531         }
 532         break;
 533     case 0x2000 ... 0x202f: /* PCI control */
 534         val = s->pci_control[(addr & 0x3f) >> 2];
 535         break;
 536     case 0xf020 ... 0xf027: /* Reset control */
 537         if (addr & 4) {
 538             val = s->reset_control;
 539         } else {
 540             val = 0;
 541         }
 542         break;
 543     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 544     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 545     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 546     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 547         /* we don't care */
 548     default:
 549         val = 0;
 550         break;
 551     }
 552     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
 553
 554     return val;
 555 }
 556
 557 static const MemoryRegionOps apb_config_ops = {
 558     .read = apb_config_readl,
 559     .write = apb_config_writel,
 560     .endianness = DEVICE_NATIVE_ENDIAN,
 561 };
 562
 563 static void apb_pci_config_write(void *opaque, hwaddr addr,
 564                                  uint64_t val, unsigned size)
 565 {
 566     APBState *s = opaque;
 567     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 568
 569     val = qemu_bswap_len(val, size);
 570     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 571     pci_data_write(phb->bus, addr, val, size);
 572 }
 573
 574 static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
 575                                     unsigned size)
 576 {
 577     uint32_t ret;
 578     APBState *s = opaque;
 579     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 580
 581     ret = pci_data_read(phb->bus, addr, size);
 582     ret = qemu_bswap_len(ret, size);
 583     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
 584     return ret;
 585 }
 586
 587 /* The APB host has an IRQ line for each IRQ line of each slot.  */
 588 static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
 589 {
 590     return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
 591 }
 592
 593 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
 594 {
 595     int bus_offset;
 596     if (pci_dev->devfn & 1)
 597         bus_offset = 16;
 598     else
 599         bus_offset = 0;
 600     return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
 601 }
 602
 603 static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 604 {
 605     APBState *s = opaque;
 606
 607     APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
 608     /* PCI IRQ map onto the first 32 INO.  */
 609     if (irq_num < 32) {
 610         if (level) {
 611             s->pci_irq_in |= 1ULL << irq_num;
 612             if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
 613                 pbm_set_request(s, irq_num);
 614             }
 615         } else {
 616             s->pci_irq_in &= ~(1ULL << irq_num);
 617         }
 618     } else {
 619         /* OBIO IRQ map onto the next 32 INO.  */
 620         if (level) {
 621             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
 622             s->pci_irq_in |= 1ULL << irq_num;
 623             if ((s->irq_request == NO_IRQ_REQUEST)
 624                 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
 625                 pbm_set_request(s, irq_num);
 626             }
 627         } else {
 628             s->pci_irq_in &= ~(1ULL << irq_num);
 629         }
 630     }
 631 }
 632
 633 static int apb_pci_bridge_initfn(PCIDevice *dev)
 634 {
 635     int rc;
 636
 637     rc = pci_bridge_initfn(dev, TYPE_PCI_BUS);
 638     if (rc < 0) {
 639         return rc;
 640     }
 641
 642     /*
 643      * command register:
 644      * According to PCI bridge spec, after reset
 645      *   bus master bit is off
 646      *   memory space enable bit is off
 647      * According to manual (805-1251.pdf).
 648      *   the reset value should be zero unless the boot pin is tied high
 649      *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
 650      */
 651     pci_set_word(dev->config + PCI_COMMAND,
 652                  PCI_COMMAND_MEMORY);
 653     pci_set_word(dev->config + PCI_STATUS,
 654                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 655                  PCI_STATUS_DEVSEL_MEDIUM);
 656     return 0;
 657 }
 658
 659 PCIBus *pci_apb_init(hwaddr special_base,
 660                      hwaddr mem_base,
 661                      qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
 662                      qemu_irq **pbm_irqs)
 663 {
 664     DeviceState *dev;
 665     SysBusDevice *s;
 666     PCIHostState *phb;
 667     APBState *d;
 668     IOMMUState *is;
 669     PCIDevice *pci_dev;
 670     PCIBridge *br;
 671
 672     /* Ultrasparc PBM main bus */
 673     dev = qdev_create(NULL, TYPE_APB);
 674     qdev_init_nofail(dev);
 675     s = SYS_BUS_DEVICE(dev);
 676     /* apb_config */
 677     sysbus_mmio_map(s, 0, special_base);
 678     /* PCI configuration space */
 679     sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
 680     /* pci_ioport */
 681     sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
 682     d = APB_DEVICE(dev);
 683
 684     memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
 685     memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
 686
 687     phb = PCI_HOST_BRIDGE(dev);
 688     phb->bus = pci_register_bus(DEVICE(phb), "pci",
 689                                 pci_apb_set_irq, pci_pbm_map_irq, d,
 690                                 &d->pci_mmio,
 691                                 get_system_io(),
 692                                 0, 32, TYPE_PCI_BUS);
 693
 694     *pbm_irqs = d->pbm_irqs;
 695     d->ivec_irqs = ivec_irqs;
 696
 697     pci_create_simple(phb->bus, 0, "pbm-pci");
 698
 699     /* APB IOMMU */
 700     is = &d->iommu;
 701     memset(is, 0, sizeof(IOMMUState));
 702
 703     memory_region_init_iommu(&is->iommu, OBJECT(dev), &pbm_iommu_ops,
 704                              "iommu-apb", UINT64_MAX);
 705     address_space_init(&is->iommu_as, &is->iommu, "pbm-as");
 706     pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
 707
 708     /* APB secondary busses */
 709     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
 710                                    "pbm-bridge");
 711     br = PCI_BRIDGE(pci_dev);
 712     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
 713                        pci_apb_map_irq);
 714     qdev_init_nofail(&pci_dev->qdev);
 715     *bus2 = pci_bridge_get_sec_bus(br);
 716
 717     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
 718                                    "pbm-bridge");
 719     br = PCI_BRIDGE(pci_dev);
 720     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
 721                        pci_apb_map_irq);
 722     qdev_init_nofail(&pci_dev->qdev);
 723     *bus3 = pci_bridge_get_sec_bus(br);
 724
 725     return phb->bus;
 726 }
 727
 728 static void pci_pbm_reset(DeviceState *d)
 729 {
 730     unsigned int i;
 731     APBState *s = APB_DEVICE(d);
 732
 733     for (i = 0; i < 8; i++) {
 734         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
 735     }
 736     for (i = 0; i < 32; i++) {
 737         s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
 738     }
 739
 740     s->irq_request = NO_IRQ_REQUEST;
 741     s->pci_irq_in = 0ULL;
 742
 743     if (s->nr_resets++ == 0) {
 744         /* Power on reset */
 745         s->reset_control = POR;
 746     }
 747 }
 748
 749 static const MemoryRegionOps pci_config_ops = {
 750     .read = apb_pci_config_read,
 751     .write = apb_pci_config_write,
 752     .endianness = DEVICE_NATIVE_ENDIAN,
 753 };
 754
 755 static int pci_pbm_init_device(SysBusDevice *dev)
 756 {
 757     APBState *s;
 758     unsigned int i;
 759
 760     s = APB_DEVICE(dev);
 761     for (i = 0; i < 8; i++) {
 762         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
 763     }
 764     for (i = 0; i < 2; i++) {
 765         s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
 766     }
 767     for (i = 0; i < 32; i++) {
 768         s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
 769     }
 770     s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
 771     s->irq_request = NO_IRQ_REQUEST;
 772     s->pci_irq_in = 0ULL;
 773
 774     /* apb_config */
 775     memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
 776                           "apb-config", 0x10000);
 777     /* at region 0 */
 778     sysbus_init_mmio(dev, &s->apb_config);
 779
 780     memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
 781                           "apb-pci-config", 0x1000000);
 782     /* at region 1 */
 783     sysbus_init_mmio(dev, &s->pci_config);
 784
 785     /* pci_ioport */
 786     memory_region_init_alias(&s->pci_ioport, OBJECT(s), "apb-pci-ioport",
 787                              get_system_io(), 0, 0x10000);
 788     /* at region 2 */
 789     sysbus_init_mmio(dev, &s->pci_ioport);
 790
 791     return 0;
 792 }
 793
 794 static int pbm_pci_host_init(PCIDevice *d)
 795 {
 796     pci_set_word(d->config + PCI_COMMAND,
 797                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 798     pci_set_word(d->config + PCI_STATUS,
 799                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 800                  PCI_STATUS_DEVSEL_MEDIUM);
 801     return 0;
 802 }
 803
 804 static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
 805 {
 806     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 807     DeviceClass *dc = DEVICE_CLASS(klass);
 808
 809     k->init = pbm_pci_host_init;
 810     k->vendor_id = PCI_VENDOR_ID_SUN;
 811     k->device_id = PCI_DEVICE_ID_SUN_SABRE;
 812     k->class_id = PCI_CLASS_BRIDGE_HOST;
 813     /*
 814      * PCI-facing part of the host bridge, not usable without the
 815      * host-facing part, which can't be device_add'ed, yet.
 816      */
 817     dc->cannot_instantiate_with_device_add_yet = true;
 818 }
 819
 820 static const TypeInfo pbm_pci_host_info = {
 821     .name          = "pbm-pci",
 822     .parent        = TYPE_PCI_DEVICE,
 823     .instance_size = sizeof(PCIDevice),
 824     .class_init    = pbm_pci_host_class_init,
 825 };
 826
 827 static void pbm_host_class_init(ObjectClass *klass, void *data)
 828 {
 829     DeviceClass *dc = DEVICE_CLASS(klass);
 830     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 831
 832     k->init = pci_pbm_init_device;
 833     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 834     dc->reset = pci_pbm_reset;
 835 }
 836
 837 static const TypeInfo pbm_host_info = {
 838     .name          = TYPE_APB,
 839     .parent        = TYPE_PCI_HOST_BRIDGE,
 840     .instance_size = sizeof(APBState),
 841     .class_init    = pbm_host_class_init,
 842 };
 843
 844 static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
 845 {
 846     DeviceClass *dc = DEVICE_CLASS(klass);
 847     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 848
 849     k->init = apb_pci_bridge_initfn;
 850     k->exit = pci_bridge_exitfn;
 851     k->vendor_id = PCI_VENDOR_ID_SUN;
 852     k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
 853     k->revision = 0x11;
 854     k->config_write = pci_bridge_write_config;
 855     k->is_bridge = 1;
 856     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 857     dc->reset = pci_bridge_reset;
 858     dc->vmsd = &vmstate_pci_device;
 859 }
 860
 861 static const TypeInfo pbm_pci_bridge_info = {
 862     .name          = "pbm-bridge",
 863     .parent        = TYPE_PCI_BRIDGE,
 864     .class_init    = pbm_pci_bridge_class_init,
 865 };
 866
 867 static void pbm_register_types(void)
 868 {
 869     type_register_static(&pbm_host_info);
 870     type_register_static(&pbm_pci_host_info);
 871     type_register_static(&pbm_pci_bridge_info);
 872 }
 873
 874 type_init(pbm_register_types)