4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
32 #include "qemu-objects.h"
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
39 # define PCI_DPRINTF(format, ...) do { } while (0)
42 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
43 static char *pcibus_get_dev_path(DeviceState
*dev
);
44 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
45 static int pcibus_reset(BusState
*qbus
);
47 struct BusInfo pci_bus_info
= {
49 .size
= sizeof(PCIBus
),
50 .print_dev
= pcibus_dev_print
,
51 .get_dev_path
= pcibus_get_dev_path
,
52 .get_fw_dev_path
= pcibus_get_fw_dev_path
,
53 .reset
= pcibus_reset
,
54 .props
= (Property
[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
57 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
61 QEMU_PCI_CAP_SERR_BITNR
, true),
62 DEFINE_PROP_END_OF_LIST()
66 static void pci_update_mappings(PCIDevice
*d
);
67 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
68 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
69 static void pci_del_option_rom(PCIDevice
*pdev
);
71 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
72 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
77 QLIST_ENTRY(PCIHostBus
) next
;
79 static QLIST_HEAD(, PCIHostBus
) host_buses
;
81 static const VMStateDescription vmstate_pcibus
= {
84 .minimum_version_id
= 1,
85 .minimum_version_id_old
= 1,
86 .fields
= (VMStateField
[]) {
87 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
88 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
93 static int pci_bar(PCIDevice
*d
, int reg
)
97 if (reg
!= PCI_ROM_SLOT
)
98 return PCI_BASE_ADDRESS_0
+ reg
* 4;
100 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
101 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
104 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
106 return (d
->irq_state
>> irq_num
) & 0x1;
109 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
111 d
->irq_state
&= ~(0x1 << irq_num
);
112 d
->irq_state
|= level
<< irq_num
;
115 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
120 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
123 pci_dev
= bus
->parent_dev
;
125 bus
->irq_count
[irq_num
] += change
;
126 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
129 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
131 assert(irq_num
>= 0);
132 assert(irq_num
< bus
->nirq
);
133 return !!bus
->irq_count
[irq_num
];
136 /* Update interrupt status bit in config space on interrupt
138 static void pci_update_irq_status(PCIDevice
*dev
)
140 if (dev
->irq_state
) {
141 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
143 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
147 void pci_device_deassert_intx(PCIDevice
*dev
)
150 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
151 qemu_set_irq(dev
->irq
[i
], 0);
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
159 void pci_device_reset(PCIDevice
*dev
)
162 /* TODO: call the below unconditionally once all pci devices
164 if (dev
->qdev
.info
) {
165 qdev_reset_all(&dev
->qdev
);
169 pci_update_irq_status(dev
);
170 pci_device_deassert_intx(dev
);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
173 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
174 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
175 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
176 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
177 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
178 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
179 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
180 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
181 PCIIORegion
*region
= &dev
->io_regions
[r
];
186 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
187 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
188 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
190 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
193 pci_update_mappings(dev
);
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
200 void pci_bus_reset(PCIBus
*bus
)
204 for (i
= 0; i
< bus
->nirq
; i
++) {
205 bus
->irq_count
[i
] = 0;
207 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
208 if (bus
->devices
[i
]) {
209 pci_device_reset(bus
->devices
[i
]);
214 static int pcibus_reset(BusState
*qbus
)
216 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
223 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
225 struct PCIHostBus
*host
;
226 host
= g_malloc0(sizeof(*host
));
227 host
->domain
= domain
;
229 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
232 PCIBus
*pci_find_root_bus(int domain
)
234 struct PCIHostBus
*host
;
236 QLIST_FOREACH(host
, &host_buses
, next
) {
237 if (host
->domain
== domain
) {
245 int pci_find_domain(const PCIBus
*bus
)
248 struct PCIHostBus
*host
;
250 /* obtain root bus */
251 while ((d
= bus
->parent_dev
) != NULL
) {
255 QLIST_FOREACH(host
, &host_buses
, next
) {
256 if (host
->bus
== bus
) {
261 abort(); /* should not be reached */
265 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
267 MemoryRegion
*address_space_mem
,
268 MemoryRegion
*address_space_io
,
271 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
272 assert(PCI_FUNC(devfn_min
) == 0);
273 bus
->devfn_min
= devfn_min
;
274 bus
->address_space_mem
= address_space_mem
;
275 bus
->address_space_io
= address_space_io
;
278 QLIST_INIT(&bus
->child
);
279 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
281 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
284 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
285 MemoryRegion
*address_space_mem
,
286 MemoryRegion
*address_space_io
,
291 bus
= g_malloc0(sizeof(*bus
));
292 bus
->qbus
.qdev_allocated
= 1;
293 pci_bus_new_inplace(bus
, parent
, name
, address_space_mem
,
294 address_space_io
, devfn_min
);
298 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
299 void *irq_opaque
, int nirq
)
301 bus
->set_irq
= set_irq
;
302 bus
->map_irq
= map_irq
;
303 bus
->irq_opaque
= irq_opaque
;
305 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
308 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
310 bus
->qbus
.allow_hotplug
= 1;
311 bus
->hotplug
= hotplug
;
312 bus
->hotplug_qdev
= qdev
;
315 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
316 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
318 MemoryRegion
*address_space_mem
,
319 MemoryRegion
*address_space_io
,
320 uint8_t devfn_min
, int nirq
)
324 bus
= pci_bus_new(parent
, name
, address_space_mem
,
325 address_space_io
, devfn_min
);
326 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
330 int pci_bus_num(PCIBus
*s
)
333 return 0; /* pci host bridge */
334 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
337 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
339 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
343 assert(size
== pci_config_size(s
));
344 config
= g_malloc(size
);
346 qemu_get_buffer(f
, config
, size
);
347 for (i
= 0; i
< size
; ++i
) {
348 if ((config
[i
] ^ s
->config
[i
]) &
349 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
354 memcpy(s
->config
, config
, size
);
356 pci_update_mappings(s
);
362 /* just put buffer */
363 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
365 const uint8_t **v
= pv
;
366 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
367 qemu_put_buffer(f
, *v
, size
);
370 static VMStateInfo vmstate_info_pci_config
= {
371 .name
= "pci config",
372 .get
= get_pci_config_device
,
373 .put
= put_pci_config_device
,
376 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
378 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
379 uint32_t irq_state
[PCI_NUM_PINS
];
381 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
382 irq_state
[i
] = qemu_get_be32(f
);
383 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
384 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
390 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
391 pci_set_irq_state(s
, i
, irq_state
[i
]);
397 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
400 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
402 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
403 qemu_put_be32(f
, pci_irq_state(s
, i
));
407 static VMStateInfo vmstate_info_pci_irq_state
= {
408 .name
= "pci irq state",
409 .get
= get_pci_irq_state
,
410 .put
= put_pci_irq_state
,
413 const VMStateDescription vmstate_pci_device
= {
416 .minimum_version_id
= 1,
417 .minimum_version_id_old
= 1,
418 .fields
= (VMStateField
[]) {
419 VMSTATE_INT32_LE(version_id
, PCIDevice
),
420 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
421 vmstate_info_pci_config
,
422 PCI_CONFIG_SPACE_SIZE
),
423 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
424 vmstate_info_pci_irq_state
,
425 PCI_NUM_PINS
* sizeof(int32_t)),
426 VMSTATE_END_OF_LIST()
430 const VMStateDescription vmstate_pcie_device
= {
433 .minimum_version_id
= 1,
434 .minimum_version_id_old
= 1,
435 .fields
= (VMStateField
[]) {
436 VMSTATE_INT32_LE(version_id
, PCIDevice
),
437 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
438 vmstate_info_pci_config
,
439 PCIE_CONFIG_SPACE_SIZE
),
440 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
441 vmstate_info_pci_irq_state
,
442 PCI_NUM_PINS
* sizeof(int32_t)),
443 VMSTATE_END_OF_LIST()
447 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
449 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
452 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
454 /* Clear interrupt status bit: it is implicit
455 * in irq_state which we are saving.
456 * This makes us compatible with old devices
457 * which never set or clear this bit. */
458 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
459 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
460 /* Restore the interrupt status bit. */
461 pci_update_irq_status(s
);
464 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
467 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
468 /* Restore the interrupt status bit. */
469 pci_update_irq_status(s
);
473 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
475 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
476 pci_default_sub_vendor_id
);
477 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
478 pci_default_sub_device_id
);
482 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
483 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
485 int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
486 unsigned int *slotp
, unsigned int *funcp
)
491 unsigned long dom
= 0, bus
= 0;
492 unsigned int slot
= 0;
493 unsigned int func
= 0;
496 val
= strtoul(p
, &e
, 16);
502 val
= strtoul(p
, &e
, 16);
509 val
= strtoul(p
, &e
, 16);
522 val
= strtoul(p
, &e
, 16);
529 /* if funcp == NULL func is 0 */
530 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
536 /* Note: QEMU doesn't implement domains other than 0 */
537 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
548 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
551 /* strip legacy tag */
552 if (!strncmp(addr
, "pci_addr=", 9)) {
555 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
, NULL
)) {
556 monitor_printf(mon
, "Invalid pci address\n");
562 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
569 return pci_find_bus(pci_find_root_bus(0), 0);
572 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
576 *devfnp
= PCI_DEVFN(slot
, 0);
577 return pci_find_bus(pci_find_root_bus(dom
), bus
);
580 static void pci_init_cmask(PCIDevice
*dev
)
582 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
583 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
584 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
585 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
586 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
587 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
588 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
589 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
592 static void pci_init_wmask(PCIDevice
*dev
)
594 int config_size
= pci_config_size(dev
);
596 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
597 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
598 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
599 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
600 PCI_COMMAND_INTX_DISABLE
);
601 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
602 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
605 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
606 config_size
- PCI_CONFIG_HEADER_SIZE
);
609 static void pci_init_w1cmask(PCIDevice
*dev
)
612 * Note: It's okay to set w1cmask even for readonly bits as
613 * long as their value is hardwired to 0.
615 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
616 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
617 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
618 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
621 static void pci_init_wmask_bridge(PCIDevice
*d
)
623 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
624 PCI_SEC_LETENCY_TIMER */
625 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
628 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
629 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
630 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
631 PCI_MEMORY_RANGE_MASK
& 0xffff);
632 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
633 PCI_MEMORY_RANGE_MASK
& 0xffff);
634 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
635 PCI_PREF_RANGE_MASK
& 0xffff);
636 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
637 PCI_PREF_RANGE_MASK
& 0xffff);
639 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
640 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
642 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
643 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
644 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
645 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
646 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
647 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
648 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
649 PCI_BRIDGE_CTL_PARITY
|
650 PCI_BRIDGE_CTL_SERR
|
653 PCI_BRIDGE_CTL_VGA_16BIT
|
654 PCI_BRIDGE_CTL_MASTER_ABORT
|
655 PCI_BRIDGE_CTL_BUS_RESET
|
656 PCI_BRIDGE_CTL_FAST_BACK
|
657 PCI_BRIDGE_CTL_DISCARD
|
658 PCI_BRIDGE_CTL_SEC_DISCARD
|
659 PCI_BRIDGE_CTL_DISCARD_SERR
);
660 /* Below does not do anything as we never set this bit, put here for
662 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
663 PCI_BRIDGE_CTL_DISCARD_STATUS
);
666 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
668 uint8_t slot
= PCI_SLOT(dev
->devfn
);
671 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
672 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
676 * multifunction bit is interpreted in two ways as follows.
677 * - all functions must set the bit to 1.
679 * - function 0 must set the bit, but the rest function (> 0)
680 * is allowed to leave the bit to 0.
681 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
683 * So OS (at least Linux) checks the bit of only function 0,
684 * and doesn't see the bit of function > 0.
686 * The below check allows both interpretation.
688 if (PCI_FUNC(dev
->devfn
)) {
689 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
690 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
691 /* function 0 should set multifunction bit */
692 error_report("PCI: single function device can't be populated "
693 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
699 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
702 /* function 0 indicates single function, so function > 0 must be NULL */
703 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
704 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
705 error_report("PCI: %x.0 indicates single function, "
706 "but %x.%x is already populated.",
714 static void pci_config_alloc(PCIDevice
*pci_dev
)
716 int config_size
= pci_config_size(pci_dev
);
718 pci_dev
->config
= g_malloc0(config_size
);
719 pci_dev
->cmask
= g_malloc0(config_size
);
720 pci_dev
->wmask
= g_malloc0(config_size
);
721 pci_dev
->w1cmask
= g_malloc0(config_size
);
722 pci_dev
->used
= g_malloc0(config_size
);
725 static void pci_config_free(PCIDevice
*pci_dev
)
727 g_free(pci_dev
->config
);
728 g_free(pci_dev
->cmask
);
729 g_free(pci_dev
->wmask
);
730 g_free(pci_dev
->w1cmask
);
731 g_free(pci_dev
->used
);
734 /* -1 for devfn means auto assign */
735 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
736 const char *name
, int devfn
,
737 const PCIDeviceInfo
*info
)
739 PCIConfigReadFunc
*config_read
= info
->config_read
;
740 PCIConfigWriteFunc
*config_write
= info
->config_write
;
743 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
744 devfn
+= PCI_FUNC_MAX
) {
745 if (!bus
->devices
[devfn
])
748 error_report("PCI: no slot/function available for %s, all in use", name
);
751 } else if (bus
->devices
[devfn
]) {
752 error_report("PCI: slot %d function %d not available for %s, in use by %s",
753 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
757 pci_dev
->devfn
= devfn
;
758 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
759 pci_dev
->irq_state
= 0;
760 pci_config_alloc(pci_dev
);
762 pci_config_set_vendor_id(pci_dev
->config
, info
->vendor_id
);
763 pci_config_set_device_id(pci_dev
->config
, info
->device_id
);
764 pci_config_set_revision(pci_dev
->config
, info
->revision
);
765 pci_config_set_class(pci_dev
->config
, info
->class_id
);
767 if (!info
->is_bridge
) {
768 if (info
->subsystem_vendor_id
|| info
->subsystem_id
) {
769 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
770 info
->subsystem_vendor_id
);
771 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
774 pci_set_default_subsystem_id(pci_dev
);
777 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
778 assert(!info
->subsystem_vendor_id
);
779 assert(!info
->subsystem_id
);
781 pci_init_cmask(pci_dev
);
782 pci_init_wmask(pci_dev
);
783 pci_init_w1cmask(pci_dev
);
784 if (info
->is_bridge
) {
785 pci_init_wmask_bridge(pci_dev
);
787 if (pci_init_multifunction(bus
, pci_dev
)) {
788 pci_config_free(pci_dev
);
793 config_read
= pci_default_read_config
;
795 config_write
= pci_default_write_config
;
796 pci_dev
->config_read
= config_read
;
797 pci_dev
->config_write
= config_write
;
798 bus
->devices
[devfn
] = pci_dev
;
799 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
800 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
804 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
806 qemu_free_irqs(pci_dev
->irq
);
807 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
808 pci_config_free(pci_dev
);
811 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
812 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
813 int instance_size
, int devfn
,
814 PCIConfigReadFunc
*config_read
,
815 PCIConfigWriteFunc
*config_write
)
818 PCIDeviceInfo info
= {
819 .config_read
= config_read
,
820 .config_write
= config_write
,
823 pci_dev
= g_malloc0(instance_size
);
824 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
, &info
);
825 if (pci_dev
== NULL
) {
826 hw_error("PCI: can't register device\n");
831 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
836 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
837 r
= &pci_dev
->io_regions
[i
];
838 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
840 memory_region_del_subregion(r
->address_space
, r
->memory
);
844 static int pci_unregister_device(DeviceState
*dev
)
846 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
847 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
851 ret
= info
->exit(pci_dev
);
855 pci_unregister_io_regions(pci_dev
);
856 pci_del_option_rom(pci_dev
);
857 g_free(pci_dev
->romfile
);
858 do_pci_unregister_device(pci_dev
);
862 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
863 uint8_t type
, MemoryRegion
*memory
)
868 pcibus_t size
= memory_region_size(memory
);
870 assert(region_num
>= 0);
871 assert(region_num
< PCI_NUM_REGIONS
);
872 if (size
& (size
-1)) {
873 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
874 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
878 r
= &pci_dev
->io_regions
[region_num
];
879 r
->addr
= PCI_BAR_UNMAPPED
;
881 r
->filtered_size
= size
;
886 addr
= pci_bar(pci_dev
, region_num
);
887 if (region_num
== PCI_ROM_SLOT
) {
888 /* ROM enable bit is writable */
889 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
891 pci_set_long(pci_dev
->config
+ addr
, type
);
892 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
893 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
894 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
895 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
897 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
898 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
900 pci_dev
->io_regions
[region_num
].memory
= memory
;
901 pci_dev
->io_regions
[region_num
].address_space
902 = type
& PCI_BASE_ADDRESS_SPACE_IO
903 ? pci_dev
->bus
->address_space_io
904 : pci_dev
->bus
->address_space_mem
;
907 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
909 return pci_dev
->io_regions
[region_num
].addr
;
912 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
915 pcibus_t base
= *addr
;
916 pcibus_t limit
= *addr
+ *size
- 1;
919 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
920 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
922 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
923 if (!(cmd
& PCI_COMMAND_IO
)) {
927 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
932 base
= MAX(base
, pci_bridge_get_base(br
, type
));
933 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
940 *size
= limit
- base
+ 1;
943 *addr
= PCI_BAR_UNMAPPED
;
947 static pcibus_t
pci_bar_address(PCIDevice
*d
,
948 int reg
, uint8_t type
, pcibus_t size
)
950 pcibus_t new_addr
, last_addr
;
951 int bar
= pci_bar(d
, reg
);
952 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
954 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
955 if (!(cmd
& PCI_COMMAND_IO
)) {
956 return PCI_BAR_UNMAPPED
;
958 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
959 last_addr
= new_addr
+ size
- 1;
960 /* NOTE: we have only 64K ioports on PC */
961 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
962 return PCI_BAR_UNMAPPED
;
967 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
968 return PCI_BAR_UNMAPPED
;
970 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
971 new_addr
= pci_get_quad(d
->config
+ bar
);
973 new_addr
= pci_get_long(d
->config
+ bar
);
975 /* the ROM slot has a specific enable bit */
976 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
977 return PCI_BAR_UNMAPPED
;
979 new_addr
&= ~(size
- 1);
980 last_addr
= new_addr
+ size
- 1;
981 /* NOTE: we do not support wrapping */
982 /* XXX: as we cannot support really dynamic
983 mappings, we handle specific values as invalid
985 if (last_addr
<= new_addr
|| new_addr
== 0 ||
986 last_addr
== PCI_BAR_UNMAPPED
) {
987 return PCI_BAR_UNMAPPED
;
990 /* Now pcibus_t is 64bit.
991 * Check if 32 bit BAR wraps around explicitly.
992 * Without this, PC ide doesn't work well.
993 * TODO: remove this work around.
995 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
996 return PCI_BAR_UNMAPPED
;
1000 * OS is allowed to set BAR beyond its addressable
1001 * bits. For example, 32 bit OS can set 64bit bar
1002 * to >4G. Check it. TODO: we might need to support
1003 * it in the future for e.g. PAE.
1005 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
1006 return PCI_BAR_UNMAPPED
;
1012 static void pci_update_mappings(PCIDevice
*d
)
1016 pcibus_t new_addr
, filtered_size
;
1018 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1019 r
= &d
->io_regions
[i
];
1021 /* this region isn't registered */
1025 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1027 /* bridge filtering */
1028 filtered_size
= r
->size
;
1029 if (new_addr
!= PCI_BAR_UNMAPPED
) {
1030 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
1033 /* This bar isn't changed */
1034 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
1037 /* now do the real mapping */
1038 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1039 memory_region_del_subregion(r
->address_space
, r
->memory
);
1042 r
->filtered_size
= filtered_size
;
1043 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1045 * TODO: currently almost all the map funcions assumes
1046 * filtered_size == size and addr & ~(size - 1) == addr.
1047 * However with bridge filtering, they aren't always true.
1048 * Teach them such cases, such that filtered_size < size and
1049 * addr & (size - 1) != 0.
1051 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1052 memory_region_add_subregion_overlap(r
->address_space
,
1057 memory_region_add_subregion_overlap(r
->address_space
,
1066 static inline int pci_irq_disabled(PCIDevice
*d
)
1068 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1071 /* Called after interrupt disabled field update in config space,
1072 * assert/deassert interrupts if necessary.
1073 * Gets original interrupt disable bit value (before update). */
1074 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1076 int i
, disabled
= pci_irq_disabled(d
);
1077 if (disabled
== was_irq_disabled
)
1079 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1080 int state
= pci_irq_state(d
, i
);
1081 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1085 uint32_t pci_default_read_config(PCIDevice
*d
,
1086 uint32_t address
, int len
)
1090 memcpy(&val
, d
->config
+ address
, len
);
1091 return le32_to_cpu(val
);
1094 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1096 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1098 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1099 uint8_t wmask
= d
->wmask
[addr
+ i
];
1100 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1101 assert(!(wmask
& w1cmask
));
1102 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1103 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1105 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1106 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1107 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1108 range_covers_byte(addr
, l
, PCI_COMMAND
))
1109 pci_update_mappings(d
);
1111 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1112 pci_update_irq_disabled(d
, was_irq_disabled
);
1115 /***********************************************************/
1116 /* generic PCI irq support */
1118 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1119 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1121 PCIDevice
*pci_dev
= opaque
;
1124 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1128 pci_set_irq_state(pci_dev
, irq_num
, level
);
1129 pci_update_irq_status(pci_dev
);
1130 if (pci_irq_disabled(pci_dev
))
1132 pci_change_irq_level(pci_dev
, irq_num
, change
);
1135 /***********************************************************/
1136 /* monitor info on PCI */
1141 const char *fw_name
;
1142 uint16_t fw_ign_bits
;
1145 static const pci_class_desc pci_class_descriptions
[] =
1147 { 0x0001, "VGA controller", "display"},
1148 { 0x0100, "SCSI controller", "scsi"},
1149 { 0x0101, "IDE controller", "ide"},
1150 { 0x0102, "Floppy controller", "fdc"},
1151 { 0x0103, "IPI controller", "ipi"},
1152 { 0x0104, "RAID controller", "raid"},
1153 { 0x0106, "SATA controller"},
1154 { 0x0107, "SAS controller"},
1155 { 0x0180, "Storage controller"},
1156 { 0x0200, "Ethernet controller", "ethernet"},
1157 { 0x0201, "Token Ring controller", "token-ring"},
1158 { 0x0202, "FDDI controller", "fddi"},
1159 { 0x0203, "ATM controller", "atm"},
1160 { 0x0280, "Network controller"},
1161 { 0x0300, "VGA controller", "display", 0x00ff},
1162 { 0x0301, "XGA controller"},
1163 { 0x0302, "3D controller"},
1164 { 0x0380, "Display controller"},
1165 { 0x0400, "Video controller", "video"},
1166 { 0x0401, "Audio controller", "sound"},
1168 { 0x0403, "Audio controller", "sound"},
1169 { 0x0480, "Multimedia controller"},
1170 { 0x0500, "RAM controller", "memory"},
1171 { 0x0501, "Flash controller", "flash"},
1172 { 0x0580, "Memory controller"},
1173 { 0x0600, "Host bridge", "host"},
1174 { 0x0601, "ISA bridge", "isa"},
1175 { 0x0602, "EISA bridge", "eisa"},
1176 { 0x0603, "MC bridge", "mca"},
1177 { 0x0604, "PCI bridge", "pci"},
1178 { 0x0605, "PCMCIA bridge", "pcmcia"},
1179 { 0x0606, "NUBUS bridge", "nubus"},
1180 { 0x0607, "CARDBUS bridge", "cardbus"},
1181 { 0x0608, "RACEWAY bridge"},
1182 { 0x0680, "Bridge"},
1183 { 0x0700, "Serial port", "serial"},
1184 { 0x0701, "Parallel port", "parallel"},
1185 { 0x0800, "Interrupt controller", "interrupt-controller"},
1186 { 0x0801, "DMA controller", "dma-controller"},
1187 { 0x0802, "Timer", "timer"},
1188 { 0x0803, "RTC", "rtc"},
1189 { 0x0900, "Keyboard", "keyboard"},
1190 { 0x0901, "Pen", "pen"},
1191 { 0x0902, "Mouse", "mouse"},
1192 { 0x0A00, "Dock station", "dock", 0x00ff},
1193 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1194 { 0x0c00, "Fireware contorller", "fireware"},
1195 { 0x0c01, "Access bus controller", "access-bus"},
1196 { 0x0c02, "SSA controller", "ssa"},
1197 { 0x0c03, "USB controller", "usb"},
1198 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1202 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1203 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1208 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1209 d
= bus
->devices
[devfn
];
1216 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1217 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1219 bus
= pci_find_bus(bus
, bus_num
);
1222 pci_for_each_device_under_bus(bus
, fn
);
1226 static void pci_device_print(Monitor
*mon
, QDict
*device
)
1230 uint64_t addr
, size
;
1232 monitor_printf(mon
, " Bus %2" PRId64
", ", qdict_get_int(device
, "bus"));
1233 monitor_printf(mon
, "device %3" PRId64
", function %" PRId64
":\n",
1234 qdict_get_int(device
, "slot"),
1235 qdict_get_int(device
, "function"));
1236 monitor_printf(mon
, " ");
1238 qdict
= qdict_get_qdict(device
, "class_info");
1239 if (qdict_haskey(qdict
, "desc")) {
1240 monitor_printf(mon
, "%s", qdict_get_str(qdict
, "desc"));
1242 monitor_printf(mon
, "Class %04" PRId64
, qdict_get_int(qdict
, "class"));
1245 qdict
= qdict_get_qdict(device
, "id");
1246 monitor_printf(mon
, ": PCI device %04" PRIx64
":%04" PRIx64
"\n",
1247 qdict_get_int(qdict
, "device"),
1248 qdict_get_int(qdict
, "vendor"));
1250 if (qdict_haskey(device
, "irq")) {
1251 monitor_printf(mon
, " IRQ %" PRId64
".\n",
1252 qdict_get_int(device
, "irq"));
1255 if (qdict_haskey(device
, "pci_bridge")) {
1258 qdict
= qdict_get_qdict(device
, "pci_bridge");
1260 info
= qdict_get_qdict(qdict
, "bus");
1261 monitor_printf(mon
, " BUS %" PRId64
".\n",
1262 qdict_get_int(info
, "number"));
1263 monitor_printf(mon
, " secondary bus %" PRId64
".\n",
1264 qdict_get_int(info
, "secondary"));
1265 monitor_printf(mon
, " subordinate bus %" PRId64
".\n",
1266 qdict_get_int(info
, "subordinate"));
1268 info
= qdict_get_qdict(qdict
, "io_range");
1269 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1270 qdict_get_int(info
, "base"),
1271 qdict_get_int(info
, "limit"));
1273 info
= qdict_get_qdict(qdict
, "memory_range");
1275 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1276 qdict_get_int(info
, "base"),
1277 qdict_get_int(info
, "limit"));
1279 info
= qdict_get_qdict(qdict
, "prefetchable_range");
1280 monitor_printf(mon
, " prefetchable memory range "
1281 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1282 qdict_get_int(info
, "base"),
1283 qdict_get_int(info
, "limit"));
1286 QLIST_FOREACH_ENTRY(qdict_get_qlist(device
, "regions"), entry
) {
1287 qdict
= qobject_to_qdict(qlist_entry_obj(entry
));
1288 monitor_printf(mon
, " BAR%d: ", (int) qdict_get_int(qdict
, "bar"));
1290 addr
= qdict_get_int(qdict
, "address");
1291 size
= qdict_get_int(qdict
, "size");
1293 if (!strcmp(qdict_get_str(qdict
, "type"), "io")) {
1294 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1295 " [0x%04"FMT_PCIBUS
"].\n",
1296 addr
, addr
+ size
- 1);
1298 monitor_printf(mon
, "%d bit%s memory at 0x%08"FMT_PCIBUS
1299 " [0x%08"FMT_PCIBUS
"].\n",
1300 qdict_get_bool(qdict
, "mem_type_64") ? 64 : 32,
1301 qdict_get_bool(qdict
, "prefetch") ?
1302 " prefetchable" : "", addr
, addr
+ size
- 1);
1306 monitor_printf(mon
, " id \"%s\"\n", qdict_get_str(device
, "qdev_id"));
1308 if (qdict_haskey(device
, "pci_bridge")) {
1309 qdict
= qdict_get_qdict(device
, "pci_bridge");
1310 if (qdict_haskey(qdict
, "devices")) {
1312 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1313 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1319 void do_pci_info_print(Monitor
*mon
, const QObject
*data
)
1321 QListEntry
*bus
, *dev
;
1323 QLIST_FOREACH_ENTRY(qobject_to_qlist(data
), bus
) {
1324 QDict
*qdict
= qobject_to_qdict(qlist_entry_obj(bus
));
1325 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1326 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1331 static QObject
*pci_get_dev_class(const PCIDevice
*dev
)
1334 const pci_class_desc
*desc
;
1336 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1337 desc
= pci_class_descriptions
;
1338 while (desc
->desc
&& class != desc
->class)
1342 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1345 return qobject_from_jsonf("{ 'class': %d }", class);
1349 static QObject
*pci_get_dev_id(const PCIDevice
*dev
)
1351 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1352 pci_get_word(dev
->config
+ PCI_VENDOR_ID
),
1353 pci_get_word(dev
->config
+ PCI_DEVICE_ID
));
1356 static QObject
*pci_get_regions_list(const PCIDevice
*dev
)
1359 QList
*regions_list
;
1361 regions_list
= qlist_new();
1363 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1365 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1371 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1372 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1373 "'address': %" PRId64
", "
1374 "'size': %" PRId64
" }",
1375 i
, r
->addr
, r
->size
);
1377 int mem_type_64
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
;
1379 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1380 "'mem_type_64': %i, 'prefetch': %i, "
1381 "'address': %" PRId64
", "
1382 "'size': %" PRId64
" }",
1384 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
,
1388 qlist_append_obj(regions_list
, obj
);
1391 return QOBJECT(regions_list
);
1394 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
);
1396 static QObject
*pci_get_dev_dict(PCIDevice
*dev
, PCIBus
*bus
, int bus_num
)
1401 obj
= qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1404 PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
),
1405 pci_get_dev_class(dev
), pci_get_dev_id(dev
),
1406 pci_get_regions_list(dev
),
1407 dev
->qdev
.id
? dev
->qdev
.id
: "");
1409 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1410 QDict
*qdict
= qobject_to_qdict(obj
);
1411 qdict_put(qdict
, "irq", qint_from_int(dev
->config
[PCI_INTERRUPT_LINE
]));
1414 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1415 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1417 QObject
*pci_bridge
;
1419 pci_bridge
= qobject_from_jsonf("{ 'bus': "
1420 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1421 "'io_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1422 "'memory_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1423 "'prefetchable_range': { 'base': %" PRId64
", 'limit': %" PRId64
"} }",
1424 dev
->config
[PCI_PRIMARY_BUS
], dev
->config
[PCI_SECONDARY_BUS
],
1425 dev
->config
[PCI_SUBORDINATE_BUS
],
1426 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1427 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1428 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1429 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1430 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1431 PCI_BASE_ADDRESS_MEM_PREFETCH
),
1432 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1433 PCI_BASE_ADDRESS_MEM_PREFETCH
));
1435 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1436 PCIBus
*child_bus
= pci_find_bus(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1439 qdict
= qobject_to_qdict(pci_bridge
);
1440 qdict_put_obj(qdict
, "devices",
1441 pci_get_devices_list(child_bus
,
1442 dev
->config
[PCI_SECONDARY_BUS
]));
1445 qdict
= qobject_to_qdict(obj
);
1446 qdict_put_obj(qdict
, "pci_bridge", pci_bridge
);
1452 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
)
1458 dev_list
= qlist_new();
1460 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1461 dev
= bus
->devices
[devfn
];
1463 qlist_append_obj(dev_list
, pci_get_dev_dict(dev
, bus
, bus_num
));
1467 return QOBJECT(dev_list
);
1470 static QObject
*pci_get_bus_dict(PCIBus
*bus
, int bus_num
)
1472 bus
= pci_find_bus(bus
, bus_num
);
1474 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1475 bus_num
, pci_get_devices_list(bus
, bus_num
));
1481 void do_pci_info(Monitor
*mon
, QObject
**ret_data
)
1484 struct PCIHostBus
*host
;
1486 bus_list
= qlist_new();
1488 QLIST_FOREACH(host
, &host_buses
, next
) {
1489 QObject
*obj
= pci_get_bus_dict(host
->bus
, 0);
1491 qlist_append_obj(bus_list
, obj
);
1495 *ret_data
= QOBJECT(bus_list
);
1498 static const char * const pci_nic_models
[] = {
1510 static const char * const pci_nic_names
[] = {
1522 /* Initialize a PCI NIC. */
1523 /* FIXME callers should check for failure, but don't */
1524 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1525 const char *default_devaddr
)
1527 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1534 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1538 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1540 error_report("Invalid PCI device address %s for device %s",
1541 devaddr
, pci_nic_names
[i
]);
1545 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1546 dev
= &pci_dev
->qdev
;
1547 qdev_set_nic_properties(dev
, nd
);
1548 if (qdev_init(dev
) < 0)
1553 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1554 const char *default_devaddr
)
1558 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1561 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1567 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1569 pci_update_mappings(d
);
1572 void pci_bridge_update_mappings(PCIBus
*b
)
1576 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1578 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1579 pci_bridge_update_mappings(child
);
1583 /* Whether a given bus number is in range of the secondary
1584 * bus of the given bridge device. */
1585 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1587 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1588 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1589 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1590 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1593 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1601 if (pci_bus_num(bus
) == bus_num
) {
1605 /* Consider all bus numbers in range for the host pci bridge. */
1606 if (bus
->parent_dev
&&
1607 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1612 for (; bus
; bus
= sec
) {
1613 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1614 assert(sec
->parent_dev
);
1615 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1618 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1627 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1629 bus
= pci_find_bus(bus
, bus_num
);
1634 return bus
->devices
[devfn
];
1637 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1639 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1640 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1643 bool is_default_rom
;
1645 /* initialize cap_present for pci_is_express() and pci_config_size() */
1646 if (info
->is_express
) {
1647 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1650 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1651 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
,
1652 pci_dev
->devfn
, info
);
1653 if (pci_dev
== NULL
)
1655 if (qdev
->hotplugged
&& info
->no_hotplug
) {
1656 qerror_report(QERR_DEVICE_NO_HOTPLUG
, info
->qdev
.name
);
1657 do_pci_unregister_device(pci_dev
);
1661 rc
= info
->init(pci_dev
);
1663 do_pci_unregister_device(pci_dev
);
1669 is_default_rom
= false;
1670 if (pci_dev
->romfile
== NULL
&& info
->romfile
!= NULL
) {
1671 pci_dev
->romfile
= g_strdup(info
->romfile
);
1672 is_default_rom
= true;
1674 pci_add_option_rom(pci_dev
, is_default_rom
);
1677 /* Let buses differentiate between hotplug and when device is
1678 * enabled during qemu machine creation. */
1679 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1680 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1681 PCI_COLDPLUG_ENABLED
);
1683 int r
= pci_unregister_device(&pci_dev
->qdev
);
1691 static int pci_unplug_device(DeviceState
*qdev
)
1693 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1694 PCIDeviceInfo
*info
= container_of(qdev
->info
, PCIDeviceInfo
, qdev
);
1696 if (info
->no_hotplug
) {
1697 qerror_report(QERR_DEVICE_NO_HOTPLUG
, info
->qdev
.name
);
1700 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1701 PCI_HOTPLUG_DISABLED
);
1704 void pci_qdev_register(PCIDeviceInfo
*info
)
1706 info
->qdev
.init
= pci_qdev_init
;
1707 info
->qdev
.unplug
= pci_unplug_device
;
1708 info
->qdev
.exit
= pci_unregister_device
;
1709 info
->qdev
.bus_info
= &pci_bus_info
;
1710 qdev_register(&info
->qdev
);
1713 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1715 while (info
->qdev
.name
) {
1716 pci_qdev_register(info
);
1721 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1726 dev
= qdev_create(&bus
->qbus
, name
);
1727 qdev_prop_set_uint32(dev
, "addr", devfn
);
1728 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1729 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1732 PCIDevice
*pci_try_create_multifunction(PCIBus
*bus
, int devfn
,
1738 dev
= qdev_try_create(&bus
->qbus
, name
);
1742 qdev_prop_set_uint32(dev
, "addr", devfn
);
1743 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1744 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1747 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1751 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1752 qdev_init_nofail(&dev
->qdev
);
1756 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1758 return pci_create_multifunction(bus
, devfn
, false, name
);
1761 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1763 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1766 PCIDevice
*pci_try_create(PCIBus
*bus
, int devfn
, const char *name
)
1768 return pci_try_create_multifunction(bus
, devfn
, false, name
);
1771 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1773 int config_size
= pci_config_size(pdev
);
1774 int offset
= PCI_CONFIG_HEADER_SIZE
;
1776 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1779 else if (i
- offset
+ 1 == size
)
1784 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1789 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1792 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1793 prev
= next
+ PCI_CAP_LIST_NEXT
)
1794 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1802 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1804 uint8_t next
, prev
, found
= 0;
1806 if (!(pdev
->used
[offset
])) {
1810 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1812 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1813 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1814 if (next
<= offset
&& next
> found
) {
1821 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1822 This is needed for an option rom which is used for more than one device. */
1823 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1827 uint16_t rom_vendor_id
;
1828 uint16_t rom_device_id
;
1830 uint16_t pcir_offset
;
1833 /* Words in rom data are little endian (like in PCI configuration),
1834 so they can be read / written with pci_get_word / pci_set_word. */
1836 /* Only a valid rom will be patched. */
1837 rom_magic
= pci_get_word(ptr
);
1838 if (rom_magic
!= 0xaa55) {
1839 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1842 pcir_offset
= pci_get_word(ptr
+ 0x18);
1843 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1844 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1848 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1849 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1850 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1851 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1853 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1854 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1858 if (vendor_id
!= rom_vendor_id
) {
1859 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1860 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1861 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1862 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1864 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1867 if (device_id
!= rom_device_id
) {
1868 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1869 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1870 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1871 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1873 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1877 /* Add an option rom for the device */
1878 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1887 if (strlen(pdev
->romfile
) == 0)
1890 if (!pdev
->rom_bar
) {
1892 * Load rom via fw_cfg instead of creating a rom bar,
1893 * for 0.11 compatibility.
1895 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1896 if (class == 0x0300) {
1897 rom_add_vga(pdev
->romfile
);
1899 rom_add_option(pdev
->romfile
, -1);
1904 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1906 path
= g_strdup(pdev
->romfile
);
1909 size
= get_image_size(path
);
1911 error_report("%s: failed to find romfile \"%s\"",
1912 __FUNCTION__
, pdev
->romfile
);
1916 if (size
& (size
- 1)) {
1917 size
= 1 << qemu_fls(size
);
1920 if (pdev
->qdev
.info
->vmsd
)
1921 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->vmsd
->name
);
1923 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->name
);
1924 pdev
->has_rom
= true;
1925 memory_region_init_ram(&pdev
->rom
, &pdev
->qdev
, name
, size
);
1926 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1927 load_image(path
, ptr
);
1930 if (is_default_rom
) {
1931 /* Only the default rom images will be patched (if needed). */
1932 pci_patch_ids(pdev
, ptr
, size
);
1935 qemu_put_ram_ptr(ptr
);
1937 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1942 static void pci_del_option_rom(PCIDevice
*pdev
)
1947 memory_region_destroy(&pdev
->rom
);
1948 pdev
->has_rom
= false;
1953 * Reserve space and add capability to the linked list in pci config space
1956 * Find and reserve space and add capability to the linked list
1957 * in pci config space */
1958 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1959 uint8_t offset
, uint8_t size
)
1962 int i
, overlapping_cap
;
1965 offset
= pci_find_space(pdev
, size
);
1970 /* Verify that capabilities don't overlap. Note: device assignment
1971 * depends on this check to verify that the device is not broken.
1972 * Should never trigger for emulated devices, but it's helpful
1973 * for debugging these. */
1974 for (i
= offset
; i
< offset
+ size
; i
++) {
1975 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
1976 if (overlapping_cap
) {
1977 fprintf(stderr
, "ERROR: %04x:%02x:%02x.%x "
1978 "Attempt to add PCI capability %x at offset "
1979 "%x overlaps existing capability %x at offset %x\n",
1980 pci_find_domain(pdev
->bus
), pci_bus_num(pdev
->bus
),
1981 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
1982 cap_id
, offset
, overlapping_cap
, i
);
1988 config
= pdev
->config
+ offset
;
1989 config
[PCI_CAP_LIST_ID
] = cap_id
;
1990 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1991 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1992 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1993 memset(pdev
->used
+ offset
, 0xFF, size
);
1994 /* Make capability read-only by default */
1995 memset(pdev
->wmask
+ offset
, 0, size
);
1996 /* Check capability by default */
1997 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2001 /* Unlink capability from the pci config space. */
2002 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2004 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2007 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2008 /* Make capability writable again */
2009 memset(pdev
->wmask
+ offset
, 0xff, size
);
2010 memset(pdev
->w1cmask
+ offset
, 0, size
);
2011 /* Clear cmask as device-specific registers can't be checked */
2012 memset(pdev
->cmask
+ offset
, 0, size
);
2013 memset(pdev
->used
+ offset
, 0, size
);
2015 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2016 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2019 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2021 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2024 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2026 PCIDevice
*d
= (PCIDevice
*)dev
;
2027 const pci_class_desc
*desc
;
2032 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2033 desc
= pci_class_descriptions
;
2034 while (desc
->desc
&& class != desc
->class)
2037 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2039 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2042 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2043 "pci id %04x:%04x (sub %04x:%04x)\n",
2044 indent
, "", ctxt
, pci_bus_num(d
->bus
),
2045 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2046 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2047 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2048 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2049 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2050 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2051 r
= &d
->io_regions
[i
];
2054 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2055 " [0x%"FMT_PCIBUS
"]\n",
2057 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2058 r
->addr
, r
->addr
+ r
->size
- 1);
2062 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2064 PCIDevice
*d
= (PCIDevice
*)dev
;
2065 const char *name
= NULL
;
2066 const pci_class_desc
*desc
= pci_class_descriptions
;
2067 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2069 while (desc
->desc
&&
2070 (class & ~desc
->fw_ign_bits
) !=
2071 (desc
->class & ~desc
->fw_ign_bits
)) {
2076 name
= desc
->fw_name
;
2080 pstrcpy(buf
, len
, name
);
2082 snprintf(buf
, len
, "pci%04x,%04x",
2083 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2084 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2090 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2092 PCIDevice
*d
= (PCIDevice
*)dev
;
2093 char path
[50], name
[33];
2096 off
= snprintf(path
, sizeof(path
), "%s@%x",
2097 pci_dev_fw_name(dev
, name
, sizeof name
),
2098 PCI_SLOT(d
->devfn
));
2099 if (PCI_FUNC(d
->devfn
))
2100 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2101 return strdup(path
);
2104 static char *pcibus_get_dev_path(DeviceState
*dev
)
2106 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2109 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2110 * 00 is added here to make this format compatible with
2111 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2112 * Slot.Function list specifies the slot and function numbers for all
2113 * devices on the path from root to the specific device. */
2114 char domain
[] = "DDDD:00";
2115 char slot
[] = ":SS.F";
2116 int domain_len
= sizeof domain
- 1 /* For '\0' */;
2117 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2122 /* Calculate # of slots on path between device and root. */;
2124 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2128 path_len
= domain_len
+ slot_len
* slot_depth
;
2130 /* Allocate memory, fill in the terminating null byte. */
2131 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2132 path
[path_len
] = '\0';
2134 /* First field is the domain. */
2135 s
= snprintf(domain
, sizeof domain
, "%04x:00", pci_find_domain(d
->bus
));
2136 assert(s
== domain_len
);
2137 memcpy(path
, domain
, domain_len
);
2139 /* Fill in slot numbers. We walk up from device to root, so need to print
2140 * them in the reverse order, last to first. */
2141 p
= path
+ path_len
;
2142 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2144 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2145 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2146 assert(s
== slot_len
);
2147 memcpy(p
, slot
, slot_len
);
2153 static int pci_qdev_find_recursive(PCIBus
*bus
,
2154 const char *id
, PCIDevice
**pdev
)
2156 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2161 /* roughly check if given qdev is pci device */
2162 if (qdev
->info
->init
== &pci_qdev_init
&&
2163 qdev
->parent_bus
->info
== &pci_bus_info
) {
2164 *pdev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
2170 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2172 struct PCIHostBus
*host
;
2175 QLIST_FOREACH(host
, &host_buses
, next
) {
2176 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
2181 if (tmp
!= -ENODEV
) {
2189 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2191 return dev
->bus
->address_space_mem
;