hw/ppc/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/hw.h"
  29 #include "hw/ppc/ppc.h"
  30 #include "ppc405.h"
  31 #include "hw/timer/m48t59.h"
  32 #include "hw/block/flash.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/qtest.h"
  35 #include "sysemu/block-backend.h"
  36 #include "hw/boards.h"
  37 #include "qemu/log.h"
  38 #include "qemu/error-report.h"
  39 #include "hw/loader.h"
  40 #include "sysemu/blockdev.h"
  41 #include "exec/address-spaces.h"
  42
  43 #define BIOS_FILENAME "ppc405_rom.bin"
  44 #define BIOS_SIZE (2048 * 1024)
  45
  46 #define KERNEL_LOAD_ADDR 0x00000000
  47 #define INITRD_LOAD_ADDR 0x01800000
  48
  49 #define USE_FLASH_BIOS
  50
  51 //#define DEBUG_BOARD_INIT
  52
  53 /*****************************************************************************/
  54 /* PPC405EP reference board (IBM) */
  55 /* Standalone board with:
  56  * - PowerPC 405EP CPU
  57  * - SDRAM (0x00000000)
  58  * - Flash (0xFFF80000)
  59  * - SRAM  (0xFFF00000)
  60  * - NVRAM (0xF0000000)
  61  * - FPGA  (0xF0300000)
  62  */
  63 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  64 struct ref405ep_fpga_t {
  65     uint8_t reg0;
  66     uint8_t reg1;
  67 };
  68
  69 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
  70 {
  71     ref405ep_fpga_t *fpga;
  72     uint32_t ret;
  73
  74     fpga = opaque;
  75     switch (addr) {
  76     case 0x0:
  77         ret = fpga->reg0;
  78         break;
  79     case 0x1:
  80         ret = fpga->reg1;
  81         break;
  82     default:
  83         ret = 0;
  84         break;
  85     }
  86
  87     return ret;
  88 }
  89
  90 static void ref405ep_fpga_writeb (void *opaque,
  91                                   hwaddr addr, uint32_t value)
  92 {
  93     ref405ep_fpga_t *fpga;
  94
  95     fpga = opaque;
  96     switch (addr) {
  97     case 0x0:
  98         /* Read only */
  99         break;
 100     case 0x1:
 101         fpga->reg1 = value;
 102         break;
 103     default:
 104         break;
 105     }
 106 }
 107
 108 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
 109 {
 110     uint32_t ret;
 111
 112     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 113     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 114
 115     return ret;
 116 }
 117
 118 static void ref405ep_fpga_writew (void *opaque,
 119                                   hwaddr addr, uint32_t value)
 120 {
 121     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 122     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 123 }
 124
 125 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
 126 {
 127     uint32_t ret;
 128
 129     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 130     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 131     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 132     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 133
 134     return ret;
 135 }
 136
 137 static void ref405ep_fpga_writel (void *opaque,
 138                                   hwaddr addr, uint32_t value)
 139 {
 140     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 141     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 142     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 143     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 144 }
 145
 146 static const MemoryRegionOps ref405ep_fpga_ops = {
 147     .old_mmio = {
 148         .read = {
 149             ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
 150         },
 151         .write = {
 152             ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
 153         },
 154     },
 155     .endianness = DEVICE_NATIVE_ENDIAN,
 156 };
 157
 158 static void ref405ep_fpga_reset (void *opaque)
 159 {
 160     ref405ep_fpga_t *fpga;
 161
 162     fpga = opaque;
 163     fpga->reg0 = 0x00;
 164     fpga->reg1 = 0x0F;
 165 }
 166
 167 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
 168 {
 169     ref405ep_fpga_t *fpga;
 170     MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
 171
 172     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 173     memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
 174                           "fpga", 0x00000100);
 175     memory_region_add_subregion(sysmem, base, fpga_memory);
 176     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 177 }
 178
 179 static void ref405ep_init(MachineState *machine)
 180 {
 181     ram_addr_t ram_size = machine->ram_size;
 182     const char *kernel_filename = machine->kernel_filename;
 183     const char *kernel_cmdline = machine->kernel_cmdline;
 184     const char *initrd_filename = machine->initrd_filename;
 185     char *filename;
 186     ppc4xx_bd_info_t bd;
 187     CPUPPCState *env;
 188     qemu_irq *pic;
 189     MemoryRegion *bios;
 190     MemoryRegion *sram = g_new(MemoryRegion, 1);
 191     ram_addr_t bdloc;
 192     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 193     hwaddr ram_bases[2], ram_sizes[2];
 194     target_ulong sram_size;
 195     long bios_size;
 196     //int phy_addr = 0;
 197     //static int phy_addr = 1;
 198     target_ulong kernel_base, initrd_base;
 199     long kernel_size, initrd_size;
 200     int linux_boot;
 201     int fl_idx, fl_sectors, len;
 202     DriveInfo *dinfo;
 203     MemoryRegion *sysmem = get_system_memory();
 204
 205     /* XXX: fix this */
 206     memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
 207                                          0x08000000);
 208     ram_bases[0] = 0;
 209     ram_sizes[0] = 0x08000000;
 210     memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
 211     ram_bases[1] = 0x00000000;
 212     ram_sizes[1] = 0x00000000;
 213     ram_size = 128 * 1024 * 1024;
 214 #ifdef DEBUG_BOARD_INIT
 215     printf("%s: register cpu\n", __func__);
 216 #endif
 217     env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 218                         33333333, &pic, kernel_filename == NULL ? 0 : 1);
 219     /* allocate SRAM */
 220     sram_size = 512 * 1024;
 221     memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
 222                            &error_fatal);
 223     vmstate_register_ram_global(sram);
 224     memory_region_add_subregion(sysmem, 0xFFF00000, sram);
 225     /* allocate and load BIOS */
 226 #ifdef DEBUG_BOARD_INIT
 227     printf("%s: register BIOS\n", __func__);
 228 #endif
 229     fl_idx = 0;
 230 #ifdef USE_FLASH_BIOS
 231     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 232     if (dinfo) {
 233         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 234
 235         bios_size = blk_getlength(blk);
 236         fl_sectors = (bios_size + 65535) >> 16;
 237 #ifdef DEBUG_BOARD_INIT
 238         printf("Register parallel flash %d size %lx"
 239                " at addr %lx '%s' %d\n",
 240                fl_idx, bios_size, -bios_size,
 241                blk_name(blk), fl_sectors);
 242 #endif
 243         pflash_cfi02_register((uint32_t)(-bios_size),
 244                               NULL, "ef405ep.bios", bios_size,
 245                               blk, 65536, fl_sectors, 1,
 246                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 247                               1);
 248         fl_idx++;
 249     } else
 250 #endif
 251     {
 252 #ifdef DEBUG_BOARD_INIT
 253         printf("Load BIOS from file\n");
 254 #endif
 255         bios = g_new(MemoryRegion, 1);
 256         memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
 257                                &error_fatal);
 258         vmstate_register_ram_global(bios);
 259
 260         if (bios_name == NULL)
 261             bios_name = BIOS_FILENAME;
 262         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 263         if (filename) {
 264             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 265             g_free(filename);
 266             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 267                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 268                 exit(1);
 269             }
 270             bios_size = (bios_size + 0xfff) & ~0xfff;
 271             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 272         } else if (!qtest_enabled() || kernel_filename != NULL) {
 273             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 274             exit(1);
 275         } else {
 276             /* Avoid an uninitialized variable warning */
 277             bios_size = -1;
 278         }
 279         memory_region_set_readonly(bios, true);
 280     }
 281     /* Register FPGA */
 282 #ifdef DEBUG_BOARD_INIT
 283     printf("%s: register FPGA\n", __func__);
 284 #endif
 285     ref405ep_fpga_init(sysmem, 0xF0300000);
 286     /* Register NVRAM */
 287 #ifdef DEBUG_BOARD_INIT
 288     printf("%s: register NVRAM\n", __func__);
 289 #endif
 290     m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
 291     /* Load kernel */
 292     linux_boot = (kernel_filename != NULL);
 293     if (linux_boot) {
 294 #ifdef DEBUG_BOARD_INIT
 295         printf("%s: load kernel\n", __func__);
 296 #endif
 297         memset(&bd, 0, sizeof(bd));
 298         bd.bi_memstart = 0x00000000;
 299         bd.bi_memsize = ram_size;
 300         bd.bi_flashstart = -bios_size;
 301         bd.bi_flashsize = -bios_size;
 302         bd.bi_flashoffset = 0;
 303         bd.bi_sramstart = 0xFFF00000;
 304         bd.bi_sramsize = sram_size;
 305         bd.bi_bootflags = 0;
 306         bd.bi_intfreq = 133333333;
 307         bd.bi_busfreq = 33333333;
 308         bd.bi_baudrate = 115200;
 309         bd.bi_s_version[0] = 'Q';
 310         bd.bi_s_version[1] = 'M';
 311         bd.bi_s_version[2] = 'U';
 312         bd.bi_s_version[3] = '\0';
 313         bd.bi_r_version[0] = 'Q';
 314         bd.bi_r_version[1] = 'E';
 315         bd.bi_r_version[2] = 'M';
 316         bd.bi_r_version[3] = 'U';
 317         bd.bi_r_version[4] = '\0';
 318         bd.bi_procfreq = 133333333;
 319         bd.bi_plb_busfreq = 33333333;
 320         bd.bi_pci_busfreq = 33333333;
 321         bd.bi_opbfreq = 33333333;
 322         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 323         env->gpr[3] = bdloc;
 324         kernel_base = KERNEL_LOAD_ADDR;
 325         /* now we can load the kernel */
 326         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 327                                           ram_size - kernel_base);
 328         if (kernel_size < 0) {
 329             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 330                     kernel_filename);
 331             exit(1);
 332         }
 333         printf("Load kernel size %ld at " TARGET_FMT_lx,
 334                kernel_size, kernel_base);
 335         /* load initrd */
 336         if (initrd_filename) {
 337             initrd_base = INITRD_LOAD_ADDR;
 338             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 339                                               ram_size - initrd_base);
 340             if (initrd_size < 0) {
 341                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 342                         initrd_filename);
 343                 exit(1);
 344             }
 345         } else {
 346             initrd_base = 0;
 347             initrd_size = 0;
 348         }
 349         env->gpr[4] = initrd_base;
 350         env->gpr[5] = initrd_size;
 351         if (kernel_cmdline != NULL) {
 352             len = strlen(kernel_cmdline);
 353             bdloc -= ((len + 255) & ~255);
 354             cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
 355             env->gpr[6] = bdloc;
 356             env->gpr[7] = bdloc + len;
 357         } else {
 358             env->gpr[6] = 0;
 359             env->gpr[7] = 0;
 360         }
 361         env->nip = KERNEL_LOAD_ADDR;
 362     } else {
 363         kernel_base = 0;
 364         kernel_size = 0;
 365         initrd_base = 0;
 366         initrd_size = 0;
 367         bdloc = 0;
 368     }
 369 #ifdef DEBUG_BOARD_INIT
 370     printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
 371     printf("%s: Done\n", __func__);
 372 #endif
 373 }
 374
 375 static void ref405ep_class_init(ObjectClass *oc, void *data)
 376 {
 377     MachineClass *mc = MACHINE_CLASS(oc);
 378
 379     mc->desc = "ref405ep";
 380     mc->init = ref405ep_init;
 381 }
 382
 383 static const TypeInfo ref405ep_type = {
 384     .name = MACHINE_TYPE_NAME("ref405ep"),
 385     .parent = TYPE_MACHINE,
 386     .class_init = ref405ep_class_init,
 387 };
 388
 389 /*****************************************************************************/
 390 /* AMCC Taihu evaluation board */
 391 /* - PowerPC 405EP processor
 392  * - SDRAM               128 MB at 0x00000000
 393  * - Boot flash          2 MB   at 0xFFE00000
 394  * - Application flash   32 MB  at 0xFC000000
 395  * - 2 serial ports
 396  * - 2 ethernet PHY
 397  * - 1 USB 1.1 device    0x50000000
 398  * - 1 LCD display       0x50100000
 399  * - 1 CPLD              0x50100000
 400  * - 1 I2C EEPROM
 401  * - 1 I2C thermal sensor
 402  * - a set of LEDs
 403  * - bit-bang SPI port using GPIOs
 404  * - 1 EBC interface connector 0 0x50200000
 405  * - 1 cardbus controller + expansion slot.
 406  * - 1 PCI expansion slot.
 407  */
 408 typedef struct taihu_cpld_t taihu_cpld_t;
 409 struct taihu_cpld_t {
 410     uint8_t reg0;
 411     uint8_t reg1;
 412 };
 413
 414 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
 415 {
 416     taihu_cpld_t *cpld;
 417     uint32_t ret;
 418
 419     cpld = opaque;
 420     switch (addr) {
 421     case 0x0:
 422         ret = cpld->reg0;
 423         break;
 424     case 0x1:
 425         ret = cpld->reg1;
 426         break;
 427     default:
 428         ret = 0;
 429         break;
 430     }
 431
 432     return ret;
 433 }
 434
 435 static void taihu_cpld_write(void *opaque, hwaddr addr,
 436                              uint64_t value, unsigned size)
 437 {
 438     taihu_cpld_t *cpld;
 439
 440     cpld = opaque;
 441     switch (addr) {
 442     case 0x0:
 443         /* Read only */
 444         break;
 445     case 0x1:
 446         cpld->reg1 = value;
 447         break;
 448     default:
 449         break;
 450     }
 451 }
 452
 453 static const MemoryRegionOps taihu_cpld_ops = {
 454     .read = taihu_cpld_read,
 455     .write = taihu_cpld_write,
 456     .impl = {
 457         .min_access_size = 1,
 458         .max_access_size = 1,
 459     },
 460     .endianness = DEVICE_NATIVE_ENDIAN,
 461 };
 462
 463 static void taihu_cpld_reset (void *opaque)
 464 {
 465     taihu_cpld_t *cpld;
 466
 467     cpld = opaque;
 468     cpld->reg0 = 0x01;
 469     cpld->reg1 = 0x80;
 470 }
 471
 472 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
 473 {
 474     taihu_cpld_t *cpld;
 475     MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
 476
 477     cpld = g_malloc0(sizeof(taihu_cpld_t));
 478     memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
 479     memory_region_add_subregion(sysmem, base, cpld_memory);
 480     qemu_register_reset(&taihu_cpld_reset, cpld);
 481 }
 482
 483 static void taihu_405ep_init(MachineState *machine)
 484 {
 485     ram_addr_t ram_size = machine->ram_size;
 486     const char *kernel_filename = machine->kernel_filename;
 487     const char *initrd_filename = machine->initrd_filename;
 488     char *filename;
 489     qemu_irq *pic;
 490     MemoryRegion *sysmem = get_system_memory();
 491     MemoryRegion *bios;
 492     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 493     MemoryRegion *ram = g_malloc0(sizeof(*ram));
 494     hwaddr ram_bases[2], ram_sizes[2];
 495     long bios_size;
 496     target_ulong kernel_base, initrd_base;
 497     long kernel_size, initrd_size;
 498     int linux_boot;
 499     int fl_idx, fl_sectors;
 500     DriveInfo *dinfo;
 501
 502     /* RAM is soldered to the board so the size cannot be changed */
 503     ram_size = 0x08000000;
 504     memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
 505                                          ram_size);
 506
 507     ram_bases[0] = 0;
 508     ram_sizes[0] = 0x04000000;
 509     memory_region_init_alias(&ram_memories[0], NULL,
 510                              "taihu_405ep.ram-0", ram, ram_bases[0],
 511                              ram_sizes[0]);
 512     ram_bases[1] = 0x04000000;
 513     ram_sizes[1] = 0x04000000;
 514     memory_region_init_alias(&ram_memories[1], NULL,
 515                              "taihu_405ep.ram-1", ram, ram_bases[1],
 516                              ram_sizes[1]);
 517 #ifdef DEBUG_BOARD_INIT
 518     printf("%s: register cpu\n", __func__);
 519 #endif
 520     ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 521                   33333333, &pic, kernel_filename == NULL ? 0 : 1);
 522     /* allocate and load BIOS */
 523 #ifdef DEBUG_BOARD_INIT
 524     printf("%s: register BIOS\n", __func__);
 525 #endif
 526     fl_idx = 0;
 527 #if defined(USE_FLASH_BIOS)
 528     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 529     if (dinfo) {
 530         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 531
 532         bios_size = blk_getlength(blk);
 533         /* XXX: should check that size is 2MB */
 534         //        bios_size = 2 * 1024 * 1024;
 535         fl_sectors = (bios_size + 65535) >> 16;
 536 #ifdef DEBUG_BOARD_INIT
 537         printf("Register parallel flash %d size %lx"
 538                " at addr %lx '%s' %d\n",
 539                fl_idx, bios_size, -bios_size,
 540                blk_name(blk), fl_sectors);
 541 #endif
 542         pflash_cfi02_register((uint32_t)(-bios_size),
 543                               NULL, "taihu_405ep.bios", bios_size,
 544                               blk, 65536, fl_sectors, 1,
 545                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 546                               1);
 547         fl_idx++;
 548     } else
 549 #endif
 550     {
 551 #ifdef DEBUG_BOARD_INIT
 552         printf("Load BIOS from file\n");
 553 #endif
 554         if (bios_name == NULL)
 555             bios_name = BIOS_FILENAME;
 556         bios = g_new(MemoryRegion, 1);
 557         memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
 558                                &error_fatal);
 559         vmstate_register_ram_global(bios);
 560         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 561         if (filename) {
 562             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 563             g_free(filename);
 564             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 565                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 566                 exit(1);
 567             }
 568             bios_size = (bios_size + 0xfff) & ~0xfff;
 569             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 570         } else if (!qtest_enabled()) {
 571             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 572             exit(1);
 573         }
 574         memory_region_set_readonly(bios, true);
 575     }
 576     /* Register Linux flash */
 577     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 578     if (dinfo) {
 579         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 580
 581         bios_size = blk_getlength(blk);
 582         /* XXX: should check that size is 32MB */
 583         bios_size = 32 * 1024 * 1024;
 584         fl_sectors = (bios_size + 65535) >> 16;
 585 #ifdef DEBUG_BOARD_INIT
 586         printf("Register parallel flash %d size %lx"
 587                " at addr " TARGET_FMT_lx " '%s'\n",
 588                fl_idx, bios_size, (target_ulong)0xfc000000,
 589                blk_name(blk));
 590 #endif
 591         pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
 592                               blk, 65536, fl_sectors, 1,
 593                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 594                               1);
 595         fl_idx++;
 596     }
 597     /* Register CLPD & LCD display */
 598 #ifdef DEBUG_BOARD_INIT
 599     printf("%s: register CPLD\n", __func__);
 600 #endif
 601     taihu_cpld_init(sysmem, 0x50100000);
 602     /* Load kernel */
 603     linux_boot = (kernel_filename != NULL);
 604     if (linux_boot) {
 605 #ifdef DEBUG_BOARD_INIT
 606         printf("%s: load kernel\n", __func__);
 607 #endif
 608         kernel_base = KERNEL_LOAD_ADDR;
 609         /* now we can load the kernel */
 610         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 611                                           ram_size - kernel_base);
 612         if (kernel_size < 0) {
 613             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 614                     kernel_filename);
 615             exit(1);
 616         }
 617         /* load initrd */
 618         if (initrd_filename) {
 619             initrd_base = INITRD_LOAD_ADDR;
 620             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 621                                               ram_size - initrd_base);
 622             if (initrd_size < 0) {
 623                 fprintf(stderr,
 624                         "qemu: could not load initial ram disk '%s'\n",
 625                         initrd_filename);
 626                 exit(1);
 627             }
 628         } else {
 629             initrd_base = 0;
 630             initrd_size = 0;
 631         }
 632     } else {
 633         kernel_base = 0;
 634         kernel_size = 0;
 635         initrd_base = 0;
 636         initrd_size = 0;
 637     }
 638 #ifdef DEBUG_BOARD_INIT
 639     printf("%s: Done\n", __func__);
 640 #endif
 641 }
 642
 643 static void taihu_class_init(ObjectClass *oc, void *data)
 644 {
 645     MachineClass *mc = MACHINE_CLASS(oc);
 646
 647     mc->desc = "taihu";
 648     mc->init = taihu_405ep_init;
 649 }
 650
 651 static const TypeInfo taihu_type = {
 652     .name = MACHINE_TYPE_NAME("taihu"),
 653     .parent = TYPE_MACHINE,
 654     .class_init = taihu_class_init,
 655 };
 656
 657 static void ppc405_machine_init(void)
 658 {
 659     type_register_static(&ref405ep_type);
 660     type_register_static(&taihu_type);
 661 }
 662
 663 type_init(ppc405_machine_init)