hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/arm/arm.h"
  30 #include "hw/arm/primecell.h"
  31 #include "hw/devices.h"
  32 #include "net/net.h"
  33 #include "sysemu/sysemu.h"
  34 #include "hw/boards.h"
  35 #include "hw/loader.h"
  36 #include "exec/address-spaces.h"
  37 #include "sysemu/block-backend.h"
  38 #include "hw/block/flash.h"
  39 #include "sysemu/device_tree.h"
  40 #include "qemu/error-report.h"
  41 #include <libfdt.h>
  42 #include "hw/char/pl011.h"
  43
  44 #define VEXPRESS_BOARD_ID 0x8e0
  45 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  46 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  47
  48 /* Number of virtio transports to create (0..8; limited by
  49  * number of available IRQ lines).
  50  */
  51 #define NUM_VIRTIO_TRANSPORTS 4
  52
  53 /* Address maps for peripherals:
  54  * the Versatile Express motherboard has two possible maps,
  55  * the "legacy" one (used for A9) and the "Cortex-A Series"
  56  * map (used for newer cores).
  57  * Individual daughterboards can also have different maps for
  58  * their peripherals.
  59  */
  60
  61 enum {
  62     VE_SYSREGS,
  63     VE_SP810,
  64     VE_SERIALPCI,
  65     VE_PL041,
  66     VE_MMCI,
  67     VE_KMI0,
  68     VE_KMI1,
  69     VE_UART0,
  70     VE_UART1,
  71     VE_UART2,
  72     VE_UART3,
  73     VE_WDT,
  74     VE_TIMER01,
  75     VE_TIMER23,
  76     VE_SERIALDVI,
  77     VE_RTC,
  78     VE_COMPACTFLASH,
  79     VE_CLCD,
  80     VE_NORFLASH0,
  81     VE_NORFLASH1,
  82     VE_NORFLASHALIAS,
  83     VE_SRAM,
  84     VE_VIDEORAM,
  85     VE_ETHERNET,
  86     VE_USB,
  87     VE_DAPROM,
  88     VE_VIRTIO,
  89 };
  90
  91 static hwaddr motherboard_legacy_map[] = {
  92     [VE_NORFLASHALIAS] = 0,
  93     /* CS7: 0x10000000 .. 0x10020000 */
  94     [VE_SYSREGS] = 0x10000000,
  95     [VE_SP810] = 0x10001000,
  96     [VE_SERIALPCI] = 0x10002000,
  97     [VE_PL041] = 0x10004000,
  98     [VE_MMCI] = 0x10005000,
  99     [VE_KMI0] = 0x10006000,
 100     [VE_KMI1] = 0x10007000,
 101     [VE_UART0] = 0x10009000,
 102     [VE_UART1] = 0x1000a000,
 103     [VE_UART2] = 0x1000b000,
 104     [VE_UART3] = 0x1000c000,
 105     [VE_WDT] = 0x1000f000,
 106     [VE_TIMER01] = 0x10011000,
 107     [VE_TIMER23] = 0x10012000,
 108     [VE_VIRTIO] = 0x10013000,
 109     [VE_SERIALDVI] = 0x10016000,
 110     [VE_RTC] = 0x10017000,
 111     [VE_COMPACTFLASH] = 0x1001a000,
 112     [VE_CLCD] = 0x1001f000,
 113     /* CS0: 0x40000000 .. 0x44000000 */
 114     [VE_NORFLASH0] = 0x40000000,
 115     /* CS1: 0x44000000 .. 0x48000000 */
 116     [VE_NORFLASH1] = 0x44000000,
 117     /* CS2: 0x48000000 .. 0x4a000000 */
 118     [VE_SRAM] = 0x48000000,
 119     /* CS3: 0x4c000000 .. 0x50000000 */
 120     [VE_VIDEORAM] = 0x4c000000,
 121     [VE_ETHERNET] = 0x4e000000,
 122     [VE_USB] = 0x4f000000,
 123 };
 124
 125 static hwaddr motherboard_aseries_map[] = {
 126     [VE_NORFLASHALIAS] = 0,
 127     /* CS0: 0x08000000 .. 0x0c000000 */
 128     [VE_NORFLASH0] = 0x08000000,
 129     /* CS4: 0x0c000000 .. 0x10000000 */
 130     [VE_NORFLASH1] = 0x0c000000,
 131     /* CS5: 0x10000000 .. 0x14000000 */
 132     /* CS1: 0x14000000 .. 0x18000000 */
 133     [VE_SRAM] = 0x14000000,
 134     /* CS2: 0x18000000 .. 0x1c000000 */
 135     [VE_VIDEORAM] = 0x18000000,
 136     [VE_ETHERNET] = 0x1a000000,
 137     [VE_USB] = 0x1b000000,
 138     /* CS3: 0x1c000000 .. 0x20000000 */
 139     [VE_DAPROM] = 0x1c000000,
 140     [VE_SYSREGS] = 0x1c010000,
 141     [VE_SP810] = 0x1c020000,
 142     [VE_SERIALPCI] = 0x1c030000,
 143     [VE_PL041] = 0x1c040000,
 144     [VE_MMCI] = 0x1c050000,
 145     [VE_KMI0] = 0x1c060000,
 146     [VE_KMI1] = 0x1c070000,
 147     [VE_UART0] = 0x1c090000,
 148     [VE_UART1] = 0x1c0a0000,
 149     [VE_UART2] = 0x1c0b0000,
 150     [VE_UART3] = 0x1c0c0000,
 151     [VE_WDT] = 0x1c0f0000,
 152     [VE_TIMER01] = 0x1c110000,
 153     [VE_TIMER23] = 0x1c120000,
 154     [VE_VIRTIO] = 0x1c130000,
 155     [VE_SERIALDVI] = 0x1c160000,
 156     [VE_RTC] = 0x1c170000,
 157     [VE_COMPACTFLASH] = 0x1c1a0000,
 158     [VE_CLCD] = 0x1c1f0000,
 159 };
 160
 161 /* Structure defining the peculiarities of a specific daughterboard */
 162
 163 typedef struct VEDBoardInfo VEDBoardInfo;
 164
 165 typedef struct {
 166     MachineClass parent;
 167     VEDBoardInfo *daughterboard;
 168 } VexpressMachineClass;
 169
 170 typedef struct {
 171     MachineState parent;
 172     bool secure;
 173 } VexpressMachineState;
 174
 175 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 176 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 177 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 178 #define VEXPRESS_MACHINE(obj) \
 179     OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE)
 180 #define VEXPRESS_MACHINE_GET_CLASS(obj) \
 181     OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE)
 182 #define VEXPRESS_MACHINE_CLASS(klass) \
 183     OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE)
 184
 185 typedef void DBoardInitFn(const VexpressMachineState *machine,
 186                           ram_addr_t ram_size,
 187                           const char *cpu_model,
 188                           qemu_irq *pic);
 189
 190 struct VEDBoardInfo {
 191     struct arm_boot_info bootinfo;
 192     const hwaddr *motherboard_map;
 193     hwaddr loader_start;
 194     const hwaddr gic_cpu_if_addr;
 195     uint32_t proc_id;
 196     uint32_t num_voltage_sensors;
 197     const uint32_t *voltages;
 198     uint32_t num_clocks;
 199     const uint32_t *clocks;
 200     DBoardInitFn *init;
 201 };
 202
 203 static void init_cpus(const char *cpu_model, const char *privdev,
 204                       hwaddr periphbase, qemu_irq *pic, bool secure)
 205 {
 206     ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 207     DeviceState *dev;
 208     SysBusDevice *busdev;
 209     int n;
 210
 211     if (!cpu_oc) {
 212         fprintf(stderr, "Unable to find CPU definition\n");
 213         exit(1);
 214     }
 215
 216     /* Create the actual CPUs */
 217     for (n = 0; n < smp_cpus; n++) {
 218         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 219
 220         if (!secure) {
 221             object_property_set_bool(cpuobj, false, "has_el3", NULL);
 222         }
 223
 224         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 225             object_property_set_int(cpuobj, periphbase,
 226                                     "reset-cbar", &error_abort);
 227         }
 228         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 229     }
 230
 231     /* Create the private peripheral devices (including the GIC);
 232      * this must happen after the CPUs are created because a15mpcore_priv
 233      * wires itself up to the CPU's generic_timer gpio out lines.
 234      */
 235     dev = qdev_create(NULL, privdev);
 236     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 237     qdev_init_nofail(dev);
 238     busdev = SYS_BUS_DEVICE(dev);
 239     sysbus_mmio_map(busdev, 0, periphbase);
 240
 241     /* Interrupts [42:0] are from the motherboard;
 242      * [47:43] are reserved; [63:48] are daughterboard
 243      * peripherals. Note that some documentation numbers
 244      * external interrupts starting from 32 (because there
 245      * are internal interrupts 0..31).
 246      */
 247     for (n = 0; n < 64; n++) {
 248         pic[n] = qdev_get_gpio_in(dev, n);
 249     }
 250
 251     /* Connect the CPUs to the GIC */
 252     for (n = 0; n < smp_cpus; n++) {
 253         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 254
 255         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 256         sysbus_connect_irq(busdev, n + smp_cpus,
 257                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 258     }
 259 }
 260
 261 static void a9_daughterboard_init(const VexpressMachineState *vms,
 262                                   ram_addr_t ram_size,
 263                                   const char *cpu_model,
 264                                   qemu_irq *pic)
 265 {
 266     MemoryRegion *sysmem = get_system_memory();
 267     MemoryRegion *ram = g_new(MemoryRegion, 1);
 268     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 269     ram_addr_t low_ram_size;
 270
 271     if (!cpu_model) {
 272         cpu_model = "cortex-a9";
 273     }
 274
 275     if (ram_size > 0x40000000) {
 276         /* 1GB is the maximum the address space permits */
 277         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 278         exit(1);
 279     }
 280
 281     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 282                                          ram_size);
 283     low_ram_size = ram_size;
 284     if (low_ram_size > 0x4000000) {
 285         low_ram_size = 0x4000000;
 286     }
 287     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 288      * address space should in theory be remappable to various
 289      * things including ROM or RAM; we always map the RAM there.
 290      */
 291     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
 292     memory_region_add_subregion(sysmem, 0x0, lowram);
 293     memory_region_add_subregion(sysmem, 0x60000000, ram);
 294
 295     /* 0x1e000000 A9MPCore (SCU) private memory region */
 296     init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure);
 297
 298     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 299
 300     /* 0x10020000 PL111 CLCD (daughterboard) */
 301     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 302
 303     /* 0x10060000 AXI RAM */
 304     /* 0x100e0000 PL341 Dynamic Memory Controller */
 305     /* 0x100e1000 PL354 Static Memory Controller */
 306     /* 0x100e2000 System Configuration Controller */
 307
 308     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 309     /* 0x100e5000 SP805 Watchdog module */
 310     /* 0x100e6000 BP147 TrustZone Protection Controller */
 311     /* 0x100e9000 PL301 'Fast' AXI matrix */
 312     /* 0x100ea000 PL301 'Slow' AXI matrix */
 313     /* 0x100ec000 TrustZone Address Space Controller */
 314     /* 0x10200000 CoreSight debug APB */
 315     /* 0x1e00a000 PL310 L2 Cache Controller */
 316     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 317 }
 318
 319 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 320  * values are in microvolts.
 321  */
 322 static const uint32_t a9_voltages[] = {
 323     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 324     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 325     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 326     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 327     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 328     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 329 };
 330
 331 /* Reset values for daughterboard oscillators (in Hz) */
 332 static const uint32_t a9_clocks[] = {
 333     45000000, /* AMBA AXI ACLK: 45MHz */
 334     23750000, /* daughterboard CLCD clock: 23.75MHz */
 335     66670000, /* Test chip reference clock: 66.67MHz */
 336 };
 337
 338 static VEDBoardInfo a9_daughterboard = {
 339     .motherboard_map = motherboard_legacy_map,
 340     .loader_start = 0x60000000,
 341     .gic_cpu_if_addr = 0x1e000100,
 342     .proc_id = 0x0c000191,
 343     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 344     .voltages = a9_voltages,
 345     .num_clocks = ARRAY_SIZE(a9_clocks),
 346     .clocks = a9_clocks,
 347     .init = a9_daughterboard_init,
 348 };
 349
 350 static void a15_daughterboard_init(const VexpressMachineState *vms,
 351                                    ram_addr_t ram_size,
 352                                    const char *cpu_model,
 353                                    qemu_irq *pic)
 354 {
 355     MemoryRegion *sysmem = get_system_memory();
 356     MemoryRegion *ram = g_new(MemoryRegion, 1);
 357     MemoryRegion *sram = g_new(MemoryRegion, 1);
 358
 359     if (!cpu_model) {
 360         cpu_model = "cortex-a15";
 361     }
 362
 363     {
 364         /* We have to use a separate 64 bit variable here to avoid the gcc
 365          * "comparison is always false due to limited range of data type"
 366          * warning if we are on a host where ram_addr_t is 32 bits.
 367          */
 368         uint64_t rsz = ram_size;
 369         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 370             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 371             exit(1);
 372         }
 373     }
 374
 375     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 376                                          ram_size);
 377     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 378     memory_region_add_subregion(sysmem, 0x80000000, ram);
 379
 380     /* 0x2c000000 A15MPCore private memory region (GIC) */
 381     init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure);
 382
 383     /* A15 daughterboard peripherals: */
 384
 385     /* 0x20000000: CoreSight interfaces: not modelled */
 386     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 387     /* 0x2a420000: SCC: not modelled */
 388     /* 0x2a430000: system counter: not modelled */
 389     /* 0x2b000000: HDLCD controller: not modelled */
 390     /* 0x2b060000: SP805 watchdog: not modelled */
 391     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 392     /* 0x2e000000: system SRAM */
 393     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 394                            &error_fatal);
 395     vmstate_register_ram_global(sram);
 396     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 397
 398     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 399     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 400 }
 401
 402 static const uint32_t a15_voltages[] = {
 403     900000, /* Vcore: 0.9V : CPU core voltage */
 404 };
 405
 406 static const uint32_t a15_clocks[] = {
 407     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 408     0, /* OSCCLK1: reserved */
 409     0, /* OSCCLK2: reserved */
 410     0, /* OSCCLK3: reserved */
 411     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 412     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 413     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 414     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 415     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 416 };
 417
 418 static VEDBoardInfo a15_daughterboard = {
 419     .motherboard_map = motherboard_aseries_map,
 420     .loader_start = 0x80000000,
 421     .gic_cpu_if_addr = 0x2c002000,
 422     .proc_id = 0x14000237,
 423     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 424     .voltages = a15_voltages,
 425     .num_clocks = ARRAY_SIZE(a15_clocks),
 426     .clocks = a15_clocks,
 427     .init = a15_daughterboard_init,
 428 };
 429
 430 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 431                                 hwaddr addr, hwaddr size, uint32_t intc,
 432                                 int irq)
 433 {
 434     /* Add a virtio_mmio node to the device tree blob:
 435      *   virtio_mmio@ADDRESS {
 436      *       compatible = "virtio,mmio";
 437      *       reg = <ADDRESS, SIZE>;
 438      *       interrupt-parent = <&intc>;
 439      *       interrupts = <0, irq, 1>;
 440      *   }
 441      * (Note that the format of the interrupts property is dependent on the
 442      * interrupt controller that interrupt-parent points to; these are for
 443      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 444      */
 445     int rc;
 446     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 447
 448     rc = qemu_fdt_add_subnode(fdt, nodename);
 449     rc |= qemu_fdt_setprop_string(fdt, nodename,
 450                                   "compatible", "virtio,mmio");
 451     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 452                                        acells, addr, scells, size);
 453     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 454     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 455     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 456     g_free(nodename);
 457     if (rc) {
 458         return -1;
 459     }
 460     return 0;
 461 }
 462
 463 static uint32_t find_int_controller(void *fdt)
 464 {
 465     /* Find the FDT node corresponding to the interrupt controller
 466      * for virtio-mmio devices. We do this by scanning the fdt for
 467      * a node with the right compatibility, since we know there is
 468      * only one GIC on a vexpress board.
 469      * We return the phandle of the node, or 0 if none was found.
 470      */
 471     const char *compat = "arm,cortex-a9-gic";
 472     int offset;
 473
 474     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 475     if (offset >= 0) {
 476         return fdt_get_phandle(fdt, offset);
 477     }
 478     return 0;
 479 }
 480
 481 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 482 {
 483     uint32_t acells, scells, intc;
 484     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 485
 486     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 487                                    NULL, &error_fatal);
 488     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 489                                    NULL, &error_fatal);
 490     intc = find_int_controller(fdt);
 491     if (!intc) {
 492         /* Not fatal, we just won't provide virtio. This will
 493          * happen with older device tree blobs.
 494          */
 495         fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in "
 496                 "dtb; will not include virtio-mmio devices in the dtb.\n");
 497     } else {
 498         int i;
 499         const hwaddr *map = daughterboard->motherboard_map;
 500
 501         /* We iterate backwards here because adding nodes
 502          * to the dtb puts them in last-first.
 503          */
 504         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 505             add_virtio_mmio_node(fdt, acells, scells,
 506                                  map[VE_VIRTIO] + 0x200 * i,
 507                                  0x200, intc, 40 + i);
 508         }
 509     }
 510 }
 511
 512
 513 /* Open code a private version of pflash registration since we
 514  * need to set non-default device width for VExpress platform.
 515  */
 516 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
 517                                           DriveInfo *di)
 518 {
 519     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 520
 521     if (di) {
 522         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
 523                             &error_abort);
 524     }
 525
 526     qdev_prop_set_uint32(dev, "num-blocks",
 527                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 528     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 529     qdev_prop_set_uint8(dev, "width", 4);
 530     qdev_prop_set_uint8(dev, "device-width", 2);
 531     qdev_prop_set_bit(dev, "big-endian", false);
 532     qdev_prop_set_uint16(dev, "id0", 0x89);
 533     qdev_prop_set_uint16(dev, "id1", 0x18);
 534     qdev_prop_set_uint16(dev, "id2", 0x00);
 535     qdev_prop_set_uint16(dev, "id3", 0x00);
 536     qdev_prop_set_string(dev, "name", name);
 537     qdev_init_nofail(dev);
 538
 539     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 540     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 541 }
 542
 543 static void vexpress_common_init(MachineState *machine)
 544 {
 545     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 546     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 547     VEDBoardInfo *daughterboard = vmc->daughterboard;
 548     DeviceState *dev, *sysctl, *pl041;
 549     qemu_irq pic[64];
 550     uint32_t sys_id;
 551     DriveInfo *dinfo;
 552     pflash_t *pflash0;
 553     ram_addr_t vram_size, sram_size;
 554     MemoryRegion *sysmem = get_system_memory();
 555     MemoryRegion *vram = g_new(MemoryRegion, 1);
 556     MemoryRegion *sram = g_new(MemoryRegion, 1);
 557     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 558     MemoryRegion *flash0mem;
 559     const hwaddr *map = daughterboard->motherboard_map;
 560     int i;
 561
 562     daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
 563
 564     /*
 565      * If a bios file was provided, attempt to map it into memory
 566      */
 567     if (bios_name) {
 568         char *fn;
 569         int image_size;
 570
 571         if (drive_get(IF_PFLASH, 0, 0)) {
 572             error_report("The contents of the first flash device may be "
 573                          "specified with -bios or with -drive if=pflash... "
 574                          "but you cannot use both options at once");
 575             exit(1);
 576         }
 577         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 578         if (!fn) {
 579             error_report("Could not find ROM image '%s'", bios_name);
 580             exit(1);
 581         }
 582         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 583                                          VEXPRESS_FLASH_SIZE);
 584         g_free(fn);
 585         if (image_size < 0) {
 586             error_report("Could not load ROM image '%s'", bios_name);
 587             exit(1);
 588         }
 589     }
 590
 591     /* Motherboard peripherals: the wiring is the same but the
 592      * addresses vary between the legacy and A-Series memory maps.
 593      */
 594
 595     sys_id = 0x1190f500;
 596
 597     sysctl = qdev_create(NULL, "realview_sysctl");
 598     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 599     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 600     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 601                          daughterboard->num_voltage_sensors);
 602     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 603         char *propname = g_strdup_printf("db-voltage[%d]", i);
 604         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 605         g_free(propname);
 606     }
 607     qdev_prop_set_uint32(sysctl, "len-db-clock",
 608                          daughterboard->num_clocks);
 609     for (i = 0; i < daughterboard->num_clocks; i++) {
 610         char *propname = g_strdup_printf("db-clock[%d]", i);
 611         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 612         g_free(propname);
 613     }
 614     qdev_init_nofail(sysctl);
 615     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 616
 617     /* VE_SP810: not modelled */
 618     /* VE_SERIALPCI: not modelled */
 619
 620     pl041 = qdev_create(NULL, "pl041");
 621     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 622     qdev_init_nofail(pl041);
 623     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 624     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 625
 626     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 627     /* Wire up MMC card detect and read-only signals */
 628     qdev_connect_gpio_out(dev, 0,
 629                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 630     qdev_connect_gpio_out(dev, 1,
 631                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 632
 633     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 634     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 635
 636     pl011_create(map[VE_UART0], pic[5], serial_hds[0]);
 637     pl011_create(map[VE_UART1], pic[6], serial_hds[1]);
 638     pl011_create(map[VE_UART2], pic[7], serial_hds[2]);
 639     pl011_create(map[VE_UART3], pic[8], serial_hds[3]);
 640
 641     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 642     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 643
 644     /* VE_SERIALDVI: not modelled */
 645
 646     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 647
 648     /* VE_COMPACTFLASH: not modelled */
 649
 650     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 651
 652     dinfo = drive_get_next(IF_PFLASH);
 653     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 654                                        dinfo);
 655     if (!pflash0) {
 656         fprintf(stderr, "vexpress: error registering flash 0.\n");
 657         exit(1);
 658     }
 659
 660     if (map[VE_NORFLASHALIAS] != -1) {
 661         /* Map flash 0 as an alias into low memory */
 662         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 663         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 664                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 665         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 666     }
 667
 668     dinfo = drive_get_next(IF_PFLASH);
 669     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 670                                   dinfo)) {
 671         fprintf(stderr, "vexpress: error registering flash 1.\n");
 672         exit(1);
 673     }
 674
 675     sram_size = 0x2000000;
 676     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 677                            &error_fatal);
 678     vmstate_register_ram_global(sram);
 679     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 680
 681     vram_size = 0x800000;
 682     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 683                            &error_fatal);
 684     vmstate_register_ram_global(vram);
 685     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 686
 687     /* 0x4e000000 LAN9118 Ethernet */
 688     if (nd_table[0].used) {
 689         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 690     }
 691
 692     /* VE_USB: not modelled */
 693
 694     /* VE_DAPROM: not modelled */
 695
 696     /* Create mmio transports, so the user can create virtio backends
 697      * (which will be automatically plugged in to the transports). If
 698      * no backend is created the transport will just sit harmlessly idle.
 699      */
 700     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 701         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 702                              pic[40 + i]);
 703     }
 704
 705     daughterboard->bootinfo.ram_size = machine->ram_size;
 706     daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
 707     daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
 708     daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
 709     daughterboard->bootinfo.nb_cpus = smp_cpus;
 710     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 711     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 712     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 713     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 714     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 715     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 716     /* Indicate that when booting Linux we should be in secure state */
 717     daughterboard->bootinfo.secure_boot = true;
 718     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 719 }
 720
 721 static bool vexpress_get_secure(Object *obj, Error **errp)
 722 {
 723     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 724
 725     return vms->secure;
 726 }
 727
 728 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 729 {
 730     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 731
 732     vms->secure = value;
 733 }
 734
 735 static void vexpress_instance_init(Object *obj)
 736 {
 737     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 738
 739     /* EL3 is enabled by default on vexpress */
 740     vms->secure = true;
 741     object_property_add_bool(obj, "secure", vexpress_get_secure,
 742                              vexpress_set_secure, NULL);
 743     object_property_set_description(obj, "secure",
 744                                     "Set on/off to enable/disable the ARM "
 745                                     "Security Extensions (TrustZone)",
 746                                     NULL);
 747 }
 748
 749 static void vexpress_class_init(ObjectClass *oc, void *data)
 750 {
 751     MachineClass *mc = MACHINE_CLASS(oc);
 752
 753     mc->desc = "ARM Versatile Express";
 754     mc->init = vexpress_common_init;
 755     mc->max_cpus = 4;
 756 }
 757
 758 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 759 {
 760     MachineClass *mc = MACHINE_CLASS(oc);
 761     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 762
 763     mc->desc = "ARM Versatile Express for Cortex-A9";
 764
 765     vmc->daughterboard = &a9_daughterboard;
 766 }
 767
 768 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 769 {
 770     MachineClass *mc = MACHINE_CLASS(oc);
 771     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 772
 773     mc->desc = "ARM Versatile Express for Cortex-A15";
 774
 775     vmc->daughterboard = &a15_daughterboard;
 776 }
 777
 778 static const TypeInfo vexpress_info = {
 779     .name = TYPE_VEXPRESS_MACHINE,
 780     .parent = TYPE_MACHINE,
 781     .abstract = true,
 782     .instance_size = sizeof(VexpressMachineState),
 783     .instance_init = vexpress_instance_init,
 784     .class_size = sizeof(VexpressMachineClass),
 785     .class_init = vexpress_class_init,
 786 };
 787
 788 static const TypeInfo vexpress_a9_info = {
 789     .name = TYPE_VEXPRESS_A9_MACHINE,
 790     .parent = TYPE_VEXPRESS_MACHINE,
 791     .class_init = vexpress_a9_class_init,
 792 };
 793
 794 static const TypeInfo vexpress_a15_info = {
 795     .name = TYPE_VEXPRESS_A15_MACHINE,
 796     .parent = TYPE_VEXPRESS_MACHINE,
 797     .class_init = vexpress_a15_class_init,
 798 };
 799
 800 static void vexpress_machine_init(void)
 801 {
 802     type_register_static(&vexpress_info);
 803     type_register_static(&vexpress_a9_info);
 804     type_register_static(&vexpress_a15_info);
 805 }
 806
 807 type_init(vexpress_machine_init);