hw/ioh3420.c

   1 /*
   2  * ioh3420.c
   3  * Intel X58 north bridge IOH
   4  * PCI Express root port device id 3420
   5  *
   6  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   7  *                    VA Linux Systems Japan K.K.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "pci_ids.h"
  24 #include "msi.h"
  25 #include "pcie.h"
  26 #include "ioh3420.h"
  27
  28 #define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
  29 #define PCI_DEVICE_ID_IOH_REV           0x2
  30 #define IOH_EP_SSVID_OFFSET             0x40
  31 #define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
  32 #define IOH_EP_SSVID_SSID               0
  33 #define IOH_EP_MSI_OFFSET               0x60
  34 #define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
  35 #define IOH_EP_MSI_NR_VECTOR            2
  36 #define IOH_EP_EXP_OFFSET               0x90
  37 #define IOH_EP_AER_OFFSET               0x100
  38
  39 static void ioh3420_write_config(PCIDevice *d,
  40                                    uint32_t address, uint32_t val, int len)
  41 {
  42     uint16_t sltctl =
  43         pci_get_word(d->config + d->exp.exp_cap + PCI_EXP_SLTCTL);
  44
  45     pci_bridge_write_config(d, address, val, len);
  46     msi_write_config(d, address, val, len);
  47     pcie_cap_slot_write_config(d, address, val, len, sltctl);
  48     /* TODO: AER */
  49 }
  50
  51 static void ioh3420_reset(DeviceState *qdev)
  52 {
  53     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
  54     msi_reset(d);
  55     pcie_cap_root_reset(d);
  56     pcie_cap_deverr_reset(d);
  57     pcie_cap_slot_reset(d);
  58     pci_bridge_reset(qdev);
  59     pci_bridge_disable_base_limit(d);
  60     /* TODO: AER */
  61 }
  62
  63 static int ioh3420_initfn(PCIDevice *d)
  64 {
  65     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  66     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  67     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
  68     int rc;
  69
  70     rc = pci_bridge_initfn(d);
  71     if (rc < 0) {
  72         return rc;
  73     }
  74
  75     d->config[PCI_REVISION_ID] = PCI_DEVICE_ID_IOH_REV;
  76     pcie_port_init_reg(d);
  77
  78     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
  79     pci_config_set_device_id(d->config, PCI_DEVICE_ID_IOH_EPORT);
  80
  81     rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
  82                                IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
  83     if (rc < 0) {
  84         return rc;
  85     }
  86     rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
  87                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  88                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  89     if (rc < 0) {
  90         return rc;
  91     }
  92     rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
  93     if (rc < 0) {
  94         return rc;
  95     }
  96     pcie_cap_deverr_init(d);
  97     pcie_cap_slot_init(d, s->slot);
  98     pcie_chassis_create(s->chassis);
  99     rc = pcie_chassis_add_slot(s);
 100     if (rc < 0) {
 101         return rc;
 102     }
 103     pcie_cap_root_init(d);
 104     /* TODO: AER */
 105     return 0;
 106 }
 107
 108 static int ioh3420_exitfn(PCIDevice *d)
 109 {
 110     /* TODO: AER */
 111     msi_uninit(d);
 112     pcie_cap_exit(d);
 113     return pci_bridge_exitfn(d);
 114 }
 115
 116 PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
 117                          const char *bus_name, pci_map_irq_fn map_irq,
 118                          uint8_t port, uint8_t chassis, uint16_t slot)
 119 {
 120     PCIDevice *d;
 121     PCIBridge *br;
 122     DeviceState *qdev;
 123
 124     d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
 125     if (!d) {
 126         return NULL;
 127     }
 128     br = DO_UPCAST(PCIBridge, dev, d);
 129
 130     qdev = &br->dev.qdev;
 131     pci_bridge_map_irq(br, bus_name, map_irq);
 132     qdev_prop_set_uint8(qdev, "port", port);
 133     qdev_prop_set_uint8(qdev, "chassis", chassis);
 134     qdev_prop_set_uint16(qdev, "slot", slot);
 135     qdev_init_nofail(qdev);
 136
 137     return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
 138 }
 139
 140 static const VMStateDescription vmstate_ioh3420 = {
 141     .name = "ioh-3240-express-root-port",
 142     .version_id = 1,
 143     .minimum_version_id = 1,
 144     .minimum_version_id_old = 1,
 145     .fields = (VMStateField[]) {
 146         VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
 147         /* TODO: AER */
 148         VMSTATE_END_OF_LIST()
 149     }
 150 };
 151
 152 static PCIDeviceInfo ioh3420_info = {
 153     .qdev.name = "ioh3420",
 154     .qdev.desc = "Intel IOH device id 3420 PCIE Root Port",
 155     .qdev.size = sizeof(PCIESlot),
 156     .qdev.reset = ioh3420_reset,
 157     .qdev.vmsd = &vmstate_ioh3420,
 158
 159     .is_express = 1,
 160     .is_bridge = 1,
 161     .config_write = ioh3420_write_config,
 162     .init = ioh3420_initfn,
 163     .exit = ioh3420_exitfn,
 164
 165     .qdev.props = (Property[]) {
 166         DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
 167         DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 168         DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 169         /* TODO: AER */
 170         DEFINE_PROP_END_OF_LIST(),
 171     }
 172 };
 173
 174 static void ioh3420_register(void)
 175 {
 176     pci_qdev_register(&ioh3420_info);
 177 }
 178
 179 device_init(ioh3420_register);
 180
 181 /*
 182  * Local variables:
 183  *  c-indent-level: 4
 184  *  c-basic-offset: 4
 185  *  tab-width: 8
 186  *  indent-tab-mode: nil
 187  * End:
 188  */