2 * ARM VFP floating-point operations
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
26 #include "fpu/softfloat.h"
29 /* VFP support. We follow the convention used for VFP instructions:
30 Single precision routines have a "s" suffix, double precision a
35 /* Convert host exception flags to vfp form. */
36 static inline int vfp_exceptbits_from_host(int host_bits
)
40 if (host_bits
& float_flag_invalid
) {
43 if (host_bits
& float_flag_divbyzero
) {
46 if (host_bits
& float_flag_overflow
) {
49 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
)) {
52 if (host_bits
& float_flag_inexact
) {
55 if (host_bits
& float_flag_input_denormal
) {
61 /* Convert vfp exception flags to target form. */
62 static inline int vfp_exceptbits_to_host(int target_bits
)
66 if (target_bits
& 1) {
67 host_bits
|= float_flag_invalid
;
69 if (target_bits
& 2) {
70 host_bits
|= float_flag_divbyzero
;
72 if (target_bits
& 4) {
73 host_bits
|= float_flag_overflow
;
75 if (target_bits
& 8) {
76 host_bits
|= float_flag_underflow
;
78 if (target_bits
& 0x10) {
79 host_bits
|= float_flag_inexact
;
81 if (target_bits
& 0x80) {
82 host_bits
|= float_flag_input_denormal
;
87 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
91 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
92 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
93 /* FZ16 does not generate an input denormal exception. */
94 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
95 & ~float_flag_input_denormal
);
96 i
|= (get_float_exception_flags(&env
->vfp
.standard_fp_status_f16
)
97 & ~float_flag_input_denormal
);
98 return vfp_exceptbits_from_host(i
);
101 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
104 uint32_t changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
107 if (changed
& (3 << 22)) {
110 case FPROUNDING_TIEEVEN
:
111 i
= float_round_nearest_even
;
113 case FPROUNDING_POSINF
:
116 case FPROUNDING_NEGINF
:
117 i
= float_round_down
;
119 case FPROUNDING_ZERO
:
120 i
= float_round_to_zero
;
123 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
124 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
126 if (changed
& FPCR_FZ16
) {
127 bool ftz_enabled
= val
& FPCR_FZ16
;
128 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
129 set_flush_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
130 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
131 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
133 if (changed
& FPCR_FZ
) {
134 bool ftz_enabled
= val
& FPCR_FZ
;
135 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
136 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
138 if (changed
& FPCR_DN
) {
139 bool dnan_enabled
= val
& FPCR_DN
;
140 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
141 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
145 * The exception flags are ORed together when we read fpscr so we
146 * only need to preserve the current state in one of our
147 * float_status values.
149 i
= vfp_exceptbits_to_host(val
);
150 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
151 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
152 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
153 set_float_exception_flags(0, &env
->vfp
.standard_fp_status_f16
);
158 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
163 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
169 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
173 fpscr
= env
->vfp
.xregs
[ARM_VFP_FPSCR
]
174 | (env
->vfp
.vec_len
<< 16)
175 | (env
->vfp
.vec_stride
<< 20);
178 * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
179 * two is not applicable to this CPU will always be zero.
181 fpscr
|= env
->v7m
.ltpsize
<< 16;
183 fpscr
|= vfp_get_fpscr_from_host(env
);
185 i
= env
->vfp
.qc
[0] | env
->vfp
.qc
[1] | env
->vfp
.qc
[2] | env
->vfp
.qc
[3];
186 fpscr
|= i
? FPCR_QC
: 0;
191 uint32_t vfp_get_fpscr(CPUARMState
*env
)
193 return HELPER(vfp_get_fpscr
)(env
);
196 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
198 ARMCPU
*cpu
= env_archcpu(env
);
200 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
201 if (!cpu_isar_feature(any_fp16
, cpu
)) {
205 vfp_set_fpscr_to_host(env
, val
);
207 if (!arm_feature(env
, ARM_FEATURE_M
)) {
209 * Short-vector length and stride; on M-profile these bits
210 * are used for different purposes.
211 * We can't make this conditional be "if MVFR0.FPShVec != 0",
212 * because in v7A no-short-vector-support cores still had to
213 * allow Stride/Len to be written with the only effect that
214 * some insns are required to UNDEF if the guest sets them.
216 env
->vfp
.vec_len
= extract32(val
, 16, 3);
217 env
->vfp
.vec_stride
= extract32(val
, 20, 2);
218 } else if (cpu_isar_feature(aa32_mve
, cpu
)) {
219 env
->v7m
.ltpsize
= extract32(val
, FPCR_LTPSIZE_SHIFT
,
220 FPCR_LTPSIZE_LENGTH
);
223 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
225 * The bit we set within fpscr_q is arbitrary; the register as a
226 * whole being zero/non-zero is what counts.
227 * TODO: M-profile MVE also has a QC bit.
229 env
->vfp
.qc
[0] = val
& FPCR_QC
;
236 * We don't implement trapped exception handling, so the
237 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
239 * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
240 * fp_status; QC, Len and Stride are stored separately earlier.
241 * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
242 * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
244 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = val
& 0xf7c80000;
247 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
249 HELPER(vfp_set_fpscr
)(env
, val
);
254 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
256 #define VFP_BINOP(name) \
257 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
259 float_status *fpst = fpstp; \
260 return float16_ ## name(a, b, fpst); \
262 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
264 float_status *fpst = fpstp; \
265 return float32_ ## name(a, b, fpst); \
267 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
269 float_status *fpst = fpstp; \
270 return float64_ ## name(a, b, fpst); \
282 dh_ctype_f16
VFP_HELPER(neg
, h
)(dh_ctype_f16 a
)
284 return float16_chs(a
);
287 float32
VFP_HELPER(neg
, s
)(float32 a
)
289 return float32_chs(a
);
292 float64
VFP_HELPER(neg
, d
)(float64 a
)
294 return float64_chs(a
);
297 dh_ctype_f16
VFP_HELPER(abs
, h
)(dh_ctype_f16 a
)
299 return float16_abs(a
);
302 float32
VFP_HELPER(abs
, s
)(float32 a
)
304 return float32_abs(a
);
307 float64
VFP_HELPER(abs
, d
)(float64 a
)
309 return float64_abs(a
);
312 dh_ctype_f16
VFP_HELPER(sqrt
, h
)(dh_ctype_f16 a
, CPUARMState
*env
)
314 return float16_sqrt(a
, &env
->vfp
.fp_status_f16
);
317 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
319 return float32_sqrt(a
, &env
->vfp
.fp_status
);
322 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
324 return float64_sqrt(a
, &env
->vfp
.fp_status
);
327 static void softfloat_to_vfp_compare(CPUARMState
*env
, FloatRelation cmp
)
331 case float_relation_equal
:
334 case float_relation_less
:
337 case float_relation_greater
:
340 case float_relation_unordered
:
344 g_assert_not_reached();
346 env
->vfp
.xregs
[ARM_VFP_FPSCR
] =
347 deposit32(env
->vfp
.xregs
[ARM_VFP_FPSCR
], 28, 4, flags
);
350 /* XXX: check quiet/signaling case */
351 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
352 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
354 softfloat_to_vfp_compare(env, \
355 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
357 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
359 softfloat_to_vfp_compare(env, \
360 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
362 DO_VFP_cmp(h
, float16
, dh_ctype_f16
, fp_status_f16
)
363 DO_VFP_cmp(s
, float32
, float32
, fp_status
)
364 DO_VFP_cmp(d
, float64
, float64
, fp_status
)
367 /* Integer to float and float to integer conversions */
369 #define CONV_ITOF(name, ftype, fsz, sign) \
370 ftype HELPER(name)(uint32_t x, void *fpstp) \
372 float_status *fpst = fpstp; \
373 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
376 #define CONV_FTOI(name, ftype, fsz, sign, round) \
377 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
379 float_status *fpst = fpstp; \
380 if (float##fsz##_is_any_nan(x)) { \
381 float_raise(float_flag_invalid, fpst); \
384 return float##fsz##_to_##sign##int32##round(x, fpst); \
387 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
388 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
389 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
390 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
392 FLOAT_CONVS(si
, h
, uint32_t, 16, )
393 FLOAT_CONVS(si
, s
, float32
, 32, )
394 FLOAT_CONVS(si
, d
, float64
, 64, )
395 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
396 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
397 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
403 /* floating point conversion */
404 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
406 return float32_to_float64(x
, &env
->vfp
.fp_status
);
409 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
411 return float64_to_float32(x
, &env
->vfp
.fp_status
);
414 uint32_t HELPER(bfcvt
)(float32 x
, void *status
)
416 return float32_to_bfloat16(x
, status
);
419 uint32_t HELPER(bfcvt_pair
)(uint64_t pair
, void *status
)
421 bfloat16 lo
= float32_to_bfloat16(extract64(pair
, 0, 32), status
);
422 bfloat16 hi
= float32_to_bfloat16(extract64(pair
, 32, 32), status
);
423 return deposit32(lo
, 16, 16, hi
);
427 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float
428 * must always round-to-nearest; the AArch64 ones honour the FPSCR
429 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to
430 * round-to-nearest so either helper will work.) AArch32 float-to-fix
431 * must round-to-zero.
433 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
434 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
436 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
438 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
439 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
444 float_status *fpst = fpstp; \
445 FloatRoundMode oldmode = fpst->float_rounding_mode; \
446 fpst->float_rounding_mode = float_round_nearest_even; \
447 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
448 fpst->float_rounding_mode = oldmode; \
452 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
453 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
456 if (unlikely(float##fsz##_is_any_nan(x))) { \
457 float_raise(float_flag_invalid, fpst); \
460 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
463 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
464 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
465 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
466 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
467 float_round_to_zero, _round_to_zero) \
468 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
469 get_float_rounding_mode(fpst), )
471 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
472 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
473 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
474 get_float_rounding_mode(fpst), )
476 VFP_CONV_FIX(sh
, d
, 64, float64
, 64, int16
)
477 VFP_CONV_FIX(sl
, d
, 64, float64
, 64, int32
)
478 VFP_CONV_FIX_A64(sq
, d
, 64, float64
, 64, int64
)
479 VFP_CONV_FIX(uh
, d
, 64, float64
, 64, uint16
)
480 VFP_CONV_FIX(ul
, d
, 64, float64
, 64, uint32
)
481 VFP_CONV_FIX_A64(uq
, d
, 64, float64
, 64, uint64
)
482 VFP_CONV_FIX(sh
, s
, 32, float32
, 32, int16
)
483 VFP_CONV_FIX(sl
, s
, 32, float32
, 32, int32
)
484 VFP_CONV_FIX_A64(sq
, s
, 32, float32
, 64, int64
)
485 VFP_CONV_FIX(uh
, s
, 32, float32
, 32, uint16
)
486 VFP_CONV_FIX(ul
, s
, 32, float32
, 32, uint32
)
487 VFP_CONV_FIX_A64(uq
, s
, 32, float32
, 64, uint64
)
488 VFP_CONV_FIX(sh
, h
, 16, dh_ctype_f16
, 32, int16
)
489 VFP_CONV_FIX(sl
, h
, 16, dh_ctype_f16
, 32, int32
)
490 VFP_CONV_FIX_A64(sq
, h
, 16, dh_ctype_f16
, 64, int64
)
491 VFP_CONV_FIX(uh
, h
, 16, dh_ctype_f16
, 32, uint16
)
492 VFP_CONV_FIX(ul
, h
, 16, dh_ctype_f16
, 32, uint32
)
493 VFP_CONV_FIX_A64(uq
, h
, 16, dh_ctype_f16
, 64, uint64
)
496 #undef VFP_CONV_FIX_FLOAT
497 #undef VFP_CONV_FLOAT_FIX_ROUND
498 #undef VFP_CONV_FIX_A64
500 /* Set the current fp rounding mode and return the old one.
501 * The argument is a softfloat float_round_ value.
503 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
505 float_status
*fp_status
= fpstp
;
507 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
508 set_float_rounding_mode(rmode
, fp_status
);
513 /* Half precision conversions. */
514 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
516 /* Squash FZ16 to 0 for the duration of conversion. In this case,
517 * it would affect flushing input denormals.
519 float_status
*fpst
= fpstp
;
520 bool save
= get_flush_inputs_to_zero(fpst
);
521 set_flush_inputs_to_zero(false, fpst
);
522 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
523 set_flush_inputs_to_zero(save
, fpst
);
527 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
529 /* Squash FZ16 to 0 for the duration of conversion. In this case,
530 * it would affect flushing output denormals.
532 float_status
*fpst
= fpstp
;
533 bool save
= get_flush_to_zero(fpst
);
534 set_flush_to_zero(false, fpst
);
535 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
536 set_flush_to_zero(save
, fpst
);
540 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
542 /* Squash FZ16 to 0 for the duration of conversion. In this case,
543 * it would affect flushing input denormals.
545 float_status
*fpst
= fpstp
;
546 bool save
= get_flush_inputs_to_zero(fpst
);
547 set_flush_inputs_to_zero(false, fpst
);
548 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
549 set_flush_inputs_to_zero(save
, fpst
);
553 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
555 /* Squash FZ16 to 0 for the duration of conversion. In this case,
556 * it would affect flushing output denormals.
558 float_status
*fpst
= fpstp
;
559 bool save
= get_flush_to_zero(fpst
);
560 set_flush_to_zero(false, fpst
);
561 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
562 set_flush_to_zero(save
, fpst
);
568 /* Constants 256 and 512 are used in some helpers; we avoid relying on
569 * int->float conversions at run-time. */
570 #define float64_256 make_float64(0x4070000000000000LL)
571 #define float64_512 make_float64(0x4080000000000000LL)
572 #define float16_maxnorm make_float16(0x7bff)
573 #define float32_maxnorm make_float32(0x7f7fffff)
574 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
576 /* Reciprocal functions
578 * The algorithm that must be used to calculate the estimate
579 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
582 /* See RecipEstimate()
584 * input is a 9 bit fixed point number
585 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
586 * result range 256 .. 511 for a number from 1.0 to 511/256.
589 static int recip_estimate(int input
)
592 assert(256 <= input
&& input
< 512);
596 assert(256 <= r
&& r
< 512);
601 * Common wrapper to call recip_estimate
603 * The parameters are exponent and 64 bit fraction (without implicit
604 * bit) where the binary point is nominally at bit 52. Returns a
605 * float64 which can then be rounded to the appropriate size by the
609 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
611 uint32_t scaled
, estimate
;
612 uint64_t result_frac
;
615 /* Handle sub-normals */
617 if (extract64(frac
, 51, 1) == 0) {
625 /* scaled = UInt('1':fraction<51:44>) */
626 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
627 estimate
= recip_estimate(scaled
);
629 result_exp
= exp_off
- *exp
;
630 result_frac
= deposit64(0, 44, 8, estimate
);
631 if (result_exp
== 0) {
632 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
633 } else if (result_exp
== -1) {
634 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
643 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
645 switch (fpst
->float_rounding_mode
) {
646 case float_round_nearest_even
: /* Round to Nearest */
648 case float_round_up
: /* Round to +Inf */
650 case float_round_down
: /* Round to -Inf */
652 case float_round_to_zero
: /* Round to Zero */
655 g_assert_not_reached();
659 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
661 float_status
*fpst
= fpstp
;
662 float16 f16
= float16_squash_input_denormal(input
, fpst
);
663 uint32_t f16_val
= float16_val(f16
);
664 uint32_t f16_sign
= float16_is_neg(f16
);
665 int f16_exp
= extract32(f16_val
, 10, 5);
666 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
669 if (float16_is_any_nan(f16
)) {
671 if (float16_is_signaling_nan(f16
, fpst
)) {
672 float_raise(float_flag_invalid
, fpst
);
673 nan
= float16_silence_nan(f16
, fpst
);
675 if (fpst
->default_nan_mode
) {
676 nan
= float16_default_nan(fpst
);
679 } else if (float16_is_infinity(f16
)) {
680 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
681 } else if (float16_is_zero(f16
)) {
682 float_raise(float_flag_divbyzero
, fpst
);
683 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
684 } else if (float16_abs(f16
) < (1 << 8)) {
685 /* Abs(value) < 2.0^-16 */
686 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
687 if (round_to_inf(fpst
, f16_sign
)) {
688 return float16_set_sign(float16_infinity
, f16_sign
);
690 return float16_set_sign(float16_maxnorm
, f16_sign
);
692 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
693 float_raise(float_flag_underflow
, fpst
);
694 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
697 f64_frac
= call_recip_estimate(&f16_exp
, 29,
698 ((uint64_t) f16_frac
) << (52 - 10));
700 /* result = sign : result_exp<4:0> : fraction<51:42> */
701 f16_val
= deposit32(0, 15, 1, f16_sign
);
702 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
703 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
704 return make_float16(f16_val
);
707 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
709 float_status
*fpst
= fpstp
;
710 float32 f32
= float32_squash_input_denormal(input
, fpst
);
711 uint32_t f32_val
= float32_val(f32
);
712 bool f32_sign
= float32_is_neg(f32
);
713 int f32_exp
= extract32(f32_val
, 23, 8);
714 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
717 if (float32_is_any_nan(f32
)) {
719 if (float32_is_signaling_nan(f32
, fpst
)) {
720 float_raise(float_flag_invalid
, fpst
);
721 nan
= float32_silence_nan(f32
, fpst
);
723 if (fpst
->default_nan_mode
) {
724 nan
= float32_default_nan(fpst
);
727 } else if (float32_is_infinity(f32
)) {
728 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
729 } else if (float32_is_zero(f32
)) {
730 float_raise(float_flag_divbyzero
, fpst
);
731 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
732 } else if (float32_abs(f32
) < (1ULL << 21)) {
733 /* Abs(value) < 2.0^-128 */
734 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
735 if (round_to_inf(fpst
, f32_sign
)) {
736 return float32_set_sign(float32_infinity
, f32_sign
);
738 return float32_set_sign(float32_maxnorm
, f32_sign
);
740 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
741 float_raise(float_flag_underflow
, fpst
);
742 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
745 f64_frac
= call_recip_estimate(&f32_exp
, 253,
746 ((uint64_t) f32_frac
) << (52 - 23));
748 /* result = sign : result_exp<7:0> : fraction<51:29> */
749 f32_val
= deposit32(0, 31, 1, f32_sign
);
750 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
751 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
752 return make_float32(f32_val
);
755 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
757 float_status
*fpst
= fpstp
;
758 float64 f64
= float64_squash_input_denormal(input
, fpst
);
759 uint64_t f64_val
= float64_val(f64
);
760 bool f64_sign
= float64_is_neg(f64
);
761 int f64_exp
= extract64(f64_val
, 52, 11);
762 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
764 /* Deal with any special cases */
765 if (float64_is_any_nan(f64
)) {
767 if (float64_is_signaling_nan(f64
, fpst
)) {
768 float_raise(float_flag_invalid
, fpst
);
769 nan
= float64_silence_nan(f64
, fpst
);
771 if (fpst
->default_nan_mode
) {
772 nan
= float64_default_nan(fpst
);
775 } else if (float64_is_infinity(f64
)) {
776 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
777 } else if (float64_is_zero(f64
)) {
778 float_raise(float_flag_divbyzero
, fpst
);
779 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
780 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
781 /* Abs(value) < 2.0^-1024 */
782 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
783 if (round_to_inf(fpst
, f64_sign
)) {
784 return float64_set_sign(float64_infinity
, f64_sign
);
786 return float64_set_sign(float64_maxnorm
, f64_sign
);
788 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
789 float_raise(float_flag_underflow
, fpst
);
790 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
793 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
795 /* result = sign : result_exp<10:0> : fraction<51:0>; */
796 f64_val
= deposit64(0, 63, 1, f64_sign
);
797 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
798 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
799 return make_float64(f64_val
);
802 /* The algorithm that must be used to calculate the estimate
803 * is specified by the ARM ARM.
806 static int do_recip_sqrt_estimate(int a
)
810 assert(128 <= a
&& a
< 512);
818 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
821 estimate
= (b
+ 1) / 2;
822 assert(256 <= estimate
&& estimate
< 512);
828 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
834 while (extract64(frac
, 51, 1) == 0) {
838 frac
= extract64(frac
, 0, 51) << 1;
842 /* scaled = UInt('01':fraction<51:45>) */
843 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
845 /* scaled = UInt('1':fraction<51:44>) */
846 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
848 estimate
= do_recip_sqrt_estimate(scaled
);
850 *exp
= (exp_off
- *exp
) / 2;
851 return extract64(estimate
, 0, 8) << 44;
854 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
856 float_status
*s
= fpstp
;
857 float16 f16
= float16_squash_input_denormal(input
, s
);
858 uint16_t val
= float16_val(f16
);
859 bool f16_sign
= float16_is_neg(f16
);
860 int f16_exp
= extract32(val
, 10, 5);
861 uint16_t f16_frac
= extract32(val
, 0, 10);
864 if (float16_is_any_nan(f16
)) {
866 if (float16_is_signaling_nan(f16
, s
)) {
867 float_raise(float_flag_invalid
, s
);
868 nan
= float16_silence_nan(f16
, s
);
870 if (s
->default_nan_mode
) {
871 nan
= float16_default_nan(s
);
874 } else if (float16_is_zero(f16
)) {
875 float_raise(float_flag_divbyzero
, s
);
876 return float16_set_sign(float16_infinity
, f16_sign
);
877 } else if (f16_sign
) {
878 float_raise(float_flag_invalid
, s
);
879 return float16_default_nan(s
);
880 } else if (float16_is_infinity(f16
)) {
884 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
885 * preserving the parity of the exponent. */
887 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
889 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
891 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
892 val
= deposit32(0, 15, 1, f16_sign
);
893 val
= deposit32(val
, 10, 5, f16_exp
);
894 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
895 return make_float16(val
);
898 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
900 float_status
*s
= fpstp
;
901 float32 f32
= float32_squash_input_denormal(input
, s
);
902 uint32_t val
= float32_val(f32
);
903 uint32_t f32_sign
= float32_is_neg(f32
);
904 int f32_exp
= extract32(val
, 23, 8);
905 uint32_t f32_frac
= extract32(val
, 0, 23);
908 if (float32_is_any_nan(f32
)) {
910 if (float32_is_signaling_nan(f32
, s
)) {
911 float_raise(float_flag_invalid
, s
);
912 nan
= float32_silence_nan(f32
, s
);
914 if (s
->default_nan_mode
) {
915 nan
= float32_default_nan(s
);
918 } else if (float32_is_zero(f32
)) {
919 float_raise(float_flag_divbyzero
, s
);
920 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
921 } else if (float32_is_neg(f32
)) {
922 float_raise(float_flag_invalid
, s
);
923 return float32_default_nan(s
);
924 } else if (float32_is_infinity(f32
)) {
928 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
929 * preserving the parity of the exponent. */
931 f64_frac
= ((uint64_t) f32_frac
) << 29;
933 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
935 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
936 val
= deposit32(0, 31, 1, f32_sign
);
937 val
= deposit32(val
, 23, 8, f32_exp
);
938 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
939 return make_float32(val
);
942 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
944 float_status
*s
= fpstp
;
945 float64 f64
= float64_squash_input_denormal(input
, s
);
946 uint64_t val
= float64_val(f64
);
947 bool f64_sign
= float64_is_neg(f64
);
948 int f64_exp
= extract64(val
, 52, 11);
949 uint64_t f64_frac
= extract64(val
, 0, 52);
951 if (float64_is_any_nan(f64
)) {
953 if (float64_is_signaling_nan(f64
, s
)) {
954 float_raise(float_flag_invalid
, s
);
955 nan
= float64_silence_nan(f64
, s
);
957 if (s
->default_nan_mode
) {
958 nan
= float64_default_nan(s
);
961 } else if (float64_is_zero(f64
)) {
962 float_raise(float_flag_divbyzero
, s
);
963 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
964 } else if (float64_is_neg(f64
)) {
965 float_raise(float_flag_invalid
, s
);
966 return float64_default_nan(s
);
967 } else if (float64_is_infinity(f64
)) {
971 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
973 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
974 val
= deposit64(0, 61, 1, f64_sign
);
975 val
= deposit64(val
, 52, 11, f64_exp
);
976 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
977 return make_float64(val
);
980 uint32_t HELPER(recpe_u32
)(uint32_t a
)
984 if ((a
& 0x80000000) == 0) {
988 input
= extract32(a
, 23, 9);
989 estimate
= recip_estimate(input
);
991 return deposit32(0, (32 - 9), 9, estimate
);
994 uint32_t HELPER(rsqrte_u32
)(uint32_t a
)
998 if ((a
& 0xc0000000) == 0) {
1002 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
1004 return deposit32(0, 23, 9, estimate
);
1007 /* VFPv4 fused multiply-accumulate */
1008 dh_ctype_f16
VFP_HELPER(muladd
, h
)(dh_ctype_f16 a
, dh_ctype_f16 b
,
1009 dh_ctype_f16 c
, void *fpstp
)
1011 float_status
*fpst
= fpstp
;
1012 return float16_muladd(a
, b
, c
, 0, fpst
);
1015 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
1017 float_status
*fpst
= fpstp
;
1018 return float32_muladd(a
, b
, c
, 0, fpst
);
1021 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
1023 float_status
*fpst
= fpstp
;
1024 return float64_muladd(a
, b
, c
, 0, fpst
);
1027 /* ARMv8 round to integral */
1028 dh_ctype_f16
HELPER(rinth_exact
)(dh_ctype_f16 x
, void *fp_status
)
1030 return float16_round_to_int(x
, fp_status
);
1033 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
1035 return float32_round_to_int(x
, fp_status
);
1038 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
1040 return float64_round_to_int(x
, fp_status
);
1043 dh_ctype_f16
HELPER(rinth
)(dh_ctype_f16 x
, void *fp_status
)
1045 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1048 ret
= float16_round_to_int(x
, fp_status
);
1050 /* Suppress any inexact exceptions the conversion produced */
1051 if (!(old_flags
& float_flag_inexact
)) {
1052 new_flags
= get_float_exception_flags(fp_status
);
1053 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1059 float32
HELPER(rints
)(float32 x
, void *fp_status
)
1061 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1064 ret
= float32_round_to_int(x
, fp_status
);
1066 /* Suppress any inexact exceptions the conversion produced */
1067 if (!(old_flags
& float_flag_inexact
)) {
1068 new_flags
= get_float_exception_flags(fp_status
);
1069 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1075 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
1077 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1080 ret
= float64_round_to_int(x
, fp_status
);
1082 new_flags
= get_float_exception_flags(fp_status
);
1084 /* Suppress any inexact exceptions the conversion produced */
1085 if (!(old_flags
& float_flag_inexact
)) {
1086 new_flags
= get_float_exception_flags(fp_status
);
1087 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1093 /* Convert ARM rounding mode to softfloat */
1094 int arm_rmode_to_sf(int rmode
)
1097 case FPROUNDING_TIEAWAY
:
1098 rmode
= float_round_ties_away
;
1100 case FPROUNDING_ODD
:
1101 /* FIXME: add support for TIEAWAY and ODD */
1102 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
1104 /* fall through for now */
1105 case FPROUNDING_TIEEVEN
:
1107 rmode
= float_round_nearest_even
;
1109 case FPROUNDING_POSINF
:
1110 rmode
= float_round_up
;
1112 case FPROUNDING_NEGINF
:
1113 rmode
= float_round_down
;
1115 case FPROUNDING_ZERO
:
1116 rmode
= float_round_to_zero
;
1123 * Implement float64 to int32_t conversion without saturation;
1124 * the result is supplied modulo 2^32.
1126 uint64_t HELPER(fjcvtzs
)(float64 value
, void *vstatus
)
1128 float_status
*status
= vstatus
;
1131 uint32_t inexact
= 1; /* !Z */
1133 sign
= extract64(value
, 63, 1);
1134 exp
= extract64(value
, 52, 11);
1135 frac
= extract64(value
, 0, 52);
1138 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1141 if (status
->flush_inputs_to_zero
) {
1142 float_raise(float_flag_input_denormal
, status
);
1144 float_raise(float_flag_inexact
, status
);
1149 } else if (exp
== 0x7ff) {
1150 /* This operation raises Invalid for both NaN and overflow (Inf). */
1151 float_raise(float_flag_invalid
, status
);
1154 int true_exp
= exp
- 1023;
1155 int shift
= true_exp
- 52;
1157 /* Restore implicit bit. */
1160 /* Shift the fraction into place. */
1162 /* The number is so large we must shift the fraction left. */
1164 /* The fraction is shifted out entirely. */
1169 } else if (shift
> -64) {
1170 /* Normal case -- shift right and notice if bits shift out. */
1171 inexact
= (frac
<< (64 + shift
)) != 0;
1174 /* The fraction is shifted out entirely. */
1178 /* Notice overflow or inexact exceptions. */
1179 if (true_exp
> 31 || frac
> (sign
? 0x80000000ull
: 0x7fffffff)) {
1180 /* Overflow, for which this operation raises invalid. */
1181 float_raise(float_flag_invalid
, status
);
1183 } else if (inexact
) {
1184 float_raise(float_flag_inexact
, status
);
1187 /* Honor the sign. */
1193 /* Pack the result and the env->ZF representation of Z together. */
1194 return deposit64(frac
, 32, 32, inexact
);
1197 uint32_t HELPER(vjcvt
)(float64 value
, CPUARMState
*env
)
1199 uint64_t pair
= HELPER(fjcvtzs
)(value
, &env
->vfp
.fp_status
);
1200 uint32_t result
= pair
;
1201 uint32_t z
= (pair
>> 32) == 0;
1203 /* Store Z, clear NCV, in FPSCR.NZCV. */
1204 env
->vfp
.xregs
[ARM_VFP_FPSCR
]
1205 = (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & ~CPSR_NZCV
) | (z
* CPSR_Z
);
1210 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1211 static float32
frint_s(float32 f
, float_status
*fpst
, int intsize
)
1213 int old_flags
= get_float_exception_flags(fpst
);
1214 uint32_t exp
= extract32(f
, 23, 8);
1216 if (unlikely(exp
== 0xff)) {
1221 /* Round and re-extract the exponent. */
1222 f
= float32_round_to_int(f
, fpst
);
1223 exp
= extract32(f
, 23, 8);
1225 /* Validate the range of the result. */
1226 if (exp
< 126 + intsize
) {
1227 /* abs(F) <= INT{N}_MAX */
1230 if (exp
== 126 + intsize
) {
1231 uint32_t sign
= extract32(f
, 31, 1);
1232 uint32_t frac
= extract32(f
, 0, 23);
1233 if (sign
&& frac
== 0) {
1234 /* F == INT{N}_MIN */
1241 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1242 * inexact exception float32_round_to_int may have raised.
1244 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1245 return (0x100u
+ 126u + intsize
) << 23;
1248 float32
HELPER(frint32_s
)(float32 f
, void *fpst
)
1250 return frint_s(f
, fpst
, 32);
1253 float32
HELPER(frint64_s
)(float32 f
, void *fpst
)
1255 return frint_s(f
, fpst
, 64);
1258 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1259 static float64
frint_d(float64 f
, float_status
*fpst
, int intsize
)
1261 int old_flags
= get_float_exception_flags(fpst
);
1262 uint32_t exp
= extract64(f
, 52, 11);
1264 if (unlikely(exp
== 0x7ff)) {
1269 /* Round and re-extract the exponent. */
1270 f
= float64_round_to_int(f
, fpst
);
1271 exp
= extract64(f
, 52, 11);
1273 /* Validate the range of the result. */
1274 if (exp
< 1022 + intsize
) {
1275 /* abs(F) <= INT{N}_MAX */
1278 if (exp
== 1022 + intsize
) {
1279 uint64_t sign
= extract64(f
, 63, 1);
1280 uint64_t frac
= extract64(f
, 0, 52);
1281 if (sign
&& frac
== 0) {
1282 /* F == INT{N}_MIN */
1289 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1290 * inexact exception float64_round_to_int may have raised.
1292 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1293 return (uint64_t)(0x800 + 1022 + intsize
) << 52;
1296 float64
HELPER(frint32_d
)(float64 f
, void *fpst
)
1298 return frint_d(f
, fpst
, 32);
1301 float64
HELPER(frint64_d
)(float64 f
, void *fpst
)
1303 return frint_d(f
, fpst
, 64);
1306 void HELPER(check_hcr_el2_trap
)(CPUARMState
*env
, uint32_t rt
, uint32_t reg
)
1314 if (!(arm_hcr_el2_eff(env
) & HCR_TID3
)) {
1319 if (!(arm_hcr_el2_eff(env
) & HCR_TID0
)) {
1324 g_assert_not_reached();
1327 syndrome
= ((EC_FPIDTRAP
<< ARM_EL_EC_SHIFT
)
1329 | (1 << 24) | (0xe << 20) | (7 << 14)
1330 | (reg
<< 10) | (rt
<< 5) | 1);
1332 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);