cpu.c

   1 /*
   2  * Target-specific parts of the CPU object
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "qapi/error.h"
  23
  24 #include "exec/target_page.h"
  25 #include "hw/qdev-core.h"
  26 #include "hw/qdev-properties.h"
  27 #include "qemu/error-report.h"
  28 #include "migration/vmstate.h"
  29 #ifdef CONFIG_USER_ONLY
  30 #include "qemu.h"
  31 #else
  32 #include "hw/core/sysemu-cpu-ops.h"
  33 #include "exec/address-spaces.h"
  34 #endif
  35 #include "sysemu/tcg.h"
  36 #include "sysemu/kvm.h"
  37 #include "sysemu/replay.h"
  38 #include "exec/translate-all.h"
  39 #include "exec/log.h"
  40 #include "hw/core/accel-cpu.h"
  41 #include "trace/trace-root.h"
  42
  43 uintptr_t qemu_host_page_size;
  44 intptr_t qemu_host_page_mask;
  45
  46 #ifndef CONFIG_USER_ONLY
  47 static int cpu_common_post_load(void *opaque, int version_id)
  48 {
  49     CPUState *cpu = opaque;
  50
  51     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
  52        version_id is increased. */
  53     cpu->interrupt_request &= ~0x01;
  54     tlb_flush(cpu);
  55
  56     /* loadvm has just updated the content of RAM, bypassing the
  57      * usual mechanisms that ensure we flush TBs for writes to
  58      * memory we've translated code from. So we must flush all TBs,
  59      * which will now be stale.
  60      */
  61     tb_flush(cpu);
  62
  63     return 0;
  64 }
  65
  66 static int cpu_common_pre_load(void *opaque)
  67 {
  68     CPUState *cpu = opaque;
  69
  70     cpu->exception_index = -1;
  71
  72     return 0;
  73 }
  74
  75 static bool cpu_common_exception_index_needed(void *opaque)
  76 {
  77     CPUState *cpu = opaque;
  78
  79     return tcg_enabled() && cpu->exception_index != -1;
  80 }
  81
  82 static const VMStateDescription vmstate_cpu_common_exception_index = {
  83     .name = "cpu_common/exception_index",
  84     .version_id = 1,
  85     .minimum_version_id = 1,
  86     .needed = cpu_common_exception_index_needed,
  87     .fields = (VMStateField[]) {
  88         VMSTATE_INT32(exception_index, CPUState),
  89         VMSTATE_END_OF_LIST()
  90     }
  91 };
  92
  93 static bool cpu_common_crash_occurred_needed(void *opaque)
  94 {
  95     CPUState *cpu = opaque;
  96
  97     return cpu->crash_occurred;
  98 }
  99
 100 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
 101     .name = "cpu_common/crash_occurred",
 102     .version_id = 1,
 103     .minimum_version_id = 1,
 104     .needed = cpu_common_crash_occurred_needed,
 105     .fields = (VMStateField[]) {
 106         VMSTATE_BOOL(crash_occurred, CPUState),
 107         VMSTATE_END_OF_LIST()
 108     }
 109 };
 110
 111 const VMStateDescription vmstate_cpu_common = {
 112     .name = "cpu_common",
 113     .version_id = 1,
 114     .minimum_version_id = 1,
 115     .pre_load = cpu_common_pre_load,
 116     .post_load = cpu_common_post_load,
 117     .fields = (VMStateField[]) {
 118         VMSTATE_UINT32(halted, CPUState),
 119         VMSTATE_UINT32(interrupt_request, CPUState),
 120         VMSTATE_END_OF_LIST()
 121     },
 122     .subsections = (const VMStateDescription*[]) {
 123         &vmstate_cpu_common_exception_index,
 124         &vmstate_cpu_common_crash_occurred,
 125         NULL
 126     }
 127 };
 128 #endif
 129
 130 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
 131 {
 132 #ifndef CONFIG_USER_ONLY
 133     CPUClass *cc = CPU_GET_CLASS(cpu);
 134 #endif
 135
 136     cpu_list_add(cpu);
 137     if (!accel_cpu_realizefn(cpu, errp)) {
 138         return;
 139     }
 140 #ifdef CONFIG_TCG
 141     /* NB: errp parameter is unused currently */
 142     if (tcg_enabled()) {
 143         tcg_exec_realizefn(cpu, errp);
 144     }
 145 #endif /* CONFIG_TCG */
 146
 147 #ifdef CONFIG_USER_ONLY
 148     assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
 149            qdev_get_vmsd(DEVICE(cpu))->unmigratable);
 150 #else
 151     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 152         vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
 153     }
 154     if (cc->sysemu_ops->legacy_vmsd != NULL) {
 155         vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
 156     }
 157 #endif /* CONFIG_USER_ONLY */
 158 }
 159
 160 void cpu_exec_unrealizefn(CPUState *cpu)
 161 {
 162 #ifndef CONFIG_USER_ONLY
 163     CPUClass *cc = CPU_GET_CLASS(cpu);
 164
 165     if (cc->sysemu_ops->legacy_vmsd != NULL) {
 166         vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
 167     }
 168     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 169         vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
 170     }
 171 #endif
 172 #ifdef CONFIG_TCG
 173     /* NB: errp parameter is unused currently */
 174     if (tcg_enabled()) {
 175         tcg_exec_unrealizefn(cpu);
 176     }
 177 #endif /* CONFIG_TCG */
 178
 179     cpu_list_remove(cpu);
 180 }
 181
 182 static Property cpu_common_props[] = {
 183 #ifndef CONFIG_USER_ONLY
 184     /*
 185      * Create a memory property for softmmu CPU object,
 186      * so users can wire up its memory. (This can't go in hw/core/cpu.c
 187      * because that file is compiled only once for both user-mode
 188      * and system builds.) The default if no link is set up is to use
 189      * the system address space.
 190      */
 191     DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 192                      MemoryRegion *),
 193 #endif
 194     DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
 195     DEFINE_PROP_END_OF_LIST(),
 196 };
 197
 198 void cpu_class_init_props(DeviceClass *dc)
 199 {
 200     device_class_set_props(dc, cpu_common_props);
 201 }
 202
 203 void cpu_exec_initfn(CPUState *cpu)
 204 {
 205     cpu->as = NULL;
 206     cpu->num_ases = 0;
 207
 208 #ifndef CONFIG_USER_ONLY
 209     cpu->thread_id = qemu_get_thread_id();
 210     cpu->memory = get_system_memory();
 211     object_ref(OBJECT(cpu->memory));
 212 #endif
 213 }
 214
 215 const char *parse_cpu_option(const char *cpu_option)
 216 {
 217     ObjectClass *oc;
 218     CPUClass *cc;
 219     gchar **model_pieces;
 220     const char *cpu_type;
 221
 222     model_pieces = g_strsplit(cpu_option, ",", 2);
 223     if (!model_pieces[0]) {
 224         error_report("-cpu option cannot be empty");
 225         exit(1);
 226     }
 227
 228     oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
 229     if (oc == NULL) {
 230         error_report("unable to find CPU model '%s'", model_pieces[0]);
 231         g_strfreev(model_pieces);
 232         exit(EXIT_FAILURE);
 233     }
 234
 235     cpu_type = object_class_get_name(oc);
 236     cc = CPU_CLASS(oc);
 237     cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
 238     g_strfreev(model_pieces);
 239     return cpu_type;
 240 }
 241
 242 #if defined(CONFIG_USER_ONLY)
 243 void tb_invalidate_phys_addr(target_ulong addr)
 244 {
 245     mmap_lock();
 246     tb_invalidate_phys_page_range(addr, addr + 1);
 247     mmap_unlock();
 248 }
 249 #else
 250 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 251 {
 252     ram_addr_t ram_addr;
 253     MemoryRegion *mr;
 254     hwaddr l = 1;
 255
 256     if (!tcg_enabled()) {
 257         return;
 258     }
 259
 260     RCU_READ_LOCK_GUARD();
 261     mr = address_space_translate(as, addr, &addr, &l, false, attrs);
 262     if (!(memory_region_is_ram(mr)
 263           || memory_region_is_romd(mr))) {
 264         return;
 265     }
 266     ram_addr = memory_region_get_ram_addr(mr) + addr;
 267     tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
 268 }
 269 #endif
 270
 271 /* Add a breakpoint.  */
 272 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 273                           CPUBreakpoint **breakpoint)
 274 {
 275     CPUClass *cc = CPU_GET_CLASS(cpu);
 276     CPUBreakpoint *bp;
 277
 278     if (cc->gdb_adjust_breakpoint) {
 279         pc = cc->gdb_adjust_breakpoint(cpu, pc);
 280     }
 281
 282     bp = g_malloc(sizeof(*bp));
 283
 284     bp->pc = pc;
 285     bp->flags = flags;
 286
 287     /* keep all GDB-injected breakpoints in front */
 288     if (flags & BP_GDB) {
 289         QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
 290     } else {
 291         QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
 292     }
 293
 294     if (breakpoint) {
 295         *breakpoint = bp;
 296     }
 297
 298     trace_breakpoint_insert(cpu->cpu_index, pc, flags);
 299     return 0;
 300 }
 301
 302 /* Remove a specific breakpoint.  */
 303 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
 304 {
 305     CPUClass *cc = CPU_GET_CLASS(cpu);
 306     CPUBreakpoint *bp;
 307
 308     if (cc->gdb_adjust_breakpoint) {
 309         pc = cc->gdb_adjust_breakpoint(cpu, pc);
 310     }
 311
 312     QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
 313         if (bp->pc == pc && bp->flags == flags) {
 314             cpu_breakpoint_remove_by_ref(cpu, bp);
 315             return 0;
 316         }
 317     }
 318     return -ENOENT;
 319 }
 320
 321 /* Remove a specific breakpoint by reference.  */
 322 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
 323 {
 324     QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
 325
 326     trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
 327     g_free(bp);
 328 }
 329
 330 /* Remove all matching breakpoints. */
 331 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
 332 {
 333     CPUBreakpoint *bp, *next;
 334
 335     QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
 336         if (bp->flags & mask) {
 337             cpu_breakpoint_remove_by_ref(cpu, bp);
 338         }
 339     }
 340 }
 341
 342 /* enable or disable single step mode. EXCP_DEBUG is returned by the
 343    CPU loop after each instruction */
 344 void cpu_single_step(CPUState *cpu, int enabled)
 345 {
 346     if (cpu->singlestep_enabled != enabled) {
 347         cpu->singlestep_enabled = enabled;
 348         if (kvm_enabled()) {
 349             kvm_update_guest_debug(cpu, 0);
 350         }
 351         trace_breakpoint_singlestep(cpu->cpu_index, enabled);
 352     }
 353 }
 354
 355 void cpu_abort(CPUState *cpu, const char *fmt, ...)
 356 {
 357     va_list ap;
 358     va_list ap2;
 359
 360     va_start(ap, fmt);
 361     va_copy(ap2, ap);
 362     fprintf(stderr, "qemu: fatal: ");
 363     vfprintf(stderr, fmt, ap);
 364     fprintf(stderr, "\n");
 365     cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 366     if (qemu_log_separate()) {
 367         FILE *logfile = qemu_log_lock();
 368         qemu_log("qemu: fatal: ");
 369         qemu_log_vprintf(fmt, ap2);
 370         qemu_log("\n");
 371         log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 372         qemu_log_flush();
 373         qemu_log_unlock(logfile);
 374         qemu_log_close();
 375     }
 376     va_end(ap2);
 377     va_end(ap);
 378     replay_finish();
 379 #if defined(CONFIG_USER_ONLY)
 380     {
 381         struct sigaction act;
 382         sigfillset(&act.sa_mask);
 383         act.sa_handler = SIG_DFL;
 384         act.sa_flags = 0;
 385         sigaction(SIGABRT, &act, NULL);
 386     }
 387 #endif
 388     abort();
 389 }
 390
 391 /* physical memory access (slow version, mainly for debug) */
 392 #if defined(CONFIG_USER_ONLY)
 393 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
 394                         void *ptr, target_ulong len, bool is_write)
 395 {
 396     int flags;
 397     target_ulong l, page;
 398     void * p;
 399     uint8_t *buf = ptr;
 400
 401     while (len > 0) {
 402         page = addr & TARGET_PAGE_MASK;
 403         l = (page + TARGET_PAGE_SIZE) - addr;
 404         if (l > len)
 405             l = len;
 406         flags = page_get_flags(page);
 407         if (!(flags & PAGE_VALID))
 408             return -1;
 409         if (is_write) {
 410             if (!(flags & PAGE_WRITE))
 411                 return -1;
 412             /* XXX: this code should not depend on lock_user */
 413             if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
 414                 return -1;
 415             memcpy(p, buf, l);
 416             unlock_user(p, addr, l);
 417         } else {
 418             if (!(flags & PAGE_READ))
 419                 return -1;
 420             /* XXX: this code should not depend on lock_user */
 421             if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
 422                 return -1;
 423             memcpy(buf, p, l);
 424             unlock_user(p, addr, 0);
 425         }
 426         len -= l;
 427         buf += l;
 428         addr += l;
 429     }
 430     return 0;
 431 }
 432 #endif
 433
 434 bool target_words_bigendian(void)
 435 {
 436 #if defined(TARGET_WORDS_BIGENDIAN)
 437     return true;
 438 #else
 439     return false;
 440 #endif
 441 }
 442
 443 void page_size_init(void)
 444 {
 445     /* NOTE: we can always suppose that qemu_host_page_size >=
 446        TARGET_PAGE_SIZE */
 447     if (qemu_host_page_size == 0) {
 448         qemu_host_page_size = qemu_real_host_page_size;
 449     }
 450     if (qemu_host_page_size < TARGET_PAGE_SIZE) {
 451         qemu_host_page_size = TARGET_PAGE_SIZE;
 452     }
 453     qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
 454 }