target-xtensa: implement LSAI group
[qemu.git] / hw / grlib_irqmp.c
blob9490a7830debec79a8eae9ae8783808ef20ceb0b
1 /*
2 * QEMU GRLIB IRQMP Emulator
4 * (Multiprocessor and extended interrupt not supported)
6 * Copyright (c) 2010-2011 AdaCore
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
27 #include "sysbus.h"
28 #include "cpu.h"
30 #include "grlib.h"
32 #include "trace.h"
34 #define IRQMP_MAX_CPU 16
35 #define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
37 /* Memory mapped register offsets */
38 #define LEVEL_OFFSET 0x00
39 #define PENDING_OFFSET 0x04
40 #define FORCE0_OFFSET 0x08
41 #define CLEAR_OFFSET 0x0C
42 #define MP_STATUS_OFFSET 0x10
43 #define BROADCAST_OFFSET 0x14
44 #define MASK_OFFSET 0x40
45 #define FORCE_OFFSET 0x80
46 #define EXTENDED_OFFSET 0xC0
48 typedef struct IRQMPState IRQMPState;
50 typedef struct IRQMP {
51 SysBusDevice busdev;
53 void *set_pil_in;
54 void *set_pil_in_opaque;
56 IRQMPState *state;
57 } IRQMP;
59 struct IRQMPState {
60 uint32_t level;
61 uint32_t pending;
62 uint32_t clear;
63 uint32_t broadcast;
65 uint32_t mask[IRQMP_MAX_CPU];
66 uint32_t force[IRQMP_MAX_CPU];
67 uint32_t extended[IRQMP_MAX_CPU];
69 IRQMP *parent;
72 static void grlib_irqmp_check_irqs(IRQMPState *state)
74 uint32_t pend = 0;
75 uint32_t level0 = 0;
76 uint32_t level1 = 0;
77 set_pil_in_fn set_pil_in;
79 assert(state != NULL);
80 assert(state->parent != NULL);
82 /* IRQ for CPU 0 (no SMP support) */
83 pend = (state->pending | state->force[0])
84 & state->mask[0];
86 level0 = pend & ~state->level;
87 level1 = pend & state->level;
89 trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
90 state->mask[0], level1, level0);
92 set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
94 /* Trigger level1 interrupt first and level0 if there is no level1 */
95 if (level1 != 0) {
96 set_pil_in(state->parent->set_pil_in_opaque, level1);
97 } else {
98 set_pil_in(state->parent->set_pil_in_opaque, level0);
102 void grlib_irqmp_ack(DeviceState *dev, int intno)
104 SysBusDevice *sdev;
105 IRQMP *irqmp;
106 IRQMPState *state;
107 uint32_t mask;
109 assert(dev != NULL);
111 sdev = sysbus_from_qdev(dev);
112 assert(sdev != NULL);
114 irqmp = FROM_SYSBUS(typeof(*irqmp), sdev);
115 assert(irqmp != NULL);
117 state = irqmp->state;
118 assert(state != NULL);
120 intno &= 15;
121 mask = 1 << intno;
123 trace_grlib_irqmp_ack(intno);
125 /* Clear registers */
126 state->pending &= ~mask;
127 state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
129 grlib_irqmp_check_irqs(state);
132 void grlib_irqmp_set_irq(void *opaque, int irq, int level)
134 IRQMP *irqmp;
135 IRQMPState *s;
136 int i = 0;
138 assert(opaque != NULL);
140 irqmp = FROM_SYSBUS(typeof(*irqmp), sysbus_from_qdev(opaque));
141 assert(irqmp != NULL);
143 s = irqmp->state;
144 assert(s != NULL);
145 assert(s->parent != NULL);
148 if (level) {
149 trace_grlib_irqmp_set_irq(irq);
151 if (s->broadcast & 1 << irq) {
152 /* Broadcasted IRQ */
153 for (i = 0; i < IRQMP_MAX_CPU; i++) {
154 s->force[i] |= 1 << irq;
156 } else {
157 s->pending |= 1 << irq;
159 grlib_irqmp_check_irqs(s);
164 static uint32_t grlib_irqmp_readl(void *opaque, target_phys_addr_t addr)
166 IRQMP *irqmp = opaque;
167 IRQMPState *state;
169 assert(irqmp != NULL);
170 state = irqmp->state;
171 assert(state != NULL);
173 addr &= 0xff;
175 /* global registers */
176 switch (addr) {
177 case LEVEL_OFFSET:
178 return state->level;
180 case PENDING_OFFSET:
181 return state->pending;
183 case FORCE0_OFFSET:
184 /* This register is an "alias" for the force register of CPU 0 */
185 return state->force[0];
187 case CLEAR_OFFSET:
188 case MP_STATUS_OFFSET:
189 /* Always read as 0 */
190 return 0;
192 case BROADCAST_OFFSET:
193 return state->broadcast;
195 default:
196 break;
199 /* mask registers */
200 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
201 int cpu = (addr - MASK_OFFSET) / 4;
202 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
204 return state->mask[cpu];
207 /* force registers */
208 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
209 int cpu = (addr - FORCE_OFFSET) / 4;
210 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
212 return state->force[cpu];
215 /* extended (not supported) */
216 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
217 int cpu = (addr - EXTENDED_OFFSET) / 4;
218 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
220 return state->extended[cpu];
223 trace_grlib_irqmp_readl_unknown(addr);
224 return 0;
227 static void
228 grlib_irqmp_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
230 IRQMP *irqmp = opaque;
231 IRQMPState *state;
233 assert(irqmp != NULL);
234 state = irqmp->state;
235 assert(state != NULL);
237 addr &= 0xff;
239 /* global registers */
240 switch (addr) {
241 case LEVEL_OFFSET:
242 value &= 0xFFFF << 1; /* clean up the value */
243 state->level = value;
244 return;
246 case PENDING_OFFSET:
247 /* Read Only */
248 return;
250 case FORCE0_OFFSET:
251 /* This register is an "alias" for the force register of CPU 0 */
253 value &= 0xFFFE; /* clean up the value */
254 state->force[0] = value;
255 grlib_irqmp_check_irqs(irqmp->state);
256 return;
258 case CLEAR_OFFSET:
259 value &= ~1; /* clean up the value */
260 state->pending &= ~value;
261 return;
263 case MP_STATUS_OFFSET:
264 /* Read Only (no SMP support) */
265 return;
267 case BROADCAST_OFFSET:
268 value &= 0xFFFE; /* clean up the value */
269 state->broadcast = value;
270 return;
272 default:
273 break;
276 /* mask registers */
277 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
278 int cpu = (addr - MASK_OFFSET) / 4;
279 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
281 value &= ~1; /* clean up the value */
282 state->mask[cpu] = value;
283 grlib_irqmp_check_irqs(irqmp->state);
284 return;
287 /* force registers */
288 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
289 int cpu = (addr - FORCE_OFFSET) / 4;
290 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
292 uint32_t force = value & 0xFFFE;
293 uint32_t clear = (value >> 16) & 0xFFFE;
294 uint32_t old = state->force[cpu];
296 state->force[cpu] = (old | force) & ~clear;
297 grlib_irqmp_check_irqs(irqmp->state);
298 return;
301 /* extended (not supported) */
302 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
303 int cpu = (addr - EXTENDED_OFFSET) / 4;
304 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
306 value &= 0xF; /* clean up the value */
307 state->extended[cpu] = value;
308 return;
311 trace_grlib_irqmp_writel_unknown(addr, value);
314 static CPUReadMemoryFunc * const grlib_irqmp_read[] = {
315 NULL, NULL, &grlib_irqmp_readl,
318 static CPUWriteMemoryFunc * const grlib_irqmp_write[] = {
319 NULL, NULL, &grlib_irqmp_writel,
322 static void grlib_irqmp_reset(DeviceState *d)
324 IRQMP *irqmp = container_of(d, IRQMP, busdev.qdev);
325 assert(irqmp != NULL);
326 assert(irqmp->state != NULL);
328 memset(irqmp->state, 0, sizeof *irqmp->state);
329 irqmp->state->parent = irqmp;
332 static int grlib_irqmp_init(SysBusDevice *dev)
334 IRQMP *irqmp = FROM_SYSBUS(typeof(*irqmp), dev);
335 int irqmp_regs;
337 assert(irqmp != NULL);
339 /* Check parameters */
340 if (irqmp->set_pil_in == NULL) {
341 return -1;
344 irqmp_regs = cpu_register_io_memory(grlib_irqmp_read,
345 grlib_irqmp_write,
346 irqmp, DEVICE_NATIVE_ENDIAN);
348 irqmp->state = g_malloc0(sizeof *irqmp->state);
350 if (irqmp_regs < 0) {
351 return -1;
354 sysbus_init_mmio(dev, IRQMP_REG_SIZE, irqmp_regs);
356 return 0;
359 static SysBusDeviceInfo grlib_irqmp_info = {
360 .init = grlib_irqmp_init,
361 .qdev.name = "grlib,irqmp",
362 .qdev.reset = grlib_irqmp_reset,
363 .qdev.size = sizeof(IRQMP),
364 .qdev.props = (Property[]) {
365 DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
366 DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
367 DEFINE_PROP_END_OF_LIST(),
371 static void grlib_irqmp_register(void)
373 sysbus_register_withprop(&grlib_irqmp_info);
376 device_init(grlib_irqmp_register)