user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/bitops.h"
  24
  25 #undef EAX
  26 #undef ECX
  27 #undef EDX
  28 #undef EBX
  29 #undef ESP
  30 #undef EBP
  31 #undef ESI
  32 #undef EDI
  33 #undef EIP
  34 #include <signal.h>
  35 #ifdef __linux__
  36 #include <sys/ucontext.h>
  37 #endif
  38
  39 //#define DEBUG_SIGNAL
  40
  41 static void exception_action(CPUArchState *env1)
  42 {
  43 #if defined(TARGET_I386)
  44     raise_exception_err(env1, env1->exception_index, env1->error_code);
  45 #else
  46     cpu_loop_exit(env1);
  47 #endif
  48 }
  49
  50 /* exit the current TB from a signal handler. The host registers are
  51    restored in a state compatible with the CPU emulator
  52  */
  53 void cpu_resume_from_signal(CPUArchState *env1, void *puc)
  54 {
  55 #ifdef __linux__
  56     struct ucontext *uc = puc;
  57 #elif defined(__OpenBSD__)
  58     struct sigcontext *uc = puc;
  59 #endif
  60
  61     if (puc) {
  62         /* XXX: use siglongjmp ? */
  63 #ifdef __linux__
  64 #ifdef __ia64
  65         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  66 #else
  67         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  68 #endif
  69 #elif defined(__OpenBSD__)
  70         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  71 #endif
  72     }
  73     env1->exception_index = -1;
  74     siglongjmp(env1->jmp_env, 1);
  75 }
  76
  77 /* 'pc' is the host PC at which the exception was raised. 'address' is
  78    the effective address of the memory exception. 'is_write' is 1 if a
  79    write caused the exception and otherwise 0'. 'old_set' is the
  80    signal set which should be restored */
  81 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
  82                                     int is_write, sigset_t *old_set,
  83                                     void *puc)
  84 {
  85     CPUArchState *env;
  86     int ret;
  87
  88 #if defined(DEBUG_SIGNAL)
  89     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  90                 pc, address, is_write, *(unsigned long *)old_set);
  91 #endif
  92     /* XXX: locking issue */
  93     if (is_write && h2g_valid(address)
  94         && page_unprotect(h2g(address), pc, puc)) {
  95         return 1;
  96     }
  97
  98     env = current_cpu->env_ptr;
  99     /* see if it is an MMU fault */
 100     ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
 101     if (ret < 0) {
 102         return 0; /* not an MMU fault */
 103     }
 104     if (ret == 0) {
 105         return 1; /* the MMU fault was handled without causing real CPU fault */
 106     }
 107     /* now we have a real cpu fault */
 108     cpu_restore_state(env, pc);
 109
 110     /* we restore the process signal mask as the sigreturn should
 111        do it (XXX: use sigsetjmp) */
 112     sigprocmask(SIG_SETMASK, old_set, NULL);
 113     exception_action(env);
 114
 115     /* never comes here */
 116     return 1;
 117 }
 118
 119 #if defined(__i386__)
 120
 121 #if defined(__APPLE__)
 122 #include <sys/ucontext.h>
 123
 124 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
 125 #define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 126 #define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 127 #define MASK_sig(context)    ((context)->uc_sigmask)
 128 #elif defined(__NetBSD__)
 129 #include <ucontext.h>
 130
 131 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 132 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 133 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 134 #define MASK_sig(context)    ((context)->uc_sigmask)
 135 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 136 #include <ucontext.h>
 137
 138 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 139 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 140 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 141 #define MASK_sig(context)    ((context)->uc_sigmask)
 142 #elif defined(__OpenBSD__)
 143 #define EIP_sig(context)     ((context)->sc_eip)
 144 #define TRAP_sig(context)    ((context)->sc_trapno)
 145 #define ERROR_sig(context)   ((context)->sc_err)
 146 #define MASK_sig(context)    ((context)->sc_mask)
 147 #else
 148 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 149 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 150 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 151 #define MASK_sig(context)    ((context)->uc_sigmask)
 152 #endif
 153
 154 int cpu_signal_handler(int host_signum, void *pinfo,
 155                        void *puc)
 156 {
 157     siginfo_t *info = pinfo;
 158 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 159     ucontext_t *uc = puc;
 160 #elif defined(__OpenBSD__)
 161     struct sigcontext *uc = puc;
 162 #else
 163     struct ucontext *uc = puc;
 164 #endif
 165     unsigned long pc;
 166     int trapno;
 167
 168 #ifndef REG_EIP
 169 /* for glibc 2.1 */
 170 #define REG_EIP    EIP
 171 #define REG_ERR    ERR
 172 #define REG_TRAPNO TRAPNO
 173 #endif
 174     pc = EIP_sig(uc);
 175     trapno = TRAP_sig(uc);
 176     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 177                              trapno == 0xe ?
 178                              (ERROR_sig(uc) >> 1) & 1 : 0,
 179                              &MASK_sig(uc), puc);
 180 }
 181
 182 #elif defined(__x86_64__)
 183
 184 #ifdef __NetBSD__
 185 #define PC_sig(context)       _UC_MACHINE_PC(context)
 186 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 187 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 188 #define MASK_sig(context)     ((context)->uc_sigmask)
 189 #elif defined(__OpenBSD__)
 190 #define PC_sig(context)       ((context)->sc_rip)
 191 #define TRAP_sig(context)     ((context)->sc_trapno)
 192 #define ERROR_sig(context)    ((context)->sc_err)
 193 #define MASK_sig(context)     ((context)->sc_mask)
 194 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 195 #include <ucontext.h>
 196
 197 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 198 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 199 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 200 #define MASK_sig(context)     ((context)->uc_sigmask)
 201 #else
 202 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 203 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 204 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 205 #define MASK_sig(context)     ((context)->uc_sigmask)
 206 #endif
 207
 208 int cpu_signal_handler(int host_signum, void *pinfo,
 209                        void *puc)
 210 {
 211     siginfo_t *info = pinfo;
 212     unsigned long pc;
 213 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 214     ucontext_t *uc = puc;
 215 #elif defined(__OpenBSD__)
 216     struct sigcontext *uc = puc;
 217 #else
 218     struct ucontext *uc = puc;
 219 #endif
 220
 221     pc = PC_sig(uc);
 222     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 223                              TRAP_sig(uc) == 0xe ?
 224                              (ERROR_sig(uc) >> 1) & 1 : 0,
 225                              &MASK_sig(uc), puc);
 226 }
 227
 228 #elif defined(_ARCH_PPC)
 229
 230 /***********************************************************************
 231  * signal context platform-specific definitions
 232  * From Wine
 233  */
 234 #ifdef linux
 235 /* All Registers access - only for local access */
 236 #define REG_sig(reg_name, context)              \
 237     ((context)->uc_mcontext.regs->reg_name)
 238 /* Gpr Registers access  */
 239 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 240 /* Program counter */
 241 #define IAR_sig(context)                       REG_sig(nip, context)
 242 /* Machine State Register (Supervisor) */
 243 #define MSR_sig(context)                       REG_sig(msr, context)
 244 /* Count register */
 245 #define CTR_sig(context)                       REG_sig(ctr, context)
 246 /* User's integer exception register */
 247 #define XER_sig(context)                       REG_sig(xer, context)
 248 /* Link register */
 249 #define LR_sig(context)                        REG_sig(link, context)
 250 /* Condition register */
 251 #define CR_sig(context)                        REG_sig(ccr, context)
 252
 253 /* Float Registers access  */
 254 #define FLOAT_sig(reg_num, context)                                     \
 255     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 256 #define FPSCR_sig(context) \
 257     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 258 /* Exception Registers access */
 259 #define DAR_sig(context)                       REG_sig(dar, context)
 260 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 261 #define TRAP_sig(context)                      REG_sig(trap, context)
 262 #endif /* linux */
 263
 264 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 265 #include <ucontext.h>
 266 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 267 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 268 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 269 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 270 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 271 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 272 /* Exception Registers access */
 273 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 274 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 275 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 276 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 277
 278 #ifdef __APPLE__
 279 #include <sys/ucontext.h>
 280 typedef struct ucontext SIGCONTEXT;
 281 /* All Registers access - only for local access */
 282 #define REG_sig(reg_name, context)              \
 283     ((context)->uc_mcontext->ss.reg_name)
 284 #define FLOATREG_sig(reg_name, context)         \
 285     ((context)->uc_mcontext->fs.reg_name)
 286 #define EXCEPREG_sig(reg_name, context)         \
 287     ((context)->uc_mcontext->es.reg_name)
 288 #define VECREG_sig(reg_name, context)           \
 289     ((context)->uc_mcontext->vs.reg_name)
 290 /* Gpr Registers access */
 291 #define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 292 /* Program counter */
 293 #define IAR_sig(context)                       REG_sig(srr0, context)
 294 /* Machine State Register (Supervisor) */
 295 #define MSR_sig(context)                       REG_sig(srr1, context)
 296 #define CTR_sig(context)                       REG_sig(ctr, context)
 297 /* Link register */
 298 #define XER_sig(context)                       REG_sig(xer, context)
 299 /* User's integer exception register */
 300 #define LR_sig(context)                        REG_sig(lr, context)
 301 /* Condition register */
 302 #define CR_sig(context)                        REG_sig(cr, context)
 303 /* Float Registers access */
 304 #define FLOAT_sig(reg_num, context)             \
 305     FLOATREG_sig(fpregs[reg_num], context)
 306 #define FPSCR_sig(context)                      \
 307     ((double)FLOATREG_sig(fpscr, context))
 308 /* Exception Registers access */
 309 /* Fault registers for coredump */
 310 #define DAR_sig(context)                       EXCEPREG_sig(dar, context)
 311 #define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 312 /* number of powerpc exception taken */
 313 #define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
 314 #endif /* __APPLE__ */
 315
 316 int cpu_signal_handler(int host_signum, void *pinfo,
 317                        void *puc)
 318 {
 319     siginfo_t *info = pinfo;
 320 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 321     ucontext_t *uc = puc;
 322 #else
 323     struct ucontext *uc = puc;
 324 #endif
 325     unsigned long pc;
 326     int is_write;
 327
 328     pc = IAR_sig(uc);
 329     is_write = 0;
 330 #if 0
 331     /* ppc 4xx case */
 332     if (DSISR_sig(uc) & 0x00800000) {
 333         is_write = 1;
 334     }
 335 #else
 336     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 337         is_write = 1;
 338     }
 339 #endif
 340     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 341                              is_write, &uc->uc_sigmask, puc);
 342 }
 343
 344 #elif defined(__alpha__)
 345
 346 int cpu_signal_handler(int host_signum, void *pinfo,
 347                            void *puc)
 348 {
 349     siginfo_t *info = pinfo;
 350     struct ucontext *uc = puc;
 351     uint32_t *pc = uc->uc_mcontext.sc_pc;
 352     uint32_t insn = *pc;
 353     int is_write = 0;
 354
 355     /* XXX: need kernel patch to get write flag faster */
 356     switch (insn >> 26) {
 357     case 0x0d: /* stw */
 358     case 0x0e: /* stb */
 359     case 0x0f: /* stq_u */
 360     case 0x24: /* stf */
 361     case 0x25: /* stg */
 362     case 0x26: /* sts */
 363     case 0x27: /* stt */
 364     case 0x2c: /* stl */
 365     case 0x2d: /* stq */
 366     case 0x2e: /* stl_c */
 367     case 0x2f: /* stq_c */
 368         is_write = 1;
 369     }
 370
 371     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 372                              is_write, &uc->uc_sigmask, puc);
 373 }
 374 #elif defined(__sparc__)
 375
 376 int cpu_signal_handler(int host_signum, void *pinfo,
 377                        void *puc)
 378 {
 379     siginfo_t *info = pinfo;
 380     int is_write;
 381     uint32_t insn;
 382 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 383     uint32_t *regs = (uint32_t *)(info + 1);
 384     void *sigmask = (regs + 20);
 385     /* XXX: is there a standard glibc define ? */
 386     unsigned long pc = regs[1];
 387 #else
 388 #ifdef __linux__
 389     struct sigcontext *sc = puc;
 390     unsigned long pc = sc->sigc_regs.tpc;
 391     void *sigmask = (void *)sc->sigc_mask;
 392 #elif defined(__OpenBSD__)
 393     struct sigcontext *uc = puc;
 394     unsigned long pc = uc->sc_pc;
 395     void *sigmask = (void *)(long)uc->sc_mask;
 396 #endif
 397 #endif
 398
 399     /* XXX: need kernel patch to get write flag faster */
 400     is_write = 0;
 401     insn = *(uint32_t *)pc;
 402     if ((insn >> 30) == 3) {
 403         switch ((insn >> 19) & 0x3f) {
 404         case 0x05: /* stb */
 405         case 0x15: /* stba */
 406         case 0x06: /* sth */
 407         case 0x16: /* stha */
 408         case 0x04: /* st */
 409         case 0x14: /* sta */
 410         case 0x07: /* std */
 411         case 0x17: /* stda */
 412         case 0x0e: /* stx */
 413         case 0x1e: /* stxa */
 414         case 0x24: /* stf */
 415         case 0x34: /* stfa */
 416         case 0x27: /* stdf */
 417         case 0x37: /* stdfa */
 418         case 0x26: /* stqf */
 419         case 0x36: /* stqfa */
 420         case 0x25: /* stfsr */
 421         case 0x3c: /* casa */
 422         case 0x3e: /* casxa */
 423             is_write = 1;
 424             break;
 425         }
 426     }
 427     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 428                              is_write, sigmask, NULL);
 429 }
 430
 431 #elif defined(__arm__)
 432
 433 int cpu_signal_handler(int host_signum, void *pinfo,
 434                        void *puc)
 435 {
 436     siginfo_t *info = pinfo;
 437     struct ucontext *uc = puc;
 438     unsigned long pc;
 439     int is_write;
 440
 441 #if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 442     pc = uc->uc_mcontext.gregs[R15];
 443 #else
 444     pc = uc->uc_mcontext.arm_pc;
 445 #endif
 446
 447     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 448      * later processor; on v5 we will always report this as a read).
 449      */
 450     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 451     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 452                              is_write,
 453                              &uc->uc_sigmask, puc);
 454 }
 455
 456 #elif defined(__aarch64__)
 457
 458 int cpu_signal_handler(int host_signum, void *pinfo,
 459                        void *puc)
 460 {
 461     siginfo_t *info = pinfo;
 462     struct ucontext *uc = puc;
 463     uint64_t pc;
 464     int is_write = 0; /* XXX how to determine? */
 465
 466     pc = uc->uc_mcontext.pc;
 467     return handle_cpu_signal(pc, (uint64_t)info->si_addr,
 468                              is_write, &uc->uc_sigmask, puc);
 469 }
 470
 471 #elif defined(__mc68000)
 472
 473 int cpu_signal_handler(int host_signum, void *pinfo,
 474                        void *puc)
 475 {
 476     siginfo_t *info = pinfo;
 477     struct ucontext *uc = puc;
 478     unsigned long pc;
 479     int is_write;
 480
 481     pc = uc->uc_mcontext.gregs[16];
 482     /* XXX: compute is_write */
 483     is_write = 0;
 484     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 485                              is_write,
 486                              &uc->uc_sigmask, puc);
 487 }
 488
 489 #elif defined(__ia64)
 490
 491 #ifndef __ISR_VALID
 492   /* This ought to be in <bits/siginfo.h>... */
 493 # define __ISR_VALID    1
 494 #endif
 495
 496 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 497 {
 498     siginfo_t *info = pinfo;
 499     struct ucontext *uc = puc;
 500     unsigned long ip;
 501     int is_write = 0;
 502
 503     ip = uc->uc_mcontext.sc_ip;
 504     switch (host_signum) {
 505     case SIGILL:
 506     case SIGFPE:
 507     case SIGSEGV:
 508     case SIGBUS:
 509     case SIGTRAP:
 510         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 511             /* ISR.W (write-access) is bit 33:  */
 512             is_write = (info->si_isr >> 33) & 1;
 513         }
 514         break;
 515
 516     default:
 517         break;
 518     }
 519     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
 520                              is_write,
 521                              (sigset_t *)&uc->uc_sigmask, puc);
 522 }
 523
 524 #elif defined(__s390__)
 525
 526 int cpu_signal_handler(int host_signum, void *pinfo,
 527                        void *puc)
 528 {
 529     siginfo_t *info = pinfo;
 530     struct ucontext *uc = puc;
 531     unsigned long pc;
 532     uint16_t *pinsn;
 533     int is_write = 0;
 534
 535     pc = uc->uc_mcontext.psw.addr;
 536
 537     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 538        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 539        from the hardware which does in fact contain the is_write value.
 540        The rt signal handler, as far as I can tell, does not give this value
 541        at all.  Not that we could get to it from here even if it were.  */
 542     /* ??? This is not even close to complete, since it ignores all
 543        of the read-modify-write instructions.  */
 544     pinsn = (uint16_t *)pc;
 545     switch (pinsn[0] >> 8) {
 546     case 0x50: /* ST */
 547     case 0x42: /* STC */
 548     case 0x40: /* STH */
 549         is_write = 1;
 550         break;
 551     case 0xc4: /* RIL format insns */
 552         switch (pinsn[0] & 0xf) {
 553         case 0xf: /* STRL */
 554         case 0xb: /* STGRL */
 555         case 0x7: /* STHRL */
 556             is_write = 1;
 557         }
 558         break;
 559     case 0xe3: /* RXY format insns */
 560         switch (pinsn[2] & 0xff) {
 561         case 0x50: /* STY */
 562         case 0x24: /* STG */
 563         case 0x72: /* STCY */
 564         case 0x70: /* STHY */
 565         case 0x8e: /* STPQ */
 566         case 0x3f: /* STRVH */
 567         case 0x3e: /* STRV */
 568         case 0x2f: /* STRVG */
 569             is_write = 1;
 570         }
 571         break;
 572     }
 573     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 574                              is_write, &uc->uc_sigmask, puc);
 575 }
 576
 577 #elif defined(__mips__)
 578
 579 int cpu_signal_handler(int host_signum, void *pinfo,
 580                        void *puc)
 581 {
 582     siginfo_t *info = pinfo;
 583     struct ucontext *uc = puc;
 584     greg_t pc = uc->uc_mcontext.pc;
 585     int is_write;
 586
 587     /* XXX: compute is_write */
 588     is_write = 0;
 589     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 590                              is_write, &uc->uc_sigmask, puc);
 591 }
 592
 593 #elif defined(__hppa__)
 594
 595 int cpu_signal_handler(int host_signum, void *pinfo,
 596                        void *puc)
 597 {
 598     siginfo_t *info = pinfo;
 599     struct ucontext *uc = puc;
 600     unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
 601     uint32_t insn = *(uint32_t *)pc;
 602     int is_write = 0;
 603
 604     /* XXX: need kernel patch to get write flag faster.  */
 605     switch (insn >> 26) {
 606     case 0x1a: /* STW */
 607     case 0x19: /* STH */
 608     case 0x18: /* STB */
 609     case 0x1b: /* STWM */
 610         is_write = 1;
 611         break;
 612
 613     case 0x09: /* CSTWX, FSTWX, FSTWS */
 614     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 615         /* Distinguish from coprocessor load ... */
 616         is_write = (insn >> 9) & 1;
 617         break;
 618
 619     case 0x03:
 620         switch ((insn >> 6) & 15) {
 621         case 0xa: /* STWS */
 622         case 0x9: /* STHS */
 623         case 0x8: /* STBS */
 624         case 0xe: /* STWAS */
 625         case 0xc: /* STBYS */
 626             is_write = 1;
 627         }
 628         break;
 629     }
 630
 631     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 632                              is_write, &uc->uc_sigmask, puc);
 633 }
 634
 635 #else
 636
 637 #error host CPU specific signal handler needed
 638
 639 #endif