?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
VMDK: open/read/write for monolithicFlat image
[qemu.git] / hw / usb-ohci.c
blob1c29b9fa6c3f4c973a42aa864b7220434548a747
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
27 */
28
29 #include "hw.h"
30 #include "qemu-timer.h"
31 #include "usb.h"
32 #include "pci.h"
33 #include "usb-ohci.h"
34 #include "sysbus.h"
35 #include "qdev-addr.h"
36
37 //#define DEBUG_OHCI
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
40 //#define DEBUG_ISOCH
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #ifdef DEBUG_OHCI
45 #define DPRINTF printf
46 #else
47 #define DPRINTF(...)
48 #endif
49
50 /* Number of Downstream Ports on the root hub. */
51
52 #define OHCI_MAX_PORTS 15
53
54 static int64_t usb_frame_time;
55 static int64_t usb_bit_time;
56
57 typedef struct OHCIPort {
58 USBPort port;
59 uint32_t ctrl;
60 } OHCIPort;
61
62 typedef struct {
63 USBBus bus;
64 qemu_irq irq;
65 int mem;
66 int num_ports;
67 const char *name;
68
69 QEMUTimer *eof_timer;
70 int64_t sof_time;
71
72 /* OHCI state */
73 /* Control partition */
74 uint32_t ctl, status;
75 uint32_t intr_status;
76 uint32_t intr;
77
78 /* memory pointer partition */
79 uint32_t hcca;
80 uint32_t ctrl_head, ctrl_cur;
81 uint32_t bulk_head, bulk_cur;
82 uint32_t per_cur;
83 uint32_t done;
84 int done_count;
85
86 /* Frame counter partition */
87 uint32_t fsmps:15;
88 uint32_t fit:1;
89 uint32_t fi:14;
90 uint32_t frt:1;
91 uint16_t frame_number;
92 uint16_t padding;
93 uint32_t pstart;
94 uint32_t lst;
95
96 /* Root Hub partition */
97 uint32_t rhdesc_a, rhdesc_b;
98 uint32_t rhstatus;
99 OHCIPort rhport[OHCI_MAX_PORTS];
100
101 /* PXA27x Non-OHCI events */
102 uint32_t hstatus;
103 uint32_t hmask;
104 uint32_t hreset;
105 uint32_t htest;
106
107 /* SM501 local memory offset */
108 target_phys_addr_t localmem_base;
109
110 /* Active packets. */
111 uint32_t old_ctl;
112 USBPacket usb_packet;
113 uint8_t usb_buf[8192];
114 uint32_t async_td;
115 int async_complete;
116
117 } OHCIState;
118
119 /* Host Controller Communications Area */
120 struct ohci_hcca {
121 uint32_t intr[32];
122 uint16_t frame, pad;
123 uint32_t done;
124 };
125
126 static void ohci_bus_stop(OHCIState *ohci);
127
128 /* Bitfields for the first word of an Endpoint Desciptor. */
129 #define OHCI_ED_FA_SHIFT 0
130 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
131 #define OHCI_ED_EN_SHIFT 7
132 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
133 #define OHCI_ED_D_SHIFT 11
134 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
135 #define OHCI_ED_S (1<<13)
136 #define OHCI_ED_K (1<<14)
137 #define OHCI_ED_F (1<<15)
138 #define OHCI_ED_MPS_SHIFT 16
139 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
140
141 /* Flags in the head field of an Endpoint Desciptor. */
142 #define OHCI_ED_H 1
143 #define OHCI_ED_C 2
144
145 /* Bitfields for the first word of a Transfer Desciptor. */
146 #define OHCI_TD_R (1<<18)
147 #define OHCI_TD_DP_SHIFT 19
148 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
149 #define OHCI_TD_DI_SHIFT 21
150 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
151 #define OHCI_TD_T0 (1<<24)
152 #define OHCI_TD_T1 (1<<24)
153 #define OHCI_TD_EC_SHIFT 26
154 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
155 #define OHCI_TD_CC_SHIFT 28
156 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
157
158 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
159 /* CC & DI - same as in the General Transfer Desciptor */
160 #define OHCI_TD_SF_SHIFT 0
161 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
162 #define OHCI_TD_FC_SHIFT 24
163 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
164
165 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
166 #define OHCI_TD_PSW_CC_SHIFT 12
167 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
168 #define OHCI_TD_PSW_SIZE_SHIFT 0
169 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
170
171 #define OHCI_PAGE_MASK 0xfffff000
172 #define OHCI_OFFSET_MASK 0xfff
173
174 #define OHCI_DPTR_MASK 0xfffffff0
175
176 #define OHCI_BM(val, field) \
177 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
178
179 #define OHCI_SET_BM(val, field, newval) do { \
180 val &= ~OHCI_##field##_MASK; \
181 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
182 } while(0)
183
184 /* endpoint descriptor */
185 struct ohci_ed {
186 uint32_t flags;
187 uint32_t tail;
188 uint32_t head;
189 uint32_t next;
190 };
191
192 /* General transfer descriptor */
193 struct ohci_td {
194 uint32_t flags;
195 uint32_t cbp;
196 uint32_t next;
197 uint32_t be;
198 };
199
200 /* Isochronous transfer descriptor */
201 struct ohci_iso_td {
202 uint32_t flags;
203 uint32_t bp;
204 uint32_t next;
205 uint32_t be;
206 uint16_t offset[8];
207 };
208
209 #define USB_HZ 12000000
210
211 /* OHCI Local stuff */
212 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
213 #define OHCI_CTL_PLE (1<<2)
214 #define OHCI_CTL_IE (1<<3)
215 #define OHCI_CTL_CLE (1<<4)
216 #define OHCI_CTL_BLE (1<<5)
217 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
218 #define OHCI_USB_RESET 0x00
219 #define OHCI_USB_RESUME 0x40
220 #define OHCI_USB_OPERATIONAL 0x80
221 #define OHCI_USB_SUSPEND 0xc0
222 #define OHCI_CTL_IR (1<<8)
223 #define OHCI_CTL_RWC (1<<9)
224 #define OHCI_CTL_RWE (1<<10)
225
226 #define OHCI_STATUS_HCR (1<<0)
227 #define OHCI_STATUS_CLF (1<<1)
228 #define OHCI_STATUS_BLF (1<<2)
229 #define OHCI_STATUS_OCR (1<<3)
230 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
231
232 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
233 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
234 #define OHCI_INTR_SF (1<<2) /* Start of frame */
235 #define OHCI_INTR_RD (1<<3) /* Resume detect */
236 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
237 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
238 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
239 #define OHCI_INTR_OC (1<<30) /* Ownership change */
240 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
241
242 #define OHCI_HCCA_SIZE 0x100
243 #define OHCI_HCCA_MASK 0xffffff00
244
245 #define OHCI_EDPTR_MASK 0xfffffff0
246
247 #define OHCI_FMI_FI 0x00003fff
248 #define OHCI_FMI_FSMPS 0xffff0000
249 #define OHCI_FMI_FIT 0x80000000
250
251 #define OHCI_FR_RT (1<<31)
252
253 #define OHCI_LS_THRESH 0x628
254
255 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
256 #define OHCI_RHA_PSM (1<<8)
257 #define OHCI_RHA_NPS (1<<9)
258 #define OHCI_RHA_DT (1<<10)
259 #define OHCI_RHA_OCPM (1<<11)
260 #define OHCI_RHA_NOCP (1<<12)
261 #define OHCI_RHA_POTPGT_MASK 0xff000000
262
263 #define OHCI_RHS_LPS (1<<0)
264 #define OHCI_RHS_OCI (1<<1)
265 #define OHCI_RHS_DRWE (1<<15)
266 #define OHCI_RHS_LPSC (1<<16)
267 #define OHCI_RHS_OCIC (1<<17)
268 #define OHCI_RHS_CRWE (1<<31)
269
270 #define OHCI_PORT_CCS (1<<0)
271 #define OHCI_PORT_PES (1<<1)
272 #define OHCI_PORT_PSS (1<<2)
273 #define OHCI_PORT_POCI (1<<3)
274 #define OHCI_PORT_PRS (1<<4)
275 #define OHCI_PORT_PPS (1<<8)
276 #define OHCI_PORT_LSDA (1<<9)
277 #define OHCI_PORT_CSC (1<<16)
278 #define OHCI_PORT_PESC (1<<17)
279 #define OHCI_PORT_PSSC (1<<18)
280 #define OHCI_PORT_OCIC (1<<19)
281 #define OHCI_PORT_PRSC (1<<20)
282 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
283 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
284
285 #define OHCI_TD_DIR_SETUP 0x0
286 #define OHCI_TD_DIR_OUT 0x1
287 #define OHCI_TD_DIR_IN 0x2
288 #define OHCI_TD_DIR_RESERVED 0x3
289
290 #define OHCI_CC_NOERROR 0x0
291 #define OHCI_CC_CRC 0x1
292 #define OHCI_CC_BITSTUFFING 0x2
293 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
294 #define OHCI_CC_STALL 0x4
295 #define OHCI_CC_DEVICENOTRESPONDING 0x5
296 #define OHCI_CC_PIDCHECKFAILURE 0x6
297 #define OHCI_CC_UNDEXPETEDPID 0x7
298 #define OHCI_CC_DATAOVERRUN 0x8
299 #define OHCI_CC_DATAUNDERRUN 0x9
300 #define OHCI_CC_BUFFEROVERRUN 0xc
301 #define OHCI_CC_BUFFERUNDERRUN 0xd
302
303 #define OHCI_HRESET_FSBIR (1 << 0)
304
305 /* Update IRQ levels */
306 static inline void ohci_intr_update(OHCIState *ohci)
307 {
308 int level = 0;
309
310 if ((ohci->intr & OHCI_INTR_MIE) &&
311 (ohci->intr_status & ohci->intr))
312 level = 1;
313
314 qemu_set_irq(ohci->irq, level);
315 }
316
317 /* Set an interrupt */
318 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
319 {
320 ohci->intr_status |= intr;
321 ohci_intr_update(ohci);
322 }
323
324 /* Attach or detach a device on a root hub port. */
325 static void ohci_attach(USBPort *port1)
326 {
327 OHCIState *s = port1->opaque;
328 OHCIPort *port = &s->rhport[port1->index];
329
330 /* set connect status */
331 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
332
333 /* update speed */
334 if (port->port.dev->speed == USB_SPEED_LOW) {
335 port->ctrl |= OHCI_PORT_LSDA;
336 } else {
337 port->ctrl &= ~OHCI_PORT_LSDA;
338 }
339
340 /* notify of remote-wakeup */
341 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
342 ohci_set_interrupt(s, OHCI_INTR_RD);
343 }
344
345 DPRINTF("usb-ohci: Attached port %d\n", port1->index);
346 }
347
348 static void ohci_detach(USBPort *port1)
349 {
350 OHCIState *s = port1->opaque;
351 OHCIPort *port = &s->rhport[port1->index];
352 uint32_t old_state = port->ctrl;
353
354 /* set connect status */
355 if (port->ctrl & OHCI_PORT_CCS) {
356 port->ctrl &= ~OHCI_PORT_CCS;
357 port->ctrl |= OHCI_PORT_CSC;
358 }
359 /* disable port */
360 if (port->ctrl & OHCI_PORT_PES) {
361 port->ctrl &= ~OHCI_PORT_PES;
362 port->ctrl |= OHCI_PORT_PESC;
363 }
364 DPRINTF("usb-ohci: Detached port %d\n", port1->index);
365
366 if (old_state != port->ctrl)
367 ohci_set_interrupt(s, OHCI_INTR_RHSC);
368 }
369
370 static void ohci_wakeup(USBDevice *dev)
371 {
372 USBBus *bus = usb_bus_from_device(dev);
373 OHCIState *s = container_of(bus, OHCIState, bus);
374 int portnum = dev->port->index;
375 OHCIPort *port = &s->rhport[portnum];
376 uint32_t intr = 0;
377 if (port->ctrl & OHCI_PORT_PSS) {
378 DPRINTF("usb-ohci: port %d: wakeup\n", portnum);
379 port->ctrl |= OHCI_PORT_PSSC;
380 port->ctrl &= ~OHCI_PORT_PSS;
381 intr = OHCI_INTR_RHSC;
382 }
383 /* Note that the controller can be suspended even if this port is not */
384 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
385 DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
386 /* This is the one state transition the controller can do by itself */
387 s->ctl &= ~OHCI_CTL_HCFS;
388 s->ctl |= OHCI_USB_RESUME;
389 /* In suspend mode only ResumeDetected is possible, not RHSC:
390 * see the OHCI spec 5.1.2.3.
391 */
392 intr = OHCI_INTR_RD;
393 }
394 ohci_set_interrupt(s, intr);
395 }
396
397 /* Reset the controller */
398 static void ohci_reset(void *opaque)
399 {
400 OHCIState *ohci = opaque;
401 OHCIPort *port;
402 int i;
403
404 ohci_bus_stop(ohci);
405 ohci->ctl = 0;
406 ohci->old_ctl = 0;
407 ohci->status = 0;
408 ohci->intr_status = 0;
409 ohci->intr = OHCI_INTR_MIE;
410
411 ohci->hcca = 0;
412 ohci->ctrl_head = ohci->ctrl_cur = 0;
413 ohci->bulk_head = ohci->bulk_cur = 0;
414 ohci->per_cur = 0;
415 ohci->done = 0;
416 ohci->done_count = 7;
417
418 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
419 * I took the value linux sets ...
420 */
421 ohci->fsmps = 0x2778;
422 ohci->fi = 0x2edf;
423 ohci->fit = 0;
424 ohci->frt = 0;
425 ohci->frame_number = 0;
426 ohci->pstart = 0;
427 ohci->lst = OHCI_LS_THRESH;
428
429 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
430 ohci->rhdesc_b = 0x0; /* Impl. specific */
431 ohci->rhstatus = 0;
432
433 for (i = 0; i < ohci->num_ports; i++)
434 {
435 port = &ohci->rhport[i];
436 port->ctrl = 0;
437 if (port->port.dev) {
438 usb_attach(&port->port, port->port.dev);
439 }
440 }
441 if (ohci->async_td) {
442 usb_cancel_packet(&ohci->usb_packet);
443 ohci->async_td = 0;
444 }
445 DPRINTF("usb-ohci: Reset %s\n", ohci->name);
446 }
447
448 /* Get an array of dwords from main memory */
449 static inline int get_dwords(OHCIState *ohci,
450 uint32_t addr, uint32_t *buf, int num)
451 {
452 int i;
453
454 addr += ohci->localmem_base;
455
456 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
457 cpu_physical_memory_read(addr, buf, sizeof(*buf));
458 *buf = le32_to_cpu(*buf);
459 }
460
461 return 1;
462 }
463
464 /* Put an array of dwords in to main memory */
465 static inline int put_dwords(OHCIState *ohci,
466 uint32_t addr, uint32_t *buf, int num)
467 {
468 int i;
469
470 addr += ohci->localmem_base;
471
472 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
473 uint32_t tmp = cpu_to_le32(*buf);
474 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
475 }
476
477 return 1;
478 }
479
480 /* Get an array of words from main memory */
481 static inline int get_words(OHCIState *ohci,
482 uint32_t addr, uint16_t *buf, int num)
483 {
484 int i;
485
486 addr += ohci->localmem_base;
487
488 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
489 cpu_physical_memory_read(addr, buf, sizeof(*buf));
490 *buf = le16_to_cpu(*buf);
491 }
492
493 return 1;
494 }
495
496 /* Put an array of words in to main memory */
497 static inline int put_words(OHCIState *ohci,
498 uint32_t addr, uint16_t *buf, int num)
499 {
500 int i;
501
502 addr += ohci->localmem_base;
503
504 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
505 uint16_t tmp = cpu_to_le16(*buf);
506 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
507 }
508
509 return 1;
510 }
511
512 static inline int ohci_read_ed(OHCIState *ohci,
513 uint32_t addr, struct ohci_ed *ed)
514 {
515 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
516 }
517
518 static inline int ohci_read_td(OHCIState *ohci,
519 uint32_t addr, struct ohci_td *td)
520 {
521 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
522 }
523
524 static inline int ohci_read_iso_td(OHCIState *ohci,
525 uint32_t addr, struct ohci_iso_td *td)
526 {
527 return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
528 get_words(ohci, addr + 16, td->offset, 8));
529 }
530
531 static inline int ohci_read_hcca(OHCIState *ohci,
532 uint32_t addr, struct ohci_hcca *hcca)
533 {
534 cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
535 return 1;
536 }
537
538 static inline int ohci_put_ed(OHCIState *ohci,
539 uint32_t addr, struct ohci_ed *ed)
540 {
541 return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
542 }
543
544 static inline int ohci_put_td(OHCIState *ohci,
545 uint32_t addr, struct ohci_td *td)
546 {
547 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
548 }
549
550 static inline int ohci_put_iso_td(OHCIState *ohci,
551 uint32_t addr, struct ohci_iso_td *td)
552 {
553 return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
554 put_words(ohci, addr + 16, td->offset, 8));
555 }
556
557 static inline int ohci_put_hcca(OHCIState *ohci,
558 uint32_t addr, struct ohci_hcca *hcca)
559 {
560 cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
561 return 1;
562 }
563
564 /* Read/Write the contents of a TD from/to main memory. */
565 static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
566 uint8_t *buf, int len, int write)
567 {
568 uint32_t ptr;
569 uint32_t n;
570
571 ptr = td->cbp;
572 n = 0x1000 - (ptr & 0xfff);
573 if (n > len)
574 n = len;
575 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
576 if (n == len)
577 return;
578 ptr = td->be & ~0xfffu;
579 buf += n;
580 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
581 }
582
583 /* Read/Write the contents of an ISO TD from/to main memory. */
584 static void ohci_copy_iso_td(OHCIState *ohci,
585 uint32_t start_addr, uint32_t end_addr,
586 uint8_t *buf, int len, int write)
587 {
588 uint32_t ptr;
589 uint32_t n;
590
591 ptr = start_addr;
592 n = 0x1000 - (ptr & 0xfff);
593 if (n > len)
594 n = len;
595 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
596 if (n == len)
597 return;
598 ptr = end_addr & ~0xfffu;
599 buf += n;
600 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
601 }
602
603 static void ohci_process_lists(OHCIState *ohci, int completion);
604
605 static void ohci_async_complete_packet(USBDevice *dev, USBPacket *packet)
606 {
607 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
608 #ifdef DEBUG_PACKET
609 DPRINTF("Async packet complete\n");
610 #endif
611 ohci->async_complete = 1;
612 ohci_process_lists(ohci, 1);
613 }
614
615 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
616
617 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
618 int completion)
619 {
620 int dir;
621 size_t len = 0;
622 #ifdef DEBUG_ISOCH
623 const char *str = NULL;
624 #endif
625 int pid;
626 int ret;
627 int i;
628 USBDevice *dev;
629 struct ohci_iso_td iso_td;
630 uint32_t addr;
631 uint16_t starting_frame;
632 int16_t relative_frame_number;
633 int frame_count;
634 uint32_t start_offset, next_offset, end_offset = 0;
635 uint32_t start_addr, end_addr;
636
637 addr = ed->head & OHCI_DPTR_MASK;
638
639 if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
640 printf("usb-ohci: ISO_TD read error at %x\n", addr);
641 return 0;
642 }
643
644 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
645 frame_count = OHCI_BM(iso_td.flags, TD_FC);
646 relative_frame_number = USUB(ohci->frame_number, starting_frame);
647
648 #ifdef DEBUG_ISOCH
649 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
650 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
651 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
652 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
653 "frame_number 0x%.8x starting_frame 0x%.8x\n"
654 "frame_count 0x%.8x relative %d\n"
655 "di 0x%.8x cc 0x%.8x\n",
656 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
657 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
658 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
659 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
660 ohci->frame_number, starting_frame,
661 frame_count, relative_frame_number,
662 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
663 #endif
664
665 if (relative_frame_number < 0) {
666 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
667 return 1;
668 } else if (relative_frame_number > frame_count) {
669 /* ISO TD expired - retire the TD to the Done Queue and continue with
670 the next ISO TD of the same ED */
671 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
672 frame_count);
673 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
674 ed->head &= ~OHCI_DPTR_MASK;
675 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
676 iso_td.next = ohci->done;
677 ohci->done = addr;
678 i = OHCI_BM(iso_td.flags, TD_DI);
679 if (i < ohci->done_count)
680 ohci->done_count = i;
681 ohci_put_iso_td(ohci, addr, &iso_td);
682 return 0;
683 }
684
685 dir = OHCI_BM(ed->flags, ED_D);
686 switch (dir) {
687 case OHCI_TD_DIR_IN:
688 #ifdef DEBUG_ISOCH
689 str = "in";
690 #endif
691 pid = USB_TOKEN_IN;
692 break;
693 case OHCI_TD_DIR_OUT:
694 #ifdef DEBUG_ISOCH
695 str = "out";
696 #endif
697 pid = USB_TOKEN_OUT;
698 break;
699 case OHCI_TD_DIR_SETUP:
700 #ifdef DEBUG_ISOCH
701 str = "setup";
702 #endif
703 pid = USB_TOKEN_SETUP;
704 break;
705 default:
706 printf("usb-ohci: Bad direction %d\n", dir);
707 return 1;
708 }
709
710 if (!iso_td.bp || !iso_td.be) {
711 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
712 return 1;
713 }
714
715 start_offset = iso_td.offset[relative_frame_number];
716 next_offset = iso_td.offset[relative_frame_number + 1];
717
718 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
719 ((relative_frame_number < frame_count) &&
720 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
721 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
722 start_offset, next_offset);
723 return 1;
724 }
725
726 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
727 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
728 start_offset, next_offset);
729 return 1;
730 }
731
732 if ((start_offset & 0x1000) == 0) {
733 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
734 (start_offset & OHCI_OFFSET_MASK);
735 } else {
736 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
737 (start_offset & OHCI_OFFSET_MASK);
738 }
739
740 if (relative_frame_number < frame_count) {
741 end_offset = next_offset - 1;
742 if ((end_offset & 0x1000) == 0) {
743 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
744 (end_offset & OHCI_OFFSET_MASK);
745 } else {
746 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
747 (end_offset & OHCI_OFFSET_MASK);
748 }
749 } else {
750 /* Last packet in the ISO TD */
751 end_addr = iso_td.be;
752 }
753
754 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
755 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
756 - (start_addr & OHCI_OFFSET_MASK);
757 } else {
758 len = end_addr - start_addr + 1;
759 }
760
761 if (len && dir != OHCI_TD_DIR_IN) {
762 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
763 }
764
765 if (completion) {
766 ret = ohci->usb_packet.len;
767 } else {
768 ret = USB_RET_NODEV;
769 for (i = 0; i < ohci->num_ports; i++) {
770 dev = ohci->rhport[i].port.dev;
771 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
772 continue;
773 ohci->usb_packet.pid = pid;
774 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
775 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
776 ohci->usb_packet.data = ohci->usb_buf;
777 ohci->usb_packet.len = len;
778 ret = usb_handle_packet(dev, &ohci->usb_packet);
779 if (ret != USB_RET_NODEV)
780 break;
781 }
782
783 if (ret == USB_RET_ASYNC) {
784 return 1;
785 }
786 }
787
788 #ifdef DEBUG_ISOCH
789 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
790 start_offset, end_offset, start_addr, end_addr, str, len, ret);
791 #endif
792
793 /* Writeback */
794 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
795 /* IN transfer succeeded */
796 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
797 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
798 OHCI_CC_NOERROR);
799 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
800 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
801 /* OUT transfer succeeded */
802 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
803 OHCI_CC_NOERROR);
804 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
805 } else {
806 if (ret > (ssize_t) len) {
807 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
808 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
809 OHCI_CC_DATAOVERRUN);
810 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
811 len);
812 } else if (ret >= 0) {
813 printf("usb-ohci: DataUnderrun %d\n", ret);
814 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
815 OHCI_CC_DATAUNDERRUN);
816 } else {
817 switch (ret) {
818 case USB_RET_NODEV:
819 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
820 OHCI_CC_DEVICENOTRESPONDING);
821 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
822 0);
823 break;
824 case USB_RET_NAK:
825 case USB_RET_STALL:
826 printf("usb-ohci: got NAK/STALL %d\n", ret);
827 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
828 OHCI_CC_STALL);
829 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
830 0);
831 break;
832 default:
833 printf("usb-ohci: Bad device response %d\n", ret);
834 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
835 OHCI_CC_UNDEXPETEDPID);
836 break;
837 }
838 }
839 }
840
841 if (relative_frame_number == frame_count) {
842 /* Last data packet of ISO TD - retire the TD to the Done Queue */
843 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
844 ed->head &= ~OHCI_DPTR_MASK;
845 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
846 iso_td.next = ohci->done;
847 ohci->done = addr;
848 i = OHCI_BM(iso_td.flags, TD_DI);
849 if (i < ohci->done_count)
850 ohci->done_count = i;
851 }
852 ohci_put_iso_td(ohci, addr, &iso_td);
853 return 1;
854 }
855
856 /* Service a transport descriptor.
857 Returns nonzero to terminate processing of this endpoint. */
858
859 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
860 {
861 int dir;
862 size_t len = 0;
863 #ifdef DEBUG_PACKET
864 const char *str = NULL;
865 #endif
866 int pid;
867 int ret;
868 int i;
869 USBDevice *dev;
870 struct ohci_td td;
871 uint32_t addr;
872 int flag_r;
873 int completion;
874
875 addr = ed->head & OHCI_DPTR_MASK;
876 /* See if this TD has already been submitted to the device. */
877 completion = (addr == ohci->async_td);
878 if (completion && !ohci->async_complete) {
879 #ifdef DEBUG_PACKET
880 DPRINTF("Skipping async TD\n");
881 #endif
882 return 1;
883 }
884 if (!ohci_read_td(ohci, addr, &td)) {
885 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
886 return 0;
887 }
888
889 dir = OHCI_BM(ed->flags, ED_D);
890 switch (dir) {
891 case OHCI_TD_DIR_OUT:
892 case OHCI_TD_DIR_IN:
893 /* Same value. */
894 break;
895 default:
896 dir = OHCI_BM(td.flags, TD_DP);
897 break;
898 }
899
900 switch (dir) {
901 case OHCI_TD_DIR_IN:
902 #ifdef DEBUG_PACKET
903 str = "in";
904 #endif
905 pid = USB_TOKEN_IN;
906 break;
907 case OHCI_TD_DIR_OUT:
908 #ifdef DEBUG_PACKET
909 str = "out";
910 #endif
911 pid = USB_TOKEN_OUT;
912 break;
913 case OHCI_TD_DIR_SETUP:
914 #ifdef DEBUG_PACKET
915 str = "setup";
916 #endif
917 pid = USB_TOKEN_SETUP;
918 break;
919 default:
920 fprintf(stderr, "usb-ohci: Bad direction\n");
921 return 1;
922 }
923 if (td.cbp && td.be) {
924 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
925 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
926 } else {
927 len = (td.be - td.cbp) + 1;
928 }
929
930 if (len && dir != OHCI_TD_DIR_IN && !completion) {
931 ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
932 }
933 }
934
935 flag_r = (td.flags & OHCI_TD_R) != 0;
936 #ifdef DEBUG_PACKET
937 DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
938 addr, (int64_t)len, str, flag_r, td.cbp, td.be);
939
940 if (len > 0 && dir != OHCI_TD_DIR_IN) {
941 DPRINTF(" data:");
942 for (i = 0; i < len; i++)
943 printf(" %.2x", ohci->usb_buf[i]);
944 DPRINTF("\n");
945 }
946 #endif
947 if (completion) {
948 ret = ohci->usb_packet.len;
949 ohci->async_td = 0;
950 ohci->async_complete = 0;
951 } else {
952 ret = USB_RET_NODEV;
953 for (i = 0; i < ohci->num_ports; i++) {
954 dev = ohci->rhport[i].port.dev;
955 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
956 continue;
957
958 if (ohci->async_td) {
959 /* ??? The hardware should allow one active packet per
960 endpoint. We only allow one active packet per controller.
961 This should be sufficient as long as devices respond in a
962 timely manner.
963 */
964 #ifdef DEBUG_PACKET
965 DPRINTF("Too many pending packets\n");
966 #endif
967 return 1;
968 }
969 ohci->usb_packet.pid = pid;
970 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
971 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
972 ohci->usb_packet.data = ohci->usb_buf;
973 ohci->usb_packet.len = len;
974 ret = usb_handle_packet(dev, &ohci->usb_packet);
975 if (ret != USB_RET_NODEV)
976 break;
977 }
978 #ifdef DEBUG_PACKET
979 DPRINTF("ret=%d\n", ret);
980 #endif
981 if (ret == USB_RET_ASYNC) {
982 ohci->async_td = addr;
983 return 1;
984 }
985 }
986 if (ret >= 0) {
987 if (dir == OHCI_TD_DIR_IN) {
988 ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
989 #ifdef DEBUG_PACKET
990 DPRINTF(" data:");
991 for (i = 0; i < ret; i++)
992 printf(" %.2x", ohci->usb_buf[i]);
993 DPRINTF("\n");
994 #endif
995 } else {
996 ret = len;
997 }
998 }
999
1000 /* Writeback */
1001 if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
1002 /* Transmission succeeded. */
1003 if (ret == len) {
1004 td.cbp = 0;
1005 } else {
1006 td.cbp += ret;
1007 if ((td.cbp & 0xfff) + ret > 0xfff) {
1008 td.cbp &= 0xfff;
1009 td.cbp |= td.be & ~0xfff;
1010 }
1011 }
1012 td.flags |= OHCI_TD_T1;
1013 td.flags ^= OHCI_TD_T0;
1014 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1015 OHCI_SET_BM(td.flags, TD_EC, 0);
1016
1017 ed->head &= ~OHCI_ED_C;
1018 if (td.flags & OHCI_TD_T0)
1019 ed->head |= OHCI_ED_C;
1020 } else {
1021 if (ret >= 0) {
1022 DPRINTF("usb-ohci: Underrun\n");
1023 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1024 } else {
1025 switch (ret) {
1026 case USB_RET_NODEV:
1027 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1028 case USB_RET_NAK:
1029 DPRINTF("usb-ohci: got NAK\n");
1030 return 1;
1031 case USB_RET_STALL:
1032 DPRINTF("usb-ohci: got STALL\n");
1033 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1034 break;
1035 case USB_RET_BABBLE:
1036 DPRINTF("usb-ohci: got BABBLE\n");
1037 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1038 break;
1039 default:
1040 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1041 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1042 OHCI_SET_BM(td.flags, TD_EC, 3);
1043 break;
1044 }
1045 }
1046 ed->head |= OHCI_ED_H;
1047 }
1048
1049 /* Retire this TD */
1050 ed->head &= ~OHCI_DPTR_MASK;
1051 ed->head |= td.next & OHCI_DPTR_MASK;
1052 td.next = ohci->done;
1053 ohci->done = addr;
1054 i = OHCI_BM(td.flags, TD_DI);
1055 if (i < ohci->done_count)
1056 ohci->done_count = i;
1057 ohci_put_td(ohci, addr, &td);
1058 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1059 }
1060
1061 /* Service an endpoint list. Returns nonzero if active TD were found. */
1062 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1063 {
1064 struct ohci_ed ed;
1065 uint32_t next_ed;
1066 uint32_t cur;
1067 int active;
1068
1069 active = 0;
1070
1071 if (head == 0)
1072 return 0;
1073
1074 for (cur = head; cur; cur = next_ed) {
1075 if (!ohci_read_ed(ohci, cur, &ed)) {
1076 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1077 return 0;
1078 }
1079
1080 next_ed = ed.next & OHCI_DPTR_MASK;
1081
1082 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1083 uint32_t addr;
1084 /* Cancel pending packets for ED that have been paused. */
1085 addr = ed.head & OHCI_DPTR_MASK;
1086 if (ohci->async_td && addr == ohci->async_td) {
1087 usb_cancel_packet(&ohci->usb_packet);
1088 ohci->async_td = 0;
1089 }
1090 continue;
1091 }
1092
1093 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1094 #ifdef DEBUG_PACKET
1095 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1096 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1097 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1098 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1099 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1100 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1101 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1102 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1103 #endif
1104 active = 1;
1105
1106 if ((ed.flags & OHCI_ED_F) == 0) {
1107 if (ohci_service_td(ohci, &ed))
1108 break;
1109 } else {
1110 /* Handle isochronous endpoints */
1111 if (ohci_service_iso_td(ohci, &ed, completion))
1112 break;
1113 }
1114 }
1115
1116 ohci_put_ed(ohci, cur, &ed);
1117 }
1118
1119 return active;
1120 }
1121
1122 /* Generate a SOF event, and set a timer for EOF */
1123 static void ohci_sof(OHCIState *ohci)
1124 {
1125 ohci->sof_time = qemu_get_clock_ns(vm_clock);
1126 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1127 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1128 }
1129
1130 /* Process Control and Bulk lists. */
1131 static void ohci_process_lists(OHCIState *ohci, int completion)
1132 {
1133 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1134 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1135 DPRINTF("usb-ohci: head %x, cur %x\n",
1136 ohci->ctrl_head, ohci->ctrl_cur);
1137 }
1138 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1139 ohci->ctrl_cur = 0;
1140 ohci->status &= ~OHCI_STATUS_CLF;
1141 }
1142 }
1143
1144 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1145 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1146 ohci->bulk_cur = 0;
1147 ohci->status &= ~OHCI_STATUS_BLF;
1148 }
1149 }
1150 }
1151
1152 /* Do frame processing on frame boundary */
1153 static void ohci_frame_boundary(void *opaque)
1154 {
1155 OHCIState *ohci = opaque;
1156 struct ohci_hcca hcca;
1157
1158 ohci_read_hcca(ohci, ohci->hcca, &hcca);
1159
1160 /* Process all the lists at the end of the frame */
1161 if (ohci->ctl & OHCI_CTL_PLE) {
1162 int n;
1163
1164 n = ohci->frame_number & 0x1f;
1165 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1166 }
1167
1168 /* Cancel all pending packets if either of the lists has been disabled. */
1169 if (ohci->async_td &&
1170 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1171 usb_cancel_packet(&ohci->usb_packet);
1172 ohci->async_td = 0;
1173 }
1174 ohci->old_ctl = ohci->ctl;
1175 ohci_process_lists(ohci, 0);
1176
1177 /* Frame boundary, so do EOF stuf here */
1178 ohci->frt = ohci->fit;
1179
1180 /* Increment frame number and take care of endianness. */
1181 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1182 hcca.frame = cpu_to_le16(ohci->frame_number);
1183
1184 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1185 if (!ohci->done)
1186 abort();
1187 if (ohci->intr & ohci->intr_status)
1188 ohci->done |= 1;
1189 hcca.done = cpu_to_le32(ohci->done);
1190 ohci->done = 0;
1191 ohci->done_count = 7;
1192 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1193 }
1194
1195 if (ohci->done_count != 7 && ohci->done_count != 0)
1196 ohci->done_count--;
1197
1198 /* Do SOF stuff here */
1199 ohci_sof(ohci);
1200
1201 /* Writeback HCCA */
1202 ohci_put_hcca(ohci, ohci->hcca, &hcca);
1203 }
1204
1205 /* Start sending SOF tokens across the USB bus, lists are processed in
1206 * next frame
1207 */
1208 static int ohci_bus_start(OHCIState *ohci)
1209 {
1210 ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1211 ohci_frame_boundary,
1212 ohci);
1213
1214 if (ohci->eof_timer == NULL) {
1215 fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1216 /* TODO: Signal unrecoverable error */
1217 return 0;
1218 }
1219
1220 DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1221
1222 ohci_sof(ohci);
1223
1224 return 1;
1225 }
1226
1227 /* Stop sending SOF tokens on the bus */
1228 static void ohci_bus_stop(OHCIState *ohci)
1229 {
1230 if (ohci->eof_timer)
1231 qemu_del_timer(ohci->eof_timer);
1232 ohci->eof_timer = NULL;
1233 }
1234
1235 /* Sets a flag in a port status register but only set it if the port is
1236 * connected, if not set ConnectStatusChange flag. If flag is enabled
1237 * return 1.
1238 */
1239 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1240 {
1241 int ret = 1;
1242
1243 /* writing a 0 has no effect */
1244 if (val == 0)
1245 return 0;
1246
1247 /* If CurrentConnectStatus is cleared we set
1248 * ConnectStatusChange
1249 */
1250 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1251 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1252 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1253 /* TODO: CSC is a wakeup event */
1254 }
1255 return 0;
1256 }
1257
1258 if (ohci->rhport[i].ctrl & val)
1259 ret = 0;
1260
1261 /* set the bit */
1262 ohci->rhport[i].ctrl |= val;
1263
1264 return ret;
1265 }
1266
1267 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1268 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1269 {
1270 val &= OHCI_FMI_FI;
1271
1272 if (val != ohci->fi) {
1273 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1274 ohci->name, ohci->fi, ohci->fi);
1275 }
1276
1277 ohci->fi = val;
1278 }
1279
1280 static void ohci_port_power(OHCIState *ohci, int i, int p)
1281 {
1282 if (p) {
1283 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1284 } else {
1285 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1286 OHCI_PORT_CCS|
1287 OHCI_PORT_PSS|
1288 OHCI_PORT_PRS);
1289 }
1290 }
1291
1292 /* Set HcControlRegister */
1293 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1294 {
1295 uint32_t old_state;
1296 uint32_t new_state;
1297
1298 old_state = ohci->ctl & OHCI_CTL_HCFS;
1299 ohci->ctl = val;
1300 new_state = ohci->ctl & OHCI_CTL_HCFS;
1301
1302 /* no state change */
1303 if (old_state == new_state)
1304 return;
1305
1306 switch (new_state) {
1307 case OHCI_USB_OPERATIONAL:
1308 ohci_bus_start(ohci);
1309 break;
1310 case OHCI_USB_SUSPEND:
1311 ohci_bus_stop(ohci);
1312 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1313 break;
1314 case OHCI_USB_RESUME:
1315 DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1316 break;
1317 case OHCI_USB_RESET:
1318 ohci_reset(ohci);
1319 DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1320 break;
1321 }
1322 }
1323
1324 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1325 {
1326 uint16_t fr;
1327 int64_t tks;
1328
1329 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1330 return (ohci->frt << 31);
1331
1332 /* Being in USB operational state guarnatees sof_time was
1333 * set already.
1334 */
1335 tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1336
1337 /* avoid muldiv if possible */
1338 if (tks >= usb_frame_time)
1339 return (ohci->frt << 31);
1340
1341 tks = muldiv64(1, tks, usb_bit_time);
1342 fr = (uint16_t)(ohci->fi - tks);
1343
1344 return (ohci->frt << 31) | fr;
1345 }
1346
1347
1348 /* Set root hub status */
1349 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1350 {
1351 uint32_t old_state;
1352
1353 old_state = ohci->rhstatus;
1354
1355 /* write 1 to clear OCIC */
1356 if (val & OHCI_RHS_OCIC)
1357 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1358
1359 if (val & OHCI_RHS_LPS) {
1360 int i;
1361
1362 for (i = 0; i < ohci->num_ports; i++)
1363 ohci_port_power(ohci, i, 0);
1364 DPRINTF("usb-ohci: powered down all ports\n");
1365 }
1366
1367 if (val & OHCI_RHS_LPSC) {
1368 int i;
1369
1370 for (i = 0; i < ohci->num_ports; i++)
1371 ohci_port_power(ohci, i, 1);
1372 DPRINTF("usb-ohci: powered up all ports\n");
1373 }
1374
1375 if (val & OHCI_RHS_DRWE)
1376 ohci->rhstatus |= OHCI_RHS_DRWE;
1377
1378 if (val & OHCI_RHS_CRWE)
1379 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1380
1381 if (old_state != ohci->rhstatus)
1382 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1383 }
1384
1385 /* Set root hub port status */
1386 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1387 {
1388 uint32_t old_state;
1389 OHCIPort *port;
1390
1391 port = &ohci->rhport[portnum];
1392 old_state = port->ctrl;
1393
1394 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1395 if (val & OHCI_PORT_WTC)
1396 port->ctrl &= ~(val & OHCI_PORT_WTC);
1397
1398 if (val & OHCI_PORT_CCS)
1399 port->ctrl &= ~OHCI_PORT_PES;
1400
1401 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1402
1403 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1404 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1405 }
1406
1407 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1408 DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1409 usb_send_msg(port->port.dev, USB_MSG_RESET);
1410 port->ctrl &= ~OHCI_PORT_PRS;
1411 /* ??? Should this also set OHCI_PORT_PESC. */
1412 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1413 }
1414
1415 /* Invert order here to ensure in ambiguous case, device is
1416 * powered up...
1417 */
1418 if (val & OHCI_PORT_LSDA)
1419 ohci_port_power(ohci, portnum, 0);
1420 if (val & OHCI_PORT_PPS)
1421 ohci_port_power(ohci, portnum, 1);
1422
1423 if (old_state != port->ctrl)
1424 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1425
1426 return;
1427 }
1428
1429 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1430 {
1431 OHCIState *ohci = ptr;
1432 uint32_t retval;
1433
1434 addr &= 0xff;
1435
1436 /* Only aligned reads are allowed on OHCI */
1437 if (addr & 3) {
1438 fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1439 return 0xffffffff;
1440 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1441 /* HcRhPortStatus */
1442 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1443 } else {
1444 switch (addr >> 2) {
1445 case 0: /* HcRevision */
1446 retval = 0x10;
1447 break;
1448
1449 case 1: /* HcControl */
1450 retval = ohci->ctl;
1451 break;
1452
1453 case 2: /* HcCommandStatus */
1454 retval = ohci->status;
1455 break;
1456
1457 case 3: /* HcInterruptStatus */
1458 retval = ohci->intr_status;
1459 break;
1460
1461 case 4: /* HcInterruptEnable */
1462 case 5: /* HcInterruptDisable */
1463 retval = ohci->intr;
1464 break;
1465
1466 case 6: /* HcHCCA */
1467 retval = ohci->hcca;
1468 break;
1469
1470 case 7: /* HcPeriodCurrentED */
1471 retval = ohci->per_cur;
1472 break;
1473
1474 case 8: /* HcControlHeadED */
1475 retval = ohci->ctrl_head;
1476 break;
1477
1478 case 9: /* HcControlCurrentED */
1479 retval = ohci->ctrl_cur;
1480 break;
1481
1482 case 10: /* HcBulkHeadED */
1483 retval = ohci->bulk_head;
1484 break;
1485
1486 case 11: /* HcBulkCurrentED */
1487 retval = ohci->bulk_cur;
1488 break;
1489
1490 case 12: /* HcDoneHead */
1491 retval = ohci->done;
1492 break;
1493
1494 case 13: /* HcFmInterretval */
1495 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1496 break;
1497
1498 case 14: /* HcFmRemaining */
1499 retval = ohci_get_frame_remaining(ohci);
1500 break;
1501
1502 case 15: /* HcFmNumber */
1503 retval = ohci->frame_number;
1504 break;
1505
1506 case 16: /* HcPeriodicStart */
1507 retval = ohci->pstart;
1508 break;
1509
1510 case 17: /* HcLSThreshold */
1511 retval = ohci->lst;
1512 break;
1513
1514 case 18: /* HcRhDescriptorA */
1515 retval = ohci->rhdesc_a;
1516 break;
1517
1518 case 19: /* HcRhDescriptorB */
1519 retval = ohci->rhdesc_b;
1520 break;
1521
1522 case 20: /* HcRhStatus */
1523 retval = ohci->rhstatus;
1524 break;
1525
1526 /* PXA27x specific registers */
1527 case 24: /* HcStatus */
1528 retval = ohci->hstatus & ohci->hmask;
1529 break;
1530
1531 case 25: /* HcHReset */
1532 retval = ohci->hreset;
1533 break;
1534
1535 case 26: /* HcHInterruptEnable */
1536 retval = ohci->hmask;
1537 break;
1538
1539 case 27: /* HcHInterruptTest */
1540 retval = ohci->htest;
1541 break;
1542
1543 default:
1544 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1545 retval = 0xffffffff;
1546 }
1547 }
1548
1549 return retval;
1550 }
1551
1552 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1553 {
1554 OHCIState *ohci = ptr;
1555
1556 addr &= 0xff;
1557
1558 /* Only aligned reads are allowed on OHCI */
1559 if (addr & 3) {
1560 fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1561 return;
1562 }
1563
1564 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1565 /* HcRhPortStatus */
1566 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1567 return;
1568 }
1569
1570 switch (addr >> 2) {
1571 case 1: /* HcControl */
1572 ohci_set_ctl(ohci, val);
1573 break;
1574
1575 case 2: /* HcCommandStatus */
1576 /* SOC is read-only */
1577 val = (val & ~OHCI_STATUS_SOC);
1578
1579 /* Bits written as '0' remain unchanged in the register */
1580 ohci->status |= val;
1581
1582 if (ohci->status & OHCI_STATUS_HCR)
1583 ohci_reset(ohci);
1584 break;
1585
1586 case 3: /* HcInterruptStatus */
1587 ohci->intr_status &= ~val;
1588 ohci_intr_update(ohci);
1589 break;
1590
1591 case 4: /* HcInterruptEnable */
1592 ohci->intr |= val;
1593 ohci_intr_update(ohci);
1594 break;
1595
1596 case 5: /* HcInterruptDisable */
1597 ohci->intr &= ~val;
1598 ohci_intr_update(ohci);
1599 break;
1600
1601 case 6: /* HcHCCA */
1602 ohci->hcca = val & OHCI_HCCA_MASK;
1603 break;
1604
1605 case 7: /* HcPeriodCurrentED */
1606 /* Ignore writes to this read-only register, Linux does them */
1607 break;
1608
1609 case 8: /* HcControlHeadED */
1610 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1611 break;
1612
1613 case 9: /* HcControlCurrentED */
1614 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1615 break;
1616
1617 case 10: /* HcBulkHeadED */
1618 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1619 break;
1620
1621 case 11: /* HcBulkCurrentED */
1622 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1623 break;
1624
1625 case 13: /* HcFmInterval */
1626 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1627 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1628 ohci_set_frame_interval(ohci, val);
1629 break;
1630
1631 case 15: /* HcFmNumber */
1632 break;
1633
1634 case 16: /* HcPeriodicStart */
1635 ohci->pstart = val & 0xffff;
1636 break;
1637
1638 case 17: /* HcLSThreshold */
1639 ohci->lst = val & 0xffff;
1640 break;
1641
1642 case 18: /* HcRhDescriptorA */
1643 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1644 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1645 break;
1646
1647 case 19: /* HcRhDescriptorB */
1648 break;
1649
1650 case 20: /* HcRhStatus */
1651 ohci_set_hub_status(ohci, val);
1652 break;
1653
1654 /* PXA27x specific registers */
1655 case 24: /* HcStatus */
1656 ohci->hstatus &= ~(val & ohci->hmask);
1657
1658 case 25: /* HcHReset */
1659 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1660 if (val & OHCI_HRESET_FSBIR)
1661 ohci_reset(ohci);
1662 break;
1663
1664 case 26: /* HcHInterruptEnable */
1665 ohci->hmask = val;
1666 break;
1667
1668 case 27: /* HcHInterruptTest */
1669 ohci->htest = val;
1670 break;
1671
1672 default:
1673 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1674 break;
1675 }
1676 }
1677
1678 static void ohci_device_destroy(USBBus *bus, USBDevice *dev)
1679 {
1680 OHCIState *ohci = container_of(bus, OHCIState, bus);
1681
1682 if (ohci->async_td && ohci->usb_packet.owner == dev) {
1683 usb_cancel_packet(&ohci->usb_packet);
1684 ohci->async_td = 0;
1685 }
1686 }
1687
1688 /* Only dword reads are defined on OHCI register space */
1689 static CPUReadMemoryFunc * const ohci_readfn[3]={
1690 ohci_mem_read,
1691 ohci_mem_read,
1692 ohci_mem_read
1693 };
1694
1695 /* Only dword writes are defined on OHCI register space */
1696 static CPUWriteMemoryFunc * const ohci_writefn[3]={
1697 ohci_mem_write,
1698 ohci_mem_write,
1699 ohci_mem_write
1700 };
1701
1702 static USBPortOps ohci_port_ops = {
1703 .attach = ohci_attach,
1704 .detach = ohci_detach,
1705 .wakeup = ohci_wakeup,
1706 .complete = ohci_async_complete_packet,
1707 };
1708
1709 static USBBusOps ohci_bus_ops = {
1710 .device_destroy = ohci_device_destroy,
1711 };
1712
1713 static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1714 int num_ports, uint32_t localmem_base)
1715 {
1716 int i;
1717
1718 if (usb_frame_time == 0) {
1719 #ifdef OHCI_TIME_WARP
1720 usb_frame_time = get_ticks_per_sec();
1721 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1722 #else
1723 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1724 if (get_ticks_per_sec() >= USB_HZ) {
1725 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1726 } else {
1727 usb_bit_time = 1;
1728 }
1729 #endif
1730 DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1731 usb_frame_time, usb_bit_time);
1732 }
1733
1734 ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
1735 DEVICE_LITTLE_ENDIAN);
1736 ohci->localmem_base = localmem_base;
1737
1738 ohci->name = dev->info->name;
1739
1740 usb_bus_new(&ohci->bus, &ohci_bus_ops, dev);
1741 ohci->num_ports = num_ports;
1742 for (i = 0; i < num_ports; i++) {
1743 usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, &ohci_port_ops,
1744 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1745 usb_port_location(&ohci->rhport[i].port, NULL, i+1);
1746 }
1747
1748 ohci->async_td = 0;
1749 qemu_register_reset(ohci_reset, ohci);
1750 }
1751
1752 typedef struct {
1753 PCIDevice pci_dev;
1754 OHCIState state;
1755 } OHCIPCIState;
1756
1757 static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1758 {
1759 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1760 int num_ports = 3;
1761
1762 ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1763 /* TODO: RST# value should be 0. */
1764 ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1765
1766 usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
1767 ohci->state.irq = ohci->pci_dev.irq[0];
1768
1769 /* TODO: avoid cast below by using dev */
1770 pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem);
1771 return 0;
1772 }
1773
1774 void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1775 {
1776 pci_create_simple(bus, devfn, "pci-ohci");
1777 }
1778
1779 typedef struct {
1780 SysBusDevice busdev;
1781 OHCIState ohci;
1782 uint32_t num_ports;
1783 target_phys_addr_t dma_offset;
1784 } OHCISysBusState;
1785
1786 static int ohci_init_pxa(SysBusDevice *dev)
1787 {
1788 OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1789
1790 usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset);
1791 sysbus_init_irq(dev, &s->ohci.irq);
1792 sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1793
1794 return 0;
1795 }
1796
1797 static PCIDeviceInfo ohci_pci_info = {
1798 .qdev.name = "pci-ohci",
1799 .qdev.desc = "Apple USB Controller",
1800 .qdev.size = sizeof(OHCIPCIState),
1801 .init = usb_ohci_initfn_pci,
1802 .vendor_id = PCI_VENDOR_ID_APPLE,
1803 .device_id = PCI_DEVICE_ID_APPLE_IPID_USB,
1804 .class_id = PCI_CLASS_SERIAL_USB,
1805 };
1806
1807 static SysBusDeviceInfo ohci_sysbus_info = {
1808 .init = ohci_init_pxa,
1809 .qdev.name = "sysbus-ohci",
1810 .qdev.desc = "OHCI USB Controller",
1811 .qdev.size = sizeof(OHCISysBusState),
1812 .qdev.props = (Property[]) {
1813 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1814 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1815 DEFINE_PROP_END_OF_LIST(),
1816 }
1817 };
1818
1819 static void ohci_register(void)
1820 {
1821 pci_qdev_register(&ohci_pci_info);
1822 sysbus_register_withprop(&ohci_sysbus_info);
1823 }
1824 device_init(ohci_register);
QEmu