4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
14 #include "internals.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/host-utils.h"
17 #include "qemu/main-loop.h"
18 #include "qemu/timer.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "qemu/range.h"
30 #include "qapi/qapi-commands-machine-target.h"
31 #include "qapi/error.h"
32 #include "qemu/guest-random.h"
35 #include "exec/cpu_ldst.h"
36 #include "semihosting/common-semi.h"
40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
42 static void switch_mode(CPUARMState
*env
, int mode
);
44 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
46 assert(ri
->fieldoffset
);
47 if (cpreg_field_is_64bit(ri
)) {
48 return CPREG_FIELD64(env
, ri
);
50 return CPREG_FIELD32(env
, ri
);
54 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
56 assert(ri
->fieldoffset
);
57 if (cpreg_field_is_64bit(ri
)) {
58 CPREG_FIELD64(env
, ri
) = value
;
60 CPREG_FIELD32(env
, ri
) = value
;
64 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
66 return (char *)env
+ ri
->fieldoffset
;
69 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
71 /* Raw read of a coprocessor register (as needed for migration, etc). */
72 if (ri
->type
& ARM_CP_CONST
) {
73 return ri
->resetvalue
;
74 } else if (ri
->raw_readfn
) {
75 return ri
->raw_readfn(env
, ri
);
76 } else if (ri
->readfn
) {
77 return ri
->readfn(env
, ri
);
79 return raw_read(env
, ri
);
83 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
86 /* Raw write of a coprocessor register (as needed for migration, etc).
87 * Note that constant registers are treated as write-ignored; the
88 * caller should check for success by whether a readback gives the
91 if (ri
->type
& ARM_CP_CONST
) {
93 } else if (ri
->raw_writefn
) {
94 ri
->raw_writefn(env
, ri
, v
);
95 } else if (ri
->writefn
) {
96 ri
->writefn(env
, ri
, v
);
98 raw_write(env
, ri
, v
);
102 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
104 /* Return true if the regdef would cause an assertion if you called
105 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
106 * program bug for it not to have the NO_RAW flag).
107 * NB that returning false here doesn't necessarily mean that calling
108 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
109 * read/write access functions which are safe for raw use" from "has
110 * read/write access functions which have side effects but has forgotten
111 * to provide raw access functions".
112 * The tests here line up with the conditions in read/write_raw_cp_reg()
113 * and assertions in raw_read()/raw_write().
115 if ((ri
->type
& ARM_CP_CONST
) ||
117 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
123 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
125 /* Write the coprocessor state from cpu->env to the (index,value) list. */
129 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
130 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
131 const ARMCPRegInfo
*ri
;
134 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
139 if (ri
->type
& ARM_CP_NO_RAW
) {
143 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
146 * Only sync if the previous list->cpustate sync succeeded.
147 * Rather than tracking the success/failure state for every
148 * item in the list, we just recheck "does the raw write we must
149 * have made in write_list_to_cpustate() read back OK" here.
151 uint64_t oldval
= cpu
->cpreg_values
[i
];
153 if (oldval
== newval
) {
157 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
158 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
162 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
164 cpu
->cpreg_values
[i
] = newval
;
169 bool write_list_to_cpustate(ARMCPU
*cpu
)
174 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
175 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
176 uint64_t v
= cpu
->cpreg_values
[i
];
177 const ARMCPRegInfo
*ri
;
179 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
184 if (ri
->type
& ARM_CP_NO_RAW
) {
187 /* Write value and confirm it reads back as written
188 * (to catch read-only registers and partially read-only
189 * registers where the incoming migration value doesn't match)
191 write_raw_cp_reg(&cpu
->env
, ri
, v
);
192 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
199 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
201 ARMCPU
*cpu
= opaque
;
202 uint32_t regidx
= (uintptr_t)key
;
203 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
205 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
206 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
207 /* The value array need not be initialized at this point */
208 cpu
->cpreg_array_len
++;
212 static void count_cpreg(gpointer key
, gpointer opaque
)
214 ARMCPU
*cpu
= opaque
;
215 const ARMCPRegInfo
*ri
;
217 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
219 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
220 cpu
->cpreg_array_len
++;
224 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
226 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
227 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
238 void init_cpreg_list(ARMCPU
*cpu
)
240 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
241 * Note that we require cpreg_tuples[] to be sorted by key ID.
246 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
247 keys
= g_list_sort(keys
, cpreg_key_compare
);
249 cpu
->cpreg_array_len
= 0;
251 g_list_foreach(keys
, count_cpreg
, cpu
);
253 arraylen
= cpu
->cpreg_array_len
;
254 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
257 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
258 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
259 cpu
->cpreg_array_len
= 0;
261 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
263 assert(cpu
->cpreg_array_len
== arraylen
);
269 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
271 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
272 const ARMCPRegInfo
*ri
,
275 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
276 arm_is_secure_below_el3(env
)) {
277 return CP_ACCESS_TRAP_UNCATEGORIZED
;
282 /* Some secure-only AArch32 registers trap to EL3 if used from
283 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
284 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
285 * We assume that the .access field is set to PL1_RW.
287 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
288 const ARMCPRegInfo
*ri
,
291 if (arm_current_el(env
) == 3) {
294 if (arm_is_secure_below_el3(env
)) {
295 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
296 return CP_ACCESS_TRAP_EL2
;
298 return CP_ACCESS_TRAP_EL3
;
300 /* This will be EL1 NS and EL2 NS, which just UNDEF */
301 return CP_ACCESS_TRAP_UNCATEGORIZED
;
304 /* Check for traps to performance monitor registers, which are controlled
305 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
307 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
310 int el
= arm_current_el(env
);
311 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
313 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
314 return CP_ACCESS_TRAP_EL2
;
316 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
317 return CP_ACCESS_TRAP_EL3
;
322 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
323 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
326 if (arm_current_el(env
) == 1) {
327 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
328 if (arm_hcr_el2_eff(env
) & trap
) {
329 return CP_ACCESS_TRAP_EL2
;
335 /* Check for traps from EL1 due to HCR_EL2.TSW. */
336 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
340 return CP_ACCESS_TRAP_EL2
;
345 /* Check for traps from EL1 due to HCR_EL2.TACR. */
346 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
349 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
350 return CP_ACCESS_TRAP_EL2
;
355 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
356 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
359 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
360 return CP_ACCESS_TRAP_EL2
;
365 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
367 ARMCPU
*cpu
= env_archcpu(env
);
369 raw_write(env
, ri
, value
);
370 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
373 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
375 ARMCPU
*cpu
= env_archcpu(env
);
377 if (raw_read(env
, ri
) != value
) {
378 /* Unlike real hardware the qemu TLB uses virtual addresses,
379 * not modified virtual addresses, so this causes a TLB flush.
382 raw_write(env
, ri
, value
);
386 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
389 ARMCPU
*cpu
= env_archcpu(env
);
391 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
392 && !extended_addresses_enabled(env
)) {
393 /* For VMSA (when not using the LPAE long descriptor page table
394 * format) this register includes the ASID, so do a TLB flush.
395 * For PMSA it is purely a process ID and no action is needed.
399 raw_write(env
, ri
, value
);
402 /* IS variants of TLB operations must affect all cores */
403 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
406 CPUState
*cs
= env_cpu(env
);
408 tlb_flush_all_cpus_synced(cs
);
411 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 CPUState
*cs
= env_cpu(env
);
416 tlb_flush_all_cpus_synced(cs
);
419 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
422 CPUState
*cs
= env_cpu(env
);
424 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
427 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
430 CPUState
*cs
= env_cpu(env
);
432 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
436 * Non-IS variants of TLB operations are upgraded to
437 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
438 * force broadcast of these operations.
440 static bool tlb_force_broadcast(CPUARMState
*env
)
442 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
445 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
448 /* Invalidate all (TLBIALL) */
449 CPUState
*cs
= env_cpu(env
);
451 if (tlb_force_broadcast(env
)) {
452 tlb_flush_all_cpus_synced(cs
);
458 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
461 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
462 CPUState
*cs
= env_cpu(env
);
464 value
&= TARGET_PAGE_MASK
;
465 if (tlb_force_broadcast(env
)) {
466 tlb_flush_page_all_cpus_synced(cs
, value
);
468 tlb_flush_page(cs
, value
);
472 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
475 /* Invalidate by ASID (TLBIASID) */
476 CPUState
*cs
= env_cpu(env
);
478 if (tlb_force_broadcast(env
)) {
479 tlb_flush_all_cpus_synced(cs
);
485 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
488 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
489 CPUState
*cs
= env_cpu(env
);
491 value
&= TARGET_PAGE_MASK
;
492 if (tlb_force_broadcast(env
)) {
493 tlb_flush_page_all_cpus_synced(cs
, value
);
495 tlb_flush_page(cs
, value
);
499 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 CPUState
*cs
= env_cpu(env
);
504 tlb_flush_by_mmuidx(cs
,
506 ARMMMUIdxBit_E10_1_PAN
|
510 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
513 CPUState
*cs
= env_cpu(env
);
515 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
517 ARMMMUIdxBit_E10_1_PAN
|
522 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
525 CPUState
*cs
= env_cpu(env
);
527 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
530 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
533 CPUState
*cs
= env_cpu(env
);
535 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
538 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 CPUState
*cs
= env_cpu(env
);
542 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
544 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
547 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
550 CPUState
*cs
= env_cpu(env
);
551 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
553 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
557 static const ARMCPRegInfo cp_reginfo
[] = {
558 /* Define the secure and non-secure FCSE identifier CP registers
559 * separately because there is no secure bank in V8 (no _EL3). This allows
560 * the secure register to be properly reset and migrated. There is also no
561 * v8 EL1 version of the register so the non-secure instance stands alone.
564 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
565 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
566 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
567 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
568 { .name
= "FCSEIDR_S",
569 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
570 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
571 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
572 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
573 /* Define the secure and non-secure context identifier CP registers
574 * separately because there is no secure bank in V8 (no _EL3). This allows
575 * the secure register to be properly reset and migrated. In the
576 * non-secure case, the 32-bit register will have reset and migration
577 * disabled during registration as it is handled by the 64-bit instance.
579 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
580 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
581 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
582 .secure
= ARM_CP_SECSTATE_NS
,
583 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
584 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
585 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
586 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
587 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
588 .secure
= ARM_CP_SECSTATE_S
,
589 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
590 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
593 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
594 /* NB: Some of these registers exist in v8 but with more precise
595 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
597 /* MMU Domain access control / MPU write buffer control */
599 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
600 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
601 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
602 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
603 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
604 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
605 * For v6 and v5, these mappings are overly broad.
607 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
608 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
609 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
610 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
611 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
612 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
613 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
614 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
615 /* Cache maintenance ops; some of this space may be overridden later. */
616 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
617 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
618 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
621 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
622 /* Not all pre-v6 cores implemented this WFI, so this is slightly
625 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
626 .access
= PL1_W
, .type
= ARM_CP_WFI
},
629 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
630 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
631 * is UNPREDICTABLE; we choose to NOP as most implementations do).
633 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
634 .access
= PL1_W
, .type
= ARM_CP_WFI
},
635 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
636 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
637 * OMAPCP will override this space.
639 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
640 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
642 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
643 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
645 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
646 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
647 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
649 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
650 * implementing it as RAZ means the "debug architecture version" bits
651 * will read as a reserved value, which should cause Linux to not try
652 * to use the debug hardware.
654 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
655 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
656 /* MMU TLB control. Note that the wildcarding means we cover not just
657 * the unified TLB ops but also the dside/iside/inner-shareable variants.
659 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
660 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
661 .type
= ARM_CP_NO_RAW
},
662 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
663 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
664 .type
= ARM_CP_NO_RAW
},
665 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
666 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
667 .type
= ARM_CP_NO_RAW
},
668 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
669 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
670 .type
= ARM_CP_NO_RAW
},
671 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
672 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
673 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
674 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
677 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
682 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
683 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
684 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
685 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
686 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
688 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
689 /* VFP coprocessor: cp10 & cp11 [23:20] */
690 mask
|= R_CPACR_ASEDIS_MASK
|
691 R_CPACR_D32DIS_MASK
|
695 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
696 /* ASEDIS [31] bit is RAO/WI */
697 value
|= R_CPACR_ASEDIS_MASK
;
700 /* VFPv3 and upwards with NEON implement 32 double precision
701 * registers (D0-D31).
703 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
704 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
705 value
|= R_CPACR_D32DIS_MASK
;
712 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
713 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
715 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
716 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
717 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
718 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
721 env
->cp15
.cpacr_el1
= value
;
724 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
727 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
728 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
730 uint64_t value
= env
->cp15
.cpacr_el1
;
732 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
733 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
734 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
740 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
742 /* Call cpacr_write() so that we reset with the correct RAO bits set
743 * for our CPU features.
745 cpacr_write(env
, ri
, 0);
748 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
751 if (arm_feature(env
, ARM_FEATURE_V8
)) {
752 /* Check if CPACR accesses are to be trapped to EL2 */
753 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
754 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
755 return CP_ACCESS_TRAP_EL2
;
756 /* Check if CPACR accesses are to be trapped to EL3 */
757 } else if (arm_current_el(env
) < 3 &&
758 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
759 return CP_ACCESS_TRAP_EL3
;
766 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
769 /* Check if CPTR accesses are set to trap to EL3 */
770 if (arm_current_el(env
) == 2 &&
771 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
772 return CP_ACCESS_TRAP_EL3
;
778 static const ARMCPRegInfo v6_cp_reginfo
[] = {
779 /* prefetch by MVA in v6, NOP in v7 */
780 { .name
= "MVA_prefetch",
781 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
782 .access
= PL1_W
, .type
= ARM_CP_NOP
},
783 /* We need to break the TB after ISB to execute self-modifying code
784 * correctly and also to take any pending interrupts immediately.
785 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
787 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
788 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
789 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
790 .access
= PL0_W
, .type
= ARM_CP_NOP
},
791 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
792 .access
= PL0_W
, .type
= ARM_CP_NOP
},
793 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
794 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
795 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
796 offsetof(CPUARMState
, cp15
.ifar_ns
) },
798 /* Watchpoint Fault Address Register : should actually only be present
799 * for 1136, 1176, 11MPCore.
801 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
802 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
803 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
804 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
805 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
806 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
809 typedef struct pm_event
{
810 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
811 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
812 bool (*supported
)(CPUARMState
*);
814 * Retrieve the current count of the underlying event. The programmed
815 * counters hold a difference from the return value from this function
817 uint64_t (*get_count
)(CPUARMState
*);
819 * Return how many nanoseconds it will take (at a minimum) for count events
820 * to occur. A negative value indicates the counter will never overflow, or
821 * that the counter has otherwise arranged for the overflow bit to be set
822 * and the PMU interrupt to be raised on overflow.
824 int64_t (*ns_per_count
)(uint64_t);
827 static bool event_always_supported(CPUARMState
*env
)
832 static uint64_t swinc_get_count(CPUARMState
*env
)
835 * SW_INCR events are written directly to the pmevcntr's by writes to
836 * PMSWINC, so there is no underlying count maintained by the PMU itself
841 static int64_t swinc_ns_per(uint64_t ignored
)
847 * Return the underlying cycle count for the PMU cycle counters. If we're in
848 * usermode, simply return 0.
850 static uint64_t cycles_get_count(CPUARMState
*env
)
852 #ifndef CONFIG_USER_ONLY
853 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
854 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
856 return cpu_get_host_ticks();
860 #ifndef CONFIG_USER_ONLY
861 static int64_t cycles_ns_per(uint64_t cycles
)
863 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
866 static bool instructions_supported(CPUARMState
*env
)
868 return icount_enabled() == 1; /* Precise instruction counting */
871 static uint64_t instructions_get_count(CPUARMState
*env
)
873 return (uint64_t)icount_get_raw();
876 static int64_t instructions_ns_per(uint64_t icount
)
878 return icount_to_ns((int64_t)icount
);
882 static bool pmuv3p1_events_supported(CPUARMState
*env
)
884 /* For events which are supported in any v8.1 PMU */
885 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
888 static bool pmuv3p4_events_supported(CPUARMState
*env
)
890 /* For events which are supported in any v8.1 PMU */
891 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
894 static uint64_t zero_event_get_count(CPUARMState
*env
)
896 /* For events which on QEMU never fire, so their count is always zero */
900 static int64_t zero_event_ns_per(uint64_t cycles
)
902 /* An event which never fires can never overflow */
906 static const pm_event pm_events
[] = {
907 { .number
= 0x000, /* SW_INCR */
908 .supported
= event_always_supported
,
909 .get_count
= swinc_get_count
,
910 .ns_per_count
= swinc_ns_per
,
912 #ifndef CONFIG_USER_ONLY
913 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
914 .supported
= instructions_supported
,
915 .get_count
= instructions_get_count
,
916 .ns_per_count
= instructions_ns_per
,
918 { .number
= 0x011, /* CPU_CYCLES, Cycle */
919 .supported
= event_always_supported
,
920 .get_count
= cycles_get_count
,
921 .ns_per_count
= cycles_ns_per
,
924 { .number
= 0x023, /* STALL_FRONTEND */
925 .supported
= pmuv3p1_events_supported
,
926 .get_count
= zero_event_get_count
,
927 .ns_per_count
= zero_event_ns_per
,
929 { .number
= 0x024, /* STALL_BACKEND */
930 .supported
= pmuv3p1_events_supported
,
931 .get_count
= zero_event_get_count
,
932 .ns_per_count
= zero_event_ns_per
,
934 { .number
= 0x03c, /* STALL */
935 .supported
= pmuv3p4_events_supported
,
936 .get_count
= zero_event_get_count
,
937 .ns_per_count
= zero_event_ns_per
,
942 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
943 * events (i.e. the statistical profiling extension), this implementation
944 * should first be updated to something sparse instead of the current
945 * supported_event_map[] array.
947 #define MAX_EVENT_ID 0x3c
948 #define UNSUPPORTED_EVENT UINT16_MAX
949 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
952 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
953 * of ARM event numbers to indices in our pm_events array.
955 * Note: Events in the 0x40XX range are not currently supported.
957 void pmu_init(ARMCPU
*cpu
)
962 * Empty supported_event_map and cpu->pmceid[01] before adding supported
965 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
966 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
971 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
972 const pm_event
*cnt
= &pm_events
[i
];
973 assert(cnt
->number
<= MAX_EVENT_ID
);
974 /* We do not currently support events in the 0x40xx range */
975 assert(cnt
->number
<= 0x3f);
977 if (cnt
->supported(&cpu
->env
)) {
978 supported_event_map
[cnt
->number
] = i
;
979 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
980 if (cnt
->number
& 0x20) {
981 cpu
->pmceid1
|= event_mask
;
983 cpu
->pmceid0
|= event_mask
;
990 * Check at runtime whether a PMU event is supported for the current machine
992 static bool event_supported(uint16_t number
)
994 if (number
> MAX_EVENT_ID
) {
997 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1000 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1003 /* Performance monitor registers user accessibility is controlled
1004 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1005 * trapping to EL2 or EL3 for other accesses.
1007 int el
= arm_current_el(env
);
1008 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1010 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1011 return CP_ACCESS_TRAP
;
1013 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1014 return CP_ACCESS_TRAP_EL2
;
1016 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1017 return CP_ACCESS_TRAP_EL3
;
1020 return CP_ACCESS_OK
;
1023 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1024 const ARMCPRegInfo
*ri
,
1027 /* ER: event counter read trap control */
1028 if (arm_feature(env
, ARM_FEATURE_V8
)
1029 && arm_current_el(env
) == 0
1030 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1032 return CP_ACCESS_OK
;
1035 return pmreg_access(env
, ri
, isread
);
1038 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1039 const ARMCPRegInfo
*ri
,
1042 /* SW: software increment write trap control */
1043 if (arm_feature(env
, ARM_FEATURE_V8
)
1044 && arm_current_el(env
) == 0
1045 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1047 return CP_ACCESS_OK
;
1050 return pmreg_access(env
, ri
, isread
);
1053 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1054 const ARMCPRegInfo
*ri
,
1057 /* ER: event counter read trap control */
1058 if (arm_feature(env
, ARM_FEATURE_V8
)
1059 && arm_current_el(env
) == 0
1060 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1061 return CP_ACCESS_OK
;
1064 return pmreg_access(env
, ri
, isread
);
1067 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1068 const ARMCPRegInfo
*ri
,
1071 /* CR: cycle counter read trap control */
1072 if (arm_feature(env
, ARM_FEATURE_V8
)
1073 && arm_current_el(env
) == 0
1074 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1076 return CP_ACCESS_OK
;
1079 return pmreg_access(env
, ri
, isread
);
1083 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1084 * We use these to decide whether we need to wrap a write to MDCR_EL2
1085 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1087 #define MDCR_EL2_PMU_ENABLE_BITS \
1088 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1089 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1091 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1092 * the current EL, security state, and register configuration.
1094 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1097 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1098 bool enabled
, prohibited
= false, filtered
;
1099 bool secure
= arm_is_secure(env
);
1100 int el
= arm_current_el(env
);
1101 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1102 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1104 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1108 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1109 (counter
< hpmn
|| counter
== 31)) {
1110 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1112 e
= mdcr_el2
& MDCR_HPME
;
1114 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1116 /* Is event counting prohibited? */
1117 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1118 prohibited
= mdcr_el2
& MDCR_HPMD
;
1121 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1124 if (counter
== 31) {
1126 * The cycle counter defaults to running. PMCR.DP says "disable
1127 * the cycle counter when event counting is prohibited".
1128 * Some MDCR bits disable the cycle counter specifically.
1130 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1131 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1133 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1136 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1141 if (counter
== 31) {
1142 filter
= env
->cp15
.pmccfiltr_el0
;
1144 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1147 p
= filter
& PMXEVTYPER_P
;
1148 u
= filter
& PMXEVTYPER_U
;
1149 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1150 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1151 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1152 m
= arm_el_is_aa64(env
, 1) &&
1153 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1156 filtered
= secure
? u
: u
!= nsu
;
1157 } else if (el
== 1) {
1158 filtered
= secure
? p
: p
!= nsk
;
1159 } else if (el
== 2) {
1165 if (counter
!= 31) {
1167 * If not checking PMCCNTR, ensure the counter is setup to an event we
1170 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1171 if (!event_supported(event
)) {
1176 return enabled
&& !prohibited
&& !filtered
;
1179 static void pmu_update_irq(CPUARMState
*env
)
1181 ARMCPU
*cpu
= env_archcpu(env
);
1182 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1183 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1186 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1189 * Return true if the clock divider is enabled and the cycle counter
1190 * is supposed to tick only once every 64 clock cycles. This is
1191 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1192 * (64-bit) cycle counter PMCR.D has no effect.
1194 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1197 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1199 /* Return true if the specified event counter is configured to be 64 bit */
1201 /* This isn't intended to be used with the cycle counter */
1202 assert(counter
< 31);
1204 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1208 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1210 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1211 * current security state, so we don't use arm_mdcr_el2_eff() here.
1213 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1214 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1216 if (hpmn
!= 0 && counter
>= hpmn
) {
1220 return env
->cp15
.c9_pmcr
& PMCRLP
;
1224 * Ensure c15_ccnt is the guest-visible count so that operations such as
1225 * enabling/disabling the counter or filtering, modifying the count itself,
1226 * etc. can be done logically. This is essentially a no-op if the counter is
1227 * not enabled at the time of the call.
1229 static void pmccntr_op_start(CPUARMState
*env
)
1231 uint64_t cycles
= cycles_get_count(env
);
1233 if (pmu_counter_enabled(env
, 31)) {
1234 uint64_t eff_cycles
= cycles
;
1235 if (pmccntr_clockdiv_enabled(env
)) {
1239 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1241 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1242 1ull << 63 : 1ull << 31;
1243 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1244 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1245 pmu_update_irq(env
);
1248 env
->cp15
.c15_ccnt
= new_pmccntr
;
1250 env
->cp15
.c15_ccnt_delta
= cycles
;
1254 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1255 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1258 static void pmccntr_op_finish(CPUARMState
*env
)
1260 if (pmu_counter_enabled(env
, 31)) {
1261 #ifndef CONFIG_USER_ONLY
1262 /* Calculate when the counter will next overflow */
1263 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1264 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1265 remaining_cycles
= (uint32_t)remaining_cycles
;
1267 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1269 if (overflow_in
> 0) {
1270 int64_t overflow_at
;
1272 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1273 overflow_in
, &overflow_at
)) {
1274 ARMCPU
*cpu
= env_archcpu(env
);
1275 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1280 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1281 if (pmccntr_clockdiv_enabled(env
)) {
1284 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1288 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1291 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1293 if (event_supported(event
)) {
1294 uint16_t event_idx
= supported_event_map
[event
];
1295 count
= pm_events
[event_idx
].get_count(env
);
1298 if (pmu_counter_enabled(env
, counter
)) {
1299 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1300 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1301 1ULL << 63 : 1ULL << 31;
1303 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1304 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1305 pmu_update_irq(env
);
1307 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1309 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1312 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1314 if (pmu_counter_enabled(env
, counter
)) {
1315 #ifndef CONFIG_USER_ONLY
1316 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1317 uint16_t event_idx
= supported_event_map
[event
];
1318 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1319 int64_t overflow_in
;
1321 if (!pmevcntr_is_64_bit(env
, counter
)) {
1322 delta
= (uint32_t)delta
;
1324 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1326 if (overflow_in
> 0) {
1327 int64_t overflow_at
;
1329 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1330 overflow_in
, &overflow_at
)) {
1331 ARMCPU
*cpu
= env_archcpu(env
);
1332 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1337 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1338 env
->cp15
.c14_pmevcntr
[counter
];
1342 void pmu_op_start(CPUARMState
*env
)
1345 pmccntr_op_start(env
);
1346 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1347 pmevcntr_op_start(env
, i
);
1351 void pmu_op_finish(CPUARMState
*env
)
1354 pmccntr_op_finish(env
);
1355 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1356 pmevcntr_op_finish(env
, i
);
1360 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1362 pmu_op_start(&cpu
->env
);
1365 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1367 pmu_op_finish(&cpu
->env
);
1370 void arm_pmu_timer_cb(void *opaque
)
1372 ARMCPU
*cpu
= opaque
;
1375 * Update all the counter values based on the current underlying counts,
1376 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1377 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1378 * counter may expire.
1380 pmu_op_start(&cpu
->env
);
1381 pmu_op_finish(&cpu
->env
);
1384 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1389 if (value
& PMCRC
) {
1390 /* The counter has been reset */
1391 env
->cp15
.c15_ccnt
= 0;
1394 if (value
& PMCRP
) {
1396 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1397 env
->cp15
.c14_pmevcntr
[i
] = 0;
1401 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1402 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1407 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1411 uint64_t overflow_mask
, new_pmswinc
;
1413 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1414 /* Increment a counter's count iff: */
1415 if ((value
& (1 << i
)) && /* counter's bit is set */
1416 /* counter is enabled and not filtered */
1417 pmu_counter_enabled(env
, i
) &&
1418 /* counter is SW_INCR */
1419 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1420 pmevcntr_op_start(env
, i
);
1423 * Detect if this write causes an overflow since we can't predict
1424 * PMSWINC overflows like we can for other events
1426 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1428 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1429 1ULL << 63 : 1ULL << 31;
1431 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1432 env
->cp15
.c9_pmovsr
|= (1 << i
);
1433 pmu_update_irq(env
);
1436 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1438 pmevcntr_op_finish(env
, i
);
1443 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1446 pmccntr_op_start(env
);
1447 ret
= env
->cp15
.c15_ccnt
;
1448 pmccntr_op_finish(env
);
1452 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1455 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1456 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1457 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1460 env
->cp15
.c9_pmselr
= value
& 0x1f;
1463 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1466 pmccntr_op_start(env
);
1467 env
->cp15
.c15_ccnt
= value
;
1468 pmccntr_op_finish(env
);
1471 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1474 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1476 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1479 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1482 pmccntr_op_start(env
);
1483 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1484 pmccntr_op_finish(env
);
1487 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1490 pmccntr_op_start(env
);
1491 /* M is not accessible from AArch32 */
1492 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1493 (value
& PMCCFILTR
);
1494 pmccntr_op_finish(env
);
1497 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1499 /* M is not visible in AArch32 */
1500 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1503 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1507 value
&= pmu_counter_mask(env
);
1508 env
->cp15
.c9_pmcnten
|= value
;
1512 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1516 value
&= pmu_counter_mask(env
);
1517 env
->cp15
.c9_pmcnten
&= ~value
;
1521 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1524 value
&= pmu_counter_mask(env
);
1525 env
->cp15
.c9_pmovsr
&= ~value
;
1526 pmu_update_irq(env
);
1529 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1532 value
&= pmu_counter_mask(env
);
1533 env
->cp15
.c9_pmovsr
|= value
;
1534 pmu_update_irq(env
);
1537 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1538 uint64_t value
, const uint8_t counter
)
1540 if (counter
== 31) {
1541 pmccfiltr_write(env
, ri
, value
);
1542 } else if (counter
< pmu_num_counters(env
)) {
1543 pmevcntr_op_start(env
, counter
);
1546 * If this counter's event type is changing, store the current
1547 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1548 * pmevcntr_op_finish has the correct baseline when it converts back to
1551 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1552 PMXEVTYPER_EVTCOUNT
;
1553 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1554 if (old_event
!= new_event
) {
1556 if (event_supported(new_event
)) {
1557 uint16_t event_idx
= supported_event_map
[new_event
];
1558 count
= pm_events
[event_idx
].get_count(env
);
1560 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1563 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1564 pmevcntr_op_finish(env
, counter
);
1566 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1567 * PMSELR value is equal to or greater than the number of implemented
1568 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1572 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1573 const uint8_t counter
)
1575 if (counter
== 31) {
1576 return env
->cp15
.pmccfiltr_el0
;
1577 } else if (counter
< pmu_num_counters(env
)) {
1578 return env
->cp15
.c14_pmevtyper
[counter
];
1581 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1582 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1588 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1591 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1592 pmevtyper_write(env
, ri
, value
, counter
);
1595 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1598 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1599 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1602 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1603 * pmu_op_finish calls when loading saved state for a migration. Because
1604 * we're potentially updating the type of event here, the value written to
1605 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1606 * different counter type. Therefore, we need to set this value to the
1607 * current count for the counter type we're writing so that pmu_op_finish
1608 * has the correct count for its calculation.
1610 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1611 if (event_supported(event
)) {
1612 uint16_t event_idx
= supported_event_map
[event
];
1613 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1614 pm_events
[event_idx
].get_count(env
);
1618 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1620 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1621 return pmevtyper_read(env
, ri
, counter
);
1624 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1627 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1630 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1632 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1635 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1636 uint64_t value
, uint8_t counter
)
1638 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1639 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1640 value
&= MAKE_64BIT_MASK(0, 32);
1642 if (counter
< pmu_num_counters(env
)) {
1643 pmevcntr_op_start(env
, counter
);
1644 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1645 pmevcntr_op_finish(env
, counter
);
1648 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1649 * are CONSTRAINED UNPREDICTABLE.
1653 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1656 if (counter
< pmu_num_counters(env
)) {
1658 pmevcntr_op_start(env
, counter
);
1659 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1660 pmevcntr_op_finish(env
, counter
);
1661 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1662 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1663 ret
&= MAKE_64BIT_MASK(0, 32);
1667 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1668 * are CONSTRAINED UNPREDICTABLE. */
1673 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1676 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1677 pmevcntr_write(env
, ri
, value
, counter
);
1680 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1682 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1683 return pmevcntr_read(env
, ri
, counter
);
1686 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1689 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1690 assert(counter
< pmu_num_counters(env
));
1691 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1692 pmevcntr_write(env
, ri
, value
, counter
);
1695 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1697 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1698 assert(counter
< pmu_num_counters(env
));
1699 return env
->cp15
.c14_pmevcntr
[counter
];
1702 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1705 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1708 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1710 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1713 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1716 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1717 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1719 env
->cp15
.c9_pmuserenr
= value
& 1;
1723 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1726 /* We have no event counters so only the C bit can be changed */
1727 value
&= pmu_counter_mask(env
);
1728 env
->cp15
.c9_pminten
|= value
;
1729 pmu_update_irq(env
);
1732 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1735 value
&= pmu_counter_mask(env
);
1736 env
->cp15
.c9_pminten
&= ~value
;
1737 pmu_update_irq(env
);
1740 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1743 /* Note that even though the AArch64 view of this register has bits
1744 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1745 * architectural requirements for bits which are RES0 only in some
1746 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1747 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1749 raw_write(env
, ri
, value
& ~0x1FULL
);
1752 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1754 /* Begin with base v8.0 state. */
1755 uint32_t valid_mask
= 0x3fff;
1756 ARMCPU
*cpu
= env_archcpu(env
);
1759 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1760 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1761 * Instead, choose the format based on the mode of EL3.
1763 if (arm_el_is_aa64(env
, 3)) {
1764 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1765 valid_mask
&= ~SCR_NET
; /* RES0 */
1767 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1768 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1769 value
|= SCR_RW
; /* RAO/WI */
1771 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1772 valid_mask
|= SCR_TERR
;
1774 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1775 valid_mask
|= SCR_TLOR
;
1777 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1778 valid_mask
|= SCR_API
| SCR_APK
;
1780 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1781 valid_mask
|= SCR_EEL2
;
1783 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1784 valid_mask
|= SCR_ATA
;
1786 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1787 valid_mask
|= SCR_ENSCXT
;
1789 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1790 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1793 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1794 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1795 valid_mask
|= SCR_TERR
;
1799 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1800 valid_mask
&= ~SCR_HCE
;
1802 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1803 * supported if EL2 exists. The bit is UNK/SBZP when
1804 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1805 * when EL2 is unavailable.
1806 * On ARMv8, this bit is always available.
1808 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1809 !arm_feature(env
, ARM_FEATURE_V8
)) {
1810 valid_mask
&= ~SCR_SMD
;
1814 /* Clear all-context RES0 bits. */
1815 value
&= valid_mask
;
1816 raw_write(env
, ri
, value
);
1819 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1822 * scr_write will set the RES1 bits on an AArch64-only CPU.
1823 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1825 scr_write(env
, ri
, 0);
1828 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1829 const ARMCPRegInfo
*ri
,
1832 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1833 return CP_ACCESS_TRAP_EL2
;
1836 return CP_ACCESS_OK
;
1839 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1841 ARMCPU
*cpu
= env_archcpu(env
);
1843 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1846 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1847 ri
->secure
& ARM_CP_SECSTATE_S
);
1849 return cpu
->ccsidr
[index
];
1852 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1855 raw_write(env
, ri
, value
& 0xf);
1858 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1860 CPUState
*cs
= env_cpu(env
);
1861 bool el1
= arm_current_el(env
) == 1;
1862 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1865 if (hcr_el2
& HCR_IMO
) {
1866 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1870 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1875 if (hcr_el2
& HCR_FMO
) {
1876 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1880 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1885 if (hcr_el2
& HCR_AMO
) {
1886 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1894 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1897 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
1898 return CP_ACCESS_TRAP_EL2
;
1901 return CP_ACCESS_OK
;
1904 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1907 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1908 return access_aa64_tid1(env
, ri
, isread
);
1911 return CP_ACCESS_OK
;
1914 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1915 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1916 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1917 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1918 /* Performance monitors are implementation defined in v7,
1919 * but with an ARM recommended set of registers, which we
1922 * Performance registers fall into three categories:
1923 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1924 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1925 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1926 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1927 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1929 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1930 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1931 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1932 .writefn
= pmcntenset_write
,
1933 .accessfn
= pmreg_access
,
1934 .raw_writefn
= raw_write
},
1935 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
1936 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1937 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1938 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1939 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1940 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1942 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1943 .accessfn
= pmreg_access
,
1944 .writefn
= pmcntenclr_write
,
1945 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
1946 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1947 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1948 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1949 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1950 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1951 .writefn
= pmcntenclr_write
},
1952 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1953 .access
= PL0_RW
, .type
= ARM_CP_IO
,
1954 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1955 .accessfn
= pmreg_access
,
1956 .writefn
= pmovsr_write
,
1957 .raw_writefn
= raw_write
},
1958 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1959 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1960 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1961 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1962 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1963 .writefn
= pmovsr_write
,
1964 .raw_writefn
= raw_write
},
1965 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1966 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1967 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1968 .writefn
= pmswinc_write
},
1969 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
1970 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
1971 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1972 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1973 .writefn
= pmswinc_write
},
1974 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1975 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1976 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1977 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1978 .raw_writefn
= raw_write
},
1979 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1980 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1981 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1982 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1983 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1984 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1985 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1986 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1987 .accessfn
= pmreg_access_ccntr
},
1988 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1989 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1990 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1992 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
1993 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
1994 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
1995 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
1996 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
1997 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1998 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2000 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2001 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2002 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2003 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2005 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2007 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2008 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2009 .accessfn
= pmreg_access
,
2010 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2011 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2012 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2013 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2014 .accessfn
= pmreg_access
,
2015 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2016 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2017 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2018 .accessfn
= pmreg_access_xevcntr
,
2019 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2020 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2021 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2022 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2023 .accessfn
= pmreg_access_xevcntr
,
2024 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2025 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2026 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2027 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2029 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2030 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2031 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2032 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2033 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2035 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2036 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2037 .access
= PL1_RW
, .accessfn
= access_tpm
,
2038 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2039 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2041 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2042 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2043 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2044 .access
= PL1_RW
, .accessfn
= access_tpm
,
2046 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2047 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2048 .resetvalue
= 0x0 },
2049 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2050 .access
= PL1_RW
, .accessfn
= access_tpm
,
2051 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2052 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2053 .writefn
= pmintenclr_write
, },
2054 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2055 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2056 .access
= PL1_RW
, .accessfn
= access_tpm
,
2057 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2058 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2059 .writefn
= pmintenclr_write
},
2060 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2061 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2063 .accessfn
= access_aa64_tid2
,
2064 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2065 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2066 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2068 .accessfn
= access_aa64_tid2
,
2069 .writefn
= csselr_write
, .resetvalue
= 0,
2070 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2071 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2072 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2073 * just RAZ for all cores:
2075 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2076 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2077 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2078 .accessfn
= access_aa64_tid1
,
2080 /* Auxiliary fault status registers: these also are IMPDEF, and we
2081 * choose to RAZ/WI for all cores.
2083 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2084 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2085 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2086 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2087 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2088 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2089 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2090 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2091 /* MAIR can just read-as-written because we don't implement caches
2092 * and so don't need to care about memory attributes.
2094 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2095 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2096 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2097 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2099 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2100 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2101 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2103 /* For non-long-descriptor page tables these are PRRR and NMRR;
2104 * regardless they still act as reads-as-written for QEMU.
2106 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2107 * allows them to assign the correct fieldoffset based on the endianness
2108 * handled in the field definitions.
2110 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2111 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2112 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2113 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2114 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2115 .resetfn
= arm_cp_reset_ignore
},
2116 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2117 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2118 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2119 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2120 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2121 .resetfn
= arm_cp_reset_ignore
},
2122 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2123 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2124 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2125 /* 32 bit ITLB invalidates */
2126 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2127 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2128 .writefn
= tlbiall_write
},
2129 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2130 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2131 .writefn
= tlbimva_write
},
2132 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2133 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2134 .writefn
= tlbiasid_write
},
2135 /* 32 bit DTLB invalidates */
2136 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2137 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2138 .writefn
= tlbiall_write
},
2139 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2140 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2141 .writefn
= tlbimva_write
},
2142 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2143 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2144 .writefn
= tlbiasid_write
},
2145 /* 32 bit TLB invalidates */
2146 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2147 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2148 .writefn
= tlbiall_write
},
2149 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2150 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2151 .writefn
= tlbimva_write
},
2152 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2153 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2154 .writefn
= tlbiasid_write
},
2155 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2156 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2157 .writefn
= tlbimvaa_write
},
2160 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2161 /* 32 bit TLB invalidates, Inner Shareable */
2162 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2163 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2164 .writefn
= tlbiall_is_write
},
2165 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2166 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2167 .writefn
= tlbimva_is_write
},
2168 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2169 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2170 .writefn
= tlbiasid_is_write
},
2171 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2172 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2173 .writefn
= tlbimvaa_is_write
},
2176 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2177 /* PMOVSSET is not implemented in v7 before v7ve */
2178 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2179 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2180 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2181 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2182 .writefn
= pmovsset_write
,
2183 .raw_writefn
= raw_write
},
2184 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2185 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2186 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2187 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2188 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2189 .writefn
= pmovsset_write
,
2190 .raw_writefn
= raw_write
},
2193 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2200 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2204 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2205 * at all, so we don't need to check whether we're v8A.
2207 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2208 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2209 return CP_ACCESS_TRAP_EL2
;
2211 return CP_ACCESS_OK
;
2214 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2217 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2218 return CP_ACCESS_TRAP
;
2220 return teecr_access(env
, ri
, isread
);
2223 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2224 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2225 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2227 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2228 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2229 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2230 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2233 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2234 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2235 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2237 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2238 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2240 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2241 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2242 .resetfn
= arm_cp_reset_ignore
},
2243 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2244 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2245 .access
= PL0_R
|PL1_W
,
2246 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2248 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2249 .access
= PL0_R
|PL1_W
,
2250 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2251 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2252 .resetfn
= arm_cp_reset_ignore
},
2253 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2254 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2256 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2257 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2259 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2260 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2264 #ifndef CONFIG_USER_ONLY
2266 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2269 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2270 * Writable only at the highest implemented exception level.
2272 int el
= arm_current_el(env
);
2278 hcr
= arm_hcr_el2_eff(env
);
2279 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2280 cntkctl
= env
->cp15
.cnthctl_el2
;
2282 cntkctl
= env
->cp15
.c14_cntkctl
;
2284 if (!extract32(cntkctl
, 0, 2)) {
2285 return CP_ACCESS_TRAP
;
2289 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2290 arm_is_secure_below_el3(env
)) {
2291 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2292 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2300 if (!isread
&& el
< arm_highest_el(env
)) {
2301 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2304 return CP_ACCESS_OK
;
2307 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2310 unsigned int cur_el
= arm_current_el(env
);
2311 bool has_el2
= arm_is_el2_enabled(env
);
2312 uint64_t hcr
= arm_hcr_el2_eff(env
);
2316 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2317 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2318 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2319 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2322 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2323 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2324 return CP_ACCESS_TRAP
;
2327 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2328 if (hcr
& HCR_E2H
) {
2329 if (timeridx
== GTIMER_PHYS
&&
2330 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2331 return CP_ACCESS_TRAP_EL2
;
2334 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2335 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2336 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2337 return CP_ACCESS_TRAP_EL2
;
2343 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2344 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2346 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2347 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2348 return CP_ACCESS_TRAP_EL2
;
2352 return CP_ACCESS_OK
;
2355 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2358 unsigned int cur_el
= arm_current_el(env
);
2359 bool has_el2
= arm_is_el2_enabled(env
);
2360 uint64_t hcr
= arm_hcr_el2_eff(env
);
2364 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2365 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2366 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2367 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2371 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2372 * EL0 if EL0[PV]TEN is zero.
2374 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2375 return CP_ACCESS_TRAP
;
2380 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2381 if (hcr
& HCR_E2H
) {
2382 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2383 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2384 return CP_ACCESS_TRAP_EL2
;
2387 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2388 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2389 return CP_ACCESS_TRAP_EL2
;
2395 return CP_ACCESS_OK
;
2398 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2399 const ARMCPRegInfo
*ri
,
2402 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2405 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2406 const ARMCPRegInfo
*ri
,
2409 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2412 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2415 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2418 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2421 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2424 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2425 const ARMCPRegInfo
*ri
,
2428 /* The AArch64 register view of the secure physical timer is
2429 * always accessible from EL3, and configurably accessible from
2432 switch (arm_current_el(env
)) {
2434 if (!arm_is_secure(env
)) {
2435 return CP_ACCESS_TRAP
;
2437 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2438 return CP_ACCESS_TRAP_EL3
;
2440 return CP_ACCESS_OK
;
2443 return CP_ACCESS_TRAP
;
2445 return CP_ACCESS_OK
;
2447 g_assert_not_reached();
2451 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2453 ARMCPU
*cpu
= env_archcpu(env
);
2455 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2458 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2460 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2463 /* Timer enabled: calculate and set current ISTATUS, irq, and
2464 * reset timer to when ISTATUS next has to change
2466 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2467 cpu
->env
.cp15
.cntvoff_el2
: 0;
2468 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2469 /* Note that this must be unsigned 64 bit arithmetic: */
2470 int istatus
= count
- offset
>= gt
->cval
;
2474 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2476 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2477 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2480 /* Next transition is when count rolls back over to zero */
2481 nexttick
= UINT64_MAX
;
2483 /* Next transition is when we hit cval */
2484 nexttick
= gt
->cval
+ offset
;
2486 /* Note that the desired next expiry time might be beyond the
2487 * signed-64-bit range of a QEMUTimer -- in this case we just
2488 * set the timer for as far in the future as possible. When the
2489 * timer expires we will reset the timer for any remaining period.
2491 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2492 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2494 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2496 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2498 /* Timer disabled: ISTATUS and timer output always clear */
2500 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2501 timer_del(cpu
->gt_timer
[timeridx
]);
2502 trace_arm_gt_recalc_disabled(timeridx
);
2506 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2509 ARMCPU
*cpu
= env_archcpu(env
);
2511 timer_del(cpu
->gt_timer
[timeridx
]);
2514 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2516 return gt_get_countervalue(env
);
2519 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2523 switch (arm_current_el(env
)) {
2525 hcr
= arm_hcr_el2_eff(env
);
2526 if (hcr
& HCR_E2H
) {
2531 hcr
= arm_hcr_el2_eff(env
);
2532 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2538 return env
->cp15
.cntvoff_el2
;
2541 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2543 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2546 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2550 trace_arm_gt_cval_write(timeridx
, value
);
2551 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2552 gt_recalc_timer(env_archcpu(env
), timeridx
);
2555 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2558 uint64_t offset
= 0;
2562 case GTIMER_HYPVIRT
:
2563 offset
= gt_virt_cnt_offset(env
);
2567 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2568 (gt_get_countervalue(env
) - offset
));
2571 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2575 uint64_t offset
= 0;
2579 case GTIMER_HYPVIRT
:
2580 offset
= gt_virt_cnt_offset(env
);
2584 trace_arm_gt_tval_write(timeridx
, value
);
2585 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2586 sextract64(value
, 0, 32);
2587 gt_recalc_timer(env_archcpu(env
), timeridx
);
2590 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2594 ARMCPU
*cpu
= env_archcpu(env
);
2595 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2597 trace_arm_gt_ctl_write(timeridx
, value
);
2598 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2599 if ((oldval
^ value
) & 1) {
2600 /* Enable toggled */
2601 gt_recalc_timer(cpu
, timeridx
);
2602 } else if ((oldval
^ value
) & 2) {
2603 /* IMASK toggled: don't need to recalculate,
2604 * just set the interrupt line based on ISTATUS
2606 int irqstate
= (oldval
& 4) && !(value
& 2);
2608 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2609 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2613 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2615 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2618 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2621 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2624 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2626 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2629 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2632 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2635 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2638 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2641 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2643 switch (arm_mmu_idx(env
)) {
2644 case ARMMMUIdx_E20_0
:
2645 case ARMMMUIdx_E20_2
:
2646 case ARMMMUIdx_E20_2_PAN
:
2647 case ARMMMUIdx_SE20_0
:
2648 case ARMMMUIdx_SE20_2
:
2649 case ARMMMUIdx_SE20_2_PAN
:
2656 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2658 switch (arm_mmu_idx(env
)) {
2659 case ARMMMUIdx_E20_0
:
2660 case ARMMMUIdx_E20_2
:
2661 case ARMMMUIdx_E20_2_PAN
:
2662 case ARMMMUIdx_SE20_0
:
2663 case ARMMMUIdx_SE20_2
:
2664 case ARMMMUIdx_SE20_2_PAN
:
2665 return GTIMER_HYPVIRT
;
2671 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2672 const ARMCPRegInfo
*ri
)
2674 int timeridx
= gt_phys_redir_timeridx(env
);
2675 return env
->cp15
.c14_timer
[timeridx
].cval
;
2678 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2681 int timeridx
= gt_phys_redir_timeridx(env
);
2682 gt_cval_write(env
, ri
, timeridx
, value
);
2685 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2686 const ARMCPRegInfo
*ri
)
2688 int timeridx
= gt_phys_redir_timeridx(env
);
2689 return gt_tval_read(env
, ri
, timeridx
);
2692 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2695 int timeridx
= gt_phys_redir_timeridx(env
);
2696 gt_tval_write(env
, ri
, timeridx
, value
);
2699 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2700 const ARMCPRegInfo
*ri
)
2702 int timeridx
= gt_phys_redir_timeridx(env
);
2703 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2706 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2709 int timeridx
= gt_phys_redir_timeridx(env
);
2710 gt_ctl_write(env
, ri
, timeridx
, value
);
2713 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2715 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2718 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2721 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2724 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2726 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2729 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2732 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2735 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2738 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2741 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2744 ARMCPU
*cpu
= env_archcpu(env
);
2746 trace_arm_gt_cntvoff_write(value
);
2747 raw_write(env
, ri
, value
);
2748 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2751 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2752 const ARMCPRegInfo
*ri
)
2754 int timeridx
= gt_virt_redir_timeridx(env
);
2755 return env
->cp15
.c14_timer
[timeridx
].cval
;
2758 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2761 int timeridx
= gt_virt_redir_timeridx(env
);
2762 gt_cval_write(env
, ri
, timeridx
, value
);
2765 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2766 const ARMCPRegInfo
*ri
)
2768 int timeridx
= gt_virt_redir_timeridx(env
);
2769 return gt_tval_read(env
, ri
, timeridx
);
2772 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2775 int timeridx
= gt_virt_redir_timeridx(env
);
2776 gt_tval_write(env
, ri
, timeridx
, value
);
2779 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2780 const ARMCPRegInfo
*ri
)
2782 int timeridx
= gt_virt_redir_timeridx(env
);
2783 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2786 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2789 int timeridx
= gt_virt_redir_timeridx(env
);
2790 gt_ctl_write(env
, ri
, timeridx
, value
);
2793 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2795 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2798 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2801 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2804 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2806 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2809 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2812 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2815 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2818 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2821 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2823 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2826 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2829 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2832 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2834 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2837 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2840 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2843 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2846 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2849 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2851 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2854 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2857 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2860 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2862 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2865 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2868 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2871 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2874 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2877 void arm_gt_ptimer_cb(void *opaque
)
2879 ARMCPU
*cpu
= opaque
;
2881 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2884 void arm_gt_vtimer_cb(void *opaque
)
2886 ARMCPU
*cpu
= opaque
;
2888 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2891 void arm_gt_htimer_cb(void *opaque
)
2893 ARMCPU
*cpu
= opaque
;
2895 gt_recalc_timer(cpu
, GTIMER_HYP
);
2898 void arm_gt_stimer_cb(void *opaque
)
2900 ARMCPU
*cpu
= opaque
;
2902 gt_recalc_timer(cpu
, GTIMER_SEC
);
2905 void arm_gt_hvtimer_cb(void *opaque
)
2907 ARMCPU
*cpu
= opaque
;
2909 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
2912 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2914 ARMCPU
*cpu
= env_archcpu(env
);
2916 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
2919 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2920 /* Note that CNTFRQ is purely reads-as-written for the benefit
2921 * of software; writing it doesn't actually change the timer frequency.
2922 * Our reset value matches the fixed frequency we implement the timer at.
2924 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2925 .type
= ARM_CP_ALIAS
,
2926 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2927 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2929 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2930 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2931 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2932 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2933 .resetfn
= arm_gt_cntfrq_reset
,
2935 /* overall control: mostly access permissions */
2936 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2937 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2939 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2942 /* per-timer control */
2943 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2944 .secure
= ARM_CP_SECSTATE_NS
,
2945 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2946 .accessfn
= gt_ptimer_access
,
2947 .fieldoffset
= offsetoflow32(CPUARMState
,
2948 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2949 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2950 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2952 { .name
= "CNTP_CTL_S",
2953 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2954 .secure
= ARM_CP_SECSTATE_S
,
2955 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2956 .accessfn
= gt_ptimer_access
,
2957 .fieldoffset
= offsetoflow32(CPUARMState
,
2958 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2959 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2961 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2962 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2963 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2964 .accessfn
= gt_ptimer_access
,
2965 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2967 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2968 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2970 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2971 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2972 .accessfn
= gt_vtimer_access
,
2973 .fieldoffset
= offsetoflow32(CPUARMState
,
2974 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2975 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2976 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2978 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2979 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2980 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2981 .accessfn
= gt_vtimer_access
,
2982 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2984 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2985 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2987 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2988 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2989 .secure
= ARM_CP_SECSTATE_NS
,
2990 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2991 .accessfn
= gt_ptimer_access
,
2992 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2994 { .name
= "CNTP_TVAL_S",
2995 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2996 .secure
= ARM_CP_SECSTATE_S
,
2997 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2998 .accessfn
= gt_ptimer_access
,
2999 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3001 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3002 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3003 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3004 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3005 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3007 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3008 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3009 .accessfn
= gt_vtimer_access
,
3010 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3012 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3013 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3014 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3015 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3016 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3018 /* The counter itself */
3019 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3020 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3021 .accessfn
= gt_pct_access
,
3022 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3024 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3025 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3026 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3027 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3029 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3030 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3031 .accessfn
= gt_vct_access
,
3032 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3034 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3035 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3036 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3037 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3039 /* Comparison value, indicating when the timer goes off */
3040 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3041 .secure
= ARM_CP_SECSTATE_NS
,
3043 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3045 .accessfn
= gt_ptimer_access
,
3046 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3047 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3049 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3050 .secure
= ARM_CP_SECSTATE_S
,
3052 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3053 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3054 .accessfn
= gt_ptimer_access
,
3055 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3057 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3058 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3061 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3062 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3063 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3064 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3066 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3068 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3069 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3070 .accessfn
= gt_vtimer_access
,
3071 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3072 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3074 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3075 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3078 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3079 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3080 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3081 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3083 /* Secure timer -- this is actually restricted to only EL3
3084 * and configurably Secure-EL1 via the accessfn.
3086 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3087 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3088 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3089 .accessfn
= gt_stimer_access
,
3090 .readfn
= gt_sec_tval_read
,
3091 .writefn
= gt_sec_tval_write
,
3092 .resetfn
= gt_sec_timer_reset
,
3094 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3095 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3096 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3097 .accessfn
= gt_stimer_access
,
3098 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3100 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3102 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3103 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3104 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3105 .accessfn
= gt_stimer_access
,
3106 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3107 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3111 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3114 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3115 return CP_ACCESS_TRAP
;
3117 return CP_ACCESS_OK
;
3122 /* In user-mode most of the generic timer registers are inaccessible
3123 * however modern kernels (4.12+) allow access to cntvct_el0
3126 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3128 ARMCPU
*cpu
= env_archcpu(env
);
3130 /* Currently we have no support for QEMUTimer in linux-user so we
3131 * can't call gt_get_countervalue(env), instead we directly
3132 * call the lower level functions.
3134 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3137 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3138 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3139 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3140 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3141 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3142 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3144 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3145 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3146 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3147 .readfn
= gt_virt_cnt_read
,
3153 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3155 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3156 raw_write(env
, ri
, value
);
3157 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3158 raw_write(env
, ri
, value
& 0xfffff6ff);
3160 raw_write(env
, ri
, value
& 0xfffff1ff);
3164 #ifndef CONFIG_USER_ONLY
3165 /* get_phys_addr() isn't present for user-mode-only targets */
3167 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3171 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3172 * Secure EL1 (which can only happen if EL3 is AArch64).
3173 * They are simply UNDEF if executed from NS EL1.
3174 * They function normally from EL2 or EL3.
3176 if (arm_current_el(env
) == 1) {
3177 if (arm_is_secure_below_el3(env
)) {
3178 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3179 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2
;
3181 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3183 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3186 return CP_ACCESS_OK
;
3190 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3191 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3195 bool format64
= false;
3196 ARMMMUFaultInfo fi
= {};
3197 GetPhysAddrResult res
= {};
3199 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &res
, &fi
);
3202 * ATS operations only do S1 or S1+S2 translations, so we never
3203 * have to deal with the ARMCacheAttrs format for S2 only.
3205 assert(!res
.cacheattrs
.is_s2_format
);
3209 * Some kinds of translation fault must cause exceptions rather
3210 * than being reported in the PAR.
3212 int current_el
= arm_current_el(env
);
3214 uint32_t syn
, fsr
, fsc
;
3215 bool take_exc
= false;
3217 if (fi
.s1ptw
&& current_el
== 1
3218 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3220 * Synchronous stage 2 fault on an access made as part of the
3221 * translation table walk for AT S1E0* or AT S1E1* insn
3222 * executed from NS EL1. If this is a synchronous external abort
3223 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3224 * to EL3. Otherwise the fault is taken as an exception to EL2,
3225 * and HPFAR_EL2 holds the faulting IPA.
3227 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3228 (env
->cp15
.scr_el3
& SCR_EA
)) {
3231 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3232 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3233 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3238 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3240 * Synchronous external aborts during a translation table walk
3241 * are taken as Data Abort exceptions.
3244 if (current_el
== 3) {
3250 target_el
= exception_target_el(env
);
3256 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3257 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3258 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3259 fsr
= arm_fi_to_lfsc(&fi
);
3260 fsc
= extract32(fsr
, 0, 6);
3262 fsr
= arm_fi_to_sfsc(&fi
);
3266 * Report exception with ESR indicating a fault due to a
3267 * translation table walk for a cache maintenance instruction.
3269 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3270 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3271 env
->exception
.vaddress
= value
;
3272 env
->exception
.fsr
= fsr
;
3273 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3279 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3282 * * TTBCR.EAE determines whether the result is returned using the
3283 * 32-bit or the 64-bit PAR format
3284 * * Instructions executed in Hyp mode always use the 64bit format
3286 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3287 * * The Non-secure TTBCR.EAE bit is set to 1
3288 * * The implementation includes EL2, and the value of HCR.VM is 1
3290 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3292 * ATS1Hx always uses the 64bit format.
3294 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3296 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3297 if (mmu_idx
== ARMMMUIdx_E10_0
||
3298 mmu_idx
== ARMMMUIdx_E10_1
||
3299 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3300 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3302 format64
|= arm_current_el(env
) == 2;
3308 /* Create a 64-bit PAR */
3309 par64
= (1 << 11); /* LPAE bit always set */
3311 par64
|= res
.phys
& ~0xfffULL
;
3312 if (!res
.attrs
.secure
) {
3313 par64
|= (1 << 9); /* NS */
3315 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3316 par64
|= res
.cacheattrs
.shareability
<< 7; /* SH */
3318 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3321 par64
|= (fsr
& 0x3f) << 1; /* FS */
3323 par64
|= (1 << 9); /* S */
3326 par64
|= (1 << 8); /* PTW */
3330 /* fsr is a DFSR/IFSR value for the short descriptor
3331 * translation table format (with WnR always clear).
3332 * Convert it to a 32-bit PAR.
3335 /* We do not set any attribute bits in the PAR */
3336 if (res
.page_size
== (1 << 24)
3337 && arm_feature(env
, ARM_FEATURE_V7
)) {
3338 par64
= (res
.phys
& 0xff000000) | (1 << 1);
3340 par64
= res
.phys
& 0xfffff000;
3342 if (!res
.attrs
.secure
) {
3343 par64
|= (1 << 9); /* NS */
3346 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3348 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3349 ((fsr
& 0xf) << 1) | 1;
3354 #endif /* CONFIG_TCG */
3356 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3359 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3362 int el
= arm_current_el(env
);
3363 bool secure
= arm_is_secure_below_el3(env
);
3365 switch (ri
->opc2
& 6) {
3367 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3370 mmu_idx
= ARMMMUIdx_SE3
;
3373 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3376 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3377 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3378 : ARMMMUIdx_Stage1_E1_PAN
);
3380 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3384 g_assert_not_reached();
3388 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3391 mmu_idx
= ARMMMUIdx_SE10_0
;
3394 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3395 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3398 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3401 g_assert_not_reached();
3405 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3406 mmu_idx
= ARMMMUIdx_E10_1
;
3409 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3410 mmu_idx
= ARMMMUIdx_E10_0
;
3413 g_assert_not_reached();
3416 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3418 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3420 /* Handled by hardware accelerator. */
3421 g_assert_not_reached();
3422 #endif /* CONFIG_TCG */
3425 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3429 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3432 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3434 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3436 /* Handled by hardware accelerator. */
3437 g_assert_not_reached();
3438 #endif /* CONFIG_TCG */
3441 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3444 if (arm_current_el(env
) == 3 &&
3445 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3446 return CP_ACCESS_TRAP
;
3448 return CP_ACCESS_OK
;
3451 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3455 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3457 int secure
= arm_is_secure_below_el3(env
);
3459 switch (ri
->opc2
& 6) {
3462 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3463 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3464 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3465 : ARMMMUIdx_Stage1_E1_PAN
);
3467 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3470 case 4: /* AT S1E2R, AT S1E2W */
3471 mmu_idx
= secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
;
3473 case 6: /* AT S1E3R, AT S1E3W */
3474 mmu_idx
= ARMMMUIdx_SE3
;
3477 g_assert_not_reached();
3480 case 2: /* AT S1E0R, AT S1E0W */
3481 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3483 case 4: /* AT S12E1R, AT S12E1W */
3484 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3486 case 6: /* AT S12E0R, AT S12E0W */
3487 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3490 g_assert_not_reached();
3493 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3495 /* Handled by hardware accelerator. */
3496 g_assert_not_reached();
3497 #endif /* CONFIG_TCG */
3501 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3502 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3503 .access
= PL1_RW
, .resetvalue
= 0,
3504 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3505 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3506 .writefn
= par_write
},
3507 #ifndef CONFIG_USER_ONLY
3508 /* This underdecoding is safe because the reginfo is NO_RAW. */
3509 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3510 .access
= PL1_W
, .accessfn
= ats_access
,
3511 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3515 /* Return basic MPU access permission bits. */
3516 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3523 for (i
= 0; i
< 16; i
+= 2) {
3524 ret
|= (val
>> i
) & mask
;
3530 /* Pad basic MPU access permission bits to extended format. */
3531 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3538 for (i
= 0; i
< 16; i
+= 2) {
3539 ret
|= (val
& mask
) << i
;
3545 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3548 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3551 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3553 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3556 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3559 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3562 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3564 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3567 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3569 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3575 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3579 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3582 ARMCPU
*cpu
= env_archcpu(env
);
3583 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3589 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3590 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3594 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3597 ARMCPU
*cpu
= env_archcpu(env
);
3598 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3600 if (value
>= nrgs
) {
3601 qemu_log_mask(LOG_GUEST_ERROR
,
3602 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3603 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3607 raw_write(env
, ri
, value
);
3610 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3611 /* Reset for all these registers is handled in arm_cpu_reset(),
3612 * because the PMSAv7 is also used by M-profile CPUs, which do
3613 * not register cpregs but still need the state to be reset.
3615 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3616 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3617 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3618 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3619 .resetfn
= arm_cp_reset_ignore
},
3620 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3621 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3622 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3623 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3624 .resetfn
= arm_cp_reset_ignore
},
3625 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3626 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3627 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3628 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3629 .resetfn
= arm_cp_reset_ignore
},
3630 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3632 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3633 .writefn
= pmsav7_rgnr_write
,
3634 .resetfn
= arm_cp_reset_ignore
},
3637 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3638 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3639 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3640 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3641 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3642 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3643 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3644 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3645 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3646 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3648 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3650 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3652 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3654 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3656 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3657 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3659 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3660 /* Protection region base and size registers */
3661 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3662 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3663 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3664 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3665 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3666 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3667 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3668 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3669 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3670 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3671 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3672 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3673 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3674 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3675 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3676 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3677 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3678 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3679 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3680 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3681 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3682 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3683 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3684 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3687 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3690 ARMCPU
*cpu
= env_archcpu(env
);
3692 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3693 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3695 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3696 * using Long-descriptor translation table format
3698 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3699 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3701 * In an implementation that includes the Security Extensions
3702 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3703 * Short-descriptor translation table format.
3705 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3711 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3712 /* With LPAE the TTBCR could result in a change of ASID
3713 * via the TTBCR.A1 bit, so do a TLB flush.
3715 tlb_flush(CPU(cpu
));
3717 raw_write(env
, ri
, value
);
3720 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3723 ARMCPU
*cpu
= env_archcpu(env
);
3725 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3726 tlb_flush(CPU(cpu
));
3727 raw_write(env
, ri
, value
);
3730 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3733 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3734 if (cpreg_field_is_64bit(ri
) &&
3735 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3736 ARMCPU
*cpu
= env_archcpu(env
);
3737 tlb_flush(CPU(cpu
));
3739 raw_write(env
, ri
, value
);
3742 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3746 * If we are running with E2&0 regime, then an ASID is active.
3747 * Flush if that might be changing. Note we're not checking
3748 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3749 * holds the active ASID, only checking the field that might.
3751 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3752 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3753 uint16_t mask
= ARMMMUIdxBit_E20_2
|
3754 ARMMMUIdxBit_E20_2_PAN
|
3757 if (arm_is_secure_below_el3(env
)) {
3758 mask
>>= ARM_MMU_IDX_A_NS
;
3761 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
3763 raw_write(env
, ri
, value
);
3766 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3769 ARMCPU
*cpu
= env_archcpu(env
);
3770 CPUState
*cs
= CPU(cpu
);
3773 * A change in VMID to the stage2 page table (Stage2) invalidates
3774 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3776 if (raw_read(env
, ri
) != value
) {
3777 uint16_t mask
= ARMMMUIdxBit_E10_1
|
3778 ARMMMUIdxBit_E10_1_PAN
|
3781 if (arm_is_secure_below_el3(env
)) {
3782 mask
>>= ARM_MMU_IDX_A_NS
;
3785 tlb_flush_by_mmuidx(cs
, mask
);
3786 raw_write(env
, ri
, value
);
3790 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3791 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3792 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
3793 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3794 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3795 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3796 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3797 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3798 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3799 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3800 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3801 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3802 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3803 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3804 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3805 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3806 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3810 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3811 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3812 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3813 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3814 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3815 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3816 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3817 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3818 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3819 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3820 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3821 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3822 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3823 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3824 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3825 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3826 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3827 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3828 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3829 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3830 .writefn
= vmsa_tcr_el12_write
,
3831 .raw_writefn
= raw_write
,
3833 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3834 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3835 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3836 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3837 .raw_writefn
= raw_write
,
3838 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
3839 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
3842 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3843 * qemu tlbs nor adjusting cached masks.
3845 static const ARMCPRegInfo ttbcr2_reginfo
= {
3846 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3847 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3848 .type
= ARM_CP_ALIAS
,
3849 .bank_fieldoffsets
= {
3850 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
3851 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
3855 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3858 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3859 /* The OS_TYPE bit in this register changes the reported CPUID! */
3860 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3861 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3864 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3867 env
->cp15
.c15_threadid
= value
& 0xffff;
3870 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3873 /* Wait-for-interrupt (deprecated) */
3874 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3877 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3880 /* On OMAP there are registers indicating the max/min index of dcache lines
3881 * containing a dirty line; cache flush operations have to reset these.
3883 env
->cp15
.c15_i_max
= 0x000;
3884 env
->cp15
.c15_i_min
= 0xff0;
3887 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3888 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3889 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3890 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3892 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3893 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3894 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3896 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3897 .writefn
= omap_ticonfig_write
},
3898 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3900 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3901 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3902 .access
= PL1_RW
, .resetvalue
= 0xff0,
3903 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3904 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3906 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3907 .writefn
= omap_threadid_write
},
3908 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3909 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3910 .type
= ARM_CP_NO_RAW
,
3911 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3912 /* TODO: Peripheral port remap register:
3913 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3914 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3917 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3918 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3919 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3920 .writefn
= omap_cachemaint_write
},
3921 { .name
= "C9", .cp
= 15, .crn
= 9,
3922 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3923 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3926 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3929 env
->cp15
.c15_cpar
= value
& 0x3fff;
3932 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3933 { .name
= "XSCALE_CPAR",
3934 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3935 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3936 .writefn
= xscale_cpar_write
, },
3937 { .name
= "XSCALE_AUXCR",
3938 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3939 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3941 /* XScale specific cache-lockdown: since we have no cache we NOP these
3942 * and hope the guest does not really rely on cache behaviour.
3944 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3945 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3946 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3947 { .name
= "XSCALE_UNLOCK_ICACHE",
3948 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3949 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3950 { .name
= "XSCALE_DCACHE_LOCK",
3951 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3952 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3953 { .name
= "XSCALE_UNLOCK_DCACHE",
3954 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3955 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3958 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3959 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3960 * implementation of this implementation-defined space.
3961 * Ideally this should eventually disappear in favour of actually
3962 * implementing the correct behaviour for all cores.
3964 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3965 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3967 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3971 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3972 /* Cache status: RAZ because we have no cache so it's always clean */
3973 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3974 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3978 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3979 /* We never have a block transfer operation in progress */
3980 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3981 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3983 /* The cache ops themselves: these all NOP for QEMU */
3984 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3985 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3986 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
3987 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3988 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
3989 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3990 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
3991 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3992 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
3993 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3994 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
3995 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3998 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
3999 /* The cache test-and-clean instructions always return (1 << 30)
4000 * to indicate that there are no dirty cache lines.
4002 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4003 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4004 .resetvalue
= (1 << 30) },
4005 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4006 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4007 .resetvalue
= (1 << 30) },
4010 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4011 /* Ignore ReadBuffer accesses */
4012 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4013 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4014 .access
= PL1_RW
, .resetvalue
= 0,
4015 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4018 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4020 unsigned int cur_el
= arm_current_el(env
);
4022 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4023 return env
->cp15
.vpidr_el2
;
4025 return raw_read(env
, ri
);
4028 static uint64_t mpidr_read_val(CPUARMState
*env
)
4030 ARMCPU
*cpu
= env_archcpu(env
);
4031 uint64_t mpidr
= cpu
->mp_affinity
;
4033 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4034 mpidr
|= (1U << 31);
4035 /* Cores which are uniprocessor (non-coherent)
4036 * but still implement the MP extensions set
4037 * bit 30. (For instance, Cortex-R5).
4039 if (cpu
->mp_is_up
) {
4040 mpidr
|= (1u << 30);
4046 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4048 unsigned int cur_el
= arm_current_el(env
);
4050 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4051 return env
->cp15
.vmpidr_el2
;
4053 return mpidr_read_val(env
);
4056 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4058 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4059 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4060 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4061 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4062 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4063 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4064 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4065 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4066 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4067 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4068 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4069 offsetof(CPUARMState
, cp15
.par_ns
)} },
4070 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4071 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4072 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4073 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4074 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4075 .writefn
= vmsa_ttbr_write
, },
4076 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4077 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4078 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4079 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4080 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4081 .writefn
= vmsa_ttbr_write
, },
4084 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4086 return vfp_get_fpcr(env
);
4089 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4092 vfp_set_fpcr(env
, value
);
4095 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4097 return vfp_get_fpsr(env
);
4100 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4103 vfp_set_fpsr(env
, value
);
4106 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4109 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4110 return CP_ACCESS_TRAP
;
4112 return CP_ACCESS_OK
;
4115 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4118 env
->daif
= value
& PSTATE_DAIF
;
4121 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4123 return env
->pstate
& PSTATE_PAN
;
4126 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4129 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4132 static const ARMCPRegInfo pan_reginfo
= {
4133 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4134 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4135 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4136 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4139 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4141 return env
->pstate
& PSTATE_UAO
;
4144 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4147 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4150 static const ARMCPRegInfo uao_reginfo
= {
4151 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4152 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4153 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4154 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4157 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4159 return env
->pstate
& PSTATE_DIT
;
4162 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4165 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4168 static const ARMCPRegInfo dit_reginfo
= {
4169 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4170 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4171 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4172 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4175 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4177 return env
->pstate
& PSTATE_SSBS
;
4180 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4183 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4186 static const ARMCPRegInfo ssbs_reginfo
= {
4187 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4188 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4189 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4190 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4193 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4194 const ARMCPRegInfo
*ri
,
4197 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4198 switch (arm_current_el(env
)) {
4200 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4201 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4202 return CP_ACCESS_TRAP
;
4206 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4207 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4208 return CP_ACCESS_TRAP_EL2
;
4212 return CP_ACCESS_OK
;
4215 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4216 const ARMCPRegInfo
*ri
,
4219 /* Cache invalidate/clean to Point of Unification... */
4220 switch (arm_current_el(env
)) {
4222 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4223 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4224 return CP_ACCESS_TRAP
;
4228 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4229 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4230 return CP_ACCESS_TRAP_EL2
;
4234 return CP_ACCESS_OK
;
4237 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4238 * Page D4-1736 (DDI0487A.b)
4241 static int vae1_tlbmask(CPUARMState
*env
)
4243 uint64_t hcr
= arm_hcr_el2_eff(env
);
4246 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4247 mask
= ARMMMUIdxBit_E20_2
|
4248 ARMMMUIdxBit_E20_2_PAN
|
4251 mask
= ARMMMUIdxBit_E10_1
|
4252 ARMMMUIdxBit_E10_1_PAN
|
4256 if (arm_is_secure_below_el3(env
)) {
4257 mask
>>= ARM_MMU_IDX_A_NS
;
4263 /* Return 56 if TBI is enabled, 64 otherwise. */
4264 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4267 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4268 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4269 int select
= extract64(addr
, 55, 1);
4271 return (tbi
>> select
) & 1 ? 56 : 64;
4274 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4276 uint64_t hcr
= arm_hcr_el2_eff(env
);
4279 /* Only the regime of the mmu_idx below is significant. */
4280 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4281 mmu_idx
= ARMMMUIdx_E20_0
;
4283 mmu_idx
= ARMMMUIdx_E10_0
;
4286 if (arm_is_secure_below_el3(env
)) {
4287 mmu_idx
&= ~ARM_MMU_IDX_A_NS
;
4290 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4293 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4296 CPUState
*cs
= env_cpu(env
);
4297 int mask
= vae1_tlbmask(env
);
4299 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4302 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4305 CPUState
*cs
= env_cpu(env
);
4306 int mask
= vae1_tlbmask(env
);
4308 if (tlb_force_broadcast(env
)) {
4309 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4311 tlb_flush_by_mmuidx(cs
, mask
);
4315 static int alle1_tlbmask(CPUARMState
*env
)
4318 * Note that the 'ALL' scope must invalidate both stage 1 and
4319 * stage 2 translations, whereas most other scopes only invalidate
4320 * stage 1 translations.
4322 if (arm_is_secure_below_el3(env
)) {
4323 return ARMMMUIdxBit_SE10_1
|
4324 ARMMMUIdxBit_SE10_1_PAN
|
4325 ARMMMUIdxBit_SE10_0
;
4327 return ARMMMUIdxBit_E10_1
|
4328 ARMMMUIdxBit_E10_1_PAN
|
4333 static int e2_tlbmask(CPUARMState
*env
)
4335 if (arm_is_secure_below_el3(env
)) {
4336 return ARMMMUIdxBit_SE20_0
|
4337 ARMMMUIdxBit_SE20_2
|
4338 ARMMMUIdxBit_SE20_2_PAN
|
4341 return ARMMMUIdxBit_E20_0
|
4342 ARMMMUIdxBit_E20_2
|
4343 ARMMMUIdxBit_E20_2_PAN
|
4348 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4351 CPUState
*cs
= env_cpu(env
);
4352 int mask
= alle1_tlbmask(env
);
4354 tlb_flush_by_mmuidx(cs
, mask
);
4357 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4360 CPUState
*cs
= env_cpu(env
);
4361 int mask
= e2_tlbmask(env
);
4363 tlb_flush_by_mmuidx(cs
, mask
);
4366 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4369 ARMCPU
*cpu
= env_archcpu(env
);
4370 CPUState
*cs
= CPU(cpu
);
4372 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4375 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4378 CPUState
*cs
= env_cpu(env
);
4379 int mask
= alle1_tlbmask(env
);
4381 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4384 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4387 CPUState
*cs
= env_cpu(env
);
4388 int mask
= e2_tlbmask(env
);
4390 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4393 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4396 CPUState
*cs
= env_cpu(env
);
4398 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4401 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4404 /* Invalidate by VA, EL2
4405 * Currently handles both VAE2 and VALE2, since we don't support
4406 * flush-last-level-only.
4408 CPUState
*cs
= env_cpu(env
);
4409 int mask
= e2_tlbmask(env
);
4410 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4412 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4415 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4418 /* Invalidate by VA, EL3
4419 * Currently handles both VAE3 and VALE3, since we don't support
4420 * flush-last-level-only.
4422 ARMCPU
*cpu
= env_archcpu(env
);
4423 CPUState
*cs
= CPU(cpu
);
4424 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4426 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4429 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4432 CPUState
*cs
= env_cpu(env
);
4433 int mask
= vae1_tlbmask(env
);
4434 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4435 int bits
= vae1_tlbbits(env
, pageaddr
);
4437 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4440 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4443 /* Invalidate by VA, EL1&0 (AArch64 version).
4444 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4445 * since we don't support flush-for-specific-ASID-only or
4446 * flush-last-level-only.
4448 CPUState
*cs
= env_cpu(env
);
4449 int mask
= vae1_tlbmask(env
);
4450 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4451 int bits
= vae1_tlbbits(env
, pageaddr
);
4453 if (tlb_force_broadcast(env
)) {
4454 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4456 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4460 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4463 CPUState
*cs
= env_cpu(env
);
4464 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4465 bool secure
= arm_is_secure_below_el3(env
);
4466 int mask
= secure
? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
;
4467 int bits
= tlbbits_for_regime(env
, secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
,
4470 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4473 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4476 CPUState
*cs
= env_cpu(env
);
4477 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4478 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_SE3
, pageaddr
);
4480 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4481 ARMMMUIdxBit_SE3
, bits
);
4484 #ifdef TARGET_AARCH64
4490 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4493 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4494 /* Extract one bit to represent the va selector in use. */
4495 uint64_t select
= sextract64(value
, 36, 1);
4496 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4497 TLBIRange ret
= { };
4499 page_size_granule
= extract64(value
, 46, 2);
4501 /* The granule encoded in value must match the granule in use. */
4502 if (page_size_granule
!= (param
.using64k
? 3 : param
.using16k
? 2 : 1)) {
4503 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4508 page_shift
= (page_size_granule
- 1) * 2 + 12;
4509 num
= extract64(value
, 39, 5);
4510 scale
= extract64(value
, 44, 2);
4511 exponent
= (5 * scale
) + 1;
4513 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4516 ret
.base
= sextract64(value
, 0, 37);
4518 ret
.base
= extract64(value
, 0, 37);
4522 * With DS=1, BaseADDR is always shifted 16 so that it is able
4523 * to address all 52 va bits. The input address is perforce
4524 * aligned on a 64k boundary regardless of translation granule.
4528 ret
.base
<<= page_shift
;
4533 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4534 int idxmap
, bool synced
)
4536 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4540 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4541 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4544 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4550 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4551 range
.length
, idxmap
, bits
);
4555 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4556 const ARMCPRegInfo
*ri
,
4560 * Invalidate by VA range, EL1&0.
4561 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4562 * since we don't support flush-for-specific-ASID-only or
4563 * flush-last-level-only.
4566 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4567 tlb_force_broadcast(env
));
4570 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4571 const ARMCPRegInfo
*ri
,
4575 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4576 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4577 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4578 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4579 * shareable specific flushes.
4582 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4585 static int vae2_tlbmask(CPUARMState
*env
)
4587 return (arm_is_secure_below_el3(env
)
4588 ? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
);
4591 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
4592 const ARMCPRegInfo
*ri
,
4596 * Invalidate by VA range, EL2.
4597 * Currently handles all of RVAE2 and RVALE2,
4598 * since we don't support flush-for-specific-ASID-only or
4599 * flush-last-level-only.
4602 do_rvae_write(env
, value
, vae2_tlbmask(env
),
4603 tlb_force_broadcast(env
));
4608 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
4609 const ARMCPRegInfo
*ri
,
4613 * Invalidate by VA range, Inner/Outer Shareable, EL2.
4614 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
4615 * since we don't support flush-for-specific-ASID-only,
4616 * flush-last-level-only or inner/outer shareable specific flushes.
4619 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
4623 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
4624 const ARMCPRegInfo
*ri
,
4628 * Invalidate by VA range, EL3.
4629 * Currently handles all of RVAE3 and RVALE3,
4630 * since we don't support flush-for-specific-ASID-only or
4631 * flush-last-level-only.
4634 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
,
4635 tlb_force_broadcast(env
));
4638 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
4639 const ARMCPRegInfo
*ri
,
4643 * Invalidate by VA range, EL3, Inner/Outer Shareable.
4644 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
4645 * since we don't support flush-for-specific-ASID-only,
4646 * flush-last-level-only or inner/outer specific flushes.
4649 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
, true);
4653 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4656 int cur_el
= arm_current_el(env
);
4659 uint64_t hcr
= arm_hcr_el2_eff(env
);
4662 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4663 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4664 return CP_ACCESS_TRAP_EL2
;
4667 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4668 return CP_ACCESS_TRAP
;
4670 if (hcr
& HCR_TDZ
) {
4671 return CP_ACCESS_TRAP_EL2
;
4674 } else if (hcr
& HCR_TDZ
) {
4675 return CP_ACCESS_TRAP_EL2
;
4678 return CP_ACCESS_OK
;
4681 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4683 ARMCPU
*cpu
= env_archcpu(env
);
4684 int dzp_bit
= 1 << 4;
4686 /* DZP indicates whether DC ZVA access is allowed */
4687 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4690 return cpu
->dcz_blocksize
| dzp_bit
;
4693 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4696 if (!(env
->pstate
& PSTATE_SP
)) {
4697 /* Access to SP_EL0 is undefined if it's being used as
4698 * the stack pointer.
4700 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4702 return CP_ACCESS_OK
;
4705 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4707 return env
->pstate
& PSTATE_SP
;
4710 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4712 update_spsel(env
, val
);
4715 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4718 ARMCPU
*cpu
= env_archcpu(env
);
4720 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4721 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4725 /* ??? Lots of these bits are not implemented. */
4727 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
4728 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
4729 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
4731 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
4732 SCTLR_ATA0
| SCTLR_ATA
);
4736 if (raw_read(env
, ri
) == value
) {
4737 /* Skip the TLB flush if nothing actually changed; Linux likes
4738 * to do a lot of pointless SCTLR writes.
4743 raw_write(env
, ri
, value
);
4745 /* This may enable/disable the MMU, so do a TLB flush. */
4746 tlb_flush(CPU(cpu
));
4748 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4750 * Normally we would always end the TB on an SCTLR write; see the
4751 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4752 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4753 * of hflags from the translator, so do it here.
4755 arm_rebuild_hflags(env
);
4759 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4763 * Some MDCR_EL3 bits affect whether PMU counters are running:
4764 * if we are trying to change any of those then we must
4765 * bracket this update with PMU start/finish calls.
4767 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
4772 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4778 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4782 * Some MDCR_EL2 bits affect whether PMU counters are running:
4783 * if we are trying to change any of those then we must
4784 * bracket this update with PMU start/finish calls.
4786 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
4791 env
->cp15
.mdcr_el2
= value
;
4797 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4798 /* Minimal set of EL0-visible registers. This will need to be expanded
4799 * significantly for system emulation of AArch64 CPUs.
4801 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4802 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4803 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4804 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4805 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4806 .type
= ARM_CP_NO_RAW
,
4807 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4808 .fieldoffset
= offsetof(CPUARMState
, daif
),
4809 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4810 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4811 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4812 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4813 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4814 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4815 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4816 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4817 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4818 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4819 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4820 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4821 .readfn
= aa64_dczid_read
},
4822 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4823 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4824 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4825 #ifndef CONFIG_USER_ONLY
4826 /* Avoid overhead of an access check that always passes in user-mode */
4827 .accessfn
= aa64_zva_access
,
4830 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4831 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4832 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4833 /* Cache ops: all NOPs since we don't emulate caches */
4834 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4835 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4836 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4837 .accessfn
= aa64_cacheop_pou_access
},
4838 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4839 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4840 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4841 .accessfn
= aa64_cacheop_pou_access
},
4842 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4843 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4844 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4845 .accessfn
= aa64_cacheop_pou_access
},
4846 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4847 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4848 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
4849 .type
= ARM_CP_NOP
},
4850 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4851 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4852 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4853 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4854 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4855 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4856 .accessfn
= aa64_cacheop_poc_access
},
4857 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4858 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4859 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4860 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4861 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4862 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4863 .accessfn
= aa64_cacheop_pou_access
},
4864 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4865 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4866 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4867 .accessfn
= aa64_cacheop_poc_access
},
4868 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4869 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4870 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4871 /* TLBI operations */
4872 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4873 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4874 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4875 .writefn
= tlbi_aa64_vmalle1is_write
},
4876 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4877 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4878 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4879 .writefn
= tlbi_aa64_vae1is_write
},
4880 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4881 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4882 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4883 .writefn
= tlbi_aa64_vmalle1is_write
},
4884 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4885 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4886 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4887 .writefn
= tlbi_aa64_vae1is_write
},
4888 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4889 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4890 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4891 .writefn
= tlbi_aa64_vae1is_write
},
4892 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4893 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4894 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4895 .writefn
= tlbi_aa64_vae1is_write
},
4896 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4897 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4898 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4899 .writefn
= tlbi_aa64_vmalle1_write
},
4900 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4901 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4902 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4903 .writefn
= tlbi_aa64_vae1_write
},
4904 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4905 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4906 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4907 .writefn
= tlbi_aa64_vmalle1_write
},
4908 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4909 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4910 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4911 .writefn
= tlbi_aa64_vae1_write
},
4912 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4913 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4914 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4915 .writefn
= tlbi_aa64_vae1_write
},
4916 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4917 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4918 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4919 .writefn
= tlbi_aa64_vae1_write
},
4920 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4921 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4922 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4923 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4924 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4925 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4926 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4927 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4928 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4929 .writefn
= tlbi_aa64_alle1is_write
},
4930 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4931 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4932 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4933 .writefn
= tlbi_aa64_alle1is_write
},
4934 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4935 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4936 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4937 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4938 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4939 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4940 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4941 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4942 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4943 .writefn
= tlbi_aa64_alle1_write
},
4944 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4945 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4946 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4947 .writefn
= tlbi_aa64_alle1is_write
},
4948 #ifndef CONFIG_USER_ONLY
4949 /* 64 bit address translation operations */
4950 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4951 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4952 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4953 .writefn
= ats_write64
},
4954 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4955 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4956 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4957 .writefn
= ats_write64
},
4958 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4959 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4960 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4961 .writefn
= ats_write64
},
4962 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4963 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4964 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4965 .writefn
= ats_write64
},
4966 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4967 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4968 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4969 .writefn
= ats_write64
},
4970 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4971 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4972 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4973 .writefn
= ats_write64
},
4974 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4975 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4976 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4977 .writefn
= ats_write64
},
4978 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4979 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4980 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4981 .writefn
= ats_write64
},
4982 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4983 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4984 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4985 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4986 .writefn
= ats_write64
},
4987 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4988 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4989 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4990 .writefn
= ats_write64
},
4991 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4992 .type
= ARM_CP_ALIAS
,
4993 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4994 .access
= PL1_RW
, .resetvalue
= 0,
4995 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4996 .writefn
= par_write
},
4998 /* TLB invalidate last level of translation table walk */
4999 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5000 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5001 .writefn
= tlbimva_is_write
},
5002 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5003 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5004 .writefn
= tlbimvaa_is_write
},
5005 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5006 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5007 .writefn
= tlbimva_write
},
5008 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5009 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5010 .writefn
= tlbimvaa_write
},
5011 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5012 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5013 .writefn
= tlbimva_hyp_write
},
5014 { .name
= "TLBIMVALHIS",
5015 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5016 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5017 .writefn
= tlbimva_hyp_is_write
},
5018 { .name
= "TLBIIPAS2",
5019 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5020 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5021 { .name
= "TLBIIPAS2IS",
5022 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5023 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5024 { .name
= "TLBIIPAS2L",
5025 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5026 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5027 { .name
= "TLBIIPAS2LIS",
5028 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5029 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5030 /* 32 bit cache operations */
5031 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5032 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5033 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5034 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5035 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5036 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5037 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5038 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5039 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5040 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5041 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5042 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5043 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5044 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5045 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5046 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5047 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5048 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5049 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5050 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5051 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5052 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5053 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5054 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5055 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5056 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5057 /* MMU Domain access control / MPU write buffer control */
5058 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5059 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5060 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5061 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5062 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5063 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5064 .type
= ARM_CP_ALIAS
,
5065 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5067 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5068 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5069 .type
= ARM_CP_ALIAS
,
5070 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5072 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5073 /* We rely on the access checks not allowing the guest to write to the
5074 * state field when SPSel indicates that it's being used as the stack
5077 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5078 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5079 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5080 .type
= ARM_CP_ALIAS
,
5081 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5082 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5083 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5084 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5085 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5086 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5087 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5088 .type
= ARM_CP_NO_RAW
,
5089 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5090 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5091 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5093 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5094 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5095 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5096 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5097 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5098 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5099 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5100 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5101 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5102 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5103 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5104 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5105 .type
= ARM_CP_ALIAS
,
5106 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5108 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5109 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5110 .type
= ARM_CP_ALIAS
,
5111 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5113 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5114 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5115 .type
= ARM_CP_ALIAS
,
5116 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5118 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5119 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5120 .type
= ARM_CP_ALIAS
,
5121 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5123 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5124 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5125 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5127 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5128 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5129 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5130 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5131 .writefn
= sdcr_write
,
5132 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5135 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5137 ARMCPU
*cpu
= env_archcpu(env
);
5139 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5140 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5142 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5145 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5146 valid_mask
&= ~HCR_HCD
;
5147 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5148 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5149 * However, if we're using the SMC PSCI conduit then QEMU is
5150 * effectively acting like EL3 firmware and so the guest at
5151 * EL2 should retain the ability to prevent EL1 from being
5152 * able to make SMC calls into the ersatz firmware, so in
5153 * that case HCR.TSC should be read/write.
5155 valid_mask
&= ~HCR_TSC
;
5158 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5159 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5160 valid_mask
|= HCR_E2H
;
5162 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5163 valid_mask
|= HCR_TERR
| HCR_TEA
;
5165 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5166 valid_mask
|= HCR_TLOR
;
5168 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5169 valid_mask
|= HCR_API
| HCR_APK
;
5171 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5172 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5174 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5175 valid_mask
|= HCR_ENSCXT
;
5177 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5178 valid_mask
|= HCR_FWB
;
5182 /* Clear RES0 bits. */
5183 value
&= valid_mask
;
5186 * These bits change the MMU setup:
5187 * HCR_VM enables stage 2 translation
5188 * HCR_PTW forbids certain page-table setups
5189 * HCR_DC disables stage1 and enables stage2 translation
5190 * HCR_DCT enables tagging on (disabled) stage1 translation
5191 * HCR_FWB changes the interpretation of stage2 descriptor bits
5193 if ((env
->cp15
.hcr_el2
^ value
) &
5194 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5195 tlb_flush(CPU(cpu
));
5197 env
->cp15
.hcr_el2
= value
;
5200 * Updates to VI and VF require us to update the status of
5201 * virtual interrupts, which are the logical OR of these bits
5202 * and the state of the input lines from the GIC. (This requires
5203 * that we have the iothread lock, which is done by marking the
5204 * reginfo structs as ARM_CP_IO.)
5205 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5206 * possible for it to be taken immediately, because VIRQ and
5207 * VFIQ are masked unless running at EL0 or EL1, and HCR
5208 * can only be written at EL2.
5210 g_assert(qemu_mutex_iothread_locked());
5211 arm_cpu_update_virq(cpu
);
5212 arm_cpu_update_vfiq(cpu
);
5213 arm_cpu_update_vserr(cpu
);
5216 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5218 do_hcr_write(env
, value
, 0);
5221 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5224 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5225 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5226 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5229 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5232 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5233 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5234 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5238 * Return the effective value of HCR_EL2.
5239 * Bits that are not included here:
5240 * RW (read from SCR_EL3.RW as needed)
5242 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5244 uint64_t ret
= env
->cp15
.hcr_el2
;
5246 if (!arm_is_el2_enabled(env
)) {
5248 * "This register has no effect if EL2 is not enabled in the
5249 * current Security state". This is ARMv8.4-SecEL2 speak for
5250 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5252 * Prior to that, the language was "In an implementation that
5253 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5254 * as if this field is 0 for all purposes other than a direct
5255 * read or write access of HCR_EL2". With lots of enumeration
5256 * on a per-field basis. In current QEMU, this is condition
5257 * is arm_is_secure_below_el3.
5259 * Since the v8.4 language applies to the entire register, and
5260 * appears to be backward compatible, use that.
5266 * For a cpu that supports both aarch64 and aarch32, we can set bits
5267 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5268 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5270 if (!arm_el_is_aa64(env
, 2)) {
5271 uint64_t aa32_valid
;
5274 * These bits are up-to-date as of ARMv8.6.
5275 * For HCR, it's easiest to list just the 2 bits that are invalid.
5276 * For HCR2, list those that are valid.
5278 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5279 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5280 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5284 if (ret
& HCR_TGE
) {
5285 /* These bits are up-to-date as of ARMv8.6. */
5286 if (ret
& HCR_E2H
) {
5287 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5288 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5289 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5290 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5291 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5292 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5294 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5296 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5297 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5298 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5306 * Corresponds to ARM pseudocode function ELIsInHost().
5308 bool el_is_in_host(CPUARMState
*env
, int el
)
5313 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5314 * Perform the simplest bit tests first, and validate EL2 afterward.
5317 return false; /* EL1 or EL3 */
5321 * Note that hcr_write() checks isar_feature_aa64_vh(),
5322 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5324 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5325 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5329 /* TGE and/or E2H set: double check those bits are currently legal. */
5330 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5333 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5336 uint64_t valid_mask
= 0;
5338 /* No features adding bits to HCRX are implemented. */
5340 /* Clear RES0 bits. */
5341 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5344 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5347 if (arm_current_el(env
) < 3
5348 && arm_feature(env
, ARM_FEATURE_EL3
)
5349 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5350 return CP_ACCESS_TRAP_EL3
;
5352 return CP_ACCESS_OK
;
5355 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5356 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5357 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5358 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5359 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5362 /* Return the effective value of HCRX_EL2. */
5363 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5366 * The bits in this register behave as 0 for all purposes other than
5367 * direct reads of the register if:
5368 * - EL2 is not enabled in the current security state,
5369 * - SCR_EL3.HXEn is 0.
5371 if (!arm_is_el2_enabled(env
)
5372 || (arm_feature(env
, ARM_FEATURE_EL3
)
5373 && !(env
->cp15
.scr_el3
& SCR_HXEN
))) {
5376 return env
->cp15
.hcrx_el2
;
5379 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5383 * For A-profile AArch32 EL3, if NSACR.CP10
5384 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5386 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5387 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5388 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5389 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
5391 env
->cp15
.cptr_el
[2] = value
;
5394 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5397 * For A-profile AArch32 EL3, if NSACR.CP10
5398 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5400 uint64_t value
= env
->cp15
.cptr_el
[2];
5402 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5403 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5404 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5409 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5410 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5412 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5413 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5414 .writefn
= hcr_write
},
5415 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5416 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5417 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5418 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5419 .writefn
= hcr_writelow
},
5420 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5421 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5422 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5423 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5424 .type
= ARM_CP_ALIAS
,
5425 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5427 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5428 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5429 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5430 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5431 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5432 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5433 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5434 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5435 .type
= ARM_CP_ALIAS
,
5436 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5438 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5439 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5440 .type
= ARM_CP_ALIAS
,
5441 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5443 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5444 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5445 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5446 .access
= PL2_RW
, .writefn
= vbar_write
,
5447 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5449 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5450 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5451 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5452 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5453 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5454 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5455 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5456 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5457 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5458 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5459 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5460 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5462 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5463 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5464 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5465 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5466 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5467 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5468 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5470 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5471 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5472 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5473 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5475 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5476 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5477 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5479 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5480 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5481 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5483 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5484 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5485 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5486 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5487 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5488 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5489 .type
= ARM_CP_ALIAS
,
5490 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5491 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
5492 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5493 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5495 /* no .writefn needed as this can't cause an ASID change */
5496 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5497 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5498 .cp
= 15, .opc1
= 6, .crm
= 2,
5499 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5500 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5501 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5502 .writefn
= vttbr_write
},
5503 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5504 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5505 .access
= PL2_RW
, .writefn
= vttbr_write
,
5506 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5507 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5508 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5509 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5510 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5511 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5512 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5513 .access
= PL2_RW
, .resetvalue
= 0,
5514 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5515 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5516 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5517 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5518 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5519 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5520 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5521 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5522 { .name
= "TLBIALLNSNH",
5523 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5524 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5525 .writefn
= tlbiall_nsnh_write
},
5526 { .name
= "TLBIALLNSNHIS",
5527 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5528 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5529 .writefn
= tlbiall_nsnh_is_write
},
5530 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5531 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5532 .writefn
= tlbiall_hyp_write
},
5533 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5534 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5535 .writefn
= tlbiall_hyp_is_write
},
5536 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5537 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5538 .writefn
= tlbimva_hyp_write
},
5539 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5540 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5541 .writefn
= tlbimva_hyp_is_write
},
5542 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5543 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5544 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5545 .writefn
= tlbi_aa64_alle2_write
},
5546 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5547 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5548 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5549 .writefn
= tlbi_aa64_vae2_write
},
5550 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5551 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5552 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5553 .writefn
= tlbi_aa64_vae2_write
},
5554 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5555 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5556 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5557 .writefn
= tlbi_aa64_alle2is_write
},
5558 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5559 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5560 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5561 .writefn
= tlbi_aa64_vae2is_write
},
5562 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5563 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5564 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5565 .writefn
= tlbi_aa64_vae2is_write
},
5566 #ifndef CONFIG_USER_ONLY
5567 /* Unlike the other EL2-related AT operations, these must
5568 * UNDEF from EL3 if EL2 is not implemented, which is why we
5569 * define them here rather than with the rest of the AT ops.
5571 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5572 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5573 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5574 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5575 .writefn
= ats_write64
},
5576 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5577 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5578 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5579 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5580 .writefn
= ats_write64
},
5581 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5582 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5583 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5584 * to behave as if SCR.NS was 1.
5586 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5588 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5589 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5591 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5592 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5593 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5594 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5595 * reset values as IMPDEF. We choose to reset to 3 to comply with
5596 * both ARMv7 and ARMv8.
5598 .access
= PL2_RW
, .resetvalue
= 3,
5599 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5600 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5601 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5602 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5603 .writefn
= gt_cntvoff_write
,
5604 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5605 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5606 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5607 .writefn
= gt_cntvoff_write
,
5608 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5609 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5610 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5611 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5612 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5613 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5614 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5615 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5616 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5617 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5618 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5619 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5620 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5621 .resetfn
= gt_hyp_timer_reset
,
5622 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5623 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5625 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5627 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5629 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5631 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5632 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5633 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5634 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5635 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5636 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5638 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5639 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5640 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5642 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5645 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5646 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5647 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5648 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5650 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5651 .writefn
= hcr_writehigh
},
5654 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5657 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
5658 return CP_ACCESS_OK
;
5660 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5663 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
5664 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5665 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
5666 .access
= PL2_RW
, .accessfn
= sel2_access
,
5667 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
5668 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5669 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
5670 .access
= PL2_RW
, .accessfn
= sel2_access
,
5671 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
5674 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5677 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5678 * At Secure EL1 it traps to EL3 or EL2.
5680 if (arm_current_el(env
) == 3) {
5681 return CP_ACCESS_OK
;
5683 if (arm_is_secure_below_el3(env
)) {
5684 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
5685 return CP_ACCESS_TRAP_EL2
;
5687 return CP_ACCESS_TRAP_EL3
;
5689 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5691 return CP_ACCESS_OK
;
5693 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5696 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5697 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5698 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5699 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5700 .resetfn
= scr_reset
, .writefn
= scr_write
},
5701 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5702 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5703 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5704 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5705 .writefn
= scr_write
},
5706 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5707 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5708 .access
= PL3_RW
, .resetvalue
= 0,
5709 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5711 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5712 .access
= PL3_RW
, .resetvalue
= 0,
5713 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5714 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5715 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5716 .writefn
= vbar_write
, .resetvalue
= 0,
5717 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5718 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5719 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5720 .access
= PL3_RW
, .resetvalue
= 0,
5721 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5722 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5723 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5725 /* no .writefn needed as this can't cause an ASID change */
5727 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5728 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5729 .type
= ARM_CP_ALIAS
,
5730 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5732 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5733 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5734 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5735 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5736 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5737 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5738 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5739 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5740 .type
= ARM_CP_ALIAS
,
5741 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5743 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5744 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5745 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5746 .access
= PL3_RW
, .writefn
= vbar_write
,
5747 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5749 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5750 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5751 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5752 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5753 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5754 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5755 .access
= PL3_RW
, .resetvalue
= 0,
5756 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5757 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5758 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5759 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5761 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5762 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5763 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5765 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5766 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5767 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5769 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5770 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5771 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5772 .writefn
= tlbi_aa64_alle3is_write
},
5773 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5774 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5775 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5776 .writefn
= tlbi_aa64_vae3is_write
},
5777 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5778 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5779 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5780 .writefn
= tlbi_aa64_vae3is_write
},
5781 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5782 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5783 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5784 .writefn
= tlbi_aa64_alle3_write
},
5785 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5786 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5787 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5788 .writefn
= tlbi_aa64_vae3_write
},
5789 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5790 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5791 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5792 .writefn
= tlbi_aa64_vae3_write
},
5795 #ifndef CONFIG_USER_ONLY
5796 /* Test if system register redirection is to occur in the current state. */
5797 static bool redirect_for_e2h(CPUARMState
*env
)
5799 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5802 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5806 if (redirect_for_e2h(env
)) {
5807 /* Switch to the saved EL2 version of the register. */
5809 readfn
= ri
->readfn
;
5811 readfn
= ri
->orig_readfn
;
5813 if (readfn
== NULL
) {
5816 return readfn(env
, ri
);
5819 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5824 if (redirect_for_e2h(env
)) {
5825 /* Switch to the saved EL2 version of the register. */
5827 writefn
= ri
->writefn
;
5829 writefn
= ri
->orig_writefn
;
5831 if (writefn
== NULL
) {
5832 writefn
= raw_write
;
5834 writefn(env
, ri
, value
);
5837 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5840 uint32_t src_key
, dst_key
, new_key
;
5841 const char *src_name
, *dst_name
, *new_name
;
5842 bool (*feature
)(const ARMISARegisters
*id
);
5845 #define K(op0, op1, crn, crm, op2) \
5846 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5848 static const struct E2HAlias aliases
[] = {
5849 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5850 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5851 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5852 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5853 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5854 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5855 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5856 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5857 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5858 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5859 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5860 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5861 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5862 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5863 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5864 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5865 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5866 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5867 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5868 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5869 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5870 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5871 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5872 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5873 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5874 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5875 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5876 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5877 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5878 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5879 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5880 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5883 * Note that redirection of ZCR is mentioned in the description
5884 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5885 * not in the summary table.
5887 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5888 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5889 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
5890 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
5892 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5893 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
5895 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
5896 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
5897 isar_feature_aa64_scxtnum
},
5899 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5900 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5906 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5907 const struct E2HAlias
*a
= &aliases
[i
];
5908 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
5911 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5915 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5916 (gpointer
)(uintptr_t)a
->src_key
);
5917 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5918 (gpointer
)(uintptr_t)a
->dst_key
);
5919 g_assert(src_reg
!= NULL
);
5920 g_assert(dst_reg
!= NULL
);
5922 /* Cross-compare names to detect typos in the keys. */
5923 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5924 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5926 /* None of the core system registers use opaque; we will. */
5927 g_assert(src_reg
->opaque
== NULL
);
5929 /* Create alias before redirection so we dup the right data. */
5930 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5932 new_reg
->name
= a
->new_name
;
5933 new_reg
->type
|= ARM_CP_ALIAS
;
5934 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5935 new_reg
->access
&= PL2_RW
| PL3_RW
;
5937 ok
= g_hash_table_insert(cpu
->cp_regs
,
5938 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
5941 src_reg
->opaque
= dst_reg
;
5942 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5943 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5944 if (!src_reg
->raw_readfn
) {
5945 src_reg
->raw_readfn
= raw_read
;
5947 if (!src_reg
->raw_writefn
) {
5948 src_reg
->raw_writefn
= raw_write
;
5950 src_reg
->readfn
= el2_e2h_read
;
5951 src_reg
->writefn
= el2_e2h_write
;
5956 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5959 int cur_el
= arm_current_el(env
);
5962 uint64_t hcr
= arm_hcr_el2_eff(env
);
5965 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5966 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5967 return CP_ACCESS_TRAP_EL2
;
5970 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5971 return CP_ACCESS_TRAP
;
5973 if (hcr
& HCR_TID2
) {
5974 return CP_ACCESS_TRAP_EL2
;
5977 } else if (hcr
& HCR_TID2
) {
5978 return CP_ACCESS_TRAP_EL2
;
5982 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5983 return CP_ACCESS_TRAP_EL2
;
5986 return CP_ACCESS_OK
;
5990 * Check for traps to RAS registers, which are controlled
5991 * by HCR_EL2.TERR and SCR_EL3.TERR.
5993 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5996 int el
= arm_current_el(env
);
5998 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
5999 return CP_ACCESS_TRAP_EL2
;
6001 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6002 return CP_ACCESS_TRAP_EL3
;
6004 return CP_ACCESS_OK
;
6007 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6009 int el
= arm_current_el(env
);
6011 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6012 return env
->cp15
.vdisr_el2
;
6014 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6015 return 0; /* RAZ/WI */
6017 return env
->cp15
.disr_el1
;
6020 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6022 int el
= arm_current_el(env
);
6024 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6025 env
->cp15
.vdisr_el2
= val
;
6028 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6029 return; /* RAZ/WI */
6031 env
->cp15
.disr_el1
= val
;
6035 * Minimal RAS implementation with no Error Records.
6036 * Which means that all of the Error Record registers:
6044 * ERXPFGCDN_EL1 (RASv1p1)
6045 * ERXPFGCTL_EL1 (RASv1p1)
6046 * ERXPFGF_EL1 (RASv1p1)
6050 * may generate UNDEFINED, which is the effect we get by not
6051 * listing them at all.
6053 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6054 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6055 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6056 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6057 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6058 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6059 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6060 .access
= PL1_R
, .accessfn
= access_terr
,
6061 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6062 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6063 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6064 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6065 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6066 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6067 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6071 * Return the exception level to which exceptions should be taken
6072 * via SVEAccessTrap. This excludes the check for whether the exception
6073 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6074 * be found by testing 0 < fp_exception_el < sve_exception_el.
6076 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6077 * pseudocode does *not* separate out the FP trap checks, but has them
6078 * all in one function.
6080 int sve_exception_el(CPUARMState
*env
, int el
)
6082 #ifndef CONFIG_USER_ONLY
6083 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6084 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6096 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6097 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6098 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6099 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6101 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6110 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6116 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6117 if (arm_feature(env
, ARM_FEATURE_EL3
)
6118 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6126 * Return the exception level to which exceptions should be taken for SME.
6127 * C.f. the ARM pseudocode function CheckSMEAccess.
6129 int sme_exception_el(CPUARMState
*env
, int el
)
6131 #ifndef CONFIG_USER_ONLY
6132 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6133 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6145 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6146 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6147 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6148 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6150 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6159 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6165 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6166 if (arm_feature(env
, ARM_FEATURE_EL3
)
6167 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6174 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
6175 static bool sme_fa64(CPUARMState
*env
, int el
)
6177 if (!cpu_isar_feature(aa64_sme_fa64
, env_archcpu(env
))) {
6181 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6182 if (!FIELD_EX64(env
->vfp
.smcr_el
[1], SMCR
, FA64
)) {
6186 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6187 if (!FIELD_EX64(env
->vfp
.smcr_el
[2], SMCR
, FA64
)) {
6191 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6192 if (!FIELD_EX64(env
->vfp
.smcr_el
[3], SMCR
, FA64
)) {
6201 * Given that SVE is enabled, return the vector length for EL.
6203 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6205 ARMCPU
*cpu
= env_archcpu(env
);
6206 uint64_t *cr
= env
->vfp
.zcr_el
;
6207 uint32_t map
= cpu
->sve_vq
.map
;
6208 uint32_t len
= ARM_MAX_VQ
- 1;
6211 cr
= env
->vfp
.smcr_el
;
6212 map
= cpu
->sme_vq
.map
;
6215 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6216 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6218 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6219 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6221 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6222 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6225 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6227 return 31 - clz32(map
);
6230 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6232 return ctz32(cpu
->sme_vq
.map
);
6235 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6237 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6240 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6243 int cur_el
= arm_current_el(env
);
6244 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6247 /* Bits other than [3:0] are RAZ/WI. */
6248 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6249 raw_write(env
, ri
, value
& 0xf);
6252 * Because we arrived here, we know both FP and SVE are enabled;
6253 * otherwise we would have trapped access to the ZCR_ELn register.
6255 new_len
= sve_vqm1_for_el(env
, cur_el
);
6256 if (new_len
< old_len
) {
6257 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6261 static const ARMCPRegInfo zcr_reginfo
[] = {
6262 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6263 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6264 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6265 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6266 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6267 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6268 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6269 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6270 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6271 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6272 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6273 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6274 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6275 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6276 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6279 #ifdef TARGET_AARCH64
6280 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6283 int el
= arm_current_el(env
);
6286 uint64_t sctlr
= arm_sctlr(env
, el
);
6287 if (!(sctlr
& SCTLR_EnTP2
)) {
6288 return CP_ACCESS_TRAP
;
6291 /* TODO: FEAT_FGT */
6293 && arm_feature(env
, ARM_FEATURE_EL3
)
6294 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6295 return CP_ACCESS_TRAP_EL3
;
6297 return CP_ACCESS_OK
;
6300 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6303 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
6304 if (arm_current_el(env
) < 3
6305 && arm_feature(env
, ARM_FEATURE_EL3
)
6306 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6307 return CP_ACCESS_TRAP_EL3
;
6309 return CP_ACCESS_OK
;
6312 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6315 helper_set_pstate_sm(env
, FIELD_EX64(value
, SVCR
, SM
));
6316 helper_set_pstate_za(env
, FIELD_EX64(value
, SVCR
, ZA
));
6317 arm_rebuild_hflags(env
);
6320 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6323 int cur_el
= arm_current_el(env
);
6324 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6327 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
6328 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
6329 raw_write(env
, ri
, value
);
6332 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
6333 * when SVL is widened (old values kept, or zeros). Choose to keep the
6334 * current values for simplicity. But for QEMU internals, we must still
6335 * apply the narrower SVL to the Zregs and Pregs -- see the comment
6336 * above aarch64_sve_narrow_vq.
6338 new_len
= sve_vqm1_for_el(env
, cur_el
);
6339 if (new_len
< old_len
) {
6340 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6344 static const ARMCPRegInfo sme_reginfo
[] = {
6345 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
6346 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
6347 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
6348 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
6349 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
6350 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
6351 .access
= PL0_RW
, .type
= ARM_CP_SME
,
6352 .fieldoffset
= offsetof(CPUARMState
, svcr
),
6353 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
6354 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
6355 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
6356 .access
= PL1_RW
, .type
= ARM_CP_SME
,
6357 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
6358 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6359 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
6360 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
6361 .access
= PL2_RW
, .type
= ARM_CP_SME
,
6362 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
6363 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6364 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
6365 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
6366 .access
= PL3_RW
, .type
= ARM_CP_SME
,
6367 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
6368 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
6369 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
6370 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
6371 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
6373 * IMPLEMENTOR = 0 (software)
6374 * REVISION = 0 (implementation defined)
6375 * SMPS = 0 (no streaming execution priority in QEMU)
6376 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
6378 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
6380 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
6382 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
6383 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
6384 .access
= PL1_RW
, .accessfn
= access_esm
,
6385 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6386 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
6387 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
6388 .access
= PL2_RW
, .accessfn
= access_esm
,
6389 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6391 #endif /* TARGET_AARCH64 */
6393 static void define_pmu_regs(ARMCPU
*cpu
)
6396 * v7 performance monitor control register: same implementor
6397 * field as main ID register, and we implement four counters in
6398 * addition to the cycle count register.
6400 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
6401 ARMCPRegInfo pmcr
= {
6402 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6404 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6405 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6406 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6407 .raw_writefn
= raw_write
,
6409 ARMCPRegInfo pmcr64
= {
6410 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6411 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6412 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6414 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6415 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
6416 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6419 define_one_arm_cp_reg(cpu
, &pmcr
);
6420 define_one_arm_cp_reg(cpu
, &pmcr64
);
6421 for (i
= 0; i
< pmcrn
; i
++) {
6422 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6423 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6424 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6425 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6426 ARMCPRegInfo pmev_regs
[] = {
6427 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6428 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6429 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6430 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6431 .accessfn
= pmreg_access_xevcntr
},
6432 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6433 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6434 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6436 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6437 .raw_readfn
= pmevcntr_rawread
,
6438 .raw_writefn
= pmevcntr_rawwrite
},
6439 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6440 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6441 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6442 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6443 .accessfn
= pmreg_access
},
6444 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6445 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6446 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6448 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6449 .raw_writefn
= pmevtyper_rawwrite
},
6451 define_arm_cp_regs(cpu
, pmev_regs
);
6452 g_free(pmevcntr_name
);
6453 g_free(pmevcntr_el0_name
);
6454 g_free(pmevtyper_name
);
6455 g_free(pmevtyper_el0_name
);
6457 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
6458 ARMCPRegInfo v81_pmu_regs
[] = {
6459 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6460 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6461 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6462 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6463 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6464 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6465 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6466 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6468 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6470 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
6471 static const ARMCPRegInfo v84_pmmir
= {
6472 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6473 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6474 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6477 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6481 /* We don't know until after realize whether there's a GICv3
6482 * attached, and that is what registers the gicv3 sysregs.
6483 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6486 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6488 ARMCPU
*cpu
= env_archcpu(env
);
6489 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6491 if (env
->gicv3state
) {
6497 #ifndef CONFIG_USER_ONLY
6498 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6500 ARMCPU
*cpu
= env_archcpu(env
);
6501 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6503 if (env
->gicv3state
) {
6510 /* Shared logic between LORID and the rest of the LOR* registers.
6511 * Secure state exclusion has already been dealt with.
6513 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6514 const ARMCPRegInfo
*ri
, bool isread
)
6516 int el
= arm_current_el(env
);
6518 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6519 return CP_ACCESS_TRAP_EL2
;
6521 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6522 return CP_ACCESS_TRAP_EL3
;
6524 return CP_ACCESS_OK
;
6527 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6528 const ARMCPRegInfo
*ri
, bool isread
)
6530 if (arm_is_secure_below_el3(env
)) {
6531 /* Access denied in secure mode. */
6532 return CP_ACCESS_TRAP
;
6534 return access_lor_ns(env
, ri
, isread
);
6538 * A trivial implementation of ARMv8.1-LOR leaves all of these
6539 * registers fixed at 0, which indicates that there are zero
6540 * supported Limited Ordering regions.
6542 static const ARMCPRegInfo lor_reginfo
[] = {
6543 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6544 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6545 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6546 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6547 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6548 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6549 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6550 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6551 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6552 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6553 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6554 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6555 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6556 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6557 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6558 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6559 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6560 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6561 .access
= PL1_R
, .accessfn
= access_lor_ns
,
6562 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6565 #ifdef TARGET_AARCH64
6566 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6569 int el
= arm_current_el(env
);
6572 arm_is_el2_enabled(env
) &&
6573 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6574 return CP_ACCESS_TRAP_EL2
;
6577 arm_feature(env
, ARM_FEATURE_EL3
) &&
6578 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6579 return CP_ACCESS_TRAP_EL3
;
6581 return CP_ACCESS_OK
;
6584 static const ARMCPRegInfo pauth_reginfo
[] = {
6585 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6586 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6587 .access
= PL1_RW
, .accessfn
= access_pauth
,
6588 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6589 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6590 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6591 .access
= PL1_RW
, .accessfn
= access_pauth
,
6592 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6593 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6594 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6595 .access
= PL1_RW
, .accessfn
= access_pauth
,
6596 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6597 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6598 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6599 .access
= PL1_RW
, .accessfn
= access_pauth
,
6600 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6601 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6602 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6603 .access
= PL1_RW
, .accessfn
= access_pauth
,
6604 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6605 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6606 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6607 .access
= PL1_RW
, .accessfn
= access_pauth
,
6608 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6609 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6610 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6611 .access
= PL1_RW
, .accessfn
= access_pauth
,
6612 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6613 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6614 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6615 .access
= PL1_RW
, .accessfn
= access_pauth
,
6616 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6617 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6618 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6619 .access
= PL1_RW
, .accessfn
= access_pauth
,
6620 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6621 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6622 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6623 .access
= PL1_RW
, .accessfn
= access_pauth
,
6624 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6627 static const ARMCPRegInfo tlbirange_reginfo
[] = {
6628 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
6629 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
6630 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6631 .writefn
= tlbi_aa64_rvae1is_write
},
6632 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
6633 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
6634 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6635 .writefn
= tlbi_aa64_rvae1is_write
},
6636 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
6637 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
6638 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6639 .writefn
= tlbi_aa64_rvae1is_write
},
6640 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
6641 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
6642 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6643 .writefn
= tlbi_aa64_rvae1is_write
},
6644 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
6645 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
6646 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6647 .writefn
= tlbi_aa64_rvae1is_write
},
6648 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
6649 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
6650 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6651 .writefn
= tlbi_aa64_rvae1is_write
},
6652 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
6653 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
6654 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6655 .writefn
= tlbi_aa64_rvae1is_write
},
6656 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
6657 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
6658 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6659 .writefn
= tlbi_aa64_rvae1is_write
},
6660 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
6661 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
6662 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6663 .writefn
= tlbi_aa64_rvae1_write
},
6664 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
6665 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
6666 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6667 .writefn
= tlbi_aa64_rvae1_write
},
6668 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
6669 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
6670 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6671 .writefn
= tlbi_aa64_rvae1_write
},
6672 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
6673 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
6674 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6675 .writefn
= tlbi_aa64_rvae1_write
},
6676 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
6677 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
6678 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6679 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
6680 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
6681 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6682 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
6683 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
6684 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6685 .writefn
= tlbi_aa64_rvae2is_write
},
6686 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
6687 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
6688 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6689 .writefn
= tlbi_aa64_rvae2is_write
},
6690 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
6691 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
6692 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6693 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
6694 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
6695 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6696 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
6697 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
6698 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6699 .writefn
= tlbi_aa64_rvae2is_write
},
6700 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
6701 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
6702 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6703 .writefn
= tlbi_aa64_rvae2is_write
},
6704 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
6705 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
6706 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6707 .writefn
= tlbi_aa64_rvae2_write
},
6708 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
6709 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
6710 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6711 .writefn
= tlbi_aa64_rvae2_write
},
6712 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
6713 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
6714 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6715 .writefn
= tlbi_aa64_rvae3is_write
},
6716 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
6717 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
6718 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6719 .writefn
= tlbi_aa64_rvae3is_write
},
6720 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
6721 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
6722 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6723 .writefn
= tlbi_aa64_rvae3is_write
},
6724 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
6725 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
6726 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6727 .writefn
= tlbi_aa64_rvae3is_write
},
6728 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
6729 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
6730 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6731 .writefn
= tlbi_aa64_rvae3_write
},
6732 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
6733 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
6734 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6735 .writefn
= tlbi_aa64_rvae3_write
},
6738 static const ARMCPRegInfo tlbios_reginfo
[] = {
6739 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
6740 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
6741 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6742 .writefn
= tlbi_aa64_vmalle1is_write
},
6743 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
6744 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
6745 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6746 .writefn
= tlbi_aa64_vae1is_write
},
6747 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
6748 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
6749 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6750 .writefn
= tlbi_aa64_vmalle1is_write
},
6751 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
6752 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
6753 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6754 .writefn
= tlbi_aa64_vae1is_write
},
6755 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
6756 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
6757 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6758 .writefn
= tlbi_aa64_vae1is_write
},
6759 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
6760 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
6761 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6762 .writefn
= tlbi_aa64_vae1is_write
},
6763 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
6764 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
6765 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6766 .writefn
= tlbi_aa64_alle2is_write
},
6767 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
6768 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
6769 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6770 .writefn
= tlbi_aa64_vae2is_write
},
6771 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
6772 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
6773 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
6774 .writefn
= tlbi_aa64_alle1is_write
},
6775 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
6776 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
6777 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6778 .writefn
= tlbi_aa64_vae2is_write
},
6779 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
6780 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
6781 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
6782 .writefn
= tlbi_aa64_alle1is_write
},
6783 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
6784 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
6785 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6786 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
6787 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
6788 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6789 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
6790 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
6791 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6792 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
6793 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
6794 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6795 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
6796 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
6797 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6798 .writefn
= tlbi_aa64_alle3is_write
},
6799 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
6800 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
6801 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6802 .writefn
= tlbi_aa64_vae3is_write
},
6803 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
6804 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
6805 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6806 .writefn
= tlbi_aa64_vae3is_write
},
6809 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6814 /* Success sets NZCV = 0000. */
6815 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
6817 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
6819 * ??? Failed, for unknown reasons in the crypto subsystem.
6820 * The best we can do is log the reason and return the
6821 * timed-out indication to the guest. There is no reason
6822 * we know to expect this failure to be transitory, so the
6823 * guest may well hang retrying the operation.
6825 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
6826 ri
->name
, error_get_pretty(err
));
6829 env
->ZF
= 0; /* NZCF = 0100 */
6835 /* We do not support re-seeding, so the two registers operate the same. */
6836 static const ARMCPRegInfo rndr_reginfo
[] = {
6837 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
6838 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6839 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
6840 .access
= PL0_R
, .readfn
= rndr_readfn
},
6841 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
6842 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6843 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
6844 .access
= PL0_R
, .readfn
= rndr_readfn
},
6847 #ifndef CONFIG_USER_ONLY
6848 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
6851 ARMCPU
*cpu
= env_archcpu(env
);
6852 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6853 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
6854 uint64_t vaddr_in
= (uint64_t) value
;
6855 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
6857 int mem_idx
= cpu_mmu_index(env
, false);
6859 /* This won't be crossing page boundaries */
6860 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
6866 /* RCU lock is already being held */
6867 mr
= memory_region_from_host(haddr
, &offset
);
6870 memory_region_writeback(mr
, offset
, dline_size
);
6875 static const ARMCPRegInfo dcpop_reg
[] = {
6876 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
6877 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
6878 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6879 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6882 static const ARMCPRegInfo dcpodp_reg
[] = {
6883 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
6884 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
6885 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6886 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6888 #endif /*CONFIG_USER_ONLY*/
6890 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6893 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
6894 return CP_ACCESS_TRAP_EL2
;
6897 return CP_ACCESS_OK
;
6900 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6903 int el
= arm_current_el(env
);
6905 if (el
< 2 && arm_is_el2_enabled(env
)) {
6906 uint64_t hcr
= arm_hcr_el2_eff(env
);
6907 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
6908 return CP_ACCESS_TRAP_EL2
;
6912 arm_feature(env
, ARM_FEATURE_EL3
) &&
6913 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
6914 return CP_ACCESS_TRAP_EL3
;
6916 return CP_ACCESS_OK
;
6919 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6921 return env
->pstate
& PSTATE_TCO
;
6924 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6926 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
6929 static const ARMCPRegInfo mte_reginfo
[] = {
6930 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
6931 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
6932 .access
= PL1_RW
, .accessfn
= access_mte
,
6933 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
6934 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
6935 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
6936 .access
= PL1_RW
, .accessfn
= access_mte
,
6937 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
6938 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
6939 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
6940 .access
= PL2_RW
, .accessfn
= access_mte
,
6941 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
6942 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
6943 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
6945 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
6946 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
6947 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
6948 .access
= PL1_RW
, .accessfn
= access_mte
,
6949 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
6950 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
6951 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
6952 .access
= PL1_RW
, .accessfn
= access_mte
,
6953 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
6954 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
6955 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
6956 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
6957 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
6958 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
6959 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
6960 .type
= ARM_CP_NO_RAW
,
6961 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
6962 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
6963 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
6964 .type
= ARM_CP_NOP
, .access
= PL1_W
,
6965 .accessfn
= aa64_cacheop_poc_access
},
6966 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
6967 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
6968 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6969 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
6970 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
6971 .type
= ARM_CP_NOP
, .access
= PL1_W
,
6972 .accessfn
= aa64_cacheop_poc_access
},
6973 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
6974 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
6975 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6976 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
6977 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
6978 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6979 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
6980 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
6981 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6982 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
6983 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
6984 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6985 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
6986 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
6987 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
6990 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
6991 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
6992 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
6993 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
6996 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
6997 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
6998 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
6999 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7000 .accessfn
= aa64_cacheop_poc_access
},
7001 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7002 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7003 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7004 .accessfn
= aa64_cacheop_poc_access
},
7005 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7006 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7007 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7008 .accessfn
= aa64_cacheop_poc_access
},
7009 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7010 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7011 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7012 .accessfn
= aa64_cacheop_poc_access
},
7013 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7014 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7015 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7016 .accessfn
= aa64_cacheop_poc_access
},
7017 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7018 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7019 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7020 .accessfn
= aa64_cacheop_poc_access
},
7021 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7022 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7023 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7024 .accessfn
= aa64_cacheop_poc_access
},
7025 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7026 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7027 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7028 .accessfn
= aa64_cacheop_poc_access
},
7029 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7030 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7031 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7032 #ifndef CONFIG_USER_ONLY
7033 /* Avoid overhead of an access check that always passes in user-mode */
7034 .accessfn
= aa64_zva_access
,
7037 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7038 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7039 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7040 #ifndef CONFIG_USER_ONLY
7041 /* Avoid overhead of an access check that always passes in user-mode */
7042 .accessfn
= aa64_zva_access
,
7047 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7050 uint64_t hcr
= arm_hcr_el2_eff(env
);
7051 int el
= arm_current_el(env
);
7053 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7054 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7055 if (hcr
& HCR_TGE
) {
7056 return CP_ACCESS_TRAP_EL2
;
7058 return CP_ACCESS_TRAP
;
7060 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7061 return CP_ACCESS_TRAP_EL2
;
7063 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7064 return CP_ACCESS_TRAP_EL2
;
7067 && arm_feature(env
, ARM_FEATURE_EL3
)
7068 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7069 return CP_ACCESS_TRAP_EL3
;
7071 return CP_ACCESS_OK
;
7074 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7075 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7076 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7077 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7078 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7079 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7080 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7081 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7082 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7083 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7084 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7085 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7086 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7087 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7088 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7090 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7092 #endif /* TARGET_AARCH64 */
7094 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7097 int el
= arm_current_el(env
);
7100 uint64_t sctlr
= arm_sctlr(env
, el
);
7101 if (!(sctlr
& SCTLR_EnRCTX
)) {
7102 return CP_ACCESS_TRAP
;
7104 } else if (el
== 1) {
7105 uint64_t hcr
= arm_hcr_el2_eff(env
);
7107 return CP_ACCESS_TRAP_EL2
;
7110 return CP_ACCESS_OK
;
7113 static const ARMCPRegInfo predinv_reginfo
[] = {
7114 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7115 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7116 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7117 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7118 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7119 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7120 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7121 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7122 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7124 * Note the AArch32 opcodes have a different OPC1.
7126 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7127 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7128 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7129 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7130 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7131 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7132 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7133 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7134 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7137 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7139 /* Read the high 32 bits of the current CCSIDR */
7140 return extract64(ccsidr_read(env
, ri
), 32, 32);
7143 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7144 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7145 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7147 .accessfn
= access_aa64_tid2
,
7148 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7151 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7154 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7155 return CP_ACCESS_TRAP_EL2
;
7158 return CP_ACCESS_OK
;
7161 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7164 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7165 return access_aa64_tid3(env
, ri
, isread
);
7168 return CP_ACCESS_OK
;
7171 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7174 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7175 return CP_ACCESS_TRAP_EL2
;
7178 return CP_ACCESS_OK
;
7181 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7182 const ARMCPRegInfo
*ri
, bool isread
)
7185 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7186 * in v7A, not in v8A.
7188 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7189 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7190 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7191 return CP_ACCESS_TRAP_EL2
;
7193 return CP_ACCESS_OK
;
7196 static const ARMCPRegInfo jazelle_regs
[] = {
7198 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7199 .access
= PL1_R
, .accessfn
= access_jazelle
,
7200 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7202 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7203 .accessfn
= access_joscr_jmcr
,
7204 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7206 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7207 .accessfn
= access_joscr_jmcr
,
7208 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7211 static const ARMCPRegInfo contextidr_el2
= {
7212 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7213 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7215 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7218 static const ARMCPRegInfo vhe_reginfo
[] = {
7219 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7220 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7221 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7222 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7223 #ifndef CONFIG_USER_ONLY
7224 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7225 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7227 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7228 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7229 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7230 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7231 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7232 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7233 .resetfn
= gt_hv_timer_reset
,
7234 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7235 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7237 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7239 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7240 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7241 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7242 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7243 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7244 .access
= PL2_RW
, .accessfn
= e2h_access
,
7245 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7246 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7247 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7248 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7249 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7250 .access
= PL2_RW
, .accessfn
= e2h_access
,
7251 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7252 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7253 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7254 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7255 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7256 .access
= PL2_RW
, .accessfn
= e2h_access
,
7257 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7258 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7259 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7260 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7261 .access
= PL2_RW
, .accessfn
= e2h_access
,
7262 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7263 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7264 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7265 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7266 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7267 .access
= PL2_RW
, .accessfn
= e2h_access
,
7268 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7269 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7270 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7271 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7272 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7273 .access
= PL2_RW
, .accessfn
= e2h_access
,
7274 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7278 #ifndef CONFIG_USER_ONLY
7279 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7280 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7281 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7282 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7283 .writefn
= ats_write64
},
7284 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7285 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7286 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7287 .writefn
= ats_write64
},
7290 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7291 { .name
= "ATS1CPRP",
7292 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7293 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7294 .writefn
= ats_write
},
7295 { .name
= "ATS1CPWP",
7296 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7297 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7298 .writefn
= ats_write
},
7303 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7304 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7305 * is non-zero, which is never for ARMv7, optionally in ARMv8
7306 * and mandatorily for ARMv8.2 and up.
7307 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7308 * implementation is RAZ/WI we can ignore this detail, as we
7311 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7312 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7313 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7314 .access
= PL1_RW
, .accessfn
= access_tacr
,
7315 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7316 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7317 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7318 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7322 void register_cp_regs_for_features(ARMCPU
*cpu
)
7324 /* Register all the coprocessor registers based on feature bits */
7325 CPUARMState
*env
= &cpu
->env
;
7326 if (arm_feature(env
, ARM_FEATURE_M
)) {
7327 /* M profile has no coprocessor registers */
7331 define_arm_cp_regs(cpu
, cp_reginfo
);
7332 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7333 /* Must go early as it is full of wildcards that may be
7334 * overridden by later definitions.
7336 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7339 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7340 /* The ID registers all have impdef reset values */
7341 ARMCPRegInfo v6_idregs
[] = {
7342 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7343 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7344 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7345 .accessfn
= access_aa32_tid3
,
7346 .resetvalue
= cpu
->isar
.id_pfr0
},
7347 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7348 * the value of the GIC field until after we define these regs.
7350 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7351 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7352 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7353 .accessfn
= access_aa32_tid3
,
7354 .readfn
= id_pfr1_read
,
7355 .writefn
= arm_cp_write_ignore
},
7356 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7357 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7358 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7359 .accessfn
= access_aa32_tid3
,
7360 .resetvalue
= cpu
->isar
.id_dfr0
},
7361 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7362 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7363 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7364 .accessfn
= access_aa32_tid3
,
7365 .resetvalue
= cpu
->id_afr0
},
7366 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7367 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7368 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7369 .accessfn
= access_aa32_tid3
,
7370 .resetvalue
= cpu
->isar
.id_mmfr0
},
7371 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7372 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7373 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7374 .accessfn
= access_aa32_tid3
,
7375 .resetvalue
= cpu
->isar
.id_mmfr1
},
7376 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7377 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7378 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7379 .accessfn
= access_aa32_tid3
,
7380 .resetvalue
= cpu
->isar
.id_mmfr2
},
7381 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7382 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7383 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7384 .accessfn
= access_aa32_tid3
,
7385 .resetvalue
= cpu
->isar
.id_mmfr3
},
7386 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7387 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7388 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7389 .accessfn
= access_aa32_tid3
,
7390 .resetvalue
= cpu
->isar
.id_isar0
},
7391 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7392 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7393 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7394 .accessfn
= access_aa32_tid3
,
7395 .resetvalue
= cpu
->isar
.id_isar1
},
7396 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7397 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7398 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7399 .accessfn
= access_aa32_tid3
,
7400 .resetvalue
= cpu
->isar
.id_isar2
},
7401 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7402 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7403 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7404 .accessfn
= access_aa32_tid3
,
7405 .resetvalue
= cpu
->isar
.id_isar3
},
7406 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7407 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7408 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7409 .accessfn
= access_aa32_tid3
,
7410 .resetvalue
= cpu
->isar
.id_isar4
},
7411 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7412 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7413 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7414 .accessfn
= access_aa32_tid3
,
7415 .resetvalue
= cpu
->isar
.id_isar5
},
7416 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7417 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7418 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7419 .accessfn
= access_aa32_tid3
,
7420 .resetvalue
= cpu
->isar
.id_mmfr4
},
7421 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7422 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7423 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7424 .accessfn
= access_aa32_tid3
,
7425 .resetvalue
= cpu
->isar
.id_isar6
},
7427 define_arm_cp_regs(cpu
, v6_idregs
);
7428 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7430 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7432 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7433 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7435 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7436 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7437 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7439 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7440 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7442 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7443 ARMCPRegInfo clidr
= {
7444 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7445 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7446 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7447 .accessfn
= access_aa64_tid2
,
7448 .resetvalue
= cpu
->clidr
7450 define_one_arm_cp_reg(cpu
, &clidr
);
7451 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7452 define_debug_regs(cpu
);
7453 define_pmu_regs(cpu
);
7455 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7457 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7459 * v8 ID registers, which all have impdef reset values.
7460 * Note that within the ID register ranges the unused slots
7461 * must all RAZ, not UNDEF; future architecture versions may
7462 * define new registers here.
7463 * ID registers which are AArch64 views of the AArch32 ID registers
7464 * which already existed in v6 and v7 are handled elsewhere,
7468 ARMCPRegInfo v8_idregs
[] = {
7470 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7471 * emulation because we don't know the right value for the
7472 * GIC field until after we define these regs.
7474 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7475 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7477 #ifdef CONFIG_USER_ONLY
7478 .type
= ARM_CP_CONST
,
7479 .resetvalue
= cpu
->isar
.id_aa64pfr0
7481 .type
= ARM_CP_NO_RAW
,
7482 .accessfn
= access_aa64_tid3
,
7483 .readfn
= id_aa64pfr0_read
,
7484 .writefn
= arm_cp_write_ignore
7487 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7488 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7489 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7490 .accessfn
= access_aa64_tid3
,
7491 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7492 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7493 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7494 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7495 .accessfn
= access_aa64_tid3
,
7497 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7498 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7499 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7500 .accessfn
= access_aa64_tid3
,
7502 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7503 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7504 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7505 .accessfn
= access_aa64_tid3
,
7506 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
7507 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7508 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7509 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7510 .accessfn
= access_aa64_tid3
,
7511 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
7512 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7513 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7514 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7515 .accessfn
= access_aa64_tid3
,
7517 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7518 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7519 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7520 .accessfn
= access_aa64_tid3
,
7522 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7523 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7524 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7525 .accessfn
= access_aa64_tid3
,
7526 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7527 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7528 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7529 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7530 .accessfn
= access_aa64_tid3
,
7531 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7532 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7533 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7534 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7535 .accessfn
= access_aa64_tid3
,
7537 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7538 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7539 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7540 .accessfn
= access_aa64_tid3
,
7542 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7543 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7544 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7545 .accessfn
= access_aa64_tid3
,
7546 .resetvalue
= cpu
->id_aa64afr0
},
7547 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7548 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7549 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7550 .accessfn
= access_aa64_tid3
,
7551 .resetvalue
= cpu
->id_aa64afr1
},
7552 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7553 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7554 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7555 .accessfn
= access_aa64_tid3
,
7557 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7558 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7559 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7560 .accessfn
= access_aa64_tid3
,
7562 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7563 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7564 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7565 .accessfn
= access_aa64_tid3
,
7566 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7567 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7568 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7569 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7570 .accessfn
= access_aa64_tid3
,
7571 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7572 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7573 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7574 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7575 .accessfn
= access_aa64_tid3
,
7577 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7578 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7579 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7580 .accessfn
= access_aa64_tid3
,
7582 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7583 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7584 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7585 .accessfn
= access_aa64_tid3
,
7587 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7588 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7589 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7590 .accessfn
= access_aa64_tid3
,
7592 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7593 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7594 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7595 .accessfn
= access_aa64_tid3
,
7597 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7598 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7599 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7600 .accessfn
= access_aa64_tid3
,
7602 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7603 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7604 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7605 .accessfn
= access_aa64_tid3
,
7606 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7607 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7608 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7609 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7610 .accessfn
= access_aa64_tid3
,
7611 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7612 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7613 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7614 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7615 .accessfn
= access_aa64_tid3
,
7616 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7617 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7618 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7619 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7620 .accessfn
= access_aa64_tid3
,
7622 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7623 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7624 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7625 .accessfn
= access_aa64_tid3
,
7627 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7628 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7629 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7630 .accessfn
= access_aa64_tid3
,
7632 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7633 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7634 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7635 .accessfn
= access_aa64_tid3
,
7637 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7638 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7639 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7640 .accessfn
= access_aa64_tid3
,
7642 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7643 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7644 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7645 .accessfn
= access_aa64_tid3
,
7646 .resetvalue
= cpu
->isar
.mvfr0
},
7647 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7648 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7649 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7650 .accessfn
= access_aa64_tid3
,
7651 .resetvalue
= cpu
->isar
.mvfr1
},
7652 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7653 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7654 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7655 .accessfn
= access_aa64_tid3
,
7656 .resetvalue
= cpu
->isar
.mvfr2
},
7658 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
7659 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
7660 * as RAZ, since it is in the "reserved for future ID
7661 * registers, RAZ" part of the AArch32 encoding space.
7663 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
7664 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7665 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7666 .accessfn
= access_aa64_tid3
,
7668 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
7669 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7670 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7671 .accessfn
= access_aa64_tid3
,
7673 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
7674 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7675 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7676 .accessfn
= access_aa64_tid3
,
7679 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
7680 * they're also RAZ for AArch64, and in v8 are gradually
7681 * being filled with AArch64-view-of-AArch32-ID-register
7682 * for new ID registers.
7684 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
7685 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7686 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7687 .accessfn
= access_aa64_tid3
,
7689 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
7690 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7691 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7692 .accessfn
= access_aa64_tid3
,
7693 .resetvalue
= cpu
->isar
.id_pfr2
},
7694 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
7695 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7696 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7697 .accessfn
= access_aa64_tid3
,
7698 .resetvalue
= cpu
->isar
.id_dfr1
},
7699 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
7700 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7701 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7702 .accessfn
= access_aa64_tid3
,
7703 .resetvalue
= cpu
->isar
.id_mmfr5
},
7704 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
7705 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7706 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7707 .accessfn
= access_aa64_tid3
,
7709 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7710 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7711 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7712 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7713 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7714 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7715 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7716 .resetvalue
= cpu
->pmceid0
},
7717 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7718 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7719 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7720 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7721 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7722 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7723 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7724 .resetvalue
= cpu
->pmceid1
},
7726 #ifdef CONFIG_USER_ONLY
7727 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7728 { .name
= "ID_AA64PFR0_EL1",
7729 .exported_bits
= 0x000f000f00ff0000,
7730 .fixed_bits
= 0x0000000000000011 },
7731 { .name
= "ID_AA64PFR1_EL1",
7732 .exported_bits
= 0x00000000000000f0 },
7733 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7735 { .name
= "ID_AA64ZFR0_EL1" },
7736 { .name
= "ID_AA64MMFR0_EL1",
7737 .fixed_bits
= 0x00000000ff000000 },
7738 { .name
= "ID_AA64MMFR1_EL1" },
7739 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7741 { .name
= "ID_AA64DFR0_EL1",
7742 .fixed_bits
= 0x0000000000000006 },
7743 { .name
= "ID_AA64DFR1_EL1" },
7744 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7746 { .name
= "ID_AA64AFR*",
7748 { .name
= "ID_AA64ISAR0_EL1",
7749 .exported_bits
= 0x00fffffff0fffff0 },
7750 { .name
= "ID_AA64ISAR1_EL1",
7751 .exported_bits
= 0x000000f0ffffffff },
7752 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7755 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7757 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7758 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7759 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7760 ARMCPRegInfo rvbar
= {
7761 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7762 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7764 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7766 define_one_arm_cp_reg(cpu
, &rvbar
);
7768 define_arm_cp_regs(cpu
, v8_idregs
);
7769 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7771 for (i
= 4; i
< 16; i
++) {
7773 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
7774 * For pre-v8 cores there are RAZ patterns for these in
7775 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
7776 * v8 extends the "must RAZ" part of the ID register space
7777 * to also cover c0, 0, c{8-15}, {0-7}.
7778 * These are STATE_AA32 because in the AArch64 sysreg space
7779 * c4-c7 is where the AArch64 ID registers live (and we've
7780 * already defined those in v8_idregs[]), and c8-c15 are not
7781 * "must RAZ" for AArch64.
7783 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
7784 ARMCPRegInfo v8_aa32_raz_idregs
= {
7786 .state
= ARM_CP_STATE_AA32
,
7787 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
7788 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7789 .accessfn
= access_aa64_tid3
,
7791 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
7796 * Register the base EL2 cpregs.
7797 * Pre v8, these registers are implemented only as part of the
7798 * Virtualization Extensions (EL2 present). Beginning with v8,
7799 * if EL2 is missing but EL3 is enabled, mostly these become
7800 * RES0 from EL3, with some specific exceptions.
7802 if (arm_feature(env
, ARM_FEATURE_EL2
)
7803 || (arm_feature(env
, ARM_FEATURE_EL3
)
7804 && arm_feature(env
, ARM_FEATURE_V8
))) {
7805 uint64_t vmpidr_def
= mpidr_read_val(env
);
7806 ARMCPRegInfo vpidr_regs
[] = {
7807 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7808 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7809 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7810 .resetvalue
= cpu
->midr
,
7811 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
7812 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7813 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7814 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7815 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
7816 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
7817 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7818 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
7819 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7820 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7821 .resetvalue
= vmpidr_def
,
7822 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
7823 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
7824 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7825 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7826 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
7827 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
7828 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
7831 * The only field of MDCR_EL2 that has a defined architectural reset
7832 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
7834 ARMCPRegInfo mdcr_el2
= {
7835 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
7836 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
7837 .writefn
= mdcr_el2_write
,
7838 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
7839 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
7841 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
7842 define_arm_cp_regs(cpu
, vpidr_regs
);
7843 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
7844 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7845 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
7847 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
7848 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
7850 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7851 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
7852 ARMCPRegInfo rvbar
= {
7853 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
7854 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
7856 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7858 define_one_arm_cp_reg(cpu
, &rvbar
);
7862 /* Register the base EL3 cpregs. */
7863 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7864 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
7865 ARMCPRegInfo el3_regs
[] = {
7866 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
7867 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
7869 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7871 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7872 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
7874 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
7875 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
7876 .resetvalue
= cpu
->reset_sctlr
},
7879 define_arm_cp_regs(cpu
, el3_regs
);
7881 /* The behaviour of NSACR is sufficiently various that we don't
7882 * try to describe it in a single reginfo:
7883 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7884 * reads as constant 0xc00 from NS EL1 and NS EL2
7885 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7886 * if v7 without EL3, register doesn't exist
7887 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7889 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7890 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7891 static const ARMCPRegInfo nsacr
= {
7892 .name
= "NSACR", .type
= ARM_CP_CONST
,
7893 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7894 .access
= PL1_RW
, .accessfn
= nsacr_access
,
7897 define_one_arm_cp_reg(cpu
, &nsacr
);
7899 static const ARMCPRegInfo nsacr
= {
7901 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7902 .access
= PL3_RW
| PL1_R
,
7904 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
7906 define_one_arm_cp_reg(cpu
, &nsacr
);
7909 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7910 static const ARMCPRegInfo nsacr
= {
7911 .name
= "NSACR", .type
= ARM_CP_CONST
,
7912 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7916 define_one_arm_cp_reg(cpu
, &nsacr
);
7920 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
7921 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7922 /* PMSAv6 not implemented */
7923 assert(arm_feature(env
, ARM_FEATURE_V7
));
7924 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7925 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
7927 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
7930 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7931 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
7932 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7933 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
7934 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
7937 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
7938 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
7940 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
7941 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
7943 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
7944 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
7946 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
7947 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
7949 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
7950 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
7952 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
7953 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
7955 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
7956 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
7958 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7959 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
7961 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7962 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
7964 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
7965 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
7967 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
7968 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
7970 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
7971 define_arm_cp_regs(cpu
, jazelle_regs
);
7973 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7974 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7975 * be read-only (ie write causes UNDEF exception).
7978 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
7979 /* Pre-v8 MIDR space.
7980 * Note that the MIDR isn't a simple constant register because
7981 * of the TI925 behaviour where writes to another register can
7982 * cause the MIDR value to change.
7984 * Unimplemented registers in the c15 0 0 0 space default to
7985 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7986 * and friends override accordingly.
7989 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
7990 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
7991 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
7992 .readfn
= midr_read
,
7993 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7994 .type
= ARM_CP_OVERRIDE
},
7995 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7997 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
7998 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8000 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8001 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8003 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8004 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8006 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8007 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8009 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8010 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8012 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8013 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8014 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8015 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8016 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8017 .readfn
= midr_read
},
8018 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
8019 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8020 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8021 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8022 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8023 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8024 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8025 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8026 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8028 .accessfn
= access_aa64_tid1
,
8029 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8031 ARMCPRegInfo id_cp_reginfo
[] = {
8032 /* These are common to v8 and pre-v8 */
8034 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8035 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8036 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8037 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8038 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8039 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8040 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8041 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8043 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8045 .accessfn
= access_aa32_tid1
,
8046 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8048 /* TLBTR is specific to VMSA */
8049 ARMCPRegInfo id_tlbtr_reginfo
= {
8051 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8053 .accessfn
= access_aa32_tid1
,
8054 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8056 /* MPUIR is specific to PMSA V6+ */
8057 ARMCPRegInfo id_mpuir_reginfo
= {
8059 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8060 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8061 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8063 static const ARMCPRegInfo crn0_wi_reginfo
= {
8064 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8065 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8066 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8068 #ifdef CONFIG_USER_ONLY
8069 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8070 { .name
= "MIDR_EL1",
8071 .exported_bits
= 0x00000000ffffffff },
8072 { .name
= "REVIDR_EL1" },
8074 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8076 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8077 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8079 /* Register the blanket "writes ignored" value first to cover the
8080 * whole space. Then update the specific ID registers to allow write
8081 * access, so that they ignore writes rather than causing them to
8084 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8085 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
8086 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
8088 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
8089 id_cp_reginfo
[i
].access
= PL1_RW
;
8091 id_mpuir_reginfo
.access
= PL1_RW
;
8092 id_tlbtr_reginfo
.access
= PL1_RW
;
8094 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8095 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8097 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8099 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8100 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8101 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8102 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8103 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8107 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8108 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8109 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8110 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8111 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8113 #ifdef CONFIG_USER_ONLY
8114 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8115 { .name
= "MPIDR_EL1",
8116 .fixed_bits
= 0x0000000080000000 },
8118 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8120 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8123 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8124 ARMCPRegInfo auxcr_reginfo
[] = {
8125 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8126 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8127 .access
= PL1_RW
, .accessfn
= access_tacr
,
8128 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8129 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8130 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8131 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8133 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8134 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8135 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8138 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8139 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8140 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8144 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8146 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8147 * There are two flavours:
8148 * (1) older 32-bit only cores have a simple 32-bit CBAR
8149 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8150 * 32-bit register visible to AArch32 at a different encoding
8151 * to the "flavour 1" register and with the bits rearranged to
8152 * be able to squash a 64-bit address into the 32-bit view.
8153 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8154 * in future if we support AArch32-only configs of some of the
8155 * AArch64 cores we might need to add a specific feature flag
8156 * to indicate cores with "flavour 2" CBAR.
8158 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8159 /* 32 bit view is [31:18] 0...0 [43:32]. */
8160 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8161 | extract64(cpu
->reset_cbar
, 32, 12);
8162 ARMCPRegInfo cbar_reginfo
[] = {
8164 .type
= ARM_CP_CONST
,
8165 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8166 .access
= PL1_R
, .resetvalue
= cbar32
},
8167 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8168 .type
= ARM_CP_CONST
,
8169 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8170 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8172 /* We don't implement a r/w 64 bit CBAR currently */
8173 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8174 define_arm_cp_regs(cpu
, cbar_reginfo
);
8176 ARMCPRegInfo cbar
= {
8178 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8179 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8180 .fieldoffset
= offsetof(CPUARMState
,
8181 cp15
.c15_config_base_address
)
8183 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8184 cbar
.access
= PL1_R
;
8185 cbar
.fieldoffset
= 0;
8186 cbar
.type
= ARM_CP_CONST
;
8188 define_one_arm_cp_reg(cpu
, &cbar
);
8192 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8193 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
8194 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8195 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8196 .access
= PL1_RW
, .writefn
= vbar_write
,
8197 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8198 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8201 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8204 /* Generic registers whose values depend on the implementation */
8206 ARMCPRegInfo sctlr
= {
8207 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8208 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8209 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8210 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8211 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8212 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8213 .raw_writefn
= raw_write
,
8215 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8216 /* Normally we would always end the TB on an SCTLR write, but Linux
8217 * arch/arm/mach-pxa/sleep.S expects two instructions following
8218 * an MMU enable to execute from cache. Imitate this behaviour.
8220 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8222 define_one_arm_cp_reg(cpu
, &sctlr
);
8225 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8226 define_arm_cp_regs(cpu
, lor_reginfo
);
8228 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8229 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8231 #ifndef CONFIG_USER_ONLY
8232 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8233 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8235 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8236 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8239 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8240 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8243 if (cpu_isar_feature(aa64_dit
, cpu
)) {
8244 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
8246 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
8247 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
8249 if (cpu_isar_feature(any_ras
, cpu
)) {
8250 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
8253 if (cpu_isar_feature(aa64_vh
, cpu
) ||
8254 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
8255 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
8257 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8258 define_arm_cp_regs(cpu
, vhe_reginfo
);
8261 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8262 define_arm_cp_regs(cpu
, zcr_reginfo
);
8265 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
8266 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
8269 #ifdef TARGET_AARCH64
8270 if (cpu_isar_feature(aa64_sme
, cpu
)) {
8271 define_arm_cp_regs(cpu
, sme_reginfo
);
8273 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8274 define_arm_cp_regs(cpu
, pauth_reginfo
);
8276 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8277 define_arm_cp_regs(cpu
, rndr_reginfo
);
8279 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
8280 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
8282 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
8283 define_arm_cp_regs(cpu
, tlbios_reginfo
);
8285 #ifndef CONFIG_USER_ONLY
8286 /* Data Cache clean instructions up to PoP */
8287 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8288 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8290 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8291 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8294 #endif /*CONFIG_USER_ONLY*/
8297 * If full MTE is enabled, add all of the system registers.
8298 * If only "instructions available at EL0" are enabled,
8299 * then define only a RAZ/WI version of PSTATE.TCO.
8301 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8302 define_arm_cp_regs(cpu
, mte_reginfo
);
8303 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8304 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8305 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8306 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8309 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
8310 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
8314 if (cpu_isar_feature(any_predinv
, cpu
)) {
8315 define_arm_cp_regs(cpu
, predinv_reginfo
);
8318 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8319 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8322 #ifndef CONFIG_USER_ONLY
8324 * Register redirections and aliases must be done last,
8325 * after the registers from the other extensions have been defined.
8327 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8328 define_arm_vh_e2h_redirects_aliases(cpu
);
8333 /* Sort alphabetically by type name, except for "any". */
8334 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8336 ObjectClass
*class_a
= (ObjectClass
*)a
;
8337 ObjectClass
*class_b
= (ObjectClass
*)b
;
8338 const char *name_a
, *name_b
;
8340 name_a
= object_class_get_name(class_a
);
8341 name_b
= object_class_get_name(class_b
);
8342 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8344 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8347 return strcmp(name_a
, name_b
);
8351 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8353 ObjectClass
*oc
= data
;
8354 CPUClass
*cc
= CPU_CLASS(oc
);
8355 const char *typename
;
8358 typename
= object_class_get_name(oc
);
8359 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8360 if (cc
->deprecation_note
) {
8361 qemu_printf(" %s (deprecated)\n", name
);
8363 qemu_printf(" %s\n", name
);
8368 void arm_cpu_list(void)
8372 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8373 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8374 qemu_printf("Available CPUs:\n");
8375 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8379 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8381 ObjectClass
*oc
= data
;
8382 CpuDefinitionInfoList
**cpu_list
= user_data
;
8383 CpuDefinitionInfo
*info
;
8384 const char *typename
;
8386 typename
= object_class_get_name(oc
);
8387 info
= g_malloc0(sizeof(*info
));
8388 info
->name
= g_strndup(typename
,
8389 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8390 info
->q_typename
= g_strdup(typename
);
8392 QAPI_LIST_PREPEND(*cpu_list
, info
);
8395 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8397 CpuDefinitionInfoList
*cpu_list
= NULL
;
8400 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8401 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8408 * Private utility function for define_one_arm_cp_reg_with_opaque():
8409 * add a single reginfo struct to the hash table.
8411 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8412 void *opaque
, CPState state
,
8413 CPSecureState secstate
,
8414 int crm
, int opc1
, int opc2
,
8417 CPUARMState
*env
= &cpu
->env
;
8420 bool is64
= r
->type
& ARM_CP_64BIT
;
8421 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
8427 case ARM_CP_STATE_AA32
:
8428 /* We assume it is a cp15 register if the .cp field is left unset. */
8429 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
8432 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
8434 case ARM_CP_STATE_AA64
:
8436 * To allow abbreviation of ARMCPRegInfo definitions, we treat
8437 * cp == 0 as equivalent to the value for "standard guest-visible
8438 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
8439 * in their AArch64 view (the .cp value may be non-zero for the
8440 * benefit of the AArch32 view).
8442 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8443 cp
= CP_REG_ARM64_SYSREG_CP
;
8445 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
8448 g_assert_not_reached();
8451 /* Overriding of an existing definition must be explicitly requested. */
8452 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8453 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
8455 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
8460 * Eliminate registers that are not present because the EL is missing.
8461 * Doing this here makes it easier to put all registers for a given
8462 * feature into the same ARMCPRegInfo array and define them all at once.
8465 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8467 * An EL2 register without EL2 but with EL3 is (usually) RES0.
8468 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
8470 int min_el
= ctz32(r
->access
) / 2;
8471 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
8472 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
8475 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
8478 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
8480 if ((r
->access
& max_el
) == 0) {
8485 /* Combine cpreg and name into one allocation. */
8486 name_len
= strlen(name
) + 1;
8487 r2
= g_malloc(sizeof(*r2
) + name_len
);
8489 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
8492 * Update fields to match the instantiation, overwiting wildcards
8493 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
8500 r2
->secure
= secstate
;
8502 r2
->opaque
= opaque
;
8506 /* This should not have been a very special register to begin. */
8507 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
8508 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
8510 * Set the special function to CONST, retaining the other flags.
8511 * This is important for e.g. ARM_CP_SVE so that we still
8512 * take the SVE trap if CPTR_EL3.EZ == 0.
8514 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
8516 * Usually, these registers become RES0, but there are a few
8517 * special cases like VPIDR_EL2 which have a constant non-zero
8518 * value with writes ignored.
8520 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
8524 * ARM_CP_CONST has precedence, so removing the callbacks and
8525 * offsets are not strictly necessary, but it is potentially
8526 * less confusing to debug later.
8530 r2
->raw_readfn
= NULL
;
8531 r2
->raw_writefn
= NULL
;
8533 r2
->fieldoffset
= 0;
8534 r2
->bank_fieldoffsets
[0] = 0;
8535 r2
->bank_fieldoffsets
[1] = 0;
8537 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
8541 * Register is banked (using both entries in array).
8542 * Overwriting fieldoffset as the array is only used to define
8543 * banked registers but later only fieldoffset is used.
8545 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8547 if (state
== ARM_CP_STATE_AA32
) {
8550 * If the register is banked then we don't need to migrate or
8551 * reset the 32-bit instance in certain cases:
8553 * 1) If the register has both 32-bit and 64-bit instances
8554 * then we can count on the 64-bit instance taking care
8555 * of the non-secure bank.
8556 * 2) If ARMv8 is enabled then we can count on a 64-bit
8557 * version taking care of the secure bank. This requires
8558 * that separate 32 and 64-bit definitions are provided.
8560 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8561 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
8562 r2
->type
|= ARM_CP_ALIAS
;
8564 } else if ((secstate
!= r
->secure
) && !ns
) {
8566 * The register is not banked so we only want to allow
8567 * migration of the non-secure instance.
8569 r2
->type
|= ARM_CP_ALIAS
;
8572 if (HOST_BIG_ENDIAN
&&
8573 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
8574 r2
->fieldoffset
+= sizeof(uint32_t);
8580 * By convention, for wildcarded registers only the first
8581 * entry is used for migration; the others are marked as
8582 * ALIAS so we don't try to transfer the register
8583 * multiple times. Special registers (ie NOP/WFI) are
8584 * never migratable and not even raw-accessible.
8586 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
8587 r2
->type
|= ARM_CP_NO_RAW
;
8589 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8590 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8591 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8592 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8596 * Check that raw accesses are either forbidden or handled. Note that
8597 * we can't assert this earlier because the setup of fieldoffset for
8598 * banked registers has to be done first.
8600 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8601 assert(!raw_accessors_invalid(r2
));
8604 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
8608 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8609 const ARMCPRegInfo
*r
, void *opaque
)
8611 /* Define implementations of coprocessor registers.
8612 * We store these in a hashtable because typically
8613 * there are less than 150 registers in a space which
8614 * is 16*16*16*8*8 = 262144 in size.
8615 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8616 * If a register is defined twice then the second definition is
8617 * used, so this can be used to define some generic registers and
8618 * then override them with implementation specific variations.
8619 * At least one of the original and the second definition should
8620 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8621 * against accidental use.
8623 * The state field defines whether the register is to be
8624 * visible in the AArch32 or AArch64 execution state. If the
8625 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8626 * reginfo structure for the AArch32 view, which sees the lower
8627 * 32 bits of the 64 bit register.
8629 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8630 * be wildcarded. AArch64 registers are always considered to be 64
8631 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8632 * the register, if any.
8634 int crm
, opc1
, opc2
;
8635 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8636 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8637 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8638 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8639 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8640 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8643 /* 64 bit registers have only CRm and Opc1 fields */
8644 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8645 /* op0 only exists in the AArch64 encodings */
8646 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8647 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8648 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8650 * This API is only for Arm's system coprocessors (14 and 15) or
8651 * (M-profile or v7A-and-earlier only) for implementation defined
8652 * coprocessors in the range 0..7. Our decode assumes this, since
8653 * 8..13 can be used for other insns including VFP and Neon. See
8654 * valid_cp() in translate.c. Assert here that we haven't tried
8655 * to use an invalid coprocessor number.
8658 case ARM_CP_STATE_BOTH
:
8659 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8664 case ARM_CP_STATE_AA32
:
8665 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
8666 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
8667 assert(r
->cp
>= 14 && r
->cp
<= 15);
8669 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
8672 case ARM_CP_STATE_AA64
:
8673 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
8676 g_assert_not_reached();
8678 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8679 * encodes a minimum access level for the register. We roll this
8680 * runtime check into our general permission check code, so check
8681 * here that the reginfo's specified permissions are strict enough
8682 * to encompass the generic architectural permission check.
8684 if (r
->state
!= ARM_CP_STATE_AA32
) {
8685 CPAccessRights mask
;
8688 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8689 mask
= PL0U_R
| PL1_RW
;
8709 /* min_EL EL1, secure mode only (we don't check the latter) */
8713 /* broken reginfo with out-of-range opc1 */
8714 g_assert_not_reached();
8716 /* assert our permissions are not too lax (stricter is fine) */
8717 assert((r
->access
& ~mask
) == 0);
8720 /* Check that the register definition has enough info to handle
8721 * reads and writes if they are permitted.
8723 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
8724 if (r
->access
& PL3_R
) {
8725 assert((r
->fieldoffset
||
8726 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8729 if (r
->access
& PL3_W
) {
8730 assert((r
->fieldoffset
||
8731 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8736 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8737 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8738 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8739 for (state
= ARM_CP_STATE_AA32
;
8740 state
<= ARM_CP_STATE_AA64
; state
++) {
8741 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8744 if (state
== ARM_CP_STATE_AA32
) {
8745 /* Under AArch32 CP registers can be common
8746 * (same for secure and non-secure world) or banked.
8750 switch (r
->secure
) {
8751 case ARM_CP_SECSTATE_S
:
8752 case ARM_CP_SECSTATE_NS
:
8753 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8754 r
->secure
, crm
, opc1
, opc2
,
8757 case ARM_CP_SECSTATE_BOTH
:
8758 name
= g_strdup_printf("%s_S", r
->name
);
8759 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8761 crm
, opc1
, opc2
, name
);
8763 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8765 crm
, opc1
, opc2
, r
->name
);
8768 g_assert_not_reached();
8771 /* AArch64 registers get mapped to non-secure instance
8773 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8775 crm
, opc1
, opc2
, r
->name
);
8783 /* Define a whole list of registers */
8784 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
8785 void *opaque
, size_t len
)
8788 for (i
= 0; i
< len
; ++i
) {
8789 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
8794 * Modify ARMCPRegInfo for access from userspace.
8796 * This is a data driven modification directed by
8797 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8798 * user-space cannot alter any values and dynamic values pertaining to
8799 * execution state are hidden from user space view anyway.
8801 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
8802 const ARMCPRegUserSpaceInfo
*mods
,
8805 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
8806 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
8807 GPatternSpec
*pat
= NULL
;
8810 pat
= g_pattern_spec_new(m
->name
);
8812 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
8813 ARMCPRegInfo
*r
= regs
+ ri
;
8815 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8816 r
->type
= ARM_CP_CONST
;
8820 } else if (strcmp(r
->name
, m
->name
) == 0) {
8821 r
->type
= ARM_CP_CONST
;
8823 r
->resetvalue
&= m
->exported_bits
;
8824 r
->resetvalue
|= m
->fixed_bits
;
8829 g_pattern_spec_free(pat
);
8834 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
8836 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
8839 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8842 /* Helper coprocessor write function for write-ignore registers */
8845 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8847 /* Helper coprocessor write function for read-as-zero registers */
8851 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
8853 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8856 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
8858 /* Return true if it is not valid for us to switch to
8859 * this CPU mode (ie all the UNPREDICTABLE cases in
8860 * the ARM ARM CPSRWriteByInstr pseudocode).
8863 /* Changes to or from Hyp via MSR and CPS are illegal. */
8864 if (write_type
== CPSRWriteByInstr
&&
8865 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
8866 mode
== ARM_CPU_MODE_HYP
)) {
8871 case ARM_CPU_MODE_USR
:
8873 case ARM_CPU_MODE_SYS
:
8874 case ARM_CPU_MODE_SVC
:
8875 case ARM_CPU_MODE_ABT
:
8876 case ARM_CPU_MODE_UND
:
8877 case ARM_CPU_MODE_IRQ
:
8878 case ARM_CPU_MODE_FIQ
:
8879 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8880 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8882 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8883 * and CPS are treated as illegal mode changes.
8885 if (write_type
== CPSRWriteByInstr
&&
8886 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
8887 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
8891 case ARM_CPU_MODE_HYP
:
8892 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
8893 case ARM_CPU_MODE_MON
:
8894 return arm_current_el(env
) < 3;
8900 uint32_t cpsr_read(CPUARMState
*env
)
8903 ZF
= (env
->ZF
== 0);
8904 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
8905 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
8906 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
8907 | ((env
->condexec_bits
& 0xfc) << 8)
8908 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
8911 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
8912 CPSRWriteType write_type
)
8914 uint32_t changed_daif
;
8915 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
8916 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
8918 if (mask
& CPSR_NZCV
) {
8919 env
->ZF
= (~val
) & CPSR_Z
;
8921 env
->CF
= (val
>> 29) & 1;
8922 env
->VF
= (val
<< 3) & 0x80000000;
8925 env
->QF
= ((val
& CPSR_Q
) != 0);
8927 env
->thumb
= ((val
& CPSR_T
) != 0);
8928 if (mask
& CPSR_IT_0_1
) {
8929 env
->condexec_bits
&= ~3;
8930 env
->condexec_bits
|= (val
>> 25) & 3;
8932 if (mask
& CPSR_IT_2_7
) {
8933 env
->condexec_bits
&= 3;
8934 env
->condexec_bits
|= (val
>> 8) & 0xfc;
8936 if (mask
& CPSR_GE
) {
8937 env
->GE
= (val
>> 16) & 0xf;
8940 /* In a V7 implementation that includes the security extensions but does
8941 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8942 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8943 * bits respectively.
8945 * In a V8 implementation, it is permitted for privileged software to
8946 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8948 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
8949 arm_feature(env
, ARM_FEATURE_EL3
) &&
8950 !arm_feature(env
, ARM_FEATURE_EL2
) &&
8951 !arm_is_secure(env
)) {
8953 changed_daif
= (env
->daif
^ val
) & mask
;
8955 if (changed_daif
& CPSR_A
) {
8956 /* Check to see if we are allowed to change the masking of async
8957 * abort exceptions from a non-secure state.
8959 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
8960 qemu_log_mask(LOG_GUEST_ERROR
,
8961 "Ignoring attempt to switch CPSR_A flag from "
8962 "non-secure world with SCR.AW bit clear\n");
8967 if (changed_daif
& CPSR_F
) {
8968 /* Check to see if we are allowed to change the masking of FIQ
8969 * exceptions from a non-secure state.
8971 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
8972 qemu_log_mask(LOG_GUEST_ERROR
,
8973 "Ignoring attempt to switch CPSR_F flag from "
8974 "non-secure world with SCR.FW bit clear\n");
8978 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8979 * If this bit is set software is not allowed to mask
8980 * FIQs, but is allowed to set CPSR_F to 0.
8982 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
8984 qemu_log_mask(LOG_GUEST_ERROR
,
8985 "Ignoring attempt to enable CPSR_F flag "
8986 "(non-maskable FIQ [NMFI] support enabled)\n");
8992 env
->daif
&= ~(CPSR_AIF
& mask
);
8993 env
->daif
|= val
& CPSR_AIF
& mask
;
8995 if (write_type
!= CPSRWriteRaw
&&
8996 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
8997 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
8998 /* Note that we can only get here in USR mode if this is a
8999 * gdb stub write; for this case we follow the architectural
9000 * behaviour for guest writes in USR mode of ignoring an attempt
9001 * to switch mode. (Those are caught by translate.c for writes
9002 * triggered by guest instructions.)
9005 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9006 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9007 * v7, and has defined behaviour in v8:
9008 * + leave CPSR.M untouched
9009 * + allow changes to the other CPSR fields
9011 * For user changes via the GDB stub, we don't set PSTATE.IL,
9012 * as this would be unnecessarily harsh for a user error.
9015 if (write_type
!= CPSRWriteByGDBStub
&&
9016 arm_feature(env
, ARM_FEATURE_V8
)) {
9020 qemu_log_mask(LOG_GUEST_ERROR
,
9021 "Illegal AArch32 mode switch attempt from %s to %s\n",
9022 aarch32_mode_name(env
->uncached_cpsr
),
9023 aarch32_mode_name(val
));
9025 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9026 write_type
== CPSRWriteExceptionReturn
?
9027 "Exception return from AArch32" :
9028 "AArch32 mode switch from",
9029 aarch32_mode_name(env
->uncached_cpsr
),
9030 aarch32_mode_name(val
), env
->regs
[15]);
9031 switch_mode(env
, val
& CPSR_M
);
9034 mask
&= ~CACHED_CPSR_BITS
;
9035 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9036 if (rebuild_hflags
) {
9037 arm_rebuild_hflags(env
);
9041 /* Sign/zero extend */
9042 uint32_t HELPER(sxtb16
)(uint32_t x
)
9045 res
= (uint16_t)(int8_t)x
;
9046 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9050 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
9053 * Take a division-by-zero exception if necessary; otherwise return
9054 * to get the usual non-trapping division behaviour (result of 0)
9056 if (arm_feature(env
, ARM_FEATURE_M
)
9057 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
9058 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
9062 uint32_t HELPER(uxtb16
)(uint32_t x
)
9065 res
= (uint16_t)(uint8_t)x
;
9066 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9070 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
9073 handle_possible_div0_trap(env
, GETPC());
9076 if (num
== INT_MIN
&& den
== -1) {
9082 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
9085 handle_possible_div0_trap(env
, GETPC());
9091 uint32_t HELPER(rbit
)(uint32_t x
)
9096 #ifdef CONFIG_USER_ONLY
9098 static void switch_mode(CPUARMState
*env
, int mode
)
9100 ARMCPU
*cpu
= env_archcpu(env
);
9102 if (mode
!= ARM_CPU_MODE_USR
) {
9103 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9107 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9108 uint32_t cur_el
, bool secure
)
9113 void aarch64_sync_64_to_32(CPUARMState
*env
)
9115 g_assert_not_reached();
9120 static void switch_mode(CPUARMState
*env
, int mode
)
9125 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9126 if (mode
== old_mode
)
9129 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9130 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9131 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9132 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9133 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9134 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9137 i
= bank_number(old_mode
);
9138 env
->banked_r13
[i
] = env
->regs
[13];
9139 env
->banked_spsr
[i
] = env
->spsr
;
9141 i
= bank_number(mode
);
9142 env
->regs
[13] = env
->banked_r13
[i
];
9143 env
->spsr
= env
->banked_spsr
[i
];
9145 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9146 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9149 /* Physical Interrupt Target EL Lookup Table
9151 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9153 * The below multi-dimensional table is used for looking up the target
9154 * exception level given numerous condition criteria. Specifically, the
9155 * target EL is based on SCR and HCR routing controls as well as the
9156 * currently executing EL and secure state.
9159 * target_el_table[2][2][2][2][2][4]
9160 * | | | | | +--- Current EL
9161 * | | | | +------ Non-secure(0)/Secure(1)
9162 * | | | +--------- HCR mask override
9163 * | | +------------ SCR exec state control
9164 * | +--------------- SCR mask override
9165 * +------------------ 32-bit(0)/64-bit(1) EL3
9167 * The table values are as such:
9171 * The ARM ARM target EL table includes entries indicating that an "exception
9172 * is not taken". The two cases where this is applicable are:
9173 * 1) An exception is taken from EL3 but the SCR does not have the exception
9175 * 2) An exception is taken from EL2 but the HCR does not have the exception
9177 * In these two cases, the below table contain a target of EL1. This value is
9178 * returned as it is expected that the consumer of the table data will check
9179 * for "target EL >= current EL" to ensure the exception is not taken.
9183 * BIT IRQ IMO Non-secure Secure
9184 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9186 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9187 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9188 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9189 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9190 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9191 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9192 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9193 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9194 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9195 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9196 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9197 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9198 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9199 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9200 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9201 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9202 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9206 * Determine the target EL for physical exceptions
9208 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9209 uint32_t cur_el
, bool secure
)
9211 CPUARMState
*env
= cs
->env_ptr
;
9216 /* Is the highest EL AArch64? */
9217 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9220 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9221 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9223 /* Either EL2 is the highest EL (and so the EL2 register width
9224 * is given by is64); or there is no EL2 or EL3, in which case
9225 * the value of 'rw' does not affect the table lookup anyway.
9230 hcr_el2
= arm_hcr_el2_eff(env
);
9233 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9234 hcr
= hcr_el2
& HCR_IMO
;
9237 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9238 hcr
= hcr_el2
& HCR_FMO
;
9241 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9242 hcr
= hcr_el2
& HCR_AMO
;
9247 * For these purposes, TGE and AMO/IMO/FMO both force the
9248 * interrupt to EL2. Fold TGE into the bit extracted above.
9250 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9252 /* Perform a table-lookup for the target EL given the current state */
9253 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9255 assert(target_el
> 0);
9260 void arm_log_exception(CPUState
*cs
)
9262 int idx
= cs
->exception_index
;
9264 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9265 const char *exc
= NULL
;
9266 static const char * const excnames
[] = {
9267 [EXCP_UDEF
] = "Undefined Instruction",
9269 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9270 [EXCP_DATA_ABORT
] = "Data Abort",
9273 [EXCP_BKPT
] = "Breakpoint",
9274 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9275 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9276 [EXCP_HVC
] = "Hypervisor Call",
9277 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9278 [EXCP_SMC
] = "Secure Monitor Call",
9279 [EXCP_VIRQ
] = "Virtual IRQ",
9280 [EXCP_VFIQ
] = "Virtual FIQ",
9281 [EXCP_SEMIHOST
] = "Semihosting call",
9282 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9283 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9284 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9285 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9286 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9287 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9288 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
9289 [EXCP_VSERR
] = "Virtual SERR",
9292 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9293 exc
= excnames
[idx
];
9298 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
9299 idx
, exc
, cs
->cpu_index
);
9304 * Function used to synchronize QEMU's AArch64 register set with AArch32
9305 * register set. This is necessary when switching between AArch32 and AArch64
9308 void aarch64_sync_32_to_64(CPUARMState
*env
)
9311 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9313 /* We can blanket copy R[0:7] to X[0:7] */
9314 for (i
= 0; i
< 8; i
++) {
9315 env
->xregs
[i
] = env
->regs
[i
];
9319 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9320 * Otherwise, they come from the banked user regs.
9322 if (mode
== ARM_CPU_MODE_FIQ
) {
9323 for (i
= 8; i
< 13; i
++) {
9324 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9327 for (i
= 8; i
< 13; i
++) {
9328 env
->xregs
[i
] = env
->regs
[i
];
9333 * Registers x13-x23 are the various mode SP and FP registers. Registers
9334 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9335 * from the mode banked register.
9337 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9338 env
->xregs
[13] = env
->regs
[13];
9339 env
->xregs
[14] = env
->regs
[14];
9341 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9342 /* HYP is an exception in that it is copied from r14 */
9343 if (mode
== ARM_CPU_MODE_HYP
) {
9344 env
->xregs
[14] = env
->regs
[14];
9346 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9350 if (mode
== ARM_CPU_MODE_HYP
) {
9351 env
->xregs
[15] = env
->regs
[13];
9353 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9356 if (mode
== ARM_CPU_MODE_IRQ
) {
9357 env
->xregs
[16] = env
->regs
[14];
9358 env
->xregs
[17] = env
->regs
[13];
9360 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9361 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9364 if (mode
== ARM_CPU_MODE_SVC
) {
9365 env
->xregs
[18] = env
->regs
[14];
9366 env
->xregs
[19] = env
->regs
[13];
9368 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9369 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9372 if (mode
== ARM_CPU_MODE_ABT
) {
9373 env
->xregs
[20] = env
->regs
[14];
9374 env
->xregs
[21] = env
->regs
[13];
9376 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9377 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9380 if (mode
== ARM_CPU_MODE_UND
) {
9381 env
->xregs
[22] = env
->regs
[14];
9382 env
->xregs
[23] = env
->regs
[13];
9384 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9385 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9389 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9390 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9391 * FIQ bank for r8-r14.
9393 if (mode
== ARM_CPU_MODE_FIQ
) {
9394 for (i
= 24; i
< 31; i
++) {
9395 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9398 for (i
= 24; i
< 29; i
++) {
9399 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9401 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9402 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9405 env
->pc
= env
->regs
[15];
9409 * Function used to synchronize QEMU's AArch32 register set with AArch64
9410 * register set. This is necessary when switching between AArch32 and AArch64
9413 void aarch64_sync_64_to_32(CPUARMState
*env
)
9416 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9418 /* We can blanket copy X[0:7] to R[0:7] */
9419 for (i
= 0; i
< 8; i
++) {
9420 env
->regs
[i
] = env
->xregs
[i
];
9424 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9425 * Otherwise, we copy x8-x12 into the banked user regs.
9427 if (mode
== ARM_CPU_MODE_FIQ
) {
9428 for (i
= 8; i
< 13; i
++) {
9429 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9432 for (i
= 8; i
< 13; i
++) {
9433 env
->regs
[i
] = env
->xregs
[i
];
9438 * Registers r13 & r14 depend on the current mode.
9439 * If we are in a given mode, we copy the corresponding x registers to r13
9440 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9443 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9444 env
->regs
[13] = env
->xregs
[13];
9445 env
->regs
[14] = env
->xregs
[14];
9447 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9450 * HYP is an exception in that it does not have its own banked r14 but
9451 * shares the USR r14
9453 if (mode
== ARM_CPU_MODE_HYP
) {
9454 env
->regs
[14] = env
->xregs
[14];
9456 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9460 if (mode
== ARM_CPU_MODE_HYP
) {
9461 env
->regs
[13] = env
->xregs
[15];
9463 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9466 if (mode
== ARM_CPU_MODE_IRQ
) {
9467 env
->regs
[14] = env
->xregs
[16];
9468 env
->regs
[13] = env
->xregs
[17];
9470 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9471 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9474 if (mode
== ARM_CPU_MODE_SVC
) {
9475 env
->regs
[14] = env
->xregs
[18];
9476 env
->regs
[13] = env
->xregs
[19];
9478 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9479 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9482 if (mode
== ARM_CPU_MODE_ABT
) {
9483 env
->regs
[14] = env
->xregs
[20];
9484 env
->regs
[13] = env
->xregs
[21];
9486 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9487 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9490 if (mode
== ARM_CPU_MODE_UND
) {
9491 env
->regs
[14] = env
->xregs
[22];
9492 env
->regs
[13] = env
->xregs
[23];
9494 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9495 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9498 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9499 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9500 * FIQ bank for r8-r14.
9502 if (mode
== ARM_CPU_MODE_FIQ
) {
9503 for (i
= 24; i
< 31; i
++) {
9504 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9507 for (i
= 24; i
< 29; i
++) {
9508 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9510 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9511 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9514 env
->regs
[15] = env
->pc
;
9517 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9518 uint32_t mask
, uint32_t offset
,
9523 /* Change the CPU state so as to actually take the exception. */
9524 switch_mode(env
, new_mode
);
9527 * For exceptions taken to AArch32 we must clear the SS bit in both
9528 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9530 env
->pstate
&= ~PSTATE_SS
;
9531 env
->spsr
= cpsr_read(env
);
9532 /* Clear IT bits. */
9533 env
->condexec_bits
= 0;
9534 /* Switch to the new mode, and to the correct instruction set. */
9535 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9537 /* This must be after mode switching. */
9538 new_el
= arm_current_el(env
);
9540 /* Set new mode endianness */
9541 env
->uncached_cpsr
&= ~CPSR_E
;
9542 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9543 env
->uncached_cpsr
|= CPSR_E
;
9545 /* J and IL must always be cleared for exception entry */
9546 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9549 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
9550 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
9551 env
->uncached_cpsr
|= CPSR_SSBS
;
9553 env
->uncached_cpsr
&= ~CPSR_SSBS
;
9557 if (new_mode
== ARM_CPU_MODE_HYP
) {
9558 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9559 env
->elr_el
[2] = env
->regs
[15];
9561 /* CPSR.PAN is normally preserved preserved unless... */
9562 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9565 if (!arm_is_secure_below_el3(env
)) {
9566 /* ... the target is EL3, from non-secure state. */
9567 env
->uncached_cpsr
&= ~CPSR_PAN
;
9570 /* ... the target is EL3, from secure state ... */
9573 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9574 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9575 env
->uncached_cpsr
|= CPSR_PAN
;
9581 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9582 * and we should just guard the thumb mode on V4
9584 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9586 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9588 env
->regs
[14] = env
->regs
[15] + offset
;
9590 env
->regs
[15] = newpc
;
9591 arm_rebuild_hflags(env
);
9594 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9597 * Handle exception entry to Hyp mode; this is sufficiently
9598 * different to entry to other AArch32 modes that we handle it
9601 * The vector table entry used is always the 0x14 Hyp mode entry point,
9602 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
9603 * The offset applied to the preferred return address is always zero
9604 * (see DDI0487C.a section G1.12.3).
9605 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9607 uint32_t addr
, mask
;
9608 ARMCPU
*cpu
= ARM_CPU(cs
);
9609 CPUARMState
*env
= &cpu
->env
;
9611 switch (cs
->exception_index
) {
9619 /* Fall through to prefetch abort. */
9620 case EXCP_PREFETCH_ABORT
:
9621 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9622 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9623 (uint32_t)env
->exception
.vaddress
);
9626 case EXCP_DATA_ABORT
:
9627 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9628 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9629 (uint32_t)env
->exception
.vaddress
);
9645 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9648 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9649 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9651 * QEMU syndrome values are v8-style. v7 has the IL bit
9652 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9653 * If this is a v7 CPU, squash the IL bit in those cases.
9655 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9656 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9657 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9658 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9659 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9662 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9665 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9670 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9673 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9676 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9680 addr
+= env
->cp15
.hvbar
;
9682 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9685 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9687 ARMCPU
*cpu
= ARM_CPU(cs
);
9688 CPUARMState
*env
= &cpu
->env
;
9695 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9696 switch (syn_get_ec(env
->exception
.syndrome
)) {
9698 case EC_BREAKPOINT_SAME_EL
:
9702 case EC_WATCHPOINT_SAME_EL
:
9708 case EC_VECTORCATCH
:
9717 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9720 if (env
->exception
.target_el
== 2) {
9721 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9725 switch (cs
->exception_index
) {
9727 new_mode
= ARM_CPU_MODE_UND
;
9736 new_mode
= ARM_CPU_MODE_SVC
;
9739 /* The PC already points to the next instruction. */
9743 /* Fall through to prefetch abort. */
9744 case EXCP_PREFETCH_ABORT
:
9745 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9746 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9747 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9748 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9749 new_mode
= ARM_CPU_MODE_ABT
;
9751 mask
= CPSR_A
| CPSR_I
;
9754 case EXCP_DATA_ABORT
:
9755 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9756 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9757 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9759 (uint32_t)env
->exception
.vaddress
);
9760 new_mode
= ARM_CPU_MODE_ABT
;
9762 mask
= CPSR_A
| CPSR_I
;
9766 new_mode
= ARM_CPU_MODE_IRQ
;
9768 /* Disable IRQ and imprecise data aborts. */
9769 mask
= CPSR_A
| CPSR_I
;
9771 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9772 /* IRQ routed to monitor mode */
9773 new_mode
= ARM_CPU_MODE_MON
;
9778 new_mode
= ARM_CPU_MODE_FIQ
;
9780 /* Disable FIQ, IRQ and imprecise data aborts. */
9781 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9782 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9783 /* FIQ routed to monitor mode */
9784 new_mode
= ARM_CPU_MODE_MON
;
9789 new_mode
= ARM_CPU_MODE_IRQ
;
9791 /* Disable IRQ and imprecise data aborts. */
9792 mask
= CPSR_A
| CPSR_I
;
9796 new_mode
= ARM_CPU_MODE_FIQ
;
9798 /* Disable FIQ, IRQ and imprecise data aborts. */
9799 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9805 * Note that this is reported as a data abort, but the DFAR
9806 * has an UNKNOWN value. Construct the SError syndrome from
9807 * AET and ExT fields.
9809 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
9811 if (extended_addresses_enabled(env
)) {
9812 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
9814 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
9816 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
9817 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9818 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
9819 env
->exception
.fsr
);
9821 new_mode
= ARM_CPU_MODE_ABT
;
9823 mask
= CPSR_A
| CPSR_I
;
9828 new_mode
= ARM_CPU_MODE_MON
;
9830 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9834 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9835 return; /* Never happens. Keep compiler happy. */
9838 if (new_mode
== ARM_CPU_MODE_MON
) {
9839 addr
+= env
->cp15
.mvbar
;
9840 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9841 /* High vectors. When enabled, base address cannot be remapped. */
9844 /* ARM v7 architectures provide a vector base address register to remap
9845 * the interrupt vector table.
9846 * This register is only followed in non-monitor mode, and is banked.
9847 * Note: only bits 31:5 are valid.
9849 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9852 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9853 env
->cp15
.scr_el3
&= ~SCR_NS
;
9856 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9859 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
9862 * Return the register number of the AArch64 view of the AArch32
9863 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
9864 * be that of the AArch32 mode the exception came from.
9866 int mode
= env
->uncached_cpsr
& CPSR_M
;
9868 switch (aarch32_reg
) {
9872 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
9875 case ARM_CPU_MODE_USR
:
9876 case ARM_CPU_MODE_SYS
:
9878 case ARM_CPU_MODE_HYP
:
9880 case ARM_CPU_MODE_IRQ
:
9882 case ARM_CPU_MODE_SVC
:
9884 case ARM_CPU_MODE_ABT
:
9886 case ARM_CPU_MODE_UND
:
9888 case ARM_CPU_MODE_FIQ
:
9891 g_assert_not_reached();
9895 case ARM_CPU_MODE_USR
:
9896 case ARM_CPU_MODE_SYS
:
9897 case ARM_CPU_MODE_HYP
:
9899 case ARM_CPU_MODE_IRQ
:
9901 case ARM_CPU_MODE_SVC
:
9903 case ARM_CPU_MODE_ABT
:
9905 case ARM_CPU_MODE_UND
:
9907 case ARM_CPU_MODE_FIQ
:
9910 g_assert_not_reached();
9915 g_assert_not_reached();
9919 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
9921 uint32_t ret
= cpsr_read(env
);
9923 /* Move DIT to the correct location for SPSR_ELx */
9924 if (ret
& CPSR_DIT
) {
9928 /* Merge PSTATE.SS into SPSR_ELx */
9929 ret
|= env
->pstate
& PSTATE_SS
;
9934 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
9936 /* Return true if this syndrome value is a synchronous external abort */
9937 switch (syn_get_ec(syndrome
)) {
9939 case EC_INSNABORT_SAME_EL
:
9941 case EC_DATAABORT_SAME_EL
:
9942 /* Look at fault status code for all the synchronous ext abort cases */
9943 switch (syndrome
& 0x3f) {
9959 /* Handle exception entry to a target EL which is using AArch64 */
9960 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
9962 ARMCPU
*cpu
= ARM_CPU(cs
);
9963 CPUARMState
*env
= &cpu
->env
;
9964 unsigned int new_el
= env
->exception
.target_el
;
9965 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
9966 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
9967 unsigned int old_mode
;
9968 unsigned int cur_el
= arm_current_el(env
);
9972 * Note that new_el can never be 0. If cur_el is 0, then
9973 * el0_a64 is is_a64(), else el0_a64 is ignored.
9975 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
9977 if (cur_el
< new_el
) {
9978 /* Entry vector offset depends on whether the implemented EL
9979 * immediately lower than the target level is using AArch32 or AArch64
9986 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
9989 hcr
= arm_hcr_el2_eff(env
);
9990 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
9991 is_aa64
= (hcr
& HCR_RW
) != 0;
9996 is_aa64
= is_a64(env
);
9999 g_assert_not_reached();
10007 } else if (pstate_read(env
) & PSTATE_SP
) {
10011 switch (cs
->exception_index
) {
10012 case EXCP_PREFETCH_ABORT
:
10013 case EXCP_DATA_ABORT
:
10015 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
10016 * to be taken to the SError vector entrypoint.
10018 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
10019 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
10022 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10023 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10024 env
->cp15
.far_el
[new_el
]);
10030 case EXCP_HYP_TRAP
:
10032 switch (syn_get_ec(env
->exception
.syndrome
)) {
10033 case EC_ADVSIMDFPACCESSTRAP
:
10035 * QEMU internal FP/SIMD syndromes from AArch32 include the
10036 * TA and coproc fields which are only exposed if the exception
10037 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10038 * AArch64 format syndrome.
10040 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10042 case EC_CP14RTTRAP
:
10043 case EC_CP15RTTRAP
:
10044 case EC_CP14DTTRAP
:
10046 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10047 * the raw register field from the insn; when taking this to
10048 * AArch64 we must convert it to the AArch64 view of the register
10049 * number. Notice that we read a 4-bit AArch32 register number and
10050 * write back a 5-bit AArch64 one.
10052 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10053 rt
= aarch64_regnum(env
, rt
);
10054 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10057 case EC_CP15RRTTRAP
:
10058 case EC_CP14RRTTRAP
:
10059 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10060 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10061 rt
= aarch64_regnum(env
, rt
);
10062 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10064 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10065 rt
= aarch64_regnum(env
, rt
);
10066 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10070 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10082 /* Construct the SError syndrome from IDS and ISS fields. */
10083 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
10084 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10087 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10091 old_mode
= pstate_read(env
);
10092 aarch64_save_sp(env
, arm_current_el(env
));
10093 env
->elr_el
[new_el
] = env
->pc
;
10095 old_mode
= cpsr_read_for_spsr_elx(env
);
10096 env
->elr_el
[new_el
] = env
->regs
[15];
10098 aarch64_sync_32_to_64(env
);
10100 env
->condexec_bits
= 0;
10102 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10104 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10105 env
->elr_el
[new_el
]);
10107 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10108 /* The value of PSTATE.PAN is normally preserved, except when ... */
10109 new_mode
|= old_mode
& PSTATE_PAN
;
10112 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10113 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10114 != (HCR_E2H
| HCR_TGE
)) {
10119 /* ... the target is EL1 ... */
10120 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10121 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10122 new_mode
|= PSTATE_PAN
;
10127 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10128 new_mode
|= PSTATE_TCO
;
10131 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10132 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
10133 new_mode
|= PSTATE_SSBS
;
10135 new_mode
&= ~PSTATE_SSBS
;
10139 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10140 env
->aarch64
= true;
10141 aarch64_restore_sp(env
, new_el
);
10142 helper_rebuild_hflags_a64(env
, new_el
);
10146 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10147 new_el
, env
->pc
, pstate_read(env
));
10151 * Do semihosting call and set the appropriate return value. All the
10152 * permission and validity checks have been done at translate time.
10154 * We only see semihosting exceptions in TCG only as they are not
10155 * trapped to the hypervisor in KVM.
10158 static void handle_semihosting(CPUState
*cs
)
10160 ARMCPU
*cpu
= ARM_CPU(cs
);
10161 CPUARMState
*env
= &cpu
->env
;
10164 qemu_log_mask(CPU_LOG_INT
,
10165 "...handling as semihosting call 0x%" PRIx64
"\n",
10167 do_common_semihosting(cs
);
10170 qemu_log_mask(CPU_LOG_INT
,
10171 "...handling as semihosting call 0x%x\n",
10173 do_common_semihosting(cs
);
10174 env
->regs
[15] += env
->thumb
? 2 : 4;
10179 /* Handle a CPU exception for A and R profile CPUs.
10180 * Do any appropriate logging, handle PSCI calls, and then hand off
10181 * to the AArch64-entry or AArch32-entry function depending on the
10182 * target exception level's register width.
10184 * Note: this is used for both TCG (as the do_interrupt tcg op),
10185 * and KVM to re-inject guest debug exceptions, and to
10186 * inject a Synchronous-External-Abort.
10188 void arm_cpu_do_interrupt(CPUState
*cs
)
10190 ARMCPU
*cpu
= ARM_CPU(cs
);
10191 CPUARMState
*env
= &cpu
->env
;
10192 unsigned int new_el
= env
->exception
.target_el
;
10194 assert(!arm_feature(env
, ARM_FEATURE_M
));
10196 arm_log_exception(cs
);
10197 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10199 if (qemu_loglevel_mask(CPU_LOG_INT
)
10200 && !excp_is_internal(cs
->exception_index
)) {
10201 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10202 syn_get_ec(env
->exception
.syndrome
),
10203 env
->exception
.syndrome
);
10206 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10207 arm_handle_psci_call(cpu
);
10208 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10213 * Semihosting semantics depend on the register width of the code
10214 * that caused the exception, not the target exception level, so
10215 * must be handled here.
10218 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10219 handle_semihosting(cs
);
10224 /* Hooks may change global state so BQL should be held, also the
10225 * BQL needs to be held for any modification of
10226 * cs->interrupt_request.
10228 g_assert(qemu_mutex_iothread_locked());
10230 arm_call_pre_el_change_hook(cpu
);
10232 assert(!excp_is_internal(cs
->exception_index
));
10233 if (arm_el_is_aa64(env
, new_el
)) {
10234 arm_cpu_do_interrupt_aarch64(cs
);
10236 arm_cpu_do_interrupt_aarch32(cs
);
10239 arm_call_el_change_hook(cpu
);
10241 if (!kvm_enabled()) {
10242 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10245 #endif /* !CONFIG_USER_ONLY */
10247 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10249 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10251 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10252 el
= (mmu_idx
== ARMMMUIdx_E20_0
|| mmu_idx
== ARMMMUIdx_SE20_0
)
10255 return env
->cp15
.sctlr_el
[el
];
10258 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10260 if (regime_has_2_ranges(mmu_idx
)) {
10261 return extract64(tcr
, 37, 2);
10262 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10263 return 0; /* VTCR_EL2 */
10265 /* Replicate the single TBI bit so we always have 2 bits. */
10266 return extract32(tcr
, 20, 1) * 3;
10270 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10272 if (regime_has_2_ranges(mmu_idx
)) {
10273 return extract64(tcr
, 51, 2);
10274 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10275 return 0; /* VTCR_EL2 */
10277 /* Replicate the single TBID bit so we always have 2 bits. */
10278 return extract32(tcr
, 29, 1) * 3;
10282 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10284 if (regime_has_2_ranges(mmu_idx
)) {
10285 return extract64(tcr
, 57, 2);
10287 /* Replicate the single TCMA bit so we always have 2 bits. */
10288 return extract32(tcr
, 30, 1) * 3;
10292 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10293 ARMMMUIdx mmu_idx
, bool data
)
10295 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
10296 bool epd
, hpd
, using16k
, using64k
, tsz_oob
, ds
;
10297 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
10298 ARMCPU
*cpu
= env_archcpu(env
);
10300 if (!regime_has_2_ranges(mmu_idx
)) {
10302 tsz
= extract32(tcr
, 0, 6);
10303 using64k
= extract32(tcr
, 14, 1);
10304 using16k
= extract32(tcr
, 15, 1);
10305 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10309 hpd
= extract32(tcr
, 24, 1);
10312 sh
= extract32(tcr
, 12, 2);
10313 ps
= extract32(tcr
, 16, 3);
10314 ds
= extract64(tcr
, 32, 1);
10317 * Bit 55 is always between the two regions, and is canonical for
10318 * determining if address tagging is enabled.
10320 select
= extract64(va
, 55, 1);
10322 tsz
= extract32(tcr
, 0, 6);
10323 epd
= extract32(tcr
, 7, 1);
10324 sh
= extract32(tcr
, 12, 2);
10325 using64k
= extract32(tcr
, 14, 1);
10326 using16k
= extract32(tcr
, 15, 1);
10327 hpd
= extract64(tcr
, 41, 1);
10329 int tg
= extract32(tcr
, 30, 2);
10330 using16k
= tg
== 1;
10331 using64k
= tg
== 3;
10332 tsz
= extract32(tcr
, 16, 6);
10333 epd
= extract32(tcr
, 23, 1);
10334 sh
= extract32(tcr
, 28, 2);
10335 hpd
= extract64(tcr
, 42, 1);
10337 ps
= extract64(tcr
, 32, 3);
10338 ds
= extract64(tcr
, 59, 1);
10341 if (cpu_isar_feature(aa64_st
, cpu
)) {
10342 max_tsz
= 48 - using64k
;
10348 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
10349 * adjust the effective value of DS, as documented.
10353 if (cpu_isar_feature(aa64_lva
, cpu
)) {
10359 case ARMMMUIdx_Stage2
:
10360 case ARMMMUIdx_Stage2_S
:
10362 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
10364 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
10369 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
10371 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
10380 if (tsz
> max_tsz
) {
10383 } else if (tsz
< min_tsz
) {
10390 /* Present TBI as a composite with TBID. */
10391 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10393 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10395 tbi
= (tbi
>> select
) & 1;
10397 return (ARMVAParameters
) {
10405 .using16k
= using16k
,
10406 .using64k
= using64k
,
10407 .tsz_oob
= tsz_oob
,
10412 /* Note that signed overflow is undefined in C. The following routines are
10413 careful to use unsigned types where modulo arithmetic is required.
10414 Failure to do so _will_ break on newer gcc. */
10416 /* Signed saturating arithmetic. */
10418 /* Perform 16-bit signed saturating addition. */
10419 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10424 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10433 /* Perform 8-bit signed saturating addition. */
10434 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10439 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10448 /* Perform 16-bit signed saturating subtraction. */
10449 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10454 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10463 /* Perform 8-bit signed saturating subtraction. */
10464 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10469 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10478 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10479 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10480 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10481 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10484 #include "op_addsub.h"
10486 /* Unsigned saturating arithmetic. */
10487 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10496 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10504 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10513 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10521 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10522 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10523 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10524 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10527 #include "op_addsub.h"
10529 /* Signed modulo arithmetic. */
10530 #define SARITH16(a, b, n, op) do { \
10532 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10533 RESULT(sum, n, 16); \
10535 ge |= 3 << (n * 2); \
10538 #define SARITH8(a, b, n, op) do { \
10540 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10541 RESULT(sum, n, 8); \
10547 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10548 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10549 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10550 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10554 #include "op_addsub.h"
10556 /* Unsigned modulo arithmetic. */
10557 #define ADD16(a, b, n) do { \
10559 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10560 RESULT(sum, n, 16); \
10561 if ((sum >> 16) == 1) \
10562 ge |= 3 << (n * 2); \
10565 #define ADD8(a, b, n) do { \
10567 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10568 RESULT(sum, n, 8); \
10569 if ((sum >> 8) == 1) \
10573 #define SUB16(a, b, n) do { \
10575 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10576 RESULT(sum, n, 16); \
10577 if ((sum >> 16) == 0) \
10578 ge |= 3 << (n * 2); \
10581 #define SUB8(a, b, n) do { \
10583 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
10584 RESULT(sum, n, 8); \
10585 if ((sum >> 8) == 0) \
10592 #include "op_addsub.h"
10594 /* Halved signed arithmetic. */
10595 #define ADD16(a, b, n) \
10596 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
10597 #define SUB16(a, b, n) \
10598 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
10599 #define ADD8(a, b, n) \
10600 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
10601 #define SUB8(a, b, n) \
10602 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
10605 #include "op_addsub.h"
10607 /* Halved unsigned arithmetic. */
10608 #define ADD16(a, b, n) \
10609 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10610 #define SUB16(a, b, n) \
10611 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10612 #define ADD8(a, b, n) \
10613 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10614 #define SUB8(a, b, n) \
10615 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10618 #include "op_addsub.h"
10620 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
10628 /* Unsigned sum of absolute byte differences. */
10629 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
10632 sum
= do_usad(a
, b
);
10633 sum
+= do_usad(a
>> 8, b
>> 8);
10634 sum
+= do_usad(a
>> 16, b
>> 16);
10635 sum
+= do_usad(a
>> 24, b
>> 24);
10639 /* For ARMv6 SEL instruction. */
10640 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
10652 mask
|= 0xff000000;
10653 return (a
& mask
) | (b
& ~mask
);
10657 * The upper bytes of val (above the number specified by 'bytes') must have
10658 * been zeroed out by the caller.
10660 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10664 stl_le_p(buf
, val
);
10666 /* zlib crc32 converts the accumulator and output to one's complement. */
10667 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
10670 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10674 stl_le_p(buf
, val
);
10676 /* Linux crc32c converts the output to one's complement. */
10677 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
10680 /* Return the exception level to which FP-disabled exceptions should
10681 * be taken, or 0 if FP is enabled.
10683 int fp_exception_el(CPUARMState
*env
, int cur_el
)
10685 #ifndef CONFIG_USER_ONLY
10688 /* CPACR and the CPTR registers don't exist before v6, so FP is
10689 * always accessible
10691 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
10695 if (arm_feature(env
, ARM_FEATURE_M
)) {
10696 /* CPACR can cause a NOCP UsageFault taken to current security state */
10697 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
10701 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
10702 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
10703 /* FP insns cause a NOCP UsageFault taken to Secure */
10711 hcr_el2
= arm_hcr_el2_eff(env
);
10713 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
10714 * 0, 2 : trap EL0 and EL1/PL1 accesses
10715 * 1 : trap only EL0 accesses
10716 * 3 : trap no accesses
10717 * This register is ignored if E2H+TGE are both set.
10719 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10720 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
10730 /* Trap from Secure PL0 or PL1 to Secure PL1. */
10731 if (!arm_el_is_aa64(env
, 3)
10732 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
10743 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
10744 * to control non-secure access to the FPU. It doesn't have any
10745 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
10747 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
10748 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
10749 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
10750 /* FP insns act as UNDEF */
10751 return cur_el
== 2 ? 2 : 1;
10756 * CPTR_EL2 is present in v7VE or v8, and changes format
10757 * with HCR_EL2.E2H (regardless of TGE).
10760 if (hcr_el2
& HCR_E2H
) {
10761 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
10763 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
10771 } else if (arm_is_el2_enabled(env
)) {
10772 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
10778 /* CPTR_EL3 : present in v8 */
10779 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
10780 /* Trap all FP ops to EL3 */
10787 /* Return the exception level we're running at if this is our mmu_idx */
10788 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
10790 if (mmu_idx
& ARM_MMU_IDX_M
) {
10791 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
10795 case ARMMMUIdx_E10_0
:
10796 case ARMMMUIdx_E20_0
:
10797 case ARMMMUIdx_SE10_0
:
10798 case ARMMMUIdx_SE20_0
:
10800 case ARMMMUIdx_E10_1
:
10801 case ARMMMUIdx_E10_1_PAN
:
10802 case ARMMMUIdx_SE10_1
:
10803 case ARMMMUIdx_SE10_1_PAN
:
10806 case ARMMMUIdx_E20_2
:
10807 case ARMMMUIdx_E20_2_PAN
:
10808 case ARMMMUIdx_SE2
:
10809 case ARMMMUIdx_SE20_2
:
10810 case ARMMMUIdx_SE20_2_PAN
:
10812 case ARMMMUIdx_SE3
:
10815 g_assert_not_reached();
10820 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
10822 g_assert_not_reached();
10826 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
10831 if (arm_feature(env
, ARM_FEATURE_M
)) {
10832 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
10835 /* See ARM pseudo-function ELIsInHost. */
10838 hcr
= arm_hcr_el2_eff(env
);
10839 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
10840 idx
= ARMMMUIdx_E20_0
;
10842 idx
= ARMMMUIdx_E10_0
;
10846 if (env
->pstate
& PSTATE_PAN
) {
10847 idx
= ARMMMUIdx_E10_1_PAN
;
10849 idx
= ARMMMUIdx_E10_1
;
10853 /* Note that TGE does not apply at EL2. */
10854 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
10855 if (env
->pstate
& PSTATE_PAN
) {
10856 idx
= ARMMMUIdx_E20_2_PAN
;
10858 idx
= ARMMMUIdx_E20_2
;
10861 idx
= ARMMMUIdx_E2
;
10865 return ARMMMUIdx_SE3
;
10867 g_assert_not_reached();
10870 if (arm_is_secure_below_el3(env
)) {
10871 idx
&= ~ARM_MMU_IDX_A_NS
;
10877 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
10879 return arm_mmu_idx_el(env
, arm_current_el(env
));
10882 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
10884 CPUARMTBFlags flags
)
10886 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
10887 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
10889 if (arm_singlestep_active(env
)) {
10890 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
10895 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
10897 CPUARMTBFlags flags
)
10899 bool sctlr_b
= arm_sctlr_b(env
);
10902 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
10904 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
10905 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
10907 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
10909 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
10912 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
10915 CPUARMTBFlags flags
= {};
10916 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
10918 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
10919 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
10920 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
10923 if (arm_v7m_is_handler_mode(env
)) {
10924 DP_TBFLAG_M32(flags
, HANDLER
, 1);
10928 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
10929 * is suppressing them because the requested execution priority
10932 if (arm_feature(env
, ARM_FEATURE_V8
) &&
10933 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
10934 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
10935 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
10938 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
10941 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
10944 CPUARMTBFlags flags
= {};
10945 int el
= arm_current_el(env
);
10947 if (arm_sctlr(env
, el
) & SCTLR_A
) {
10948 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
10951 if (arm_el_is_aa64(env
, 1)) {
10952 DP_TBFLAG_A32(flags
, VFPEN
, 1);
10955 if (el
< 2 && env
->cp15
.hstr_el2
&&
10956 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10957 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
10960 if (env
->uncached_cpsr
& CPSR_IL
) {
10961 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
10965 * The SME exception we are testing for is raised via
10966 * AArch64.CheckFPAdvSIMDEnabled(), as called from
10967 * AArch32.CheckAdvSIMDOrFPEnabled().
10970 && FIELD_EX64(env
->svcr
, SVCR
, SM
)
10971 && (!arm_is_el2_enabled(env
)
10972 || (arm_el_is_aa64(env
, 2) && !(env
->cp15
.hcr_el2
& HCR_TGE
)))
10973 && arm_el_is_aa64(env
, 1)
10974 && !sme_fa64(env
, el
)) {
10975 DP_TBFLAG_A32(flags
, SME_TRAP_NONSTREAMING
, 1);
10978 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
10981 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
10984 CPUARMTBFlags flags
= {};
10985 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
10986 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
10990 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
10992 /* Get control bits for tagged addresses. */
10993 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10994 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10996 DP_TBFLAG_A64(flags
, TBII
, tbii
);
10997 DP_TBFLAG_A64(flags
, TBID
, tbid
);
10999 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
11000 int sve_el
= sve_exception_el(env
, el
);
11003 * If either FP or SVE are disabled, translator does not need len.
11004 * If SVE EL > FP EL, FP exception has precedence, and translator
11005 * does not need SVE EL. Save potential re-translations by forcing
11006 * the unneeded data to zero.
11009 if (sve_el
> fp_el
) {
11012 } else if (sve_el
== 0) {
11013 DP_TBFLAG_A64(flags
, VL
, sve_vqm1_for_el(env
, el
));
11015 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
11017 if (cpu_isar_feature(aa64_sme
, env_archcpu(env
))) {
11018 int sme_el
= sme_exception_el(env
, el
);
11019 bool sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
11021 DP_TBFLAG_A64(flags
, SMEEXC_EL
, sme_el
);
11023 /* Similarly, do not compute SVL if SME is disabled. */
11024 int svl
= sve_vqm1_for_el_sm(env
, el
, true);
11025 DP_TBFLAG_A64(flags
, SVL
, svl
);
11027 /* If SVE is disabled, we will not have set VL above. */
11028 DP_TBFLAG_A64(flags
, VL
, svl
);
11032 DP_TBFLAG_A64(flags
, PSTATE_SM
, 1);
11033 DP_TBFLAG_A64(flags
, SME_TRAP_NONSTREAMING
, !sme_fa64(env
, el
));
11035 DP_TBFLAG_A64(flags
, PSTATE_ZA
, FIELD_EX64(env
->svcr
, SVCR
, ZA
));
11038 sctlr
= regime_sctlr(env
, stage1
);
11040 if (sctlr
& SCTLR_A
) {
11041 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11044 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
11045 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11048 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
11050 * In order to save space in flags, we record only whether
11051 * pauth is "inactive", meaning all insns are implemented as
11052 * a nop, or "active" when some action must be performed.
11053 * The decision of which action to take is left to a helper.
11055 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
11056 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
11060 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11061 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
11062 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
11063 DP_TBFLAG_A64(flags
, BT
, 1);
11067 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
11068 if (!(env
->pstate
& PSTATE_UAO
)) {
11070 case ARMMMUIdx_E10_1
:
11071 case ARMMMUIdx_E10_1_PAN
:
11072 case ARMMMUIdx_SE10_1
:
11073 case ARMMMUIdx_SE10_1_PAN
:
11074 /* TODO: ARMv8.3-NV */
11075 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11077 case ARMMMUIdx_E20_2
:
11078 case ARMMMUIdx_E20_2_PAN
:
11079 case ARMMMUIdx_SE20_2
:
11080 case ARMMMUIdx_SE20_2_PAN
:
11082 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
11083 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
11085 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
11086 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11094 if (env
->pstate
& PSTATE_IL
) {
11095 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11098 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
11100 * Set MTE_ACTIVE if any access may be Checked, and leave clear
11101 * if all accesses must be Unchecked:
11102 * 1) If no TBI, then there are no tags in the address to check,
11103 * 2) If Tag Check Override, then all accesses are Unchecked,
11104 * 3) If Tag Check Fail == 0, then Checked access have no effect,
11105 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
11107 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
11108 DP_TBFLAG_A64(flags
, ATA
, 1);
11110 && !(env
->pstate
& PSTATE_TCO
)
11111 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
11112 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
11115 /* And again for unprivileged accesses, if required. */
11116 if (EX_TBFLAG_A64(flags
, UNPRIV
)
11118 && !(env
->pstate
& PSTATE_TCO
)
11119 && (sctlr
& SCTLR_TCF0
)
11120 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
11121 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
11123 /* Cache TCMA as well as TBI. */
11124 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
11127 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11130 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
11132 int el
= arm_current_el(env
);
11133 int fp_el
= fp_exception_el(env
, el
);
11134 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11137 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11138 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
11139 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11141 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11145 void arm_rebuild_hflags(CPUARMState
*env
)
11147 env
->hflags
= rebuild_hflags_internal(env
);
11151 * If we have triggered a EL state change we can't rely on the
11152 * translator having passed it to us, we need to recompute.
11154 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
11156 int el
= arm_current_el(env
);
11157 int fp_el
= fp_exception_el(env
, el
);
11158 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11160 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11163 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
11165 int fp_el
= fp_exception_el(env
, el
);
11166 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11168 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11172 * If we have triggered a EL state change we can't rely on the
11173 * translator having passed it to us, we need to recompute.
11175 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
11177 int el
= arm_current_el(env
);
11178 int fp_el
= fp_exception_el(env
, el
);
11179 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11180 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11183 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
11185 int fp_el
= fp_exception_el(env
, el
);
11186 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11188 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11191 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
11193 int fp_el
= fp_exception_el(env
, el
);
11194 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11196 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11199 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
11201 #ifdef CONFIG_DEBUG_TCG
11202 CPUARMTBFlags c
= env
->hflags
;
11203 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
11205 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
11206 fprintf(stderr
, "TCG hflags mismatch "
11207 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
11208 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
11209 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
11215 static bool mve_no_pred(CPUARMState
*env
)
11218 * Return true if there is definitely no predication of MVE
11219 * instructions by VPR or LTPSIZE. (Returning false even if there
11220 * isn't any predication is OK; generated code will just be
11222 * If the CPU does not implement MVE then this TB flag is always 0.
11224 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
11225 * logic in gen_update_fp_context() needs to be updated to match.
11227 * We do not include the effect of the ECI bits here -- they are
11228 * tracked in other TB flags. This simplifies the logic for
11229 * "when did we emit code that changes the MVE_NO_PRED TB flag
11230 * and thus need to end the TB?".
11232 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
11235 if (env
->v7m
.vpr
) {
11238 if (env
->v7m
.ltpsize
< 4) {
11244 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
11245 target_ulong
*cs_base
, uint32_t *pflags
)
11247 CPUARMTBFlags flags
;
11249 assert_hflags_rebuild_correctly(env
);
11250 flags
= env
->hflags
;
11252 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
11254 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11255 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
11258 *pc
= env
->regs
[15];
11260 if (arm_feature(env
, ARM_FEATURE_M
)) {
11261 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11262 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
11263 != env
->v7m
.secure
) {
11264 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
11267 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
11268 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
11269 (env
->v7m
.secure
&&
11270 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
11272 * ASPEN is set, but FPCA/SFPA indicate that there is no
11273 * active FP context; we must create a new FP context before
11274 * executing any FP insn.
11276 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
11279 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
11280 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
11281 DP_TBFLAG_M32(flags
, LSPACT
, 1);
11284 if (mve_no_pred(env
)) {
11285 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
11289 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
11290 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
11292 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11293 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
11295 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
11296 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
11298 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
11299 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11303 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
11304 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
11308 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
11309 * states defined in the ARM ARM for software singlestep:
11310 * SS_ACTIVE PSTATE.SS State
11311 * 0 x Inactive (the TB flag for SS is always 0)
11312 * 1 0 Active-pending
11313 * 1 1 Active-not-pending
11314 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
11316 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
11317 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
11320 *pflags
= flags
.flags
;
11321 *cs_base
= flags
.flags2
;
11324 #ifdef TARGET_AARCH64
11326 * The manual says that when SVE is enabled and VQ is widened the
11327 * implementation is allowed to zero the previously inaccessible
11328 * portion of the registers. The corollary to that is that when
11329 * SVE is enabled and VQ is narrowed we are also allowed to zero
11330 * the now inaccessible portion of the registers.
11332 * The intent of this is that no predicate bit beyond VQ is ever set.
11333 * Which means that some operations on predicate registers themselves
11334 * may operate on full uint64_t or even unrolled across the maximum
11335 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
11336 * may well be cheaper than conditionals to restrict the operation
11337 * to the relevant portion of a uint16_t[16].
11339 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
11344 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
11345 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
11347 /* Zap the high bits of the zregs. */
11348 for (i
= 0; i
< 32; i
++) {
11349 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
11352 /* Zap the high bits of the pregs and ffr. */
11355 pmask
= ~(-1ULL << (16 * (vq
& 3)));
11357 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
11358 for (i
= 0; i
< 17; ++i
) {
11359 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
11365 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
11370 exc_el
= sme_exception_el(env
, el
);
11372 exc_el
= sve_exception_el(env
, el
);
11375 return 0; /* disabled */
11377 return sve_vqm1_for_el_sm(env
, el
, sm
);
11381 * Notice a change in SVE vector size when changing EL.
11383 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
11384 int new_el
, bool el0_a64
)
11386 ARMCPU
*cpu
= env_archcpu(env
);
11387 int old_len
, new_len
;
11388 bool old_a64
, new_a64
, sm
;
11390 /* Nothing to do if no SVE. */
11391 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
11395 /* Nothing to do if FP is disabled in either EL. */
11396 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
11400 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
11401 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
11404 * Both AArch64.TakeException and AArch64.ExceptionReturn
11405 * invoke ResetSVEState when taking an exception from, or
11406 * returning to, AArch32 state when PSTATE.SM is enabled.
11408 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
11409 if (old_a64
!= new_a64
&& sm
) {
11410 arm_reset_sve_state(env
);
11415 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
11416 * at ELx, or not available because the EL is in AArch32 state, then
11417 * for all purposes other than a direct read, the ZCR_ELx.LEN field
11418 * has an effective value of 0".
11420 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
11421 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
11422 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
11423 * we already have the correct register contents when encountering the
11424 * vq0->vq0 transition between EL0->EL1.
11426 old_len
= new_len
= 0;
11428 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
11431 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
11434 /* When changing vector length, clear inaccessible state. */
11435 if (new_len
< old_len
) {
11436 aarch64_sve_narrow_vq(env
, new_len
+ 1);