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ppc64: disable gen_pause() for linux-user mode
[qemu.git] / target-ppc / translate.c
blob72b67e42cf2509a0dcd616f91063c661a37f19fb
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 int le_mode;
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 int sf_mode;
205 int has_cfar;
206 #endif
207 int fpu_enabled;
208 int altivec_enabled;
209 int vsx_enabled;
210 int spe_enabled;
211 int tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_reset_fpstatus(void)
255 {
256 gen_helper_reset_fpstatus(cpu_env);
257 }
258
259 static inline void gen_compute_fprf(TCGv_i64 arg)
260 {
261 gen_helper_compute_fprf(cpu_env, arg);
262 gen_helper_float_check_status(cpu_env);
263 }
264
265 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
266 {
267 if (ctx->access_type != access_type) {
268 tcg_gen_movi_i32(cpu_access_type, access_type);
269 ctx->access_type = access_type;
270 }
271 }
272
273 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
274 {
275 if (NARROW_MODE(ctx)) {
276 nip = (uint32_t)nip;
277 }
278 tcg_gen_movi_tl(cpu_nip, nip);
279 }
280
281 void gen_update_current_nip(void *opaque)
282 {
283 DisasContext *ctx = opaque;
284
285 tcg_gen_movi_tl(cpu_nip, ctx->nip);
286 }
287
288 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
289 {
290 TCGv_i32 t0, t1;
291 if (ctx->exception == POWERPC_EXCP_NONE) {
292 gen_update_nip(ctx, ctx->nip);
293 }
294 t0 = tcg_const_i32(excp);
295 t1 = tcg_const_i32(error);
296 gen_helper_raise_exception_err(cpu_env, t0, t1);
297 tcg_temp_free_i32(t0);
298 tcg_temp_free_i32(t1);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
303 {
304 TCGv_i32 t0;
305 if (ctx->exception == POWERPC_EXCP_NONE) {
306 gen_update_nip(ctx, ctx->nip);
307 }
308 t0 = tcg_const_i32(excp);
309 gen_helper_raise_exception(cpu_env, t0);
310 tcg_temp_free_i32(t0);
311 ctx->exception = (excp);
312 }
313
314 static inline void gen_debug_exception(DisasContext *ctx)
315 {
316 TCGv_i32 t0;
317
318 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
319 (ctx->exception != POWERPC_EXCP_SYNC)) {
320 gen_update_nip(ctx, ctx->nip);
321 }
322 t0 = tcg_const_i32(EXCP_DEBUG);
323 gen_helper_raise_exception(cpu_env, t0);
324 tcg_temp_free_i32(t0);
325 }
326
327 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
328 {
329 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
330 }
331
332 /* Stop translation */
333 static inline void gen_stop_exception(DisasContext *ctx)
334 {
335 gen_update_nip(ctx, ctx->nip);
336 ctx->exception = POWERPC_EXCP_STOP;
337 }
338
339 #ifndef CONFIG_USER_ONLY
340 /* No need to update nip here, as execution flow will change */
341 static inline void gen_sync_exception(DisasContext *ctx)
342 {
343 ctx->exception = POWERPC_EXCP_SYNC;
344 }
345 #endif
346
347 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
348 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
349
350 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
351 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
352
353 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
354 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
355
356 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
357 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
358
359 typedef struct opcode_t {
360 unsigned char opc1, opc2, opc3;
361 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
362 unsigned char pad[5];
363 #else
364 unsigned char pad[1];
365 #endif
366 opc_handler_t handler;
367 const char *oname;
368 } opcode_t;
369
370 /*****************************************************************************/
371 /*** Instruction decoding ***/
372 #define EXTRACT_HELPER(name, shift, nb) \
373 static inline uint32_t name(uint32_t opcode) \
374 { \
375 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
376 }
377
378 #define EXTRACT_SHELPER(name, shift, nb) \
379 static inline int32_t name(uint32_t opcode) \
380 { \
381 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
382 }
383
384 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
385 static inline uint32_t name(uint32_t opcode) \
386 { \
387 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
388 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
389 }
390 /* Opcode part 1 */
391 EXTRACT_HELPER(opc1, 26, 6);
392 /* Opcode part 2 */
393 EXTRACT_HELPER(opc2, 1, 5);
394 /* Opcode part 3 */
395 EXTRACT_HELPER(opc3, 6, 5);
396 /* Update Cr0 flags */
397 EXTRACT_HELPER(Rc, 0, 1);
398 /* Update Cr6 flags (Altivec) */
399 EXTRACT_HELPER(Rc21, 10, 1);
400 /* Destination */
401 EXTRACT_HELPER(rD, 21, 5);
402 /* Source */
403 EXTRACT_HELPER(rS, 21, 5);
404 /* First operand */
405 EXTRACT_HELPER(rA, 16, 5);
406 /* Second operand */
407 EXTRACT_HELPER(rB, 11, 5);
408 /* Third operand */
409 EXTRACT_HELPER(rC, 6, 5);
410 /*** Get CRn ***/
411 EXTRACT_HELPER(crfD, 23, 3);
412 EXTRACT_HELPER(crfS, 18, 3);
413 EXTRACT_HELPER(crbD, 21, 5);
414 EXTRACT_HELPER(crbA, 16, 5);
415 EXTRACT_HELPER(crbB, 11, 5);
416 /* SPR / TBL */
417 EXTRACT_HELPER(_SPR, 11, 10);
418 static inline uint32_t SPR(uint32_t opcode)
419 {
420 uint32_t sprn = _SPR(opcode);
421
422 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
423 }
424 /*** Get constants ***/
425 /* 16 bits signed immediate value */
426 EXTRACT_SHELPER(SIMM, 0, 16);
427 /* 16 bits unsigned immediate value */
428 EXTRACT_HELPER(UIMM, 0, 16);
429 /* 5 bits signed immediate value */
430 EXTRACT_HELPER(SIMM5, 16, 5);
431 /* 5 bits signed immediate value */
432 EXTRACT_HELPER(UIMM5, 16, 5);
433 /* Bit count */
434 EXTRACT_HELPER(NB, 11, 5);
435 /* Shift count */
436 EXTRACT_HELPER(SH, 11, 5);
437 /* Vector shift count */
438 EXTRACT_HELPER(VSH, 6, 4);
439 /* Mask start */
440 EXTRACT_HELPER(MB, 6, 5);
441 /* Mask end */
442 EXTRACT_HELPER(ME, 1, 5);
443 /* Trap operand */
444 EXTRACT_HELPER(TO, 21, 5);
445
446 EXTRACT_HELPER(CRM, 12, 8);
447
448 #ifndef CONFIG_USER_ONLY
449 EXTRACT_HELPER(SR, 16, 4);
450 #endif
451
452 /* mtfsf/mtfsfi */
453 EXTRACT_HELPER(FPBF, 23, 3);
454 EXTRACT_HELPER(FPIMM, 12, 4);
455 EXTRACT_HELPER(FPL, 25, 1);
456 EXTRACT_HELPER(FPFLM, 17, 8);
457 EXTRACT_HELPER(FPW, 16, 1);
458
459 /*** Jump target decoding ***/
460 /* Immediate address */
461 static inline target_ulong LI(uint32_t opcode)
462 {
463 return (opcode >> 0) & 0x03FFFFFC;
464 }
465
466 static inline uint32_t BD(uint32_t opcode)
467 {
468 return (opcode >> 0) & 0xFFFC;
469 }
470
471 EXTRACT_HELPER(BO, 21, 5);
472 EXTRACT_HELPER(BI, 16, 5);
473 /* Absolute/relative address */
474 EXTRACT_HELPER(AA, 1, 1);
475 /* Link */
476 EXTRACT_HELPER(LK, 0, 1);
477
478 /* DFP Z22-form */
479 EXTRACT_HELPER(DCM, 10, 6)
480
481 /* DFP Z23-form */
482 EXTRACT_HELPER(RMC, 9, 2)
483
484 /* Create a mask between <start> and <end> bits */
485 static inline target_ulong MASK(uint32_t start, uint32_t end)
486 {
487 target_ulong ret;
488
489 #if defined(TARGET_PPC64)
490 if (likely(start == 0)) {
491 ret = UINT64_MAX << (63 - end);
492 } else if (likely(end == 63)) {
493 ret = UINT64_MAX >> start;
494 }
495 #else
496 if (likely(start == 0)) {
497 ret = UINT32_MAX << (31 - end);
498 } else if (likely(end == 31)) {
499 ret = UINT32_MAX >> start;
500 }
501 #endif
502 else {
503 ret = (((target_ulong)(-1ULL)) >> (start)) ^
504 (((target_ulong)(-1ULL) >> (end)) >> 1);
505 if (unlikely(start > end))
506 return ~ret;
507 }
508
509 return ret;
510 }
511
512 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
513 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
514 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
515 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
516 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
517 EXTRACT_HELPER(DM, 8, 2);
518 EXTRACT_HELPER(UIM, 16, 2);
519 EXTRACT_HELPER(SHW, 8, 2);
520 EXTRACT_HELPER(SP, 19, 2);
521 /*****************************************************************************/
522 /* PowerPC instructions table */
523
524 #if defined(DO_PPC_STATISTICS)
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 .oname = stringify(name), \
537 }, \
538 .oname = stringify(name), \
539 }
540 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
541 { \
542 .opc1 = op1, \
543 .opc2 = op2, \
544 .opc3 = op3, \
545 .pad = { 0, }, \
546 .handler = { \
547 .inval1 = invl1, \
548 .inval2 = invl2, \
549 .type = _typ, \
550 .type2 = _typ2, \
551 .handler = &gen_##name, \
552 .oname = stringify(name), \
553 }, \
554 .oname = stringify(name), \
555 }
556 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
557 { \
558 .opc1 = op1, \
559 .opc2 = op2, \
560 .opc3 = op3, \
561 .pad = { 0, }, \
562 .handler = { \
563 .inval1 = invl, \
564 .type = _typ, \
565 .type2 = _typ2, \
566 .handler = &gen_##name, \
567 .oname = onam, \
568 }, \
569 .oname = onam, \
570 }
571 #else
572 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
573 { \
574 .opc1 = op1, \
575 .opc2 = op2, \
576 .opc3 = op3, \
577 .pad = { 0, }, \
578 .handler = { \
579 .inval1 = invl, \
580 .type = _typ, \
581 .type2 = _typ2, \
582 .handler = &gen_##name, \
583 }, \
584 .oname = stringify(name), \
585 }
586 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
587 { \
588 .opc1 = op1, \
589 .opc2 = op2, \
590 .opc3 = op3, \
591 .pad = { 0, }, \
592 .handler = { \
593 .inval1 = invl1, \
594 .inval2 = invl2, \
595 .type = _typ, \
596 .type2 = _typ2, \
597 .handler = &gen_##name, \
598 }, \
599 .oname = stringify(name), \
600 }
601 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
602 { \
603 .opc1 = op1, \
604 .opc2 = op2, \
605 .opc3 = op3, \
606 .pad = { 0, }, \
607 .handler = { \
608 .inval1 = invl, \
609 .type = _typ, \
610 .type2 = _typ2, \
611 .handler = &gen_##name, \
612 }, \
613 .oname = onam, \
614 }
615 #endif
616
617 /* SPR load/store helpers */
618 static inline void gen_load_spr(TCGv t, int reg)
619 {
620 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
621 }
622
623 static inline void gen_store_spr(int reg, TCGv t)
624 {
625 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
626 }
627
628 /* Invalid instruction */
629 static void gen_invalid(DisasContext *ctx)
630 {
631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
632 }
633
634 static opc_handler_t invalid_handler = {
635 .inval1 = 0xFFFFFFFF,
636 .inval2 = 0xFFFFFFFF,
637 .type = PPC_NONE,
638 .type2 = PPC_NONE,
639 .handler = gen_invalid,
640 };
641
642 /*** Integer comparison ***/
643
644 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
645 {
646 TCGv t0 = tcg_temp_new();
647 TCGv_i32 t1 = tcg_temp_new_i32();
648
649 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
650
651 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
652 tcg_gen_trunc_tl_i32(t1, t0);
653 tcg_gen_shli_i32(t1, t1, CRF_LT);
654 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
655
656 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
657 tcg_gen_trunc_tl_i32(t1, t0);
658 tcg_gen_shli_i32(t1, t1, CRF_GT);
659 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
660
661 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
662 tcg_gen_trunc_tl_i32(t1, t0);
663 tcg_gen_shli_i32(t1, t1, CRF_EQ);
664 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
665
666 tcg_temp_free(t0);
667 tcg_temp_free_i32(t1);
668 }
669
670 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
671 {
672 TCGv t0 = tcg_const_tl(arg1);
673 gen_op_cmp(arg0, t0, s, crf);
674 tcg_temp_free(t0);
675 }
676
677 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
678 {
679 TCGv t0, t1;
680 t0 = tcg_temp_new();
681 t1 = tcg_temp_new();
682 if (s) {
683 tcg_gen_ext32s_tl(t0, arg0);
684 tcg_gen_ext32s_tl(t1, arg1);
685 } else {
686 tcg_gen_ext32u_tl(t0, arg0);
687 tcg_gen_ext32u_tl(t1, arg1);
688 }
689 gen_op_cmp(t0, t1, s, crf);
690 tcg_temp_free(t1);
691 tcg_temp_free(t0);
692 }
693
694 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
695 {
696 TCGv t0 = tcg_const_tl(arg1);
697 gen_op_cmp32(arg0, t0, s, crf);
698 tcg_temp_free(t0);
699 }
700
701 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
702 {
703 if (NARROW_MODE(ctx)) {
704 gen_op_cmpi32(reg, 0, 1, 0);
705 } else {
706 gen_op_cmpi(reg, 0, 1, 0);
707 }
708 }
709
710 /* cmp */
711 static void gen_cmp(DisasContext *ctx)
712 {
713 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
714 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
715 1, crfD(ctx->opcode));
716 } else {
717 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
718 1, crfD(ctx->opcode));
719 }
720 }
721
722 /* cmpi */
723 static void gen_cmpi(DisasContext *ctx)
724 {
725 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
726 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
727 1, crfD(ctx->opcode));
728 } else {
729 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
730 1, crfD(ctx->opcode));
731 }
732 }
733
734 /* cmpl */
735 static void gen_cmpl(DisasContext *ctx)
736 {
737 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
738 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
739 0, crfD(ctx->opcode));
740 } else {
741 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
742 0, crfD(ctx->opcode));
743 }
744 }
745
746 /* cmpli */
747 static void gen_cmpli(DisasContext *ctx)
748 {
749 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
750 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
751 0, crfD(ctx->opcode));
752 } else {
753 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
754 0, crfD(ctx->opcode));
755 }
756 }
757
758 /* isel (PowerPC 2.03 specification) */
759 static void gen_isel(DisasContext *ctx)
760 {
761 uint32_t bi = rC(ctx->opcode);
762 uint32_t mask = 0x08 >> (bi & 0x03);
763 TCGv t0 = tcg_temp_new();
764 TCGv zr;
765
766 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
767 tcg_gen_andi_tl(t0, t0, mask);
768
769 zr = tcg_const_tl(0);
770 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
771 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
772 cpu_gpr[rB(ctx->opcode)]);
773 tcg_temp_free(zr);
774 tcg_temp_free(t0);
775 }
776
777 /* cmpb: PowerPC 2.05 specification */
778 static void gen_cmpb(DisasContext *ctx)
779 {
780 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
781 cpu_gpr[rB(ctx->opcode)]);
782 }
783
784 /*** Integer arithmetic ***/
785
786 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
787 TCGv arg1, TCGv arg2, int sub)
788 {
789 TCGv t0 = tcg_temp_new();
790
791 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
792 tcg_gen_xor_tl(t0, arg1, arg2);
793 if (sub) {
794 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
795 } else {
796 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
797 }
798 tcg_temp_free(t0);
799 if (NARROW_MODE(ctx)) {
800 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
801 }
802 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
803 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
804 }
805
806 /* Common add function */
807 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
808 TCGv arg2, bool add_ca, bool compute_ca,
809 bool compute_ov, bool compute_rc0)
810 {
811 TCGv t0 = ret;
812
813 if (compute_ca || compute_ov) {
814 t0 = tcg_temp_new();
815 }
816
817 if (compute_ca) {
818 if (NARROW_MODE(ctx)) {
819 /* Caution: a non-obvious corner case of the spec is that we
820 must produce the *entire* 64-bit addition, but produce the
821 carry into bit 32. */
822 TCGv t1 = tcg_temp_new();
823 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
824 tcg_gen_add_tl(t0, arg1, arg2);
825 if (add_ca) {
826 tcg_gen_add_tl(t0, t0, cpu_ca);
827 }
828 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
829 tcg_temp_free(t1);
830 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
831 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
832 } else {
833 TCGv zero = tcg_const_tl(0);
834 if (add_ca) {
835 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
836 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
837 } else {
838 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
839 }
840 tcg_temp_free(zero);
841 }
842 } else {
843 tcg_gen_add_tl(t0, arg1, arg2);
844 if (add_ca) {
845 tcg_gen_add_tl(t0, t0, cpu_ca);
846 }
847 }
848
849 if (compute_ov) {
850 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
851 }
852 if (unlikely(compute_rc0)) {
853 gen_set_Rc0(ctx, t0);
854 }
855
856 if (!TCGV_EQUAL(t0, ret)) {
857 tcg_gen_mov_tl(ret, t0);
858 tcg_temp_free(t0);
859 }
860 }
861 /* Add functions with two operands */
862 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
863 static void glue(gen_, name)(DisasContext *ctx) \
864 { \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
867 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 }
869 /* Add functions with one operand and one immediate */
870 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
871 add_ca, compute_ca, compute_ov) \
872 static void glue(gen_, name)(DisasContext *ctx) \
873 { \
874 TCGv t0 = tcg_const_tl(const_val); \
875 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
876 cpu_gpr[rA(ctx->opcode)], t0, \
877 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
878 tcg_temp_free(t0); \
879 }
880
881 /* add add. addo addo. */
882 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
883 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
884 /* addc addc. addco addco. */
885 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
886 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
887 /* adde adde. addeo addeo. */
888 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
889 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
890 /* addme addme. addmeo addmeo. */
891 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
892 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
893 /* addze addze. addzeo addzeo.*/
894 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
895 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
896 /* addi */
897 static void gen_addi(DisasContext *ctx)
898 {
899 target_long simm = SIMM(ctx->opcode);
900
901 if (rA(ctx->opcode) == 0) {
902 /* li case */
903 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
904 } else {
905 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
906 cpu_gpr[rA(ctx->opcode)], simm);
907 }
908 }
909 /* addic addic.*/
910 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
911 {
912 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
913 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
914 c, 0, 1, 0, compute_rc0);
915 tcg_temp_free(c);
916 }
917
918 static void gen_addic(DisasContext *ctx)
919 {
920 gen_op_addic(ctx, 0);
921 }
922
923 static void gen_addic_(DisasContext *ctx)
924 {
925 gen_op_addic(ctx, 1);
926 }
927
928 /* addis */
929 static void gen_addis(DisasContext *ctx)
930 {
931 target_long simm = SIMM(ctx->opcode);
932
933 if (rA(ctx->opcode) == 0) {
934 /* lis case */
935 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
936 } else {
937 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
938 cpu_gpr[rA(ctx->opcode)], simm << 16);
939 }
940 }
941
942 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
943 TCGv arg2, int sign, int compute_ov)
944 {
945 TCGLabel *l1 = gen_new_label();
946 TCGLabel *l2 = gen_new_label();
947 TCGv_i32 t0 = tcg_temp_local_new_i32();
948 TCGv_i32 t1 = tcg_temp_local_new_i32();
949
950 tcg_gen_trunc_tl_i32(t0, arg1);
951 tcg_gen_trunc_tl_i32(t1, arg2);
952 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
953 if (sign) {
954 TCGLabel *l3 = gen_new_label();
955 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
956 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
957 gen_set_label(l3);
958 tcg_gen_div_i32(t0, t0, t1);
959 } else {
960 tcg_gen_divu_i32(t0, t0, t1);
961 }
962 if (compute_ov) {
963 tcg_gen_movi_tl(cpu_ov, 0);
964 }
965 tcg_gen_br(l2);
966 gen_set_label(l1);
967 if (sign) {
968 tcg_gen_sari_i32(t0, t0, 31);
969 } else {
970 tcg_gen_movi_i32(t0, 0);
971 }
972 if (compute_ov) {
973 tcg_gen_movi_tl(cpu_ov, 1);
974 tcg_gen_movi_tl(cpu_so, 1);
975 }
976 gen_set_label(l2);
977 tcg_gen_extu_i32_tl(ret, t0);
978 tcg_temp_free_i32(t0);
979 tcg_temp_free_i32(t1);
980 if (unlikely(Rc(ctx->opcode) != 0))
981 gen_set_Rc0(ctx, ret);
982 }
983 /* Div functions */
984 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
985 static void glue(gen_, name)(DisasContext *ctx) \
986 { \
987 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
988 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
989 sign, compute_ov); \
990 }
991 /* divwu divwu. divwuo divwuo. */
992 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
993 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
994 /* divw divw. divwo divwo. */
995 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
996 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
997
998 /* div[wd]eu[o][.] */
999 #define GEN_DIVE(name, hlpr, compute_ov) \
1000 static void gen_##name(DisasContext *ctx) \
1001 { \
1002 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1003 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1004 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1005 tcg_temp_free_i32(t0); \
1006 if (unlikely(Rc(ctx->opcode) != 0)) { \
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1008 } \
1009 }
1010
1011 GEN_DIVE(divweu, divweu, 0);
1012 GEN_DIVE(divweuo, divweu, 1);
1013 GEN_DIVE(divwe, divwe, 0);
1014 GEN_DIVE(divweo, divwe, 1);
1015
1016 #if defined(TARGET_PPC64)
1017 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1018 TCGv arg2, int sign, int compute_ov)
1019 {
1020 TCGLabel *l1 = gen_new_label();
1021 TCGLabel *l2 = gen_new_label();
1022
1023 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1024 if (sign) {
1025 TCGLabel *l3 = gen_new_label();
1026 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1027 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1028 gen_set_label(l3);
1029 tcg_gen_div_i64(ret, arg1, arg2);
1030 } else {
1031 tcg_gen_divu_i64(ret, arg1, arg2);
1032 }
1033 if (compute_ov) {
1034 tcg_gen_movi_tl(cpu_ov, 0);
1035 }
1036 tcg_gen_br(l2);
1037 gen_set_label(l1);
1038 if (sign) {
1039 tcg_gen_sari_i64(ret, arg1, 63);
1040 } else {
1041 tcg_gen_movi_i64(ret, 0);
1042 }
1043 if (compute_ov) {
1044 tcg_gen_movi_tl(cpu_ov, 1);
1045 tcg_gen_movi_tl(cpu_so, 1);
1046 }
1047 gen_set_label(l2);
1048 if (unlikely(Rc(ctx->opcode) != 0))
1049 gen_set_Rc0(ctx, ret);
1050 }
1051 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1052 static void glue(gen_, name)(DisasContext *ctx) \
1053 { \
1054 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1055 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1056 sign, compute_ov); \
1057 }
1058 /* divwu divwu. divwuo divwuo. */
1059 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1060 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1061 /* divw divw. divwo divwo. */
1062 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1063 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1064
1065 GEN_DIVE(divdeu, divdeu, 0);
1066 GEN_DIVE(divdeuo, divdeu, 1);
1067 GEN_DIVE(divde, divde, 0);
1068 GEN_DIVE(divdeo, divde, 1);
1069 #endif
1070
1071 /* mulhw mulhw. */
1072 static void gen_mulhw(DisasContext *ctx)
1073 {
1074 TCGv_i32 t0 = tcg_temp_new_i32();
1075 TCGv_i32 t1 = tcg_temp_new_i32();
1076
1077 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1078 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1079 tcg_gen_muls2_i32(t0, t1, t0, t1);
1080 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1081 tcg_temp_free_i32(t0);
1082 tcg_temp_free_i32(t1);
1083 if (unlikely(Rc(ctx->opcode) != 0))
1084 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1085 }
1086
1087 /* mulhwu mulhwu. */
1088 static void gen_mulhwu(DisasContext *ctx)
1089 {
1090 TCGv_i32 t0 = tcg_temp_new_i32();
1091 TCGv_i32 t1 = tcg_temp_new_i32();
1092
1093 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1094 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1095 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1096 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1097 tcg_temp_free_i32(t0);
1098 tcg_temp_free_i32(t1);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mullw mullw. */
1104 static void gen_mullw(DisasContext *ctx)
1105 {
1106 #if defined(TARGET_PPC64)
1107 TCGv_i64 t0, t1;
1108 t0 = tcg_temp_new_i64();
1109 t1 = tcg_temp_new_i64();
1110 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1111 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1112 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1113 tcg_temp_free(t0);
1114 tcg_temp_free(t1);
1115 #else
1116 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1117 cpu_gpr[rB(ctx->opcode)]);
1118 #endif
1119 if (unlikely(Rc(ctx->opcode) != 0))
1120 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1121 }
1122
1123 /* mullwo mullwo. */
1124 static void gen_mullwo(DisasContext *ctx)
1125 {
1126 TCGv_i32 t0 = tcg_temp_new_i32();
1127 TCGv_i32 t1 = tcg_temp_new_i32();
1128
1129 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1130 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1131 tcg_gen_muls2_i32(t0, t1, t0, t1);
1132 #if defined(TARGET_PPC64)
1133 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1134 #else
1135 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1136 #endif
1137
1138 tcg_gen_sari_i32(t0, t0, 31);
1139 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1140 tcg_gen_extu_i32_tl(cpu_ov, t0);
1141 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1142
1143 tcg_temp_free_i32(t0);
1144 tcg_temp_free_i32(t1);
1145 if (unlikely(Rc(ctx->opcode) != 0))
1146 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1147 }
1148
1149 /* mulli */
1150 static void gen_mulli(DisasContext *ctx)
1151 {
1152 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1153 SIMM(ctx->opcode));
1154 }
1155
1156 #if defined(TARGET_PPC64)
1157 /* mulhd mulhd. */
1158 static void gen_mulhd(DisasContext *ctx)
1159 {
1160 TCGv lo = tcg_temp_new();
1161 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1162 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1163 tcg_temp_free(lo);
1164 if (unlikely(Rc(ctx->opcode) != 0)) {
1165 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1166 }
1167 }
1168
1169 /* mulhdu mulhdu. */
1170 static void gen_mulhdu(DisasContext *ctx)
1171 {
1172 TCGv lo = tcg_temp_new();
1173 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1174 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1175 tcg_temp_free(lo);
1176 if (unlikely(Rc(ctx->opcode) != 0)) {
1177 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1178 }
1179 }
1180
1181 /* mulld mulld. */
1182 static void gen_mulld(DisasContext *ctx)
1183 {
1184 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1185 cpu_gpr[rB(ctx->opcode)]);
1186 if (unlikely(Rc(ctx->opcode) != 0))
1187 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1188 }
1189
1190 /* mulldo mulldo. */
1191 static void gen_mulldo(DisasContext *ctx)
1192 {
1193 TCGv_i64 t0 = tcg_temp_new_i64();
1194 TCGv_i64 t1 = tcg_temp_new_i64();
1195
1196 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1197 cpu_gpr[rB(ctx->opcode)]);
1198 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1199
1200 tcg_gen_sari_i64(t0, t0, 63);
1201 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1202 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1203
1204 tcg_temp_free_i64(t0);
1205 tcg_temp_free_i64(t1);
1206
1207 if (unlikely(Rc(ctx->opcode) != 0)) {
1208 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1209 }
1210 }
1211 #endif
1212
1213 /* Common subf function */
1214 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1215 TCGv arg2, bool add_ca, bool compute_ca,
1216 bool compute_ov, bool compute_rc0)
1217 {
1218 TCGv t0 = ret;
1219
1220 if (compute_ca || compute_ov) {
1221 t0 = tcg_temp_new();
1222 }
1223
1224 if (compute_ca) {
1225 /* dest = ~arg1 + arg2 [+ ca]. */
1226 if (NARROW_MODE(ctx)) {
1227 /* Caution: a non-obvious corner case of the spec is that we
1228 must produce the *entire* 64-bit addition, but produce the
1229 carry into bit 32. */
1230 TCGv inv1 = tcg_temp_new();
1231 TCGv t1 = tcg_temp_new();
1232 tcg_gen_not_tl(inv1, arg1);
1233 if (add_ca) {
1234 tcg_gen_add_tl(t0, arg2, cpu_ca);
1235 } else {
1236 tcg_gen_addi_tl(t0, arg2, 1);
1237 }
1238 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1239 tcg_gen_add_tl(t0, t0, inv1);
1240 tcg_temp_free(inv1);
1241 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1242 tcg_temp_free(t1);
1243 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1244 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1245 } else if (add_ca) {
1246 TCGv zero, inv1 = tcg_temp_new();
1247 tcg_gen_not_tl(inv1, arg1);
1248 zero = tcg_const_tl(0);
1249 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1250 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1251 tcg_temp_free(zero);
1252 tcg_temp_free(inv1);
1253 } else {
1254 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1255 tcg_gen_sub_tl(t0, arg2, arg1);
1256 }
1257 } else if (add_ca) {
1258 /* Since we're ignoring carry-out, we can simplify the
1259 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1260 tcg_gen_sub_tl(t0, arg2, arg1);
1261 tcg_gen_add_tl(t0, t0, cpu_ca);
1262 tcg_gen_subi_tl(t0, t0, 1);
1263 } else {
1264 tcg_gen_sub_tl(t0, arg2, arg1);
1265 }
1266
1267 if (compute_ov) {
1268 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1269 }
1270 if (unlikely(compute_rc0)) {
1271 gen_set_Rc0(ctx, t0);
1272 }
1273
1274 if (!TCGV_EQUAL(t0, ret)) {
1275 tcg_gen_mov_tl(ret, t0);
1276 tcg_temp_free(t0);
1277 }
1278 }
1279 /* Sub functions with Two operands functions */
1280 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1281 static void glue(gen_, name)(DisasContext *ctx) \
1282 { \
1283 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1284 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1285 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1286 }
1287 /* Sub functions with one operand and one immediate */
1288 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1289 add_ca, compute_ca, compute_ov) \
1290 static void glue(gen_, name)(DisasContext *ctx) \
1291 { \
1292 TCGv t0 = tcg_const_tl(const_val); \
1293 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1294 cpu_gpr[rA(ctx->opcode)], t0, \
1295 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1296 tcg_temp_free(t0); \
1297 }
1298 /* subf subf. subfo subfo. */
1299 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1300 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1301 /* subfc subfc. subfco subfco. */
1302 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1303 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1304 /* subfe subfe. subfeo subfo. */
1305 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1306 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1307 /* subfme subfme. subfmeo subfmeo. */
1308 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1309 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1310 /* subfze subfze. subfzeo subfzeo.*/
1311 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1312 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1313
1314 /* subfic */
1315 static void gen_subfic(DisasContext *ctx)
1316 {
1317 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1318 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1319 c, 0, 1, 0, 0);
1320 tcg_temp_free(c);
1321 }
1322
1323 /* neg neg. nego nego. */
1324 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1325 {
1326 TCGv zero = tcg_const_tl(0);
1327 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1328 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1329 tcg_temp_free(zero);
1330 }
1331
1332 static void gen_neg(DisasContext *ctx)
1333 {
1334 gen_op_arith_neg(ctx, 0);
1335 }
1336
1337 static void gen_nego(DisasContext *ctx)
1338 {
1339 gen_op_arith_neg(ctx, 1);
1340 }
1341
1342 /*** Integer logical ***/
1343 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1344 static void glue(gen_, name)(DisasContext *ctx) \
1345 { \
1346 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1347 cpu_gpr[rB(ctx->opcode)]); \
1348 if (unlikely(Rc(ctx->opcode) != 0)) \
1349 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1350 }
1351
1352 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1353 static void glue(gen_, name)(DisasContext *ctx) \
1354 { \
1355 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1356 if (unlikely(Rc(ctx->opcode) != 0)) \
1357 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1358 }
1359
1360 /* and & and. */
1361 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1362 /* andc & andc. */
1363 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1364
1365 /* andi. */
1366 static void gen_andi_(DisasContext *ctx)
1367 {
1368 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1369 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1370 }
1371
1372 /* andis. */
1373 static void gen_andis_(DisasContext *ctx)
1374 {
1375 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1376 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1377 }
1378
1379 /* cntlzw */
1380 static void gen_cntlzw(DisasContext *ctx)
1381 {
1382 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1383 if (unlikely(Rc(ctx->opcode) != 0))
1384 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1385 }
1386 /* eqv & eqv. */
1387 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1388 /* extsb & extsb. */
1389 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1390 /* extsh & extsh. */
1391 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1392 /* nand & nand. */
1393 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1394 /* nor & nor. */
1395 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1396
1397 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1398 static void gen_pause(DisasContext *ctx)
1399 {
1400 TCGv_i32 t0 = tcg_const_i32(0);
1401 tcg_gen_st_i32(t0, cpu_env,
1402 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1403 tcg_temp_free_i32(t0);
1404
1405 /* Stop translation, this gives other CPUs a chance to run */
1406 gen_exception_err(ctx, EXCP_HLT, 1);
1407 }
1408 #endif /* defined(TARGET_PPC64) */
1409
1410 /* or & or. */
1411 static void gen_or(DisasContext *ctx)
1412 {
1413 int rs, ra, rb;
1414
1415 rs = rS(ctx->opcode);
1416 ra = rA(ctx->opcode);
1417 rb = rB(ctx->opcode);
1418 /* Optimisation for mr. ri case */
1419 if (rs != ra || rs != rb) {
1420 if (rs != rb)
1421 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1422 else
1423 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1424 if (unlikely(Rc(ctx->opcode) != 0))
1425 gen_set_Rc0(ctx, cpu_gpr[ra]);
1426 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1427 gen_set_Rc0(ctx, cpu_gpr[rs]);
1428 #if defined(TARGET_PPC64)
1429 } else {
1430 int prio = 0;
1431
1432 switch (rs) {
1433 case 1:
1434 /* Set process priority to low */
1435 prio = 2;
1436 break;
1437 case 6:
1438 /* Set process priority to medium-low */
1439 prio = 3;
1440 break;
1441 case 2:
1442 /* Set process priority to normal */
1443 prio = 4;
1444 break;
1445 #if !defined(CONFIG_USER_ONLY)
1446 case 31:
1447 if (!ctx->pr) {
1448 /* Set process priority to very low */
1449 prio = 1;
1450 }
1451 break;
1452 case 5:
1453 if (!ctx->pr) {
1454 /* Set process priority to medium-hight */
1455 prio = 5;
1456 }
1457 break;
1458 case 3:
1459 if (!ctx->pr) {
1460 /* Set process priority to high */
1461 prio = 6;
1462 }
1463 break;
1464 case 7:
1465 if (ctx->hv && !ctx->pr) {
1466 /* Set process priority to very high */
1467 prio = 7;
1468 }
1469 break;
1470 #endif
1471 default:
1472 /* nop */
1473 break;
1474 }
1475 if (prio) {
1476 TCGv t0 = tcg_temp_new();
1477 gen_load_spr(t0, SPR_PPR);
1478 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1479 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1480 gen_store_spr(SPR_PPR, t0);
1481 tcg_temp_free(t0);
1482 /* Pause us out of TCG otherwise spin loops with smt_low
1483 * eat too much CPU and the kernel hangs
1484 */
1485 #if !defined(CONFIG_USER_ONLY)
1486 gen_pause(ctx);
1487 #endif
1488 }
1489 #endif
1490 }
1491 }
1492 /* orc & orc. */
1493 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1494
1495 /* xor & xor. */
1496 static void gen_xor(DisasContext *ctx)
1497 {
1498 /* Optimisation for "set to zero" case */
1499 if (rS(ctx->opcode) != rB(ctx->opcode))
1500 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1501 else
1502 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1503 if (unlikely(Rc(ctx->opcode) != 0))
1504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1505 }
1506
1507 /* ori */
1508 static void gen_ori(DisasContext *ctx)
1509 {
1510 target_ulong uimm = UIMM(ctx->opcode);
1511
1512 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1513 return;
1514 }
1515 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1516 }
1517
1518 /* oris */
1519 static void gen_oris(DisasContext *ctx)
1520 {
1521 target_ulong uimm = UIMM(ctx->opcode);
1522
1523 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1524 /* NOP */
1525 return;
1526 }
1527 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1528 }
1529
1530 /* xori */
1531 static void gen_xori(DisasContext *ctx)
1532 {
1533 target_ulong uimm = UIMM(ctx->opcode);
1534
1535 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1536 /* NOP */
1537 return;
1538 }
1539 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1540 }
1541
1542 /* xoris */
1543 static void gen_xoris(DisasContext *ctx)
1544 {
1545 target_ulong uimm = UIMM(ctx->opcode);
1546
1547 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1548 /* NOP */
1549 return;
1550 }
1551 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1552 }
1553
1554 /* popcntb : PowerPC 2.03 specification */
1555 static void gen_popcntb(DisasContext *ctx)
1556 {
1557 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1558 }
1559
1560 static void gen_popcntw(DisasContext *ctx)
1561 {
1562 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1563 }
1564
1565 #if defined(TARGET_PPC64)
1566 /* popcntd: PowerPC 2.06 specification */
1567 static void gen_popcntd(DisasContext *ctx)
1568 {
1569 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1570 }
1571 #endif
1572
1573 /* prtyw: PowerPC 2.05 specification */
1574 static void gen_prtyw(DisasContext *ctx)
1575 {
1576 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1577 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1578 TCGv t0 = tcg_temp_new();
1579 tcg_gen_shri_tl(t0, rs, 16);
1580 tcg_gen_xor_tl(ra, rs, t0);
1581 tcg_gen_shri_tl(t0, ra, 8);
1582 tcg_gen_xor_tl(ra, ra, t0);
1583 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1584 tcg_temp_free(t0);
1585 }
1586
1587 #if defined(TARGET_PPC64)
1588 /* prtyd: PowerPC 2.05 specification */
1589 static void gen_prtyd(DisasContext *ctx)
1590 {
1591 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1592 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1593 TCGv t0 = tcg_temp_new();
1594 tcg_gen_shri_tl(t0, rs, 32);
1595 tcg_gen_xor_tl(ra, rs, t0);
1596 tcg_gen_shri_tl(t0, ra, 16);
1597 tcg_gen_xor_tl(ra, ra, t0);
1598 tcg_gen_shri_tl(t0, ra, 8);
1599 tcg_gen_xor_tl(ra, ra, t0);
1600 tcg_gen_andi_tl(ra, ra, 1);
1601 tcg_temp_free(t0);
1602 }
1603 #endif
1604
1605 #if defined(TARGET_PPC64)
1606 /* bpermd */
1607 static void gen_bpermd(DisasContext *ctx)
1608 {
1609 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1610 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1611 }
1612 #endif
1613
1614 #if defined(TARGET_PPC64)
1615 /* extsw & extsw. */
1616 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1617
1618 /* cntlzd */
1619 static void gen_cntlzd(DisasContext *ctx)
1620 {
1621 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1622 if (unlikely(Rc(ctx->opcode) != 0))
1623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1624 }
1625 #endif
1626
1627 /*** Integer rotate ***/
1628
1629 /* rlwimi & rlwimi. */
1630 static void gen_rlwimi(DisasContext *ctx)
1631 {
1632 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1633 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1634 uint32_t sh = SH(ctx->opcode);
1635 uint32_t mb = MB(ctx->opcode);
1636 uint32_t me = ME(ctx->opcode);
1637
1638 if (sh == (31-me) && mb <= me) {
1639 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1640 } else {
1641 target_ulong mask;
1642 TCGv t1;
1643
1644 #if defined(TARGET_PPC64)
1645 mb += 32;
1646 me += 32;
1647 #endif
1648 mask = MASK(mb, me);
1649
1650 t1 = tcg_temp_new();
1651 if (mask <= 0xffffffffu) {
1652 TCGv_i32 t0 = tcg_temp_new_i32();
1653 tcg_gen_trunc_tl_i32(t0, t_rs);
1654 tcg_gen_rotli_i32(t0, t0, sh);
1655 tcg_gen_extu_i32_tl(t1, t0);
1656 tcg_temp_free_i32(t0);
1657 } else {
1658 #if defined(TARGET_PPC64)
1659 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1660 tcg_gen_rotli_i64(t1, t1, sh);
1661 #else
1662 g_assert_not_reached();
1663 #endif
1664 }
1665
1666 tcg_gen_andi_tl(t1, t1, mask);
1667 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1668 tcg_gen_or_tl(t_ra, t_ra, t1);
1669 tcg_temp_free(t1);
1670 }
1671 if (unlikely(Rc(ctx->opcode) != 0)) {
1672 gen_set_Rc0(ctx, t_ra);
1673 }
1674 }
1675
1676 /* rlwinm & rlwinm. */
1677 static void gen_rlwinm(DisasContext *ctx)
1678 {
1679 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1680 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1681 uint32_t sh = SH(ctx->opcode);
1682 uint32_t mb = MB(ctx->opcode);
1683 uint32_t me = ME(ctx->opcode);
1684
1685 if (mb == 0 && me == (31 - sh)) {
1686 tcg_gen_shli_tl(t_ra, t_rs, sh);
1687 tcg_gen_ext32u_tl(t_ra, t_ra);
1688 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1689 tcg_gen_ext32u_tl(t_ra, t_rs);
1690 tcg_gen_shri_tl(t_ra, t_ra, mb);
1691 } else {
1692 target_ulong mask;
1693 #if defined(TARGET_PPC64)
1694 mb += 32;
1695 me += 32;
1696 #endif
1697 mask = MASK(mb, me);
1698
1699 if (sh == 0) {
1700 tcg_gen_andi_tl(t_ra, t_rs, mask);
1701 } else if (mask <= 0xffffffffu) {
1702 TCGv_i32 t0 = tcg_temp_new_i32();
1703 tcg_gen_trunc_tl_i32(t0, t_rs);
1704 tcg_gen_rotli_i32(t0, t0, sh);
1705 tcg_gen_andi_i32(t0, t0, mask);
1706 tcg_gen_extu_i32_tl(t_ra, t0);
1707 tcg_temp_free_i32(t0);
1708 } else {
1709 #if defined(TARGET_PPC64)
1710 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1711 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1712 tcg_gen_andi_i64(t_ra, t_ra, mask);
1713 #else
1714 g_assert_not_reached();
1715 #endif
1716 }
1717 }
1718 if (unlikely(Rc(ctx->opcode) != 0)) {
1719 gen_set_Rc0(ctx, t_ra);
1720 }
1721 }
1722
1723 /* rlwnm & rlwnm. */
1724 static void gen_rlwnm(DisasContext *ctx)
1725 {
1726 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1727 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1728 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1729 uint32_t mb = MB(ctx->opcode);
1730 uint32_t me = ME(ctx->opcode);
1731 target_ulong mask;
1732
1733 #if defined(TARGET_PPC64)
1734 mb += 32;
1735 me += 32;
1736 #endif
1737 mask = MASK(mb, me);
1738
1739 if (mask <= 0xffffffffu) {
1740 TCGv_i32 t0 = tcg_temp_new_i32();
1741 TCGv_i32 t1 = tcg_temp_new_i32();
1742 tcg_gen_trunc_tl_i32(t0, t_rb);
1743 tcg_gen_trunc_tl_i32(t1, t_rs);
1744 tcg_gen_andi_i32(t0, t0, 0x1f);
1745 tcg_gen_rotl_i32(t1, t1, t0);
1746 tcg_gen_extu_i32_tl(t_ra, t1);
1747 tcg_temp_free_i32(t0);
1748 tcg_temp_free_i32(t1);
1749 } else {
1750 #if defined(TARGET_PPC64)
1751 TCGv_i64 t0 = tcg_temp_new_i64();
1752 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1753 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1754 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1755 tcg_temp_free_i64(t0);
1756 #else
1757 g_assert_not_reached();
1758 #endif
1759 }
1760
1761 tcg_gen_andi_tl(t_ra, t_ra, mask);
1762
1763 if (unlikely(Rc(ctx->opcode) != 0)) {
1764 gen_set_Rc0(ctx, t_ra);
1765 }
1766 }
1767
1768 #if defined(TARGET_PPC64)
1769 #define GEN_PPC64_R2(name, opc1, opc2) \
1770 static void glue(gen_, name##0)(DisasContext *ctx) \
1771 { \
1772 gen_##name(ctx, 0); \
1773 } \
1774 \
1775 static void glue(gen_, name##1)(DisasContext *ctx) \
1776 { \
1777 gen_##name(ctx, 1); \
1778 }
1779 #define GEN_PPC64_R4(name, opc1, opc2) \
1780 static void glue(gen_, name##0)(DisasContext *ctx) \
1781 { \
1782 gen_##name(ctx, 0, 0); \
1783 } \
1784 \
1785 static void glue(gen_, name##1)(DisasContext *ctx) \
1786 { \
1787 gen_##name(ctx, 0, 1); \
1788 } \
1789 \
1790 static void glue(gen_, name##2)(DisasContext *ctx) \
1791 { \
1792 gen_##name(ctx, 1, 0); \
1793 } \
1794 \
1795 static void glue(gen_, name##3)(DisasContext *ctx) \
1796 { \
1797 gen_##name(ctx, 1, 1); \
1798 }
1799
1800 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1801 {
1802 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1803 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1804
1805 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1806 tcg_gen_shli_tl(t_ra, t_rs, sh);
1807 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1808 tcg_gen_shri_tl(t_ra, t_rs, mb);
1809 } else {
1810 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1811 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1812 }
1813 if (unlikely(Rc(ctx->opcode) != 0)) {
1814 gen_set_Rc0(ctx, t_ra);
1815 }
1816 }
1817
1818 /* rldicl - rldicl. */
1819 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1820 {
1821 uint32_t sh, mb;
1822
1823 sh = SH(ctx->opcode) | (shn << 5);
1824 mb = MB(ctx->opcode) | (mbn << 5);
1825 gen_rldinm(ctx, mb, 63, sh);
1826 }
1827 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1828
1829 /* rldicr - rldicr. */
1830 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1831 {
1832 uint32_t sh, me;
1833
1834 sh = SH(ctx->opcode) | (shn << 5);
1835 me = MB(ctx->opcode) | (men << 5);
1836 gen_rldinm(ctx, 0, me, sh);
1837 }
1838 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1839
1840 /* rldic - rldic. */
1841 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1842 {
1843 uint32_t sh, mb;
1844
1845 sh = SH(ctx->opcode) | (shn << 5);
1846 mb = MB(ctx->opcode) | (mbn << 5);
1847 gen_rldinm(ctx, mb, 63 - sh, sh);
1848 }
1849 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1850
1851 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1852 {
1853 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1854 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1855 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1856 TCGv t0;
1857
1858 t0 = tcg_temp_new();
1859 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1860 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1861 tcg_temp_free(t0);
1862
1863 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1864 if (unlikely(Rc(ctx->opcode) != 0)) {
1865 gen_set_Rc0(ctx, t_ra);
1866 }
1867 }
1868
1869 /* rldcl - rldcl. */
1870 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1871 {
1872 uint32_t mb;
1873
1874 mb = MB(ctx->opcode) | (mbn << 5);
1875 gen_rldnm(ctx, mb, 63);
1876 }
1877 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1878
1879 /* rldcr - rldcr. */
1880 static inline void gen_rldcr(DisasContext *ctx, int men)
1881 {
1882 uint32_t me;
1883
1884 me = MB(ctx->opcode) | (men << 5);
1885 gen_rldnm(ctx, 0, me);
1886 }
1887 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1888
1889 /* rldimi - rldimi. */
1890 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1891 {
1892 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1893 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1894 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1895 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1896 uint32_t me = 63 - sh;
1897
1898 if (mb <= me) {
1899 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1900 } else {
1901 target_ulong mask = MASK(mb, me);
1902 TCGv t1 = tcg_temp_new();
1903
1904 tcg_gen_rotli_tl(t1, t_rs, sh);
1905 tcg_gen_andi_tl(t1, t1, mask);
1906 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1907 tcg_gen_or_tl(t_ra, t_ra, t1);
1908 tcg_temp_free(t1);
1909 }
1910 if (unlikely(Rc(ctx->opcode) != 0)) {
1911 gen_set_Rc0(ctx, t_ra);
1912 }
1913 }
1914 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1915 #endif
1916
1917 /*** Integer shift ***/
1918
1919 /* slw & slw. */
1920 static void gen_slw(DisasContext *ctx)
1921 {
1922 TCGv t0, t1;
1923
1924 t0 = tcg_temp_new();
1925 /* AND rS with a mask that is 0 when rB >= 0x20 */
1926 #if defined(TARGET_PPC64)
1927 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1928 tcg_gen_sari_tl(t0, t0, 0x3f);
1929 #else
1930 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1931 tcg_gen_sari_tl(t0, t0, 0x1f);
1932 #endif
1933 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1934 t1 = tcg_temp_new();
1935 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1936 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1937 tcg_temp_free(t1);
1938 tcg_temp_free(t0);
1939 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1940 if (unlikely(Rc(ctx->opcode) != 0))
1941 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1942 }
1943
1944 /* sraw & sraw. */
1945 static void gen_sraw(DisasContext *ctx)
1946 {
1947 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1948 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1949 if (unlikely(Rc(ctx->opcode) != 0))
1950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1951 }
1952
1953 /* srawi & srawi. */
1954 static void gen_srawi(DisasContext *ctx)
1955 {
1956 int sh = SH(ctx->opcode);
1957 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1958 TCGv src = cpu_gpr[rS(ctx->opcode)];
1959 if (sh == 0) {
1960 tcg_gen_ext32s_tl(dst, src);
1961 tcg_gen_movi_tl(cpu_ca, 0);
1962 } else {
1963 TCGv t0;
1964 tcg_gen_ext32s_tl(dst, src);
1965 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1966 t0 = tcg_temp_new();
1967 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1968 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1969 tcg_temp_free(t0);
1970 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1971 tcg_gen_sari_tl(dst, dst, sh);
1972 }
1973 if (unlikely(Rc(ctx->opcode) != 0)) {
1974 gen_set_Rc0(ctx, dst);
1975 }
1976 }
1977
1978 /* srw & srw. */
1979 static void gen_srw(DisasContext *ctx)
1980 {
1981 TCGv t0, t1;
1982
1983 t0 = tcg_temp_new();
1984 /* AND rS with a mask that is 0 when rB >= 0x20 */
1985 #if defined(TARGET_PPC64)
1986 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1987 tcg_gen_sari_tl(t0, t0, 0x3f);
1988 #else
1989 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1990 tcg_gen_sari_tl(t0, t0, 0x1f);
1991 #endif
1992 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1993 tcg_gen_ext32u_tl(t0, t0);
1994 t1 = tcg_temp_new();
1995 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1996 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1997 tcg_temp_free(t1);
1998 tcg_temp_free(t0);
1999 if (unlikely(Rc(ctx->opcode) != 0))
2000 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2001 }
2002
2003 #if defined(TARGET_PPC64)
2004 /* sld & sld. */
2005 static void gen_sld(DisasContext *ctx)
2006 {
2007 TCGv t0, t1;
2008
2009 t0 = tcg_temp_new();
2010 /* AND rS with a mask that is 0 when rB >= 0x40 */
2011 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2012 tcg_gen_sari_tl(t0, t0, 0x3f);
2013 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2014 t1 = tcg_temp_new();
2015 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2016 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2017 tcg_temp_free(t1);
2018 tcg_temp_free(t0);
2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021 }
2022
2023 /* srad & srad. */
2024 static void gen_srad(DisasContext *ctx)
2025 {
2026 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2027 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2028 if (unlikely(Rc(ctx->opcode) != 0))
2029 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2030 }
2031 /* sradi & sradi. */
2032 static inline void gen_sradi(DisasContext *ctx, int n)
2033 {
2034 int sh = SH(ctx->opcode) + (n << 5);
2035 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2036 TCGv src = cpu_gpr[rS(ctx->opcode)];
2037 if (sh == 0) {
2038 tcg_gen_mov_tl(dst, src);
2039 tcg_gen_movi_tl(cpu_ca, 0);
2040 } else {
2041 TCGv t0;
2042 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2043 t0 = tcg_temp_new();
2044 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2045 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2046 tcg_temp_free(t0);
2047 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2048 tcg_gen_sari_tl(dst, src, sh);
2049 }
2050 if (unlikely(Rc(ctx->opcode) != 0)) {
2051 gen_set_Rc0(ctx, dst);
2052 }
2053 }
2054
2055 static void gen_sradi0(DisasContext *ctx)
2056 {
2057 gen_sradi(ctx, 0);
2058 }
2059
2060 static void gen_sradi1(DisasContext *ctx)
2061 {
2062 gen_sradi(ctx, 1);
2063 }
2064
2065 /* srd & srd. */
2066 static void gen_srd(DisasContext *ctx)
2067 {
2068 TCGv t0, t1;
2069
2070 t0 = tcg_temp_new();
2071 /* AND rS with a mask that is 0 when rB >= 0x40 */
2072 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2073 tcg_gen_sari_tl(t0, t0, 0x3f);
2074 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2075 t1 = tcg_temp_new();
2076 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2077 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2078 tcg_temp_free(t1);
2079 tcg_temp_free(t0);
2080 if (unlikely(Rc(ctx->opcode) != 0))
2081 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2082 }
2083 #endif
2084
2085 #if defined(TARGET_PPC64)
2086 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2087 {
2088 TCGv_i32 tmp = tcg_temp_new_i32();
2089 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2090 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2091 tcg_temp_free_i32(tmp);
2092 }
2093 #else
2094 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2095 {
2096 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2097 }
2098 #endif
2099
2100 /*** Floating-Point arithmetic ***/
2101 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2102 static void gen_f##name(DisasContext *ctx) \
2103 { \
2104 if (unlikely(!ctx->fpu_enabled)) { \
2105 gen_exception(ctx, POWERPC_EXCP_FPU); \
2106 return; \
2107 } \
2108 /* NIP cannot be restored if the memory exception comes from an helper */ \
2109 gen_update_nip(ctx, ctx->nip - 4); \
2110 gen_reset_fpstatus(); \
2111 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2112 cpu_fpr[rA(ctx->opcode)], \
2113 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2114 if (isfloat) { \
2115 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2116 cpu_fpr[rD(ctx->opcode)]); \
2117 } \
2118 if (set_fprf) { \
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2120 } \
2121 if (unlikely(Rc(ctx->opcode) != 0)) { \
2122 gen_set_cr1_from_fpscr(ctx); \
2123 } \
2124 }
2125
2126 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2127 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2128 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2129
2130 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2131 static void gen_f##name(DisasContext *ctx) \
2132 { \
2133 if (unlikely(!ctx->fpu_enabled)) { \
2134 gen_exception(ctx, POWERPC_EXCP_FPU); \
2135 return; \
2136 } \
2137 /* NIP cannot be restored if the memory exception comes from an helper */ \
2138 gen_update_nip(ctx, ctx->nip - 4); \
2139 gen_reset_fpstatus(); \
2140 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2141 cpu_fpr[rA(ctx->opcode)], \
2142 cpu_fpr[rB(ctx->opcode)]); \
2143 if (isfloat) { \
2144 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2145 cpu_fpr[rD(ctx->opcode)]); \
2146 } \
2147 if (set_fprf) { \
2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2149 } \
2150 if (unlikely(Rc(ctx->opcode) != 0)) { \
2151 gen_set_cr1_from_fpscr(ctx); \
2152 } \
2153 }
2154 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2155 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2156 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2157
2158 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2159 static void gen_f##name(DisasContext *ctx) \
2160 { \
2161 if (unlikely(!ctx->fpu_enabled)) { \
2162 gen_exception(ctx, POWERPC_EXCP_FPU); \
2163 return; \
2164 } \
2165 /* NIP cannot be restored if the memory exception comes from an helper */ \
2166 gen_update_nip(ctx, ctx->nip - 4); \
2167 gen_reset_fpstatus(); \
2168 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2169 cpu_fpr[rA(ctx->opcode)], \
2170 cpu_fpr[rC(ctx->opcode)]); \
2171 if (isfloat) { \
2172 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2173 cpu_fpr[rD(ctx->opcode)]); \
2174 } \
2175 if (set_fprf) { \
2176 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2177 } \
2178 if (unlikely(Rc(ctx->opcode) != 0)) { \
2179 gen_set_cr1_from_fpscr(ctx); \
2180 } \
2181 }
2182 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2183 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2184 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2185
2186 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2187 static void gen_f##name(DisasContext *ctx) \
2188 { \
2189 if (unlikely(!ctx->fpu_enabled)) { \
2190 gen_exception(ctx, POWERPC_EXCP_FPU); \
2191 return; \
2192 } \
2193 /* NIP cannot be restored if the memory exception comes from an helper */ \
2194 gen_update_nip(ctx, ctx->nip - 4); \
2195 gen_reset_fpstatus(); \
2196 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2197 cpu_fpr[rB(ctx->opcode)]); \
2198 if (set_fprf) { \
2199 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2200 } \
2201 if (unlikely(Rc(ctx->opcode) != 0)) { \
2202 gen_set_cr1_from_fpscr(ctx); \
2203 } \
2204 }
2205
2206 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2207 static void gen_f##name(DisasContext *ctx) \
2208 { \
2209 if (unlikely(!ctx->fpu_enabled)) { \
2210 gen_exception(ctx, POWERPC_EXCP_FPU); \
2211 return; \
2212 } \
2213 /* NIP cannot be restored if the memory exception comes from an helper */ \
2214 gen_update_nip(ctx, ctx->nip - 4); \
2215 gen_reset_fpstatus(); \
2216 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2217 cpu_fpr[rB(ctx->opcode)]); \
2218 if (set_fprf) { \
2219 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2220 } \
2221 if (unlikely(Rc(ctx->opcode) != 0)) { \
2222 gen_set_cr1_from_fpscr(ctx); \
2223 } \
2224 }
2225
2226 /* fadd - fadds */
2227 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2228 /* fdiv - fdivs */
2229 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2230 /* fmul - fmuls */
2231 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2232
2233 /* fre */
2234 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2235
2236 /* fres */
2237 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2238
2239 /* frsqrte */
2240 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2241
2242 /* frsqrtes */
2243 static void gen_frsqrtes(DisasContext *ctx)
2244 {
2245 if (unlikely(!ctx->fpu_enabled)) {
2246 gen_exception(ctx, POWERPC_EXCP_FPU);
2247 return;
2248 }
2249 /* NIP cannot be restored if the memory exception comes from an helper */
2250 gen_update_nip(ctx, ctx->nip - 4);
2251 gen_reset_fpstatus();
2252 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2253 cpu_fpr[rB(ctx->opcode)]);
2254 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2255 cpu_fpr[rD(ctx->opcode)]);
2256 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2257 if (unlikely(Rc(ctx->opcode) != 0)) {
2258 gen_set_cr1_from_fpscr(ctx);
2259 }
2260 }
2261
2262 /* fsel */
2263 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2264 /* fsub - fsubs */
2265 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2266 /* Optional: */
2267
2268 /* fsqrt */
2269 static void gen_fsqrt(DisasContext *ctx)
2270 {
2271 if (unlikely(!ctx->fpu_enabled)) {
2272 gen_exception(ctx, POWERPC_EXCP_FPU);
2273 return;
2274 }
2275 /* NIP cannot be restored if the memory exception comes from an helper */
2276 gen_update_nip(ctx, ctx->nip - 4);
2277 gen_reset_fpstatus();
2278 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2279 cpu_fpr[rB(ctx->opcode)]);
2280 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2281 if (unlikely(Rc(ctx->opcode) != 0)) {
2282 gen_set_cr1_from_fpscr(ctx);
2283 }
2284 }
2285
2286 static void gen_fsqrts(DisasContext *ctx)
2287 {
2288 if (unlikely(!ctx->fpu_enabled)) {
2289 gen_exception(ctx, POWERPC_EXCP_FPU);
2290 return;
2291 }
2292 /* NIP cannot be restored if the memory exception comes from an helper */
2293 gen_update_nip(ctx, ctx->nip - 4);
2294 gen_reset_fpstatus();
2295 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2296 cpu_fpr[rB(ctx->opcode)]);
2297 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2298 cpu_fpr[rD(ctx->opcode)]);
2299 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2300 if (unlikely(Rc(ctx->opcode) != 0)) {
2301 gen_set_cr1_from_fpscr(ctx);
2302 }
2303 }
2304
2305 /*** Floating-Point multiply-and-add ***/
2306 /* fmadd - fmadds */
2307 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2308 /* fmsub - fmsubs */
2309 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2310 /* fnmadd - fnmadds */
2311 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2312 /* fnmsub - fnmsubs */
2313 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2314
2315 /*** Floating-Point round & convert ***/
2316 /* fctiw */
2317 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2318 /* fctiwu */
2319 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2320 /* fctiwz */
2321 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2322 /* fctiwuz */
2323 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2324 /* frsp */
2325 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2326 /* fcfid */
2327 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2328 /* fcfids */
2329 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2330 /* fcfidu */
2331 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2332 /* fcfidus */
2333 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2334 /* fctid */
2335 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2336 /* fctidu */
2337 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2338 /* fctidz */
2339 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2340 /* fctidu */
2341 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2342
2343 /* frin */
2344 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2345 /* friz */
2346 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2347 /* frip */
2348 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2349 /* frim */
2350 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2351
2352 static void gen_ftdiv(DisasContext *ctx)
2353 {
2354 if (unlikely(!ctx->fpu_enabled)) {
2355 gen_exception(ctx, POWERPC_EXCP_FPU);
2356 return;
2357 }
2358 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2359 cpu_fpr[rB(ctx->opcode)]);
2360 }
2361
2362 static void gen_ftsqrt(DisasContext *ctx)
2363 {
2364 if (unlikely(!ctx->fpu_enabled)) {
2365 gen_exception(ctx, POWERPC_EXCP_FPU);
2366 return;
2367 }
2368 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2369 }
2370
2371
2372
2373 /*** Floating-Point compare ***/
2374
2375 /* fcmpo */
2376 static void gen_fcmpo(DisasContext *ctx)
2377 {
2378 TCGv_i32 crf;
2379 if (unlikely(!ctx->fpu_enabled)) {
2380 gen_exception(ctx, POWERPC_EXCP_FPU);
2381 return;
2382 }
2383 /* NIP cannot be restored if the memory exception comes from an helper */
2384 gen_update_nip(ctx, ctx->nip - 4);
2385 gen_reset_fpstatus();
2386 crf = tcg_const_i32(crfD(ctx->opcode));
2387 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2388 cpu_fpr[rB(ctx->opcode)], crf);
2389 tcg_temp_free_i32(crf);
2390 gen_helper_float_check_status(cpu_env);
2391 }
2392
2393 /* fcmpu */
2394 static void gen_fcmpu(DisasContext *ctx)
2395 {
2396 TCGv_i32 crf;
2397 if (unlikely(!ctx->fpu_enabled)) {
2398 gen_exception(ctx, POWERPC_EXCP_FPU);
2399 return;
2400 }
2401 /* NIP cannot be restored if the memory exception comes from an helper */
2402 gen_update_nip(ctx, ctx->nip - 4);
2403 gen_reset_fpstatus();
2404 crf = tcg_const_i32(crfD(ctx->opcode));
2405 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2406 cpu_fpr[rB(ctx->opcode)], crf);
2407 tcg_temp_free_i32(crf);
2408 gen_helper_float_check_status(cpu_env);
2409 }
2410
2411 /*** Floating-point move ***/
2412 /* fabs */
2413 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2414 static void gen_fabs(DisasContext *ctx)
2415 {
2416 if (unlikely(!ctx->fpu_enabled)) {
2417 gen_exception(ctx, POWERPC_EXCP_FPU);
2418 return;
2419 }
2420 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2421 ~(1ULL << 63));
2422 if (unlikely(Rc(ctx->opcode))) {
2423 gen_set_cr1_from_fpscr(ctx);
2424 }
2425 }
2426
2427 /* fmr - fmr. */
2428 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2429 static void gen_fmr(DisasContext *ctx)
2430 {
2431 if (unlikely(!ctx->fpu_enabled)) {
2432 gen_exception(ctx, POWERPC_EXCP_FPU);
2433 return;
2434 }
2435 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2436 if (unlikely(Rc(ctx->opcode))) {
2437 gen_set_cr1_from_fpscr(ctx);
2438 }
2439 }
2440
2441 /* fnabs */
2442 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2443 static void gen_fnabs(DisasContext *ctx)
2444 {
2445 if (unlikely(!ctx->fpu_enabled)) {
2446 gen_exception(ctx, POWERPC_EXCP_FPU);
2447 return;
2448 }
2449 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2450 1ULL << 63);
2451 if (unlikely(Rc(ctx->opcode))) {
2452 gen_set_cr1_from_fpscr(ctx);
2453 }
2454 }
2455
2456 /* fneg */
2457 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2458 static void gen_fneg(DisasContext *ctx)
2459 {
2460 if (unlikely(!ctx->fpu_enabled)) {
2461 gen_exception(ctx, POWERPC_EXCP_FPU);
2462 return;
2463 }
2464 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2465 1ULL << 63);
2466 if (unlikely(Rc(ctx->opcode))) {
2467 gen_set_cr1_from_fpscr(ctx);
2468 }
2469 }
2470
2471 /* fcpsgn: PowerPC 2.05 specification */
2472 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2473 static void gen_fcpsgn(DisasContext *ctx)
2474 {
2475 if (unlikely(!ctx->fpu_enabled)) {
2476 gen_exception(ctx, POWERPC_EXCP_FPU);
2477 return;
2478 }
2479 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2480 cpu_fpr[rB(ctx->opcode)], 0, 63);
2481 if (unlikely(Rc(ctx->opcode))) {
2482 gen_set_cr1_from_fpscr(ctx);
2483 }
2484 }
2485
2486 static void gen_fmrgew(DisasContext *ctx)
2487 {
2488 TCGv_i64 b0;
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 b0 = tcg_temp_new_i64();
2494 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2495 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2496 b0, 0, 32);
2497 tcg_temp_free_i64(b0);
2498 }
2499
2500 static void gen_fmrgow(DisasContext *ctx)
2501 {
2502 if (unlikely(!ctx->fpu_enabled)) {
2503 gen_exception(ctx, POWERPC_EXCP_FPU);
2504 return;
2505 }
2506 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2507 cpu_fpr[rB(ctx->opcode)],
2508 cpu_fpr[rA(ctx->opcode)],
2509 32, 32);
2510 }
2511
2512 /*** Floating-Point status & ctrl register ***/
2513
2514 /* mcrfs */
2515 static void gen_mcrfs(DisasContext *ctx)
2516 {
2517 TCGv tmp = tcg_temp_new();
2518 TCGv_i32 tmask;
2519 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2520 int bfa;
2521 int nibble;
2522 int shift;
2523
2524 if (unlikely(!ctx->fpu_enabled)) {
2525 gen_exception(ctx, POWERPC_EXCP_FPU);
2526 return;
2527 }
2528 bfa = crfS(ctx->opcode);
2529 nibble = 7 - bfa;
2530 shift = 4 * nibble;
2531 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2532 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2533 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2534 tcg_temp_free(tmp);
2535 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2536 /* Only the exception bits (including FX) should be cleared if read */
2537 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2538 /* FEX and VX need to be updated, so don't set fpscr directly */
2539 tmask = tcg_const_i32(1 << nibble);
2540 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2541 tcg_temp_free_i32(tmask);
2542 tcg_temp_free_i64(tnew_fpscr);
2543 }
2544
2545 /* mffs */
2546 static void gen_mffs(DisasContext *ctx)
2547 {
2548 if (unlikely(!ctx->fpu_enabled)) {
2549 gen_exception(ctx, POWERPC_EXCP_FPU);
2550 return;
2551 }
2552 gen_reset_fpstatus();
2553 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2554 if (unlikely(Rc(ctx->opcode))) {
2555 gen_set_cr1_from_fpscr(ctx);
2556 }
2557 }
2558
2559 /* mtfsb0 */
2560 static void gen_mtfsb0(DisasContext *ctx)
2561 {
2562 uint8_t crb;
2563
2564 if (unlikely(!ctx->fpu_enabled)) {
2565 gen_exception(ctx, POWERPC_EXCP_FPU);
2566 return;
2567 }
2568 crb = 31 - crbD(ctx->opcode);
2569 gen_reset_fpstatus();
2570 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2571 TCGv_i32 t0;
2572 /* NIP cannot be restored if the memory exception comes from an helper */
2573 gen_update_nip(ctx, ctx->nip - 4);
2574 t0 = tcg_const_i32(crb);
2575 gen_helper_fpscr_clrbit(cpu_env, t0);
2576 tcg_temp_free_i32(t0);
2577 }
2578 if (unlikely(Rc(ctx->opcode) != 0)) {
2579 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2580 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2581 }
2582 }
2583
2584 /* mtfsb1 */
2585 static void gen_mtfsb1(DisasContext *ctx)
2586 {
2587 uint8_t crb;
2588
2589 if (unlikely(!ctx->fpu_enabled)) {
2590 gen_exception(ctx, POWERPC_EXCP_FPU);
2591 return;
2592 }
2593 crb = 31 - crbD(ctx->opcode);
2594 gen_reset_fpstatus();
2595 /* XXX: we pretend we can only do IEEE floating-point computations */
2596 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2597 TCGv_i32 t0;
2598 /* NIP cannot be restored if the memory exception comes from an helper */
2599 gen_update_nip(ctx, ctx->nip - 4);
2600 t0 = tcg_const_i32(crb);
2601 gen_helper_fpscr_setbit(cpu_env, t0);
2602 tcg_temp_free_i32(t0);
2603 }
2604 if (unlikely(Rc(ctx->opcode) != 0)) {
2605 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2606 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2607 }
2608 /* We can raise a differed exception */
2609 gen_helper_float_check_status(cpu_env);
2610 }
2611
2612 /* mtfsf */
2613 static void gen_mtfsf(DisasContext *ctx)
2614 {
2615 TCGv_i32 t0;
2616 int flm, l, w;
2617
2618 if (unlikely(!ctx->fpu_enabled)) {
2619 gen_exception(ctx, POWERPC_EXCP_FPU);
2620 return;
2621 }
2622 flm = FPFLM(ctx->opcode);
2623 l = FPL(ctx->opcode);
2624 w = FPW(ctx->opcode);
2625 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2627 return;
2628 }
2629 /* NIP cannot be restored if the memory exception comes from an helper */
2630 gen_update_nip(ctx, ctx->nip - 4);
2631 gen_reset_fpstatus();
2632 if (l) {
2633 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2634 } else {
2635 t0 = tcg_const_i32(flm << (w * 8));
2636 }
2637 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2638 tcg_temp_free_i32(t0);
2639 if (unlikely(Rc(ctx->opcode) != 0)) {
2640 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2641 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2642 }
2643 /* We can raise a differed exception */
2644 gen_helper_float_check_status(cpu_env);
2645 }
2646
2647 /* mtfsfi */
2648 static void gen_mtfsfi(DisasContext *ctx)
2649 {
2650 int bf, sh, w;
2651 TCGv_i64 t0;
2652 TCGv_i32 t1;
2653
2654 if (unlikely(!ctx->fpu_enabled)) {
2655 gen_exception(ctx, POWERPC_EXCP_FPU);
2656 return;
2657 }
2658 w = FPW(ctx->opcode);
2659 bf = FPBF(ctx->opcode);
2660 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2661 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2662 return;
2663 }
2664 sh = (8 * w) + 7 - bf;
2665 /* NIP cannot be restored if the memory exception comes from an helper */
2666 gen_update_nip(ctx, ctx->nip - 4);
2667 gen_reset_fpstatus();
2668 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2669 t1 = tcg_const_i32(1 << sh);
2670 gen_helper_store_fpscr(cpu_env, t0, t1);
2671 tcg_temp_free_i64(t0);
2672 tcg_temp_free_i32(t1);
2673 if (unlikely(Rc(ctx->opcode) != 0)) {
2674 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2675 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2676 }
2677 /* We can raise a differed exception */
2678 gen_helper_float_check_status(cpu_env);
2679 }
2680
2681 /*** Addressing modes ***/
2682 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2683 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2684 target_long maskl)
2685 {
2686 target_long simm = SIMM(ctx->opcode);
2687
2688 simm &= ~maskl;
2689 if (rA(ctx->opcode) == 0) {
2690 if (NARROW_MODE(ctx)) {
2691 simm = (uint32_t)simm;
2692 }
2693 tcg_gen_movi_tl(EA, simm);
2694 } else if (likely(simm != 0)) {
2695 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2696 if (NARROW_MODE(ctx)) {
2697 tcg_gen_ext32u_tl(EA, EA);
2698 }
2699 } else {
2700 if (NARROW_MODE(ctx)) {
2701 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2702 } else {
2703 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2704 }
2705 }
2706 }
2707
2708 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2709 {
2710 if (rA(ctx->opcode) == 0) {
2711 if (NARROW_MODE(ctx)) {
2712 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2713 } else {
2714 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2715 }
2716 } else {
2717 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2718 if (NARROW_MODE(ctx)) {
2719 tcg_gen_ext32u_tl(EA, EA);
2720 }
2721 }
2722 }
2723
2724 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2725 {
2726 if (rA(ctx->opcode) == 0) {
2727 tcg_gen_movi_tl(EA, 0);
2728 } else if (NARROW_MODE(ctx)) {
2729 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2730 } else {
2731 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2732 }
2733 }
2734
2735 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2736 target_long val)
2737 {
2738 tcg_gen_addi_tl(ret, arg1, val);
2739 if (NARROW_MODE(ctx)) {
2740 tcg_gen_ext32u_tl(ret, ret);
2741 }
2742 }
2743
2744 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2745 {
2746 TCGLabel *l1 = gen_new_label();
2747 TCGv t0 = tcg_temp_new();
2748 TCGv_i32 t1, t2;
2749 /* NIP cannot be restored if the memory exception comes from an helper */
2750 gen_update_nip(ctx, ctx->nip - 4);
2751 tcg_gen_andi_tl(t0, EA, mask);
2752 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2753 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2754 t2 = tcg_const_i32(0);
2755 gen_helper_raise_exception_err(cpu_env, t1, t2);
2756 tcg_temp_free_i32(t1);
2757 tcg_temp_free_i32(t2);
2758 gen_set_label(l1);
2759 tcg_temp_free(t0);
2760 }
2761
2762 /*** Integer load ***/
2763 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2764 {
2765 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2766 }
2767
2768 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2769 {
2770 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2771 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2772 }
2773
2774 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2775 {
2776 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2777 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2778 }
2779
2780 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2781 {
2782 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2783 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2784 }
2785
2786 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2787 {
2788 TCGv tmp = tcg_temp_new();
2789 gen_qemu_ld32u(ctx, tmp, addr);
2790 tcg_gen_extu_tl_i64(val, tmp);
2791 tcg_temp_free(tmp);
2792 }
2793
2794 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2795 {
2796 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2797 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2798 }
2799
2800 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2801 {
2802 TCGv tmp = tcg_temp_new();
2803 gen_qemu_ld32s(ctx, tmp, addr);
2804 tcg_gen_ext_tl_i64(val, tmp);
2805 tcg_temp_free(tmp);
2806 }
2807
2808 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2809 {
2810 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2811 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2812 }
2813
2814 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2815 {
2816 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2817 }
2818
2819 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2820 {
2821 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2822 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2823 }
2824
2825 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2826 {
2827 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2828 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2829 }
2830
2831 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2832 {
2833 TCGv tmp = tcg_temp_new();
2834 tcg_gen_trunc_i64_tl(tmp, val);
2835 gen_qemu_st32(ctx, tmp, addr);
2836 tcg_temp_free(tmp);
2837 }
2838
2839 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2840 {
2841 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2842 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2843 }
2844
2845 #define GEN_LD(name, ldop, opc, type) \
2846 static void glue(gen_, name)(DisasContext *ctx) \
2847 { \
2848 TCGv EA; \
2849 gen_set_access_type(ctx, ACCESS_INT); \
2850 EA = tcg_temp_new(); \
2851 gen_addr_imm_index(ctx, EA, 0); \
2852 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2853 tcg_temp_free(EA); \
2854 }
2855
2856 #define GEN_LDU(name, ldop, opc, type) \
2857 static void glue(gen_, name##u)(DisasContext *ctx) \
2858 { \
2859 TCGv EA; \
2860 if (unlikely(rA(ctx->opcode) == 0 || \
2861 rA(ctx->opcode) == rD(ctx->opcode))) { \
2862 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2863 return; \
2864 } \
2865 gen_set_access_type(ctx, ACCESS_INT); \
2866 EA = tcg_temp_new(); \
2867 if (type == PPC_64B) \
2868 gen_addr_imm_index(ctx, EA, 0x03); \
2869 else \
2870 gen_addr_imm_index(ctx, EA, 0); \
2871 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2872 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2873 tcg_temp_free(EA); \
2874 }
2875
2876 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2877 static void glue(gen_, name##ux)(DisasContext *ctx) \
2878 { \
2879 TCGv EA; \
2880 if (unlikely(rA(ctx->opcode) == 0 || \
2881 rA(ctx->opcode) == rD(ctx->opcode))) { \
2882 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2883 return; \
2884 } \
2885 gen_set_access_type(ctx, ACCESS_INT); \
2886 EA = tcg_temp_new(); \
2887 gen_addr_reg_index(ctx, EA); \
2888 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2889 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2890 tcg_temp_free(EA); \
2891 }
2892
2893 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2894 static void glue(gen_, name##x)(DisasContext *ctx) \
2895 { \
2896 TCGv EA; \
2897 gen_set_access_type(ctx, ACCESS_INT); \
2898 EA = tcg_temp_new(); \
2899 gen_addr_reg_index(ctx, EA); \
2900 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2901 tcg_temp_free(EA); \
2902 }
2903 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2904 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2905
2906 #define GEN_LDS(name, ldop, op, type) \
2907 GEN_LD(name, ldop, op | 0x20, type); \
2908 GEN_LDU(name, ldop, op | 0x21, type); \
2909 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2910 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2911
2912 /* lbz lbzu lbzux lbzx */
2913 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2914 /* lha lhau lhaux lhax */
2915 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2916 /* lhz lhzu lhzux lhzx */
2917 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2918 /* lwz lwzu lwzux lwzx */
2919 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2920 #if defined(TARGET_PPC64)
2921 /* lwaux */
2922 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2923 /* lwax */
2924 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2925 /* ldux */
2926 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2927 /* ldx */
2928 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2929
2930 static void gen_ld(DisasContext *ctx)
2931 {
2932 TCGv EA;
2933 if (Rc(ctx->opcode)) {
2934 if (unlikely(rA(ctx->opcode) == 0 ||
2935 rA(ctx->opcode) == rD(ctx->opcode))) {
2936 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2937 return;
2938 }
2939 }
2940 gen_set_access_type(ctx, ACCESS_INT);
2941 EA = tcg_temp_new();
2942 gen_addr_imm_index(ctx, EA, 0x03);
2943 if (ctx->opcode & 0x02) {
2944 /* lwa (lwau is undefined) */
2945 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2946 } else {
2947 /* ld - ldu */
2948 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2949 }
2950 if (Rc(ctx->opcode))
2951 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2952 tcg_temp_free(EA);
2953 }
2954
2955 /* lq */
2956 static void gen_lq(DisasContext *ctx)
2957 {
2958 int ra, rd;
2959 TCGv EA;
2960
2961 /* lq is a legal user mode instruction starting in ISA 2.07 */
2962 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2963 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2964
2965 if (!legal_in_user_mode && ctx->pr) {
2966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2967 return;
2968 }
2969
2970 if (!le_is_supported && ctx->le_mode) {
2971 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2972 return;
2973 }
2974
2975 ra = rA(ctx->opcode);
2976 rd = rD(ctx->opcode);
2977 if (unlikely((rd & 1) || rd == ra)) {
2978 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2979 return;
2980 }
2981
2982 gen_set_access_type(ctx, ACCESS_INT);
2983 EA = tcg_temp_new();
2984 gen_addr_imm_index(ctx, EA, 0x0F);
2985
2986 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2987 64-bit byteswap already. */
2988 if (unlikely(ctx->le_mode)) {
2989 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2990 gen_addr_add(ctx, EA, EA, 8);
2991 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2992 } else {
2993 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2994 gen_addr_add(ctx, EA, EA, 8);
2995 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2996 }
2997 tcg_temp_free(EA);
2998 }
2999 #endif
3000
3001 /*** Integer store ***/
3002 #define GEN_ST(name, stop, opc, type) \
3003 static void glue(gen_, name)(DisasContext *ctx) \
3004 { \
3005 TCGv EA; \
3006 gen_set_access_type(ctx, ACCESS_INT); \
3007 EA = tcg_temp_new(); \
3008 gen_addr_imm_index(ctx, EA, 0); \
3009 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3010 tcg_temp_free(EA); \
3011 }
3012
3013 #define GEN_STU(name, stop, opc, type) \
3014 static void glue(gen_, stop##u)(DisasContext *ctx) \
3015 { \
3016 TCGv EA; \
3017 if (unlikely(rA(ctx->opcode) == 0)) { \
3018 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3019 return; \
3020 } \
3021 gen_set_access_type(ctx, ACCESS_INT); \
3022 EA = tcg_temp_new(); \
3023 if (type == PPC_64B) \
3024 gen_addr_imm_index(ctx, EA, 0x03); \
3025 else \
3026 gen_addr_imm_index(ctx, EA, 0); \
3027 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3028 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3029 tcg_temp_free(EA); \
3030 }
3031
3032 #define GEN_STUX(name, stop, opc2, opc3, type) \
3033 static void glue(gen_, name##ux)(DisasContext *ctx) \
3034 { \
3035 TCGv EA; \
3036 if (unlikely(rA(ctx->opcode) == 0)) { \
3037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3038 return; \
3039 } \
3040 gen_set_access_type(ctx, ACCESS_INT); \
3041 EA = tcg_temp_new(); \
3042 gen_addr_reg_index(ctx, EA); \
3043 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3044 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3045 tcg_temp_free(EA); \
3046 }
3047
3048 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3049 static void glue(gen_, name##x)(DisasContext *ctx) \
3050 { \
3051 TCGv EA; \
3052 gen_set_access_type(ctx, ACCESS_INT); \
3053 EA = tcg_temp_new(); \
3054 gen_addr_reg_index(ctx, EA); \
3055 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3056 tcg_temp_free(EA); \
3057 }
3058 #define GEN_STX(name, stop, opc2, opc3, type) \
3059 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3060
3061 #define GEN_STS(name, stop, op, type) \
3062 GEN_ST(name, stop, op | 0x20, type); \
3063 GEN_STU(name, stop, op | 0x21, type); \
3064 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3065 GEN_STX(name, stop, 0x17, op | 0x00, type)
3066
3067 /* stb stbu stbux stbx */
3068 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3069 /* sth sthu sthux sthx */
3070 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3071 /* stw stwu stwux stwx */
3072 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3073 #if defined(TARGET_PPC64)
3074 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3075 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3076
3077 static void gen_std(DisasContext *ctx)
3078 {
3079 int rs;
3080 TCGv EA;
3081
3082 rs = rS(ctx->opcode);
3083 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3084 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3085 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3086
3087 if (!(ctx->insns_flags & PPC_64BX)) {
3088 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3089 }
3090
3091 if (!legal_in_user_mode && ctx->pr) {
3092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3093 return;
3094 }
3095
3096 if (!le_is_supported && ctx->le_mode) {
3097 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3098 return;
3099 }
3100
3101 if (unlikely(rs & 1)) {
3102 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3103 return;
3104 }
3105 gen_set_access_type(ctx, ACCESS_INT);
3106 EA = tcg_temp_new();
3107 gen_addr_imm_index(ctx, EA, 0x03);
3108
3109 /* We only need to swap high and low halves. gen_qemu_st64 does
3110 necessary 64-bit byteswap already. */
3111 if (unlikely(ctx->le_mode)) {
3112 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3113 gen_addr_add(ctx, EA, EA, 8);
3114 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3115 } else {
3116 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3117 gen_addr_add(ctx, EA, EA, 8);
3118 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3119 }
3120 tcg_temp_free(EA);
3121 } else {
3122 /* std / stdu*/
3123 if (Rc(ctx->opcode)) {
3124 if (unlikely(rA(ctx->opcode) == 0)) {
3125 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3126 return;
3127 }
3128 }
3129 gen_set_access_type(ctx, ACCESS_INT);
3130 EA = tcg_temp_new();
3131 gen_addr_imm_index(ctx, EA, 0x03);
3132 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3133 if (Rc(ctx->opcode))
3134 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3135 tcg_temp_free(EA);
3136 }
3137 }
3138 #endif
3139 /*** Integer load and store with byte reverse ***/
3140
3141 /* lhbrx */
3142 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3143 {
3144 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3145 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3146 }
3147 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3148
3149 /* lwbrx */
3150 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3151 {
3152 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3153 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3154 }
3155 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3156
3157 #if defined(TARGET_PPC64)
3158 /* ldbrx */
3159 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3160 {
3161 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3162 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3163 }
3164 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3165 #endif /* TARGET_PPC64 */
3166
3167 /* sthbrx */
3168 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3169 {
3170 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3171 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3172 }
3173 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3174
3175 /* stwbrx */
3176 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3177 {
3178 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3179 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3180 }
3181 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3182
3183 #if defined(TARGET_PPC64)
3184 /* stdbrx */
3185 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3186 {
3187 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3188 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3189 }
3190 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3191 #endif /* TARGET_PPC64 */
3192
3193 /*** Integer load and store multiple ***/
3194
3195 /* lmw */
3196 static void gen_lmw(DisasContext *ctx)
3197 {
3198 TCGv t0;
3199 TCGv_i32 t1;
3200 gen_set_access_type(ctx, ACCESS_INT);
3201 /* NIP cannot be restored if the memory exception comes from an helper */
3202 gen_update_nip(ctx, ctx->nip - 4);
3203 t0 = tcg_temp_new();
3204 t1 = tcg_const_i32(rD(ctx->opcode));
3205 gen_addr_imm_index(ctx, t0, 0);
3206 gen_helper_lmw(cpu_env, t0, t1);
3207 tcg_temp_free(t0);
3208 tcg_temp_free_i32(t1);
3209 }
3210
3211 /* stmw */
3212 static void gen_stmw(DisasContext *ctx)
3213 {
3214 TCGv t0;
3215 TCGv_i32 t1;
3216 gen_set_access_type(ctx, ACCESS_INT);
3217 /* NIP cannot be restored if the memory exception comes from an helper */
3218 gen_update_nip(ctx, ctx->nip - 4);
3219 t0 = tcg_temp_new();
3220 t1 = tcg_const_i32(rS(ctx->opcode));
3221 gen_addr_imm_index(ctx, t0, 0);
3222 gen_helper_stmw(cpu_env, t0, t1);
3223 tcg_temp_free(t0);
3224 tcg_temp_free_i32(t1);
3225 }
3226
3227 /*** Integer load and store strings ***/
3228
3229 /* lswi */
3230 /* PowerPC32 specification says we must generate an exception if
3231 * rA is in the range of registers to be loaded.
3232 * In an other hand, IBM says this is valid, but rA won't be loaded.
3233 * For now, I'll follow the spec...
3234 */
3235 static void gen_lswi(DisasContext *ctx)
3236 {
3237 TCGv t0;
3238 TCGv_i32 t1, t2;
3239 int nb = NB(ctx->opcode);
3240 int start = rD(ctx->opcode);
3241 int ra = rA(ctx->opcode);
3242 int nr;
3243
3244 if (nb == 0)
3245 nb = 32;
3246 nr = (nb + 3) / 4;
3247 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3248 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3249 return;
3250 }
3251 gen_set_access_type(ctx, ACCESS_INT);
3252 /* NIP cannot be restored if the memory exception comes from an helper */
3253 gen_update_nip(ctx, ctx->nip - 4);
3254 t0 = tcg_temp_new();
3255 gen_addr_register(ctx, t0);
3256 t1 = tcg_const_i32(nb);
3257 t2 = tcg_const_i32(start);
3258 gen_helper_lsw(cpu_env, t0, t1, t2);
3259 tcg_temp_free(t0);
3260 tcg_temp_free_i32(t1);
3261 tcg_temp_free_i32(t2);
3262 }
3263
3264 /* lswx */
3265 static void gen_lswx(DisasContext *ctx)
3266 {
3267 TCGv t0;
3268 TCGv_i32 t1, t2, t3;
3269 gen_set_access_type(ctx, ACCESS_INT);
3270 /* NIP cannot be restored if the memory exception comes from an helper */
3271 gen_update_nip(ctx, ctx->nip - 4);
3272 t0 = tcg_temp_new();
3273 gen_addr_reg_index(ctx, t0);
3274 t1 = tcg_const_i32(rD(ctx->opcode));
3275 t2 = tcg_const_i32(rA(ctx->opcode));
3276 t3 = tcg_const_i32(rB(ctx->opcode));
3277 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3278 tcg_temp_free(t0);
3279 tcg_temp_free_i32(t1);
3280 tcg_temp_free_i32(t2);
3281 tcg_temp_free_i32(t3);
3282 }
3283
3284 /* stswi */
3285 static void gen_stswi(DisasContext *ctx)
3286 {
3287 TCGv t0;
3288 TCGv_i32 t1, t2;
3289 int nb = NB(ctx->opcode);
3290 gen_set_access_type(ctx, ACCESS_INT);
3291 /* NIP cannot be restored if the memory exception comes from an helper */
3292 gen_update_nip(ctx, ctx->nip - 4);
3293 t0 = tcg_temp_new();
3294 gen_addr_register(ctx, t0);
3295 if (nb == 0)
3296 nb = 32;
3297 t1 = tcg_const_i32(nb);
3298 t2 = tcg_const_i32(rS(ctx->opcode));
3299 gen_helper_stsw(cpu_env, t0, t1, t2);
3300 tcg_temp_free(t0);
3301 tcg_temp_free_i32(t1);
3302 tcg_temp_free_i32(t2);
3303 }
3304
3305 /* stswx */
3306 static void gen_stswx(DisasContext *ctx)
3307 {
3308 TCGv t0;
3309 TCGv_i32 t1, t2;
3310 gen_set_access_type(ctx, ACCESS_INT);
3311 /* NIP cannot be restored if the memory exception comes from an helper */
3312 gen_update_nip(ctx, ctx->nip - 4);
3313 t0 = tcg_temp_new();
3314 gen_addr_reg_index(ctx, t0);
3315 t1 = tcg_temp_new_i32();
3316 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3317 tcg_gen_andi_i32(t1, t1, 0x7F);
3318 t2 = tcg_const_i32(rS(ctx->opcode));
3319 gen_helper_stsw(cpu_env, t0, t1, t2);
3320 tcg_temp_free(t0);
3321 tcg_temp_free_i32(t1);
3322 tcg_temp_free_i32(t2);
3323 }
3324
3325 /*** Memory synchronisation ***/
3326 /* eieio */
3327 static void gen_eieio(DisasContext *ctx)
3328 {
3329 }
3330
3331 #if !defined(CONFIG_USER_ONLY)
3332 static inline void gen_check_tlb_flush(DisasContext *ctx)
3333 {
3334 TCGv_i32 t;
3335 TCGLabel *l;
3336
3337 if (!ctx->lazy_tlb_flush) {
3338 return;
3339 }
3340 l = gen_new_label();
3341 t = tcg_temp_new_i32();
3342 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3343 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3344 gen_helper_check_tlb_flush(cpu_env);
3345 gen_set_label(l);
3346 tcg_temp_free_i32(t);
3347 }
3348 #else
3349 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3350 #endif
3351
3352 /* isync */
3353 static void gen_isync(DisasContext *ctx)
3354 {
3355 /*
3356 * We need to check for a pending TLB flush. This can only happen in
3357 * kernel mode however so check MSR_PR
3358 */
3359 if (!ctx->pr) {
3360 gen_check_tlb_flush(ctx);
3361 }
3362 gen_stop_exception(ctx);
3363 }
3364
3365 #define LARX(name, len, loadop) \
3366 static void gen_##name(DisasContext *ctx) \
3367 { \
3368 TCGv t0; \
3369 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3370 gen_set_access_type(ctx, ACCESS_RES); \
3371 t0 = tcg_temp_local_new(); \
3372 gen_addr_reg_index(ctx, t0); \
3373 if ((len) > 1) { \
3374 gen_check_align(ctx, t0, (len)-1); \
3375 } \
3376 gen_qemu_##loadop(ctx, gpr, t0); \
3377 tcg_gen_mov_tl(cpu_reserve, t0); \
3378 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3379 tcg_temp_free(t0); \
3380 }
3381
3382 /* lwarx */
3383 LARX(lbarx, 1, ld8u);
3384 LARX(lharx, 2, ld16u);
3385 LARX(lwarx, 4, ld32u);
3386
3387
3388 #if defined(CONFIG_USER_ONLY)
3389 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3390 int reg, int size)
3391 {
3392 TCGv t0 = tcg_temp_new();
3393 uint32_t save_exception = ctx->exception;
3394
3395 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3396 tcg_gen_movi_tl(t0, (size << 5) | reg);
3397 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3398 tcg_temp_free(t0);
3399 gen_update_nip(ctx, ctx->nip-4);
3400 ctx->exception = POWERPC_EXCP_BRANCH;
3401 gen_exception(ctx, POWERPC_EXCP_STCX);
3402 ctx->exception = save_exception;
3403 }
3404 #else
3405 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3406 int reg, int size)
3407 {
3408 TCGLabel *l1;
3409
3410 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3411 l1 = gen_new_label();
3412 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3413 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3414 #if defined(TARGET_PPC64)
3415 if (size == 8) {
3416 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3417 } else
3418 #endif
3419 if (size == 4) {
3420 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3421 } else if (size == 2) {
3422 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3423 #if defined(TARGET_PPC64)
3424 } else if (size == 16) {
3425 TCGv gpr1, gpr2 , EA8;
3426 if (unlikely(ctx->le_mode)) {
3427 gpr1 = cpu_gpr[reg+1];
3428 gpr2 = cpu_gpr[reg];
3429 } else {
3430 gpr1 = cpu_gpr[reg];
3431 gpr2 = cpu_gpr[reg+1];
3432 }
3433 gen_qemu_st64(ctx, gpr1, EA);
3434 EA8 = tcg_temp_local_new();
3435 gen_addr_add(ctx, EA8, EA, 8);
3436 gen_qemu_st64(ctx, gpr2, EA8);
3437 tcg_temp_free(EA8);
3438 #endif
3439 } else {
3440 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3441 }
3442 gen_set_label(l1);
3443 tcg_gen_movi_tl(cpu_reserve, -1);
3444 }
3445 #endif
3446
3447 #define STCX(name, len) \
3448 static void gen_##name(DisasContext *ctx) \
3449 { \
3450 TCGv t0; \
3451 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3452 gen_inval_exception(ctx, \
3453 POWERPC_EXCP_INVAL_INVAL); \
3454 return; \
3455 } \
3456 gen_set_access_type(ctx, ACCESS_RES); \
3457 t0 = tcg_temp_local_new(); \
3458 gen_addr_reg_index(ctx, t0); \
3459 if (len > 1) { \
3460 gen_check_align(ctx, t0, (len)-1); \
3461 } \
3462 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3463 tcg_temp_free(t0); \
3464 }
3465
3466 STCX(stbcx_, 1);
3467 STCX(sthcx_, 2);
3468 STCX(stwcx_, 4);
3469
3470 #if defined(TARGET_PPC64)
3471 /* ldarx */
3472 LARX(ldarx, 8, ld64);
3473
3474 /* lqarx */
3475 static void gen_lqarx(DisasContext *ctx)
3476 {
3477 TCGv EA;
3478 int rd = rD(ctx->opcode);
3479 TCGv gpr1, gpr2;
3480
3481 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3482 (rd == rB(ctx->opcode)))) {
3483 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3484 return;
3485 }
3486
3487 gen_set_access_type(ctx, ACCESS_RES);
3488 EA = tcg_temp_local_new();
3489 gen_addr_reg_index(ctx, EA);
3490 gen_check_align(ctx, EA, 15);
3491 if (unlikely(ctx->le_mode)) {
3492 gpr1 = cpu_gpr[rd+1];
3493 gpr2 = cpu_gpr[rd];
3494 } else {
3495 gpr1 = cpu_gpr[rd];
3496 gpr2 = cpu_gpr[rd+1];
3497 }
3498 gen_qemu_ld64(ctx, gpr1, EA);
3499 tcg_gen_mov_tl(cpu_reserve, EA);
3500
3501 gen_addr_add(ctx, EA, EA, 8);
3502 gen_qemu_ld64(ctx, gpr2, EA);
3503
3504 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3505 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3506
3507 tcg_temp_free(EA);
3508 }
3509
3510 /* stdcx. */
3511 STCX(stdcx_, 8);
3512 STCX(stqcx_, 16);
3513 #endif /* defined(TARGET_PPC64) */
3514
3515 /* sync */
3516 static void gen_sync(DisasContext *ctx)
3517 {
3518 uint32_t l = (ctx->opcode >> 21) & 3;
3519
3520 /*
3521 * We may need to check for a pending TLB flush.
3522 *
3523 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3524 *
3525 * Additionally, this can only happen in kernel mode however so
3526 * check MSR_PR as well.
3527 */
3528 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3529 gen_check_tlb_flush(ctx);
3530 }
3531 }
3532
3533 /* wait */
3534 static void gen_wait(DisasContext *ctx)
3535 {
3536 TCGv_i32 t0 = tcg_const_i32(1);
3537 tcg_gen_st_i32(t0, cpu_env,
3538 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3539 tcg_temp_free_i32(t0);
3540 /* Stop translation, as the CPU is supposed to sleep from now */
3541 gen_exception_err(ctx, EXCP_HLT, 1);
3542 }
3543
3544 /*** Floating-point load ***/
3545 #define GEN_LDF(name, ldop, opc, type) \
3546 static void glue(gen_, name)(DisasContext *ctx) \
3547 { \
3548 TCGv EA; \
3549 if (unlikely(!ctx->fpu_enabled)) { \
3550 gen_exception(ctx, POWERPC_EXCP_FPU); \
3551 return; \
3552 } \
3553 gen_set_access_type(ctx, ACCESS_FLOAT); \
3554 EA = tcg_temp_new(); \
3555 gen_addr_imm_index(ctx, EA, 0); \
3556 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3557 tcg_temp_free(EA); \
3558 }
3559
3560 #define GEN_LDUF(name, ldop, opc, type) \
3561 static void glue(gen_, name##u)(DisasContext *ctx) \
3562 { \
3563 TCGv EA; \
3564 if (unlikely(!ctx->fpu_enabled)) { \
3565 gen_exception(ctx, POWERPC_EXCP_FPU); \
3566 return; \
3567 } \
3568 if (unlikely(rA(ctx->opcode) == 0)) { \
3569 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3570 return; \
3571 } \
3572 gen_set_access_type(ctx, ACCESS_FLOAT); \
3573 EA = tcg_temp_new(); \
3574 gen_addr_imm_index(ctx, EA, 0); \
3575 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3576 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3577 tcg_temp_free(EA); \
3578 }
3579
3580 #define GEN_LDUXF(name, ldop, opc, type) \
3581 static void glue(gen_, name##ux)(DisasContext *ctx) \
3582 { \
3583 TCGv EA; \
3584 if (unlikely(!ctx->fpu_enabled)) { \
3585 gen_exception(ctx, POWERPC_EXCP_FPU); \
3586 return; \
3587 } \
3588 if (unlikely(rA(ctx->opcode) == 0)) { \
3589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3590 return; \
3591 } \
3592 gen_set_access_type(ctx, ACCESS_FLOAT); \
3593 EA = tcg_temp_new(); \
3594 gen_addr_reg_index(ctx, EA); \
3595 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3596 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3597 tcg_temp_free(EA); \
3598 }
3599
3600 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3601 static void glue(gen_, name##x)(DisasContext *ctx) \
3602 { \
3603 TCGv EA; \
3604 if (unlikely(!ctx->fpu_enabled)) { \
3605 gen_exception(ctx, POWERPC_EXCP_FPU); \
3606 return; \
3607 } \
3608 gen_set_access_type(ctx, ACCESS_FLOAT); \
3609 EA = tcg_temp_new(); \
3610 gen_addr_reg_index(ctx, EA); \
3611 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3612 tcg_temp_free(EA); \
3613 }
3614
3615 #define GEN_LDFS(name, ldop, op, type) \
3616 GEN_LDF(name, ldop, op | 0x20, type); \
3617 GEN_LDUF(name, ldop, op | 0x21, type); \
3618 GEN_LDUXF(name, ldop, op | 0x01, type); \
3619 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3620
3621 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3622 {
3623 TCGv t0 = tcg_temp_new();
3624 TCGv_i32 t1 = tcg_temp_new_i32();
3625 gen_qemu_ld32u(ctx, t0, arg2);
3626 tcg_gen_trunc_tl_i32(t1, t0);
3627 tcg_temp_free(t0);
3628 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3629 tcg_temp_free_i32(t1);
3630 }
3631
3632 /* lfd lfdu lfdux lfdx */
3633 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3634 /* lfs lfsu lfsux lfsx */
3635 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3636
3637 /* lfdp */
3638 static void gen_lfdp(DisasContext *ctx)
3639 {
3640 TCGv EA;
3641 if (unlikely(!ctx->fpu_enabled)) {
3642 gen_exception(ctx, POWERPC_EXCP_FPU);
3643 return;
3644 }
3645 gen_set_access_type(ctx, ACCESS_FLOAT);
3646 EA = tcg_temp_new();
3647 gen_addr_imm_index(ctx, EA, 0);
3648 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3649 64-bit byteswap already. */
3650 if (unlikely(ctx->le_mode)) {
3651 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3652 tcg_gen_addi_tl(EA, EA, 8);
3653 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3654 } else {
3655 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3656 tcg_gen_addi_tl(EA, EA, 8);
3657 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3658 }
3659 tcg_temp_free(EA);
3660 }
3661
3662 /* lfdpx */
3663 static void gen_lfdpx(DisasContext *ctx)
3664 {
3665 TCGv EA;
3666 if (unlikely(!ctx->fpu_enabled)) {
3667 gen_exception(ctx, POWERPC_EXCP_FPU);
3668 return;
3669 }
3670 gen_set_access_type(ctx, ACCESS_FLOAT);
3671 EA = tcg_temp_new();
3672 gen_addr_reg_index(ctx, EA);
3673 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3674 64-bit byteswap already. */
3675 if (unlikely(ctx->le_mode)) {
3676 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3677 tcg_gen_addi_tl(EA, EA, 8);
3678 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3679 } else {
3680 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3681 tcg_gen_addi_tl(EA, EA, 8);
3682 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3683 }
3684 tcg_temp_free(EA);
3685 }
3686
3687 /* lfiwax */
3688 static void gen_lfiwax(DisasContext *ctx)
3689 {
3690 TCGv EA;
3691 TCGv t0;
3692 if (unlikely(!ctx->fpu_enabled)) {
3693 gen_exception(ctx, POWERPC_EXCP_FPU);
3694 return;
3695 }
3696 gen_set_access_type(ctx, ACCESS_FLOAT);
3697 EA = tcg_temp_new();
3698 t0 = tcg_temp_new();
3699 gen_addr_reg_index(ctx, EA);
3700 gen_qemu_ld32s(ctx, t0, EA);
3701 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3702 tcg_temp_free(EA);
3703 tcg_temp_free(t0);
3704 }
3705
3706 /* lfiwzx */
3707 static void gen_lfiwzx(DisasContext *ctx)
3708 {
3709 TCGv EA;
3710 if (unlikely(!ctx->fpu_enabled)) {
3711 gen_exception(ctx, POWERPC_EXCP_FPU);
3712 return;
3713 }
3714 gen_set_access_type(ctx, ACCESS_FLOAT);
3715 EA = tcg_temp_new();
3716 gen_addr_reg_index(ctx, EA);
3717 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3718 tcg_temp_free(EA);
3719 }
3720 /*** Floating-point store ***/
3721 #define GEN_STF(name, stop, opc, type) \
3722 static void glue(gen_, name)(DisasContext *ctx) \
3723 { \
3724 TCGv EA; \
3725 if (unlikely(!ctx->fpu_enabled)) { \
3726 gen_exception(ctx, POWERPC_EXCP_FPU); \
3727 return; \
3728 } \
3729 gen_set_access_type(ctx, ACCESS_FLOAT); \
3730 EA = tcg_temp_new(); \
3731 gen_addr_imm_index(ctx, EA, 0); \
3732 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3733 tcg_temp_free(EA); \
3734 }
3735
3736 #define GEN_STUF(name, stop, opc, type) \
3737 static void glue(gen_, name##u)(DisasContext *ctx) \
3738 { \
3739 TCGv EA; \
3740 if (unlikely(!ctx->fpu_enabled)) { \
3741 gen_exception(ctx, POWERPC_EXCP_FPU); \
3742 return; \
3743 } \
3744 if (unlikely(rA(ctx->opcode) == 0)) { \
3745 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3746 return; \
3747 } \
3748 gen_set_access_type(ctx, ACCESS_FLOAT); \
3749 EA = tcg_temp_new(); \
3750 gen_addr_imm_index(ctx, EA, 0); \
3751 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3752 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3753 tcg_temp_free(EA); \
3754 }
3755
3756 #define GEN_STUXF(name, stop, opc, type) \
3757 static void glue(gen_, name##ux)(DisasContext *ctx) \
3758 { \
3759 TCGv EA; \
3760 if (unlikely(!ctx->fpu_enabled)) { \
3761 gen_exception(ctx, POWERPC_EXCP_FPU); \
3762 return; \
3763 } \
3764 if (unlikely(rA(ctx->opcode) == 0)) { \
3765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3766 return; \
3767 } \
3768 gen_set_access_type(ctx, ACCESS_FLOAT); \
3769 EA = tcg_temp_new(); \
3770 gen_addr_reg_index(ctx, EA); \
3771 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3772 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3773 tcg_temp_free(EA); \
3774 }
3775
3776 #define GEN_STXF(name, stop, opc2, opc3, type) \
3777 static void glue(gen_, name##x)(DisasContext *ctx) \
3778 { \
3779 TCGv EA; \
3780 if (unlikely(!ctx->fpu_enabled)) { \
3781 gen_exception(ctx, POWERPC_EXCP_FPU); \
3782 return; \
3783 } \
3784 gen_set_access_type(ctx, ACCESS_FLOAT); \
3785 EA = tcg_temp_new(); \
3786 gen_addr_reg_index(ctx, EA); \
3787 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3788 tcg_temp_free(EA); \
3789 }
3790
3791 #define GEN_STFS(name, stop, op, type) \
3792 GEN_STF(name, stop, op | 0x20, type); \
3793 GEN_STUF(name, stop, op | 0x21, type); \
3794 GEN_STUXF(name, stop, op | 0x01, type); \
3795 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3796
3797 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3798 {
3799 TCGv_i32 t0 = tcg_temp_new_i32();
3800 TCGv t1 = tcg_temp_new();
3801 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3802 tcg_gen_extu_i32_tl(t1, t0);
3803 tcg_temp_free_i32(t0);
3804 gen_qemu_st32(ctx, t1, arg2);
3805 tcg_temp_free(t1);
3806 }
3807
3808 /* stfd stfdu stfdux stfdx */
3809 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3810 /* stfs stfsu stfsux stfsx */
3811 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3812
3813 /* stfdp */
3814 static void gen_stfdp(DisasContext *ctx)
3815 {
3816 TCGv EA;
3817 if (unlikely(!ctx->fpu_enabled)) {
3818 gen_exception(ctx, POWERPC_EXCP_FPU);
3819 return;
3820 }
3821 gen_set_access_type(ctx, ACCESS_FLOAT);
3822 EA = tcg_temp_new();
3823 gen_addr_imm_index(ctx, EA, 0);
3824 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3825 64-bit byteswap already. */
3826 if (unlikely(ctx->le_mode)) {
3827 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3828 tcg_gen_addi_tl(EA, EA, 8);
3829 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3830 } else {
3831 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3832 tcg_gen_addi_tl(EA, EA, 8);
3833 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3834 }
3835 tcg_temp_free(EA);
3836 }
3837
3838 /* stfdpx */
3839 static void gen_stfdpx(DisasContext *ctx)
3840 {
3841 TCGv EA;
3842 if (unlikely(!ctx->fpu_enabled)) {
3843 gen_exception(ctx, POWERPC_EXCP_FPU);
3844 return;
3845 }
3846 gen_set_access_type(ctx, ACCESS_FLOAT);
3847 EA = tcg_temp_new();
3848 gen_addr_reg_index(ctx, EA);
3849 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3850 64-bit byteswap already. */
3851 if (unlikely(ctx->le_mode)) {
3852 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3853 tcg_gen_addi_tl(EA, EA, 8);
3854 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3855 } else {
3856 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3857 tcg_gen_addi_tl(EA, EA, 8);
3858 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3859 }
3860 tcg_temp_free(EA);
3861 }
3862
3863 /* Optional: */
3864 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3865 {
3866 TCGv t0 = tcg_temp_new();
3867 tcg_gen_trunc_i64_tl(t0, arg1),
3868 gen_qemu_st32(ctx, t0, arg2);
3869 tcg_temp_free(t0);
3870 }
3871 /* stfiwx */
3872 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3873
3874 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3875 {
3876 #if defined(TARGET_PPC64)
3877 if (ctx->has_cfar)
3878 tcg_gen_movi_tl(cpu_cfar, nip);
3879 #endif
3880 }
3881
3882 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3883 {
3884 if (unlikely(ctx->singlestep_enabled)) {
3885 return false;
3886 }
3887
3888 #ifndef CONFIG_USER_ONLY
3889 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3890 #else
3891 return true;
3892 #endif
3893 }
3894
3895 /*** Branch ***/
3896 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3897 {
3898 if (NARROW_MODE(ctx)) {
3899 dest = (uint32_t) dest;
3900 }
3901 if (use_goto_tb(ctx, dest)) {
3902 tcg_gen_goto_tb(n);
3903 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3904 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3905 } else {
3906 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3907 if (unlikely(ctx->singlestep_enabled)) {
3908 if ((ctx->singlestep_enabled &
3909 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3910 (ctx->exception == POWERPC_EXCP_BRANCH ||
3911 ctx->exception == POWERPC_EXCP_TRACE)) {
3912 target_ulong tmp = ctx->nip;
3913 ctx->nip = dest;
3914 gen_exception(ctx, POWERPC_EXCP_TRACE);
3915 ctx->nip = tmp;
3916 }
3917 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3918 gen_debug_exception(ctx);
3919 }
3920 }
3921 tcg_gen_exit_tb(0);
3922 }
3923 }
3924
3925 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3926 {
3927 if (NARROW_MODE(ctx)) {
3928 nip = (uint32_t)nip;
3929 }
3930 tcg_gen_movi_tl(cpu_lr, nip);
3931 }
3932
3933 /* b ba bl bla */
3934 static void gen_b(DisasContext *ctx)
3935 {
3936 target_ulong li, target;
3937
3938 ctx->exception = POWERPC_EXCP_BRANCH;
3939 /* sign extend LI */
3940 li = LI(ctx->opcode);
3941 li = (li ^ 0x02000000) - 0x02000000;
3942 if (likely(AA(ctx->opcode) == 0)) {
3943 target = ctx->nip + li - 4;
3944 } else {
3945 target = li;
3946 }
3947 if (LK(ctx->opcode)) {
3948 gen_setlr(ctx, ctx->nip);
3949 }
3950 gen_update_cfar(ctx, ctx->nip);
3951 gen_goto_tb(ctx, 0, target);
3952 }
3953
3954 #define BCOND_IM 0
3955 #define BCOND_LR 1
3956 #define BCOND_CTR 2
3957 #define BCOND_TAR 3
3958
3959 static inline void gen_bcond(DisasContext *ctx, int type)
3960 {
3961 uint32_t bo = BO(ctx->opcode);
3962 TCGLabel *l1;
3963 TCGv target;
3964
3965 ctx->exception = POWERPC_EXCP_BRANCH;
3966 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3967 target = tcg_temp_local_new();
3968 if (type == BCOND_CTR)
3969 tcg_gen_mov_tl(target, cpu_ctr);
3970 else if (type == BCOND_TAR)
3971 gen_load_spr(target, SPR_TAR);
3972 else
3973 tcg_gen_mov_tl(target, cpu_lr);
3974 } else {
3975 TCGV_UNUSED(target);
3976 }
3977 if (LK(ctx->opcode))
3978 gen_setlr(ctx, ctx->nip);
3979 l1 = gen_new_label();
3980 if ((bo & 0x4) == 0) {
3981 /* Decrement and test CTR */
3982 TCGv temp = tcg_temp_new();
3983 if (unlikely(type == BCOND_CTR)) {
3984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3985 return;
3986 }
3987 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3988 if (NARROW_MODE(ctx)) {
3989 tcg_gen_ext32u_tl(temp, cpu_ctr);
3990 } else {
3991 tcg_gen_mov_tl(temp, cpu_ctr);
3992 }
3993 if (bo & 0x2) {
3994 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3995 } else {
3996 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3997 }
3998 tcg_temp_free(temp);
3999 }
4000 if ((bo & 0x10) == 0) {
4001 /* Test CR */
4002 uint32_t bi = BI(ctx->opcode);
4003 uint32_t mask = 0x08 >> (bi & 0x03);
4004 TCGv_i32 temp = tcg_temp_new_i32();
4005
4006 if (bo & 0x8) {
4007 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4008 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4009 } else {
4010 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4011 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4012 }
4013 tcg_temp_free_i32(temp);
4014 }
4015 gen_update_cfar(ctx, ctx->nip);
4016 if (type == BCOND_IM) {
4017 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4018 if (likely(AA(ctx->opcode) == 0)) {
4019 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
4020 } else {
4021 gen_goto_tb(ctx, 0, li);
4022 }
4023 gen_set_label(l1);
4024 gen_goto_tb(ctx, 1, ctx->nip);
4025 } else {
4026 if (NARROW_MODE(ctx)) {
4027 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4028 } else {
4029 tcg_gen_andi_tl(cpu_nip, target, ~3);
4030 }
4031 tcg_gen_exit_tb(0);
4032 gen_set_label(l1);
4033 gen_update_nip(ctx, ctx->nip);
4034 tcg_gen_exit_tb(0);
4035 }
4036 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4037 tcg_temp_free(target);
4038 }
4039 }
4040
4041 static void gen_bc(DisasContext *ctx)
4042 {
4043 gen_bcond(ctx, BCOND_IM);
4044 }
4045
4046 static void gen_bcctr(DisasContext *ctx)
4047 {
4048 gen_bcond(ctx, BCOND_CTR);
4049 }
4050
4051 static void gen_bclr(DisasContext *ctx)
4052 {
4053 gen_bcond(ctx, BCOND_LR);
4054 }
4055
4056 static void gen_bctar(DisasContext *ctx)
4057 {
4058 gen_bcond(ctx, BCOND_TAR);
4059 }
4060
4061 /*** Condition register logical ***/
4062 #define GEN_CRLOGIC(name, tcg_op, opc) \
4063 static void glue(gen_, name)(DisasContext *ctx) \
4064 { \
4065 uint8_t bitmask; \
4066 int sh; \
4067 TCGv_i32 t0, t1; \
4068 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4069 t0 = tcg_temp_new_i32(); \
4070 if (sh > 0) \
4071 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4072 else if (sh < 0) \
4073 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4074 else \
4075 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4076 t1 = tcg_temp_new_i32(); \
4077 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4078 if (sh > 0) \
4079 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4080 else if (sh < 0) \
4081 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4082 else \
4083 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4084 tcg_op(t0, t0, t1); \
4085 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4086 tcg_gen_andi_i32(t0, t0, bitmask); \
4087 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4088 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4089 tcg_temp_free_i32(t0); \
4090 tcg_temp_free_i32(t1); \
4091 }
4092
4093 /* crand */
4094 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4095 /* crandc */
4096 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4097 /* creqv */
4098 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4099 /* crnand */
4100 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4101 /* crnor */
4102 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4103 /* cror */
4104 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4105 /* crorc */
4106 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4107 /* crxor */
4108 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4109
4110 /* mcrf */
4111 static void gen_mcrf(DisasContext *ctx)
4112 {
4113 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4114 }
4115
4116 /*** System linkage ***/
4117
4118 /* rfi (supervisor only) */
4119 static void gen_rfi(DisasContext *ctx)
4120 {
4121 #if defined(CONFIG_USER_ONLY)
4122 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4123 #else
4124 /* Restore CPU state */
4125 if (unlikely(ctx->pr)) {
4126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4127 return;
4128 }
4129 gen_update_cfar(ctx, ctx->nip);
4130 gen_helper_rfi(cpu_env);
4131 gen_sync_exception(ctx);
4132 #endif
4133 }
4134
4135 #if defined(TARGET_PPC64)
4136 static void gen_rfid(DisasContext *ctx)
4137 {
4138 #if defined(CONFIG_USER_ONLY)
4139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4140 #else
4141 /* Restore CPU state */
4142 if (unlikely(ctx->pr)) {
4143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4144 return;
4145 }
4146 gen_update_cfar(ctx, ctx->nip);
4147 gen_helper_rfid(cpu_env);
4148 gen_sync_exception(ctx);
4149 #endif
4150 }
4151
4152 static void gen_hrfid(DisasContext *ctx)
4153 {
4154 #if defined(CONFIG_USER_ONLY)
4155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4156 #else
4157 /* Restore CPU state */
4158 if (unlikely(ctx->pr || !ctx->hv)) {
4159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4160 return;
4161 }
4162 gen_helper_hrfid(cpu_env);
4163 gen_sync_exception(ctx);
4164 #endif
4165 }
4166 #endif
4167
4168 /* sc */
4169 #if defined(CONFIG_USER_ONLY)
4170 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4171 #else
4172 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4173 #endif
4174 static void gen_sc(DisasContext *ctx)
4175 {
4176 uint32_t lev;
4177
4178 lev = (ctx->opcode >> 5) & 0x7F;
4179 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4180 }
4181
4182 /*** Trap ***/
4183
4184 /* tw */
4185 static void gen_tw(DisasContext *ctx)
4186 {
4187 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4188 /* Update the nip since this might generate a trap exception */
4189 gen_update_nip(ctx, ctx->nip);
4190 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4191 t0);
4192 tcg_temp_free_i32(t0);
4193 }
4194
4195 /* twi */
4196 static void gen_twi(DisasContext *ctx)
4197 {
4198 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4199 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4200 /* Update the nip since this might generate a trap exception */
4201 gen_update_nip(ctx, ctx->nip);
4202 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4203 tcg_temp_free(t0);
4204 tcg_temp_free_i32(t1);
4205 }
4206
4207 #if defined(TARGET_PPC64)
4208 /* td */
4209 static void gen_td(DisasContext *ctx)
4210 {
4211 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4212 /* Update the nip since this might generate a trap exception */
4213 gen_update_nip(ctx, ctx->nip);
4214 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4215 t0);
4216 tcg_temp_free_i32(t0);
4217 }
4218
4219 /* tdi */
4220 static void gen_tdi(DisasContext *ctx)
4221 {
4222 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4223 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4224 /* Update the nip since this might generate a trap exception */
4225 gen_update_nip(ctx, ctx->nip);
4226 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4227 tcg_temp_free(t0);
4228 tcg_temp_free_i32(t1);
4229 }
4230 #endif
4231
4232 /*** Processor control ***/
4233
4234 static void gen_read_xer(TCGv dst)
4235 {
4236 TCGv t0 = tcg_temp_new();
4237 TCGv t1 = tcg_temp_new();
4238 TCGv t2 = tcg_temp_new();
4239 tcg_gen_mov_tl(dst, cpu_xer);
4240 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4241 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4242 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4243 tcg_gen_or_tl(t0, t0, t1);
4244 tcg_gen_or_tl(dst, dst, t2);
4245 tcg_gen_or_tl(dst, dst, t0);
4246 tcg_temp_free(t0);
4247 tcg_temp_free(t1);
4248 tcg_temp_free(t2);
4249 }
4250
4251 static void gen_write_xer(TCGv src)
4252 {
4253 tcg_gen_andi_tl(cpu_xer, src,
4254 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4255 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4256 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4257 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4258 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4259 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4260 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4261 }
4262
4263 /* mcrxr */
4264 static void gen_mcrxr(DisasContext *ctx)
4265 {
4266 TCGv_i32 t0 = tcg_temp_new_i32();
4267 TCGv_i32 t1 = tcg_temp_new_i32();
4268 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4269
4270 tcg_gen_trunc_tl_i32(t0, cpu_so);
4271 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4272 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4273 tcg_gen_shli_i32(t0, t0, 3);
4274 tcg_gen_shli_i32(t1, t1, 2);
4275 tcg_gen_shli_i32(dst, dst, 1);
4276 tcg_gen_or_i32(dst, dst, t0);
4277 tcg_gen_or_i32(dst, dst, t1);
4278 tcg_temp_free_i32(t0);
4279 tcg_temp_free_i32(t1);
4280
4281 tcg_gen_movi_tl(cpu_so, 0);
4282 tcg_gen_movi_tl(cpu_ov, 0);
4283 tcg_gen_movi_tl(cpu_ca, 0);
4284 }
4285
4286 /* mfcr mfocrf */
4287 static void gen_mfcr(DisasContext *ctx)
4288 {
4289 uint32_t crm, crn;
4290
4291 if (likely(ctx->opcode & 0x00100000)) {
4292 crm = CRM(ctx->opcode);
4293 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4294 crn = ctz32 (crm);
4295 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4296 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4297 cpu_gpr[rD(ctx->opcode)], crn * 4);
4298 }
4299 } else {
4300 TCGv_i32 t0 = tcg_temp_new_i32();
4301 tcg_gen_mov_i32(t0, cpu_crf[0]);
4302 tcg_gen_shli_i32(t0, t0, 4);
4303 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4304 tcg_gen_shli_i32(t0, t0, 4);
4305 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4306 tcg_gen_shli_i32(t0, t0, 4);
4307 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4308 tcg_gen_shli_i32(t0, t0, 4);
4309 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4310 tcg_gen_shli_i32(t0, t0, 4);
4311 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4312 tcg_gen_shli_i32(t0, t0, 4);
4313 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4314 tcg_gen_shli_i32(t0, t0, 4);
4315 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4316 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4317 tcg_temp_free_i32(t0);
4318 }
4319 }
4320
4321 /* mfmsr */
4322 static void gen_mfmsr(DisasContext *ctx)
4323 {
4324 #if defined(CONFIG_USER_ONLY)
4325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4326 #else
4327 if (unlikely(ctx->pr)) {
4328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4329 return;
4330 }
4331 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4332 #endif
4333 }
4334
4335 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4336 {
4337 #if 0
4338 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4339 printf("ERROR: try to access SPR %d !\n", sprn);
4340 #endif
4341 }
4342 #define SPR_NOACCESS (&spr_noaccess)
4343
4344 /* mfspr */
4345 static inline void gen_op_mfspr(DisasContext *ctx)
4346 {
4347 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4348 uint32_t sprn = SPR(ctx->opcode);
4349
4350 #if defined(CONFIG_USER_ONLY)
4351 read_cb = ctx->spr_cb[sprn].uea_read;
4352 #else
4353 if (ctx->pr) {
4354 read_cb = ctx->spr_cb[sprn].uea_read;
4355 } else if (ctx->hv) {
4356 read_cb = ctx->spr_cb[sprn].hea_read;
4357 } else {
4358 read_cb = ctx->spr_cb[sprn].oea_read;
4359 }
4360 #endif
4361 if (likely(read_cb != NULL)) {
4362 if (likely(read_cb != SPR_NOACCESS)) {
4363 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4364 } else {
4365 /* Privilege exception */
4366 /* This is a hack to avoid warnings when running Linux:
4367 * this OS breaks the PowerPC virtualisation model,
4368 * allowing userland application to read the PVR
4369 */
4370 if (sprn != SPR_PVR) {
4371 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4372 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4373 if (qemu_log_separate()) {
4374 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4375 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4376 }
4377 }
4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4379 }
4380 } else {
4381 /* Not defined */
4382 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4383 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4384 if (qemu_log_separate()) {
4385 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4386 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4387 }
4388 /* Only generate an exception in user space, otherwise this is a nop */
4389 if (ctx->pr) {
4390 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4391 }
4392 }
4393 }
4394
4395 static void gen_mfspr(DisasContext *ctx)
4396 {
4397 gen_op_mfspr(ctx);
4398 }
4399
4400 /* mftb */
4401 static void gen_mftb(DisasContext *ctx)
4402 {
4403 gen_op_mfspr(ctx);
4404 }
4405
4406 /* mtcrf mtocrf*/
4407 static void gen_mtcrf(DisasContext *ctx)
4408 {
4409 uint32_t crm, crn;
4410
4411 crm = CRM(ctx->opcode);
4412 if (likely((ctx->opcode & 0x00100000))) {
4413 if (crm && ((crm & (crm - 1)) == 0)) {
4414 TCGv_i32 temp = tcg_temp_new_i32();
4415 crn = ctz32 (crm);
4416 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4417 tcg_gen_shri_i32(temp, temp, crn * 4);
4418 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4419 tcg_temp_free_i32(temp);
4420 }
4421 } else {
4422 TCGv_i32 temp = tcg_temp_new_i32();
4423 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4424 for (crn = 0 ; crn < 8 ; crn++) {
4425 if (crm & (1 << crn)) {
4426 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4427 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4428 }
4429 }
4430 tcg_temp_free_i32(temp);
4431 }
4432 }
4433
4434 /* mtmsr */
4435 #if defined(TARGET_PPC64)
4436 static void gen_mtmsrd(DisasContext *ctx)
4437 {
4438 #if defined(CONFIG_USER_ONLY)
4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4440 #else
4441 if (unlikely(ctx->pr)) {
4442 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4443 return;
4444 }
4445 if (ctx->opcode & 0x00010000) {
4446 /* Special form that does not need any synchronisation */
4447 TCGv t0 = tcg_temp_new();
4448 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4449 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4450 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4451 tcg_temp_free(t0);
4452 } else {
4453 /* XXX: we need to update nip before the store
4454 * if we enter power saving mode, we will exit the loop
4455 * directly from ppc_store_msr
4456 */
4457 gen_update_nip(ctx, ctx->nip);
4458 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4459 /* Must stop the translation as machine state (may have) changed */
4460 /* Note that mtmsr is not always defined as context-synchronizing */
4461 gen_stop_exception(ctx);
4462 }
4463 #endif
4464 }
4465 #endif
4466
4467 static void gen_mtmsr(DisasContext *ctx)
4468 {
4469 #if defined(CONFIG_USER_ONLY)
4470 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4471 #else
4472 if (unlikely(ctx->pr)) {
4473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4474 return;
4475 }
4476 if (ctx->opcode & 0x00010000) {
4477 /* Special form that does not need any synchronisation */
4478 TCGv t0 = tcg_temp_new();
4479 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4480 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4481 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4482 tcg_temp_free(t0);
4483 } else {
4484 TCGv msr = tcg_temp_new();
4485
4486 /* XXX: we need to update nip before the store
4487 * if we enter power saving mode, we will exit the loop
4488 * directly from ppc_store_msr
4489 */
4490 gen_update_nip(ctx, ctx->nip);
4491 #if defined(TARGET_PPC64)
4492 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4493 #else
4494 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4495 #endif
4496 gen_helper_store_msr(cpu_env, msr);
4497 tcg_temp_free(msr);
4498 /* Must stop the translation as machine state (may have) changed */
4499 /* Note that mtmsr is not always defined as context-synchronizing */
4500 gen_stop_exception(ctx);
4501 }
4502 #endif
4503 }
4504
4505 /* mtspr */
4506 static void gen_mtspr(DisasContext *ctx)
4507 {
4508 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4509 uint32_t sprn = SPR(ctx->opcode);
4510
4511 #if defined(CONFIG_USER_ONLY)
4512 write_cb = ctx->spr_cb[sprn].uea_write;
4513 #else
4514 if (ctx->pr) {
4515 write_cb = ctx->spr_cb[sprn].uea_write;
4516 } else if (ctx->hv) {
4517 write_cb = ctx->spr_cb[sprn].hea_write;
4518 } else {
4519 write_cb = ctx->spr_cb[sprn].oea_write;
4520 }
4521 #endif
4522 if (likely(write_cb != NULL)) {
4523 if (likely(write_cb != SPR_NOACCESS)) {
4524 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4525 } else {
4526 /* Privilege exception */
4527 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4528 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4529 if (qemu_log_separate()) {
4530 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4531 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4532 }
4533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4534 }
4535 } else {
4536 /* Not defined */
4537 if (qemu_log_separate()) {
4538 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4539 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4540 }
4541 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4542 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4543
4544 /* Only generate an exception in user space, otherwise this is a nop */
4545 if (ctx->pr) {
4546 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4547 }
4548 }
4549 }
4550
4551 /*** Cache management ***/
4552
4553 /* dcbf */
4554 static void gen_dcbf(DisasContext *ctx)
4555 {
4556 /* XXX: specification says this is treated as a load by the MMU */
4557 TCGv t0;
4558 gen_set_access_type(ctx, ACCESS_CACHE);
4559 t0 = tcg_temp_new();
4560 gen_addr_reg_index(ctx, t0);
4561 gen_qemu_ld8u(ctx, t0, t0);
4562 tcg_temp_free(t0);
4563 }
4564
4565 /* dcbi (Supervisor only) */
4566 static void gen_dcbi(DisasContext *ctx)
4567 {
4568 #if defined(CONFIG_USER_ONLY)
4569 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4570 #else
4571 TCGv EA, val;
4572 if (unlikely(ctx->pr)) {
4573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4574 return;
4575 }
4576 EA = tcg_temp_new();
4577 gen_set_access_type(ctx, ACCESS_CACHE);
4578 gen_addr_reg_index(ctx, EA);
4579 val = tcg_temp_new();
4580 /* XXX: specification says this should be treated as a store by the MMU */
4581 gen_qemu_ld8u(ctx, val, EA);
4582 gen_qemu_st8(ctx, val, EA);
4583 tcg_temp_free(val);
4584 tcg_temp_free(EA);
4585 #endif
4586 }
4587
4588 /* dcdst */
4589 static void gen_dcbst(DisasContext *ctx)
4590 {
4591 /* XXX: specification say this is treated as a load by the MMU */
4592 TCGv t0;
4593 gen_set_access_type(ctx, ACCESS_CACHE);
4594 t0 = tcg_temp_new();
4595 gen_addr_reg_index(ctx, t0);
4596 gen_qemu_ld8u(ctx, t0, t0);
4597 tcg_temp_free(t0);
4598 }
4599
4600 /* dcbt */
4601 static void gen_dcbt(DisasContext *ctx)
4602 {
4603 /* interpreted as no-op */
4604 /* XXX: specification say this is treated as a load by the MMU
4605 * but does not generate any exception
4606 */
4607 }
4608
4609 /* dcbtst */
4610 static void gen_dcbtst(DisasContext *ctx)
4611 {
4612 /* interpreted as no-op */
4613 /* XXX: specification say this is treated as a load by the MMU
4614 * but does not generate any exception
4615 */
4616 }
4617
4618 /* dcbtls */
4619 static void gen_dcbtls(DisasContext *ctx)
4620 {
4621 /* Always fails locking the cache */
4622 TCGv t0 = tcg_temp_new();
4623 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4624 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4625 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4626 tcg_temp_free(t0);
4627 }
4628
4629 /* dcbz */
4630 static void gen_dcbz(DisasContext *ctx)
4631 {
4632 TCGv tcgv_addr;
4633 TCGv_i32 tcgv_is_dcbzl;
4634 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4635
4636 gen_set_access_type(ctx, ACCESS_CACHE);
4637 /* NIP cannot be restored if the memory exception comes from an helper */
4638 gen_update_nip(ctx, ctx->nip - 4);
4639 tcgv_addr = tcg_temp_new();
4640 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4641
4642 gen_addr_reg_index(ctx, tcgv_addr);
4643 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4644
4645 tcg_temp_free(tcgv_addr);
4646 tcg_temp_free_i32(tcgv_is_dcbzl);
4647 }
4648
4649 /* dst / dstt */
4650 static void gen_dst(DisasContext *ctx)
4651 {
4652 if (rA(ctx->opcode) == 0) {
4653 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4654 } else {
4655 /* interpreted as no-op */
4656 }
4657 }
4658
4659 /* dstst /dststt */
4660 static void gen_dstst(DisasContext *ctx)
4661 {
4662 if (rA(ctx->opcode) == 0) {
4663 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4664 } else {
4665 /* interpreted as no-op */
4666 }
4667
4668 }
4669
4670 /* dss / dssall */
4671 static void gen_dss(DisasContext *ctx)
4672 {
4673 /* interpreted as no-op */
4674 }
4675
4676 /* icbi */
4677 static void gen_icbi(DisasContext *ctx)
4678 {
4679 TCGv t0;
4680 gen_set_access_type(ctx, ACCESS_CACHE);
4681 /* NIP cannot be restored if the memory exception comes from an helper */
4682 gen_update_nip(ctx, ctx->nip - 4);
4683 t0 = tcg_temp_new();
4684 gen_addr_reg_index(ctx, t0);
4685 gen_helper_icbi(cpu_env, t0);
4686 tcg_temp_free(t0);
4687 }
4688
4689 /* Optional: */
4690 /* dcba */
4691 static void gen_dcba(DisasContext *ctx)
4692 {
4693 /* interpreted as no-op */
4694 /* XXX: specification say this is treated as a store by the MMU
4695 * but does not generate any exception
4696 */
4697 }
4698
4699 /*** Segment register manipulation ***/
4700 /* Supervisor only: */
4701
4702 /* mfsr */
4703 static void gen_mfsr(DisasContext *ctx)
4704 {
4705 #if defined(CONFIG_USER_ONLY)
4706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4707 #else
4708 TCGv t0;
4709 if (unlikely(ctx->pr)) {
4710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4711 return;
4712 }
4713 t0 = tcg_const_tl(SR(ctx->opcode));
4714 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4715 tcg_temp_free(t0);
4716 #endif
4717 }
4718
4719 /* mfsrin */
4720 static void gen_mfsrin(DisasContext *ctx)
4721 {
4722 #if defined(CONFIG_USER_ONLY)
4723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4724 #else
4725 TCGv t0;
4726 if (unlikely(ctx->pr)) {
4727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4728 return;
4729 }
4730 t0 = tcg_temp_new();
4731 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4732 tcg_gen_andi_tl(t0, t0, 0xF);
4733 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4734 tcg_temp_free(t0);
4735 #endif
4736 }
4737
4738 /* mtsr */
4739 static void gen_mtsr(DisasContext *ctx)
4740 {
4741 #if defined(CONFIG_USER_ONLY)
4742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4743 #else
4744 TCGv t0;
4745 if (unlikely(ctx->pr)) {
4746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4747 return;
4748 }
4749 t0 = tcg_const_tl(SR(ctx->opcode));
4750 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4751 tcg_temp_free(t0);
4752 #endif
4753 }
4754
4755 /* mtsrin */
4756 static void gen_mtsrin(DisasContext *ctx)
4757 {
4758 #if defined(CONFIG_USER_ONLY)
4759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4760 #else
4761 TCGv t0;
4762 if (unlikely(ctx->pr)) {
4763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4764 return;
4765 }
4766 t0 = tcg_temp_new();
4767 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4768 tcg_gen_andi_tl(t0, t0, 0xF);
4769 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4770 tcg_temp_free(t0);
4771 #endif
4772 }
4773
4774 #if defined(TARGET_PPC64)
4775 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4776
4777 /* mfsr */
4778 static void gen_mfsr_64b(DisasContext *ctx)
4779 {
4780 #if defined(CONFIG_USER_ONLY)
4781 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4782 #else
4783 TCGv t0;
4784 if (unlikely(ctx->pr)) {
4785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4786 return;
4787 }
4788 t0 = tcg_const_tl(SR(ctx->opcode));
4789 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4790 tcg_temp_free(t0);
4791 #endif
4792 }
4793
4794 /* mfsrin */
4795 static void gen_mfsrin_64b(DisasContext *ctx)
4796 {
4797 #if defined(CONFIG_USER_ONLY)
4798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4799 #else
4800 TCGv t0;
4801 if (unlikely(ctx->pr)) {
4802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4803 return;
4804 }
4805 t0 = tcg_temp_new();
4806 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4807 tcg_gen_andi_tl(t0, t0, 0xF);
4808 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4809 tcg_temp_free(t0);
4810 #endif
4811 }
4812
4813 /* mtsr */
4814 static void gen_mtsr_64b(DisasContext *ctx)
4815 {
4816 #if defined(CONFIG_USER_ONLY)
4817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4818 #else
4819 TCGv t0;
4820 if (unlikely(ctx->pr)) {
4821 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4822 return;
4823 }
4824 t0 = tcg_const_tl(SR(ctx->opcode));
4825 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4826 tcg_temp_free(t0);
4827 #endif
4828 }
4829
4830 /* mtsrin */
4831 static void gen_mtsrin_64b(DisasContext *ctx)
4832 {
4833 #if defined(CONFIG_USER_ONLY)
4834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4835 #else
4836 TCGv t0;
4837 if (unlikely(ctx->pr)) {
4838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4839 return;
4840 }
4841 t0 = tcg_temp_new();
4842 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4843 tcg_gen_andi_tl(t0, t0, 0xF);
4844 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4845 tcg_temp_free(t0);
4846 #endif
4847 }
4848
4849 /* slbmte */
4850 static void gen_slbmte(DisasContext *ctx)
4851 {
4852 #if defined(CONFIG_USER_ONLY)
4853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4854 #else
4855 if (unlikely(ctx->pr)) {
4856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4857 return;
4858 }
4859 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4860 cpu_gpr[rS(ctx->opcode)]);
4861 #endif
4862 }
4863
4864 static void gen_slbmfee(DisasContext *ctx)
4865 {
4866 #if defined(CONFIG_USER_ONLY)
4867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4868 #else
4869 if (unlikely(ctx->pr)) {
4870 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4871 return;
4872 }
4873 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4874 cpu_gpr[rB(ctx->opcode)]);
4875 #endif
4876 }
4877
4878 static void gen_slbmfev(DisasContext *ctx)
4879 {
4880 #if defined(CONFIG_USER_ONLY)
4881 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4882 #else
4883 if (unlikely(ctx->pr)) {
4884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4885 return;
4886 }
4887 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4888 cpu_gpr[rB(ctx->opcode)]);
4889 #endif
4890 }
4891
4892 static void gen_slbfee_(DisasContext *ctx)
4893 {
4894 #if defined(CONFIG_USER_ONLY)
4895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4896 #else
4897 TCGLabel *l1, *l2;
4898
4899 if (unlikely(ctx->pr)) {
4900 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4901 return;
4902 }
4903 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4904 cpu_gpr[rB(ctx->opcode)]);
4905 l1 = gen_new_label();
4906 l2 = gen_new_label();
4907 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4908 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4909 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4910 tcg_gen_br(l2);
4911 gen_set_label(l1);
4912 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4913 gen_set_label(l2);
4914 #endif
4915 }
4916 #endif /* defined(TARGET_PPC64) */
4917
4918 /*** Lookaside buffer management ***/
4919 /* Optional & supervisor only: */
4920
4921 /* tlbia */
4922 static void gen_tlbia(DisasContext *ctx)
4923 {
4924 #if defined(CONFIG_USER_ONLY)
4925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4926 #else
4927 if (unlikely(ctx->pr || !ctx->hv)) {
4928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4929 return;
4930 }
4931 gen_helper_tlbia(cpu_env);
4932 #endif
4933 }
4934
4935 /* tlbiel */
4936 static void gen_tlbiel(DisasContext *ctx)
4937 {
4938 #if defined(CONFIG_USER_ONLY)
4939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4940 #else
4941 if (unlikely(ctx->pr)) {
4942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4943 return;
4944 }
4945 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4946 #endif
4947 }
4948
4949 /* tlbie */
4950 static void gen_tlbie(DisasContext *ctx)
4951 {
4952 #if defined(CONFIG_USER_ONLY)
4953 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4954 #else
4955 if (unlikely(ctx->pr || !ctx->hv)) {
4956 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4957 return;
4958 }
4959 if (NARROW_MODE(ctx)) {
4960 TCGv t0 = tcg_temp_new();
4961 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4962 gen_helper_tlbie(cpu_env, t0);
4963 tcg_temp_free(t0);
4964 } else {
4965 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4966 }
4967 #endif
4968 }
4969
4970 /* tlbsync */
4971 static void gen_tlbsync(DisasContext *ctx)
4972 {
4973 #if defined(CONFIG_USER_ONLY)
4974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4975 #else
4976 if (unlikely(ctx->pr || !ctx->hv)) {
4977 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4978 return;
4979 }
4980 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4981 * embedded however needs to deal with tlbsync. We don't try to be
4982 * fancy and swallow the overhead of checking for both.
4983 */
4984 gen_check_tlb_flush(ctx);
4985 #endif
4986 }
4987
4988 #if defined(TARGET_PPC64)
4989 /* slbia */
4990 static void gen_slbia(DisasContext *ctx)
4991 {
4992 #if defined(CONFIG_USER_ONLY)
4993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4994 #else
4995 if (unlikely(ctx->pr)) {
4996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4997 return;
4998 }
4999 gen_helper_slbia(cpu_env);
5000 #endif
5001 }
5002
5003 /* slbie */
5004 static void gen_slbie(DisasContext *ctx)
5005 {
5006 #if defined(CONFIG_USER_ONLY)
5007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5008 #else
5009 if (unlikely(ctx->pr)) {
5010 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5011 return;
5012 }
5013 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5014 #endif
5015 }
5016 #endif
5017
5018 /*** External control ***/
5019 /* Optional: */
5020
5021 /* eciwx */
5022 static void gen_eciwx(DisasContext *ctx)
5023 {
5024 TCGv t0;
5025 /* Should check EAR[E] ! */
5026 gen_set_access_type(ctx, ACCESS_EXT);
5027 t0 = tcg_temp_new();
5028 gen_addr_reg_index(ctx, t0);
5029 gen_check_align(ctx, t0, 0x03);
5030 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5031 tcg_temp_free(t0);
5032 }
5033
5034 /* ecowx */
5035 static void gen_ecowx(DisasContext *ctx)
5036 {
5037 TCGv t0;
5038 /* Should check EAR[E] ! */
5039 gen_set_access_type(ctx, ACCESS_EXT);
5040 t0 = tcg_temp_new();
5041 gen_addr_reg_index(ctx, t0);
5042 gen_check_align(ctx, t0, 0x03);
5043 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5044 tcg_temp_free(t0);
5045 }
5046
5047 /* PowerPC 601 specific instructions */
5048
5049 /* abs - abs. */
5050 static void gen_abs(DisasContext *ctx)
5051 {
5052 TCGLabel *l1 = gen_new_label();
5053 TCGLabel *l2 = gen_new_label();
5054 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5055 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5056 tcg_gen_br(l2);
5057 gen_set_label(l1);
5058 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5059 gen_set_label(l2);
5060 if (unlikely(Rc(ctx->opcode) != 0))
5061 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5062 }
5063
5064 /* abso - abso. */
5065 static void gen_abso(DisasContext *ctx)
5066 {
5067 TCGLabel *l1 = gen_new_label();
5068 TCGLabel *l2 = gen_new_label();
5069 TCGLabel *l3 = gen_new_label();
5070 /* Start with XER OV disabled, the most likely case */
5071 tcg_gen_movi_tl(cpu_ov, 0);
5072 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5073 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5074 tcg_gen_movi_tl(cpu_ov, 1);
5075 tcg_gen_movi_tl(cpu_so, 1);
5076 tcg_gen_br(l2);
5077 gen_set_label(l1);
5078 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5079 tcg_gen_br(l3);
5080 gen_set_label(l2);
5081 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5082 gen_set_label(l3);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5085 }
5086
5087 /* clcs */
5088 static void gen_clcs(DisasContext *ctx)
5089 {
5090 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5091 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5092 tcg_temp_free_i32(t0);
5093 /* Rc=1 sets CR0 to an undefined state */
5094 }
5095
5096 /* div - div. */
5097 static void gen_div(DisasContext *ctx)
5098 {
5099 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5100 cpu_gpr[rB(ctx->opcode)]);
5101 if (unlikely(Rc(ctx->opcode) != 0))
5102 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5103 }
5104
5105 /* divo - divo. */
5106 static void gen_divo(DisasContext *ctx)
5107 {
5108 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5109 cpu_gpr[rB(ctx->opcode)]);
5110 if (unlikely(Rc(ctx->opcode) != 0))
5111 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5112 }
5113
5114 /* divs - divs. */
5115 static void gen_divs(DisasContext *ctx)
5116 {
5117 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5118 cpu_gpr[rB(ctx->opcode)]);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5121 }
5122
5123 /* divso - divso. */
5124 static void gen_divso(DisasContext *ctx)
5125 {
5126 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5127 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5128 if (unlikely(Rc(ctx->opcode) != 0))
5129 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5130 }
5131
5132 /* doz - doz. */
5133 static void gen_doz(DisasContext *ctx)
5134 {
5135 TCGLabel *l1 = gen_new_label();
5136 TCGLabel *l2 = gen_new_label();
5137 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5138 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5139 tcg_gen_br(l2);
5140 gen_set_label(l1);
5141 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5142 gen_set_label(l2);
5143 if (unlikely(Rc(ctx->opcode) != 0))
5144 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5145 }
5146
5147 /* dozo - dozo. */
5148 static void gen_dozo(DisasContext *ctx)
5149 {
5150 TCGLabel *l1 = gen_new_label();
5151 TCGLabel *l2 = gen_new_label();
5152 TCGv t0 = tcg_temp_new();
5153 TCGv t1 = tcg_temp_new();
5154 TCGv t2 = tcg_temp_new();
5155 /* Start with XER OV disabled, the most likely case */
5156 tcg_gen_movi_tl(cpu_ov, 0);
5157 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5158 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5159 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5160 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5161 tcg_gen_andc_tl(t1, t1, t2);
5162 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5163 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5164 tcg_gen_movi_tl(cpu_ov, 1);
5165 tcg_gen_movi_tl(cpu_so, 1);
5166 tcg_gen_br(l2);
5167 gen_set_label(l1);
5168 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5169 gen_set_label(l2);
5170 tcg_temp_free(t0);
5171 tcg_temp_free(t1);
5172 tcg_temp_free(t2);
5173 if (unlikely(Rc(ctx->opcode) != 0))
5174 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5175 }
5176
5177 /* dozi */
5178 static void gen_dozi(DisasContext *ctx)
5179 {
5180 target_long simm = SIMM(ctx->opcode);
5181 TCGLabel *l1 = gen_new_label();
5182 TCGLabel *l2 = gen_new_label();
5183 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5184 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5185 tcg_gen_br(l2);
5186 gen_set_label(l1);
5187 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5188 gen_set_label(l2);
5189 if (unlikely(Rc(ctx->opcode) != 0))
5190 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5191 }
5192
5193 /* lscbx - lscbx. */
5194 static void gen_lscbx(DisasContext *ctx)
5195 {
5196 TCGv t0 = tcg_temp_new();
5197 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5198 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5199 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5200
5201 gen_addr_reg_index(ctx, t0);
5202 /* NIP cannot be restored if the memory exception comes from an helper */
5203 gen_update_nip(ctx, ctx->nip - 4);
5204 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5205 tcg_temp_free_i32(t1);
5206 tcg_temp_free_i32(t2);
5207 tcg_temp_free_i32(t3);
5208 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5209 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5210 if (unlikely(Rc(ctx->opcode) != 0))
5211 gen_set_Rc0(ctx, t0);
5212 tcg_temp_free(t0);
5213 }
5214
5215 /* maskg - maskg. */
5216 static void gen_maskg(DisasContext *ctx)
5217 {
5218 TCGLabel *l1 = gen_new_label();
5219 TCGv t0 = tcg_temp_new();
5220 TCGv t1 = tcg_temp_new();
5221 TCGv t2 = tcg_temp_new();
5222 TCGv t3 = tcg_temp_new();
5223 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5224 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5225 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5226 tcg_gen_addi_tl(t2, t0, 1);
5227 tcg_gen_shr_tl(t2, t3, t2);
5228 tcg_gen_shr_tl(t3, t3, t1);
5229 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5230 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5231 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5232 gen_set_label(l1);
5233 tcg_temp_free(t0);
5234 tcg_temp_free(t1);
5235 tcg_temp_free(t2);
5236 tcg_temp_free(t3);
5237 if (unlikely(Rc(ctx->opcode) != 0))
5238 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5239 }
5240
5241 /* maskir - maskir. */
5242 static void gen_maskir(DisasContext *ctx)
5243 {
5244 TCGv t0 = tcg_temp_new();
5245 TCGv t1 = tcg_temp_new();
5246 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5247 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5248 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5249 tcg_temp_free(t0);
5250 tcg_temp_free(t1);
5251 if (unlikely(Rc(ctx->opcode) != 0))
5252 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5253 }
5254
5255 /* mul - mul. */
5256 static void gen_mul(DisasContext *ctx)
5257 {
5258 TCGv_i64 t0 = tcg_temp_new_i64();
5259 TCGv_i64 t1 = tcg_temp_new_i64();
5260 TCGv t2 = tcg_temp_new();
5261 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5262 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5263 tcg_gen_mul_i64(t0, t0, t1);
5264 tcg_gen_trunc_i64_tl(t2, t0);
5265 gen_store_spr(SPR_MQ, t2);
5266 tcg_gen_shri_i64(t1, t0, 32);
5267 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5268 tcg_temp_free_i64(t0);
5269 tcg_temp_free_i64(t1);
5270 tcg_temp_free(t2);
5271 if (unlikely(Rc(ctx->opcode) != 0))
5272 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5273 }
5274
5275 /* mulo - mulo. */
5276 static void gen_mulo(DisasContext *ctx)
5277 {
5278 TCGLabel *l1 = gen_new_label();
5279 TCGv_i64 t0 = tcg_temp_new_i64();
5280 TCGv_i64 t1 = tcg_temp_new_i64();
5281 TCGv t2 = tcg_temp_new();
5282 /* Start with XER OV disabled, the most likely case */
5283 tcg_gen_movi_tl(cpu_ov, 0);
5284 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5285 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5286 tcg_gen_mul_i64(t0, t0, t1);
5287 tcg_gen_trunc_i64_tl(t2, t0);
5288 gen_store_spr(SPR_MQ, t2);
5289 tcg_gen_shri_i64(t1, t0, 32);
5290 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5291 tcg_gen_ext32s_i64(t1, t0);
5292 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5293 tcg_gen_movi_tl(cpu_ov, 1);
5294 tcg_gen_movi_tl(cpu_so, 1);
5295 gen_set_label(l1);
5296 tcg_temp_free_i64(t0);
5297 tcg_temp_free_i64(t1);
5298 tcg_temp_free(t2);
5299 if (unlikely(Rc(ctx->opcode) != 0))
5300 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5301 }
5302
5303 /* nabs - nabs. */
5304 static void gen_nabs(DisasContext *ctx)
5305 {
5306 TCGLabel *l1 = gen_new_label();
5307 TCGLabel *l2 = gen_new_label();
5308 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5309 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5310 tcg_gen_br(l2);
5311 gen_set_label(l1);
5312 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5313 gen_set_label(l2);
5314 if (unlikely(Rc(ctx->opcode) != 0))
5315 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5316 }
5317
5318 /* nabso - nabso. */
5319 static void gen_nabso(DisasContext *ctx)
5320 {
5321 TCGLabel *l1 = gen_new_label();
5322 TCGLabel *l2 = gen_new_label();
5323 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5324 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5325 tcg_gen_br(l2);
5326 gen_set_label(l1);
5327 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5328 gen_set_label(l2);
5329 /* nabs never overflows */
5330 tcg_gen_movi_tl(cpu_ov, 0);
5331 if (unlikely(Rc(ctx->opcode) != 0))
5332 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5333 }
5334
5335 /* rlmi - rlmi. */
5336 static void gen_rlmi(DisasContext *ctx)
5337 {
5338 uint32_t mb = MB(ctx->opcode);
5339 uint32_t me = ME(ctx->opcode);
5340 TCGv t0 = tcg_temp_new();
5341 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5342 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5343 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5344 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5345 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5346 tcg_temp_free(t0);
5347 if (unlikely(Rc(ctx->opcode) != 0))
5348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5349 }
5350
5351 /* rrib - rrib. */
5352 static void gen_rrib(DisasContext *ctx)
5353 {
5354 TCGv t0 = tcg_temp_new();
5355 TCGv t1 = tcg_temp_new();
5356 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5357 tcg_gen_movi_tl(t1, 0x80000000);
5358 tcg_gen_shr_tl(t1, t1, t0);
5359 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5360 tcg_gen_and_tl(t0, t0, t1);
5361 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5362 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5363 tcg_temp_free(t0);
5364 tcg_temp_free(t1);
5365 if (unlikely(Rc(ctx->opcode) != 0))
5366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5367 }
5368
5369 /* sle - sle. */
5370 static void gen_sle(DisasContext *ctx)
5371 {
5372 TCGv t0 = tcg_temp_new();
5373 TCGv t1 = tcg_temp_new();
5374 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5375 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5376 tcg_gen_subfi_tl(t1, 32, t1);
5377 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5378 tcg_gen_or_tl(t1, t0, t1);
5379 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5380 gen_store_spr(SPR_MQ, t1);
5381 tcg_temp_free(t0);
5382 tcg_temp_free(t1);
5383 if (unlikely(Rc(ctx->opcode) != 0))
5384 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5385 }
5386
5387 /* sleq - sleq. */
5388 static void gen_sleq(DisasContext *ctx)
5389 {
5390 TCGv t0 = tcg_temp_new();
5391 TCGv t1 = tcg_temp_new();
5392 TCGv t2 = tcg_temp_new();
5393 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5394 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5395 tcg_gen_shl_tl(t2, t2, t0);
5396 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5397 gen_load_spr(t1, SPR_MQ);
5398 gen_store_spr(SPR_MQ, t0);
5399 tcg_gen_and_tl(t0, t0, t2);
5400 tcg_gen_andc_tl(t1, t1, t2);
5401 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5402 tcg_temp_free(t0);
5403 tcg_temp_free(t1);
5404 tcg_temp_free(t2);
5405 if (unlikely(Rc(ctx->opcode) != 0))
5406 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5407 }
5408
5409 /* sliq - sliq. */
5410 static void gen_sliq(DisasContext *ctx)
5411 {
5412 int sh = SH(ctx->opcode);
5413 TCGv t0 = tcg_temp_new();
5414 TCGv t1 = tcg_temp_new();
5415 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5416 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5417 tcg_gen_or_tl(t1, t0, t1);
5418 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5419 gen_store_spr(SPR_MQ, t1);
5420 tcg_temp_free(t0);
5421 tcg_temp_free(t1);
5422 if (unlikely(Rc(ctx->opcode) != 0))
5423 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5424 }
5425
5426 /* slliq - slliq. */
5427 static void gen_slliq(DisasContext *ctx)
5428 {
5429 int sh = SH(ctx->opcode);
5430 TCGv t0 = tcg_temp_new();
5431 TCGv t1 = tcg_temp_new();
5432 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5433 gen_load_spr(t1, SPR_MQ);
5434 gen_store_spr(SPR_MQ, t0);
5435 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5436 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5437 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5438 tcg_temp_free(t0);
5439 tcg_temp_free(t1);
5440 if (unlikely(Rc(ctx->opcode) != 0))
5441 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5442 }
5443
5444 /* sllq - sllq. */
5445 static void gen_sllq(DisasContext *ctx)
5446 {
5447 TCGLabel *l1 = gen_new_label();
5448 TCGLabel *l2 = gen_new_label();
5449 TCGv t0 = tcg_temp_local_new();
5450 TCGv t1 = tcg_temp_local_new();
5451 TCGv t2 = tcg_temp_local_new();
5452 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5453 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5454 tcg_gen_shl_tl(t1, t1, t2);
5455 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5456 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5457 gen_load_spr(t0, SPR_MQ);
5458 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5459 tcg_gen_br(l2);
5460 gen_set_label(l1);
5461 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5462 gen_load_spr(t2, SPR_MQ);
5463 tcg_gen_andc_tl(t1, t2, t1);
5464 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5465 gen_set_label(l2);
5466 tcg_temp_free(t0);
5467 tcg_temp_free(t1);
5468 tcg_temp_free(t2);
5469 if (unlikely(Rc(ctx->opcode) != 0))
5470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5471 }
5472
5473 /* slq - slq. */
5474 static void gen_slq(DisasContext *ctx)
5475 {
5476 TCGLabel *l1 = gen_new_label();
5477 TCGv t0 = tcg_temp_new();
5478 TCGv t1 = tcg_temp_new();
5479 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5480 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5481 tcg_gen_subfi_tl(t1, 32, t1);
5482 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5483 tcg_gen_or_tl(t1, t0, t1);
5484 gen_store_spr(SPR_MQ, t1);
5485 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5486 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5487 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5488 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5489 gen_set_label(l1);
5490 tcg_temp_free(t0);
5491 tcg_temp_free(t1);
5492 if (unlikely(Rc(ctx->opcode) != 0))
5493 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5494 }
5495
5496 /* sraiq - sraiq. */
5497 static void gen_sraiq(DisasContext *ctx)
5498 {
5499 int sh = SH(ctx->opcode);
5500 TCGLabel *l1 = gen_new_label();
5501 TCGv t0 = tcg_temp_new();
5502 TCGv t1 = tcg_temp_new();
5503 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5504 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5505 tcg_gen_or_tl(t0, t0, t1);
5506 gen_store_spr(SPR_MQ, t0);
5507 tcg_gen_movi_tl(cpu_ca, 0);
5508 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5509 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5510 tcg_gen_movi_tl(cpu_ca, 1);
5511 gen_set_label(l1);
5512 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5513 tcg_temp_free(t0);
5514 tcg_temp_free(t1);
5515 if (unlikely(Rc(ctx->opcode) != 0))
5516 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5517 }
5518
5519 /* sraq - sraq. */
5520 static void gen_sraq(DisasContext *ctx)
5521 {
5522 TCGLabel *l1 = gen_new_label();
5523 TCGLabel *l2 = gen_new_label();
5524 TCGv t0 = tcg_temp_new();
5525 TCGv t1 = tcg_temp_local_new();
5526 TCGv t2 = tcg_temp_local_new();
5527 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5528 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5529 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5530 tcg_gen_subfi_tl(t2, 32, t2);
5531 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5532 tcg_gen_or_tl(t0, t0, t2);
5533 gen_store_spr(SPR_MQ, t0);
5534 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5535 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5536 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5537 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5538 gen_set_label(l1);
5539 tcg_temp_free(t0);
5540 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5541 tcg_gen_movi_tl(cpu_ca, 0);
5542 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5543 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5544 tcg_gen_movi_tl(cpu_ca, 1);
5545 gen_set_label(l2);
5546 tcg_temp_free(t1);
5547 tcg_temp_free(t2);
5548 if (unlikely(Rc(ctx->opcode) != 0))
5549 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5550 }
5551
5552 /* sre - sre. */
5553 static void gen_sre(DisasContext *ctx)
5554 {
5555 TCGv t0 = tcg_temp_new();
5556 TCGv t1 = tcg_temp_new();
5557 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5558 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5559 tcg_gen_subfi_tl(t1, 32, t1);
5560 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5561 tcg_gen_or_tl(t1, t0, t1);
5562 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5563 gen_store_spr(SPR_MQ, t1);
5564 tcg_temp_free(t0);
5565 tcg_temp_free(t1);
5566 if (unlikely(Rc(ctx->opcode) != 0))
5567 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5568 }
5569
5570 /* srea - srea. */
5571 static void gen_srea(DisasContext *ctx)
5572 {
5573 TCGv t0 = tcg_temp_new();
5574 TCGv t1 = tcg_temp_new();
5575 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5576 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5577 gen_store_spr(SPR_MQ, t0);
5578 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5579 tcg_temp_free(t0);
5580 tcg_temp_free(t1);
5581 if (unlikely(Rc(ctx->opcode) != 0))
5582 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5583 }
5584
5585 /* sreq */
5586 static void gen_sreq(DisasContext *ctx)
5587 {
5588 TCGv t0 = tcg_temp_new();
5589 TCGv t1 = tcg_temp_new();
5590 TCGv t2 = tcg_temp_new();
5591 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5592 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5593 tcg_gen_shr_tl(t1, t1, t0);
5594 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5595 gen_load_spr(t2, SPR_MQ);
5596 gen_store_spr(SPR_MQ, t0);
5597 tcg_gen_and_tl(t0, t0, t1);
5598 tcg_gen_andc_tl(t2, t2, t1);
5599 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5600 tcg_temp_free(t0);
5601 tcg_temp_free(t1);
5602 tcg_temp_free(t2);
5603 if (unlikely(Rc(ctx->opcode) != 0))
5604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5605 }
5606
5607 /* sriq */
5608 static void gen_sriq(DisasContext *ctx)
5609 {
5610 int sh = SH(ctx->opcode);
5611 TCGv t0 = tcg_temp_new();
5612 TCGv t1 = tcg_temp_new();
5613 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5614 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5615 tcg_gen_or_tl(t1, t0, t1);
5616 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5617 gen_store_spr(SPR_MQ, t1);
5618 tcg_temp_free(t0);
5619 tcg_temp_free(t1);
5620 if (unlikely(Rc(ctx->opcode) != 0))
5621 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5622 }
5623
5624 /* srliq */
5625 static void gen_srliq(DisasContext *ctx)
5626 {
5627 int sh = SH(ctx->opcode);
5628 TCGv t0 = tcg_temp_new();
5629 TCGv t1 = tcg_temp_new();
5630 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5631 gen_load_spr(t1, SPR_MQ);
5632 gen_store_spr(SPR_MQ, t0);
5633 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5634 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5635 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5636 tcg_temp_free(t0);
5637 tcg_temp_free(t1);
5638 if (unlikely(Rc(ctx->opcode) != 0))
5639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5640 }
5641
5642 /* srlq */
5643 static void gen_srlq(DisasContext *ctx)
5644 {
5645 TCGLabel *l1 = gen_new_label();
5646 TCGLabel *l2 = gen_new_label();
5647 TCGv t0 = tcg_temp_local_new();
5648 TCGv t1 = tcg_temp_local_new();
5649 TCGv t2 = tcg_temp_local_new();
5650 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5651 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5652 tcg_gen_shr_tl(t2, t1, t2);
5653 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5654 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5655 gen_load_spr(t0, SPR_MQ);
5656 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5657 tcg_gen_br(l2);
5658 gen_set_label(l1);
5659 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5660 tcg_gen_and_tl(t0, t0, t2);
5661 gen_load_spr(t1, SPR_MQ);
5662 tcg_gen_andc_tl(t1, t1, t2);
5663 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5664 gen_set_label(l2);
5665 tcg_temp_free(t0);
5666 tcg_temp_free(t1);
5667 tcg_temp_free(t2);
5668 if (unlikely(Rc(ctx->opcode) != 0))
5669 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5670 }
5671
5672 /* srq */
5673 static void gen_srq(DisasContext *ctx)
5674 {
5675 TCGLabel *l1 = gen_new_label();
5676 TCGv t0 = tcg_temp_new();
5677 TCGv t1 = tcg_temp_new();
5678 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5679 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5680 tcg_gen_subfi_tl(t1, 32, t1);
5681 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5682 tcg_gen_or_tl(t1, t0, t1);
5683 gen_store_spr(SPR_MQ, t1);
5684 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5686 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5687 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5688 gen_set_label(l1);
5689 tcg_temp_free(t0);
5690 tcg_temp_free(t1);
5691 if (unlikely(Rc(ctx->opcode) != 0))
5692 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5693 }
5694
5695 /* PowerPC 602 specific instructions */
5696
5697 /* dsa */
5698 static void gen_dsa(DisasContext *ctx)
5699 {
5700 /* XXX: TODO */
5701 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5702 }
5703
5704 /* esa */
5705 static void gen_esa(DisasContext *ctx)
5706 {
5707 /* XXX: TODO */
5708 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5709 }
5710
5711 /* mfrom */
5712 static void gen_mfrom(DisasContext *ctx)
5713 {
5714 #if defined(CONFIG_USER_ONLY)
5715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5716 #else
5717 if (unlikely(ctx->pr)) {
5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5719 return;
5720 }
5721 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5722 #endif
5723 }
5724
5725 /* 602 - 603 - G2 TLB management */
5726
5727 /* tlbld */
5728 static void gen_tlbld_6xx(DisasContext *ctx)
5729 {
5730 #if defined(CONFIG_USER_ONLY)
5731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5732 #else
5733 if (unlikely(ctx->pr)) {
5734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5735 return;
5736 }
5737 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5738 #endif
5739 }
5740
5741 /* tlbli */
5742 static void gen_tlbli_6xx(DisasContext *ctx)
5743 {
5744 #if defined(CONFIG_USER_ONLY)
5745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5746 #else
5747 if (unlikely(ctx->pr)) {
5748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5749 return;
5750 }
5751 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5752 #endif
5753 }
5754
5755 /* 74xx TLB management */
5756
5757 /* tlbld */
5758 static void gen_tlbld_74xx(DisasContext *ctx)
5759 {
5760 #if defined(CONFIG_USER_ONLY)
5761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5762 #else
5763 if (unlikely(ctx->pr)) {
5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5765 return;
5766 }
5767 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5768 #endif
5769 }
5770
5771 /* tlbli */
5772 static void gen_tlbli_74xx(DisasContext *ctx)
5773 {
5774 #if defined(CONFIG_USER_ONLY)
5775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5776 #else
5777 if (unlikely(ctx->pr)) {
5778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5779 return;
5780 }
5781 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5782 #endif
5783 }
5784
5785 /* POWER instructions not in PowerPC 601 */
5786
5787 /* clf */
5788 static void gen_clf(DisasContext *ctx)
5789 {
5790 /* Cache line flush: implemented as no-op */
5791 }
5792
5793 /* cli */
5794 static void gen_cli(DisasContext *ctx)
5795 {
5796 /* Cache line invalidate: privileged and treated as no-op */
5797 #if defined(CONFIG_USER_ONLY)
5798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5799 #else
5800 if (unlikely(ctx->pr)) {
5801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5802 return;
5803 }
5804 #endif
5805 }
5806
5807 /* dclst */
5808 static void gen_dclst(DisasContext *ctx)
5809 {
5810 /* Data cache line store: treated as no-op */
5811 }
5812
5813 static void gen_mfsri(DisasContext *ctx)
5814 {
5815 #if defined(CONFIG_USER_ONLY)
5816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5817 #else
5818 int ra = rA(ctx->opcode);
5819 int rd = rD(ctx->opcode);
5820 TCGv t0;
5821 if (unlikely(ctx->pr)) {
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 return;
5824 }
5825 t0 = tcg_temp_new();
5826 gen_addr_reg_index(ctx, t0);
5827 tcg_gen_shri_tl(t0, t0, 28);
5828 tcg_gen_andi_tl(t0, t0, 0xF);
5829 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5830 tcg_temp_free(t0);
5831 if (ra != 0 && ra != rd)
5832 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5833 #endif
5834 }
5835
5836 static void gen_rac(DisasContext *ctx)
5837 {
5838 #if defined(CONFIG_USER_ONLY)
5839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5840 #else
5841 TCGv t0;
5842 if (unlikely(ctx->pr)) {
5843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5844 return;
5845 }
5846 t0 = tcg_temp_new();
5847 gen_addr_reg_index(ctx, t0);
5848 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5849 tcg_temp_free(t0);
5850 #endif
5851 }
5852
5853 static void gen_rfsvc(DisasContext *ctx)
5854 {
5855 #if defined(CONFIG_USER_ONLY)
5856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5857 #else
5858 if (unlikely(ctx->pr)) {
5859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5860 return;
5861 }
5862 gen_helper_rfsvc(cpu_env);
5863 gen_sync_exception(ctx);
5864 #endif
5865 }
5866
5867 /* svc is not implemented for now */
5868
5869 /* POWER2 specific instructions */
5870 /* Quad manipulation (load/store two floats at a time) */
5871
5872 /* lfq */
5873 static void gen_lfq(DisasContext *ctx)
5874 {
5875 int rd = rD(ctx->opcode);
5876 TCGv t0;
5877 gen_set_access_type(ctx, ACCESS_FLOAT);
5878 t0 = tcg_temp_new();
5879 gen_addr_imm_index(ctx, t0, 0);
5880 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5881 gen_addr_add(ctx, t0, t0, 8);
5882 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5883 tcg_temp_free(t0);
5884 }
5885
5886 /* lfqu */
5887 static void gen_lfqu(DisasContext *ctx)
5888 {
5889 int ra = rA(ctx->opcode);
5890 int rd = rD(ctx->opcode);
5891 TCGv t0, t1;
5892 gen_set_access_type(ctx, ACCESS_FLOAT);
5893 t0 = tcg_temp_new();
5894 t1 = tcg_temp_new();
5895 gen_addr_imm_index(ctx, t0, 0);
5896 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5897 gen_addr_add(ctx, t1, t0, 8);
5898 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5899 if (ra != 0)
5900 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5901 tcg_temp_free(t0);
5902 tcg_temp_free(t1);
5903 }
5904
5905 /* lfqux */
5906 static void gen_lfqux(DisasContext *ctx)
5907 {
5908 int ra = rA(ctx->opcode);
5909 int rd = rD(ctx->opcode);
5910 gen_set_access_type(ctx, ACCESS_FLOAT);
5911 TCGv t0, t1;
5912 t0 = tcg_temp_new();
5913 gen_addr_reg_index(ctx, t0);
5914 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5915 t1 = tcg_temp_new();
5916 gen_addr_add(ctx, t1, t0, 8);
5917 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5918 tcg_temp_free(t1);
5919 if (ra != 0)
5920 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5921 tcg_temp_free(t0);
5922 }
5923
5924 /* lfqx */
5925 static void gen_lfqx(DisasContext *ctx)
5926 {
5927 int rd = rD(ctx->opcode);
5928 TCGv t0;
5929 gen_set_access_type(ctx, ACCESS_FLOAT);
5930 t0 = tcg_temp_new();
5931 gen_addr_reg_index(ctx, t0);
5932 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5933 gen_addr_add(ctx, t0, t0, 8);
5934 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5935 tcg_temp_free(t0);
5936 }
5937
5938 /* stfq */
5939 static void gen_stfq(DisasContext *ctx)
5940 {
5941 int rd = rD(ctx->opcode);
5942 TCGv t0;
5943 gen_set_access_type(ctx, ACCESS_FLOAT);
5944 t0 = tcg_temp_new();
5945 gen_addr_imm_index(ctx, t0, 0);
5946 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5947 gen_addr_add(ctx, t0, t0, 8);
5948 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5949 tcg_temp_free(t0);
5950 }
5951
5952 /* stfqu */
5953 static void gen_stfqu(DisasContext *ctx)
5954 {
5955 int ra = rA(ctx->opcode);
5956 int rd = rD(ctx->opcode);
5957 TCGv t0, t1;
5958 gen_set_access_type(ctx, ACCESS_FLOAT);
5959 t0 = tcg_temp_new();
5960 gen_addr_imm_index(ctx, t0, 0);
5961 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5962 t1 = tcg_temp_new();
5963 gen_addr_add(ctx, t1, t0, 8);
5964 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5965 tcg_temp_free(t1);
5966 if (ra != 0)
5967 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5968 tcg_temp_free(t0);
5969 }
5970
5971 /* stfqux */
5972 static void gen_stfqux(DisasContext *ctx)
5973 {
5974 int ra = rA(ctx->opcode);
5975 int rd = rD(ctx->opcode);
5976 TCGv t0, t1;
5977 gen_set_access_type(ctx, ACCESS_FLOAT);
5978 t0 = tcg_temp_new();
5979 gen_addr_reg_index(ctx, t0);
5980 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5981 t1 = tcg_temp_new();
5982 gen_addr_add(ctx, t1, t0, 8);
5983 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5984 tcg_temp_free(t1);
5985 if (ra != 0)
5986 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5987 tcg_temp_free(t0);
5988 }
5989
5990 /* stfqx */
5991 static void gen_stfqx(DisasContext *ctx)
5992 {
5993 int rd = rD(ctx->opcode);
5994 TCGv t0;
5995 gen_set_access_type(ctx, ACCESS_FLOAT);
5996 t0 = tcg_temp_new();
5997 gen_addr_reg_index(ctx, t0);
5998 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5999 gen_addr_add(ctx, t0, t0, 8);
6000 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6001 tcg_temp_free(t0);
6002 }
6003
6004 /* BookE specific instructions */
6005
6006 /* XXX: not implemented on 440 ? */
6007 static void gen_mfapidi(DisasContext *ctx)
6008 {
6009 /* XXX: TODO */
6010 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6011 }
6012
6013 /* XXX: not implemented on 440 ? */
6014 static void gen_tlbiva(DisasContext *ctx)
6015 {
6016 #if defined(CONFIG_USER_ONLY)
6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6018 #else
6019 TCGv t0;
6020 if (unlikely(ctx->pr)) {
6021 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6022 return;
6023 }
6024 t0 = tcg_temp_new();
6025 gen_addr_reg_index(ctx, t0);
6026 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6027 tcg_temp_free(t0);
6028 #endif
6029 }
6030
6031 /* All 405 MAC instructions are translated here */
6032 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6033 int ra, int rb, int rt, int Rc)
6034 {
6035 TCGv t0, t1;
6036
6037 t0 = tcg_temp_local_new();
6038 t1 = tcg_temp_local_new();
6039
6040 switch (opc3 & 0x0D) {
6041 case 0x05:
6042 /* macchw - macchw. - macchwo - macchwo. */
6043 /* macchws - macchws. - macchwso - macchwso. */
6044 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6045 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6046 /* mulchw - mulchw. */
6047 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6048 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6049 tcg_gen_ext16s_tl(t1, t1);
6050 break;
6051 case 0x04:
6052 /* macchwu - macchwu. - macchwuo - macchwuo. */
6053 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6054 /* mulchwu - mulchwu. */
6055 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6056 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6057 tcg_gen_ext16u_tl(t1, t1);
6058 break;
6059 case 0x01:
6060 /* machhw - machhw. - machhwo - machhwo. */
6061 /* machhws - machhws. - machhwso - machhwso. */
6062 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6063 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6064 /* mulhhw - mulhhw. */
6065 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6066 tcg_gen_ext16s_tl(t0, t0);
6067 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6068 tcg_gen_ext16s_tl(t1, t1);
6069 break;
6070 case 0x00:
6071 /* machhwu - machhwu. - machhwuo - machhwuo. */
6072 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6073 /* mulhhwu - mulhhwu. */
6074 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6075 tcg_gen_ext16u_tl(t0, t0);
6076 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6077 tcg_gen_ext16u_tl(t1, t1);
6078 break;
6079 case 0x0D:
6080 /* maclhw - maclhw. - maclhwo - maclhwo. */
6081 /* maclhws - maclhws. - maclhwso - maclhwso. */
6082 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6083 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6084 /* mullhw - mullhw. */
6085 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6086 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6087 break;
6088 case 0x0C:
6089 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6090 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6091 /* mullhwu - mullhwu. */
6092 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6093 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6094 break;
6095 }
6096 if (opc2 & 0x04) {
6097 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6098 tcg_gen_mul_tl(t1, t0, t1);
6099 if (opc2 & 0x02) {
6100 /* nmultiply-and-accumulate (0x0E) */
6101 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6102 } else {
6103 /* multiply-and-accumulate (0x0C) */
6104 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6105 }
6106
6107 if (opc3 & 0x12) {
6108 /* Check overflow and/or saturate */
6109 TCGLabel *l1 = gen_new_label();
6110
6111 if (opc3 & 0x10) {
6112 /* Start with XER OV disabled, the most likely case */
6113 tcg_gen_movi_tl(cpu_ov, 0);
6114 }
6115 if (opc3 & 0x01) {
6116 /* Signed */
6117 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6118 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6119 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6120 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6121 if (opc3 & 0x02) {
6122 /* Saturate */
6123 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6124 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6125 }
6126 } else {
6127 /* Unsigned */
6128 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6129 if (opc3 & 0x02) {
6130 /* Saturate */
6131 tcg_gen_movi_tl(t0, UINT32_MAX);
6132 }
6133 }
6134 if (opc3 & 0x10) {
6135 /* Check overflow */
6136 tcg_gen_movi_tl(cpu_ov, 1);
6137 tcg_gen_movi_tl(cpu_so, 1);
6138 }
6139 gen_set_label(l1);
6140 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6141 }
6142 } else {
6143 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6144 }
6145 tcg_temp_free(t0);
6146 tcg_temp_free(t1);
6147 if (unlikely(Rc) != 0) {
6148 /* Update Rc0 */
6149 gen_set_Rc0(ctx, cpu_gpr[rt]);
6150 }
6151 }
6152
6153 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6154 static void glue(gen_, name)(DisasContext *ctx) \
6155 { \
6156 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6157 rD(ctx->opcode), Rc(ctx->opcode)); \
6158 }
6159
6160 /* macchw - macchw. */
6161 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6162 /* macchwo - macchwo. */
6163 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6164 /* macchws - macchws. */
6165 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6166 /* macchwso - macchwso. */
6167 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6168 /* macchwsu - macchwsu. */
6169 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6170 /* macchwsuo - macchwsuo. */
6171 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6172 /* macchwu - macchwu. */
6173 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6174 /* macchwuo - macchwuo. */
6175 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6176 /* machhw - machhw. */
6177 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6178 /* machhwo - machhwo. */
6179 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6180 /* machhws - machhws. */
6181 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6182 /* machhwso - machhwso. */
6183 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6184 /* machhwsu - machhwsu. */
6185 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6186 /* machhwsuo - machhwsuo. */
6187 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6188 /* machhwu - machhwu. */
6189 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6190 /* machhwuo - machhwuo. */
6191 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6192 /* maclhw - maclhw. */
6193 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6194 /* maclhwo - maclhwo. */
6195 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6196 /* maclhws - maclhws. */
6197 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6198 /* maclhwso - maclhwso. */
6199 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6200 /* maclhwu - maclhwu. */
6201 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6202 /* maclhwuo - maclhwuo. */
6203 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6204 /* maclhwsu - maclhwsu. */
6205 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6206 /* maclhwsuo - maclhwsuo. */
6207 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6208 /* nmacchw - nmacchw. */
6209 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6210 /* nmacchwo - nmacchwo. */
6211 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6212 /* nmacchws - nmacchws. */
6213 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6214 /* nmacchwso - nmacchwso. */
6215 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6216 /* nmachhw - nmachhw. */
6217 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6218 /* nmachhwo - nmachhwo. */
6219 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6220 /* nmachhws - nmachhws. */
6221 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6222 /* nmachhwso - nmachhwso. */
6223 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6224 /* nmaclhw - nmaclhw. */
6225 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6226 /* nmaclhwo - nmaclhwo. */
6227 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6228 /* nmaclhws - nmaclhws. */
6229 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6230 /* nmaclhwso - nmaclhwso. */
6231 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6232
6233 /* mulchw - mulchw. */
6234 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6235 /* mulchwu - mulchwu. */
6236 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6237 /* mulhhw - mulhhw. */
6238 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6239 /* mulhhwu - mulhhwu. */
6240 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6241 /* mullhw - mullhw. */
6242 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6243 /* mullhwu - mullhwu. */
6244 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6245
6246 /* mfdcr */
6247 static void gen_mfdcr(DisasContext *ctx)
6248 {
6249 #if defined(CONFIG_USER_ONLY)
6250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6251 #else
6252 TCGv dcrn;
6253 if (unlikely(ctx->pr)) {
6254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6255 return;
6256 }
6257 /* NIP cannot be restored if the memory exception comes from an helper */
6258 gen_update_nip(ctx, ctx->nip - 4);
6259 dcrn = tcg_const_tl(SPR(ctx->opcode));
6260 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6261 tcg_temp_free(dcrn);
6262 #endif
6263 }
6264
6265 /* mtdcr */
6266 static void gen_mtdcr(DisasContext *ctx)
6267 {
6268 #if defined(CONFIG_USER_ONLY)
6269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6270 #else
6271 TCGv dcrn;
6272 if (unlikely(ctx->pr)) {
6273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6274 return;
6275 }
6276 /* NIP cannot be restored if the memory exception comes from an helper */
6277 gen_update_nip(ctx, ctx->nip - 4);
6278 dcrn = tcg_const_tl(SPR(ctx->opcode));
6279 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6280 tcg_temp_free(dcrn);
6281 #endif
6282 }
6283
6284 /* mfdcrx */
6285 /* XXX: not implemented on 440 ? */
6286 static void gen_mfdcrx(DisasContext *ctx)
6287 {
6288 #if defined(CONFIG_USER_ONLY)
6289 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6290 #else
6291 if (unlikely(ctx->pr)) {
6292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6293 return;
6294 }
6295 /* NIP cannot be restored if the memory exception comes from an helper */
6296 gen_update_nip(ctx, ctx->nip - 4);
6297 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6298 cpu_gpr[rA(ctx->opcode)]);
6299 /* Note: Rc update flag set leads to undefined state of Rc0 */
6300 #endif
6301 }
6302
6303 /* mtdcrx */
6304 /* XXX: not implemented on 440 ? */
6305 static void gen_mtdcrx(DisasContext *ctx)
6306 {
6307 #if defined(CONFIG_USER_ONLY)
6308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6309 #else
6310 if (unlikely(ctx->pr)) {
6311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6312 return;
6313 }
6314 /* NIP cannot be restored if the memory exception comes from an helper */
6315 gen_update_nip(ctx, ctx->nip - 4);
6316 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6317 cpu_gpr[rS(ctx->opcode)]);
6318 /* Note: Rc update flag set leads to undefined state of Rc0 */
6319 #endif
6320 }
6321
6322 /* mfdcrux (PPC 460) : user-mode access to DCR */
6323 static void gen_mfdcrux(DisasContext *ctx)
6324 {
6325 /* NIP cannot be restored if the memory exception comes from an helper */
6326 gen_update_nip(ctx, ctx->nip - 4);
6327 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6328 cpu_gpr[rA(ctx->opcode)]);
6329 /* Note: Rc update flag set leads to undefined state of Rc0 */
6330 }
6331
6332 /* mtdcrux (PPC 460) : user-mode access to DCR */
6333 static void gen_mtdcrux(DisasContext *ctx)
6334 {
6335 /* NIP cannot be restored if the memory exception comes from an helper */
6336 gen_update_nip(ctx, ctx->nip - 4);
6337 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6338 cpu_gpr[rS(ctx->opcode)]);
6339 /* Note: Rc update flag set leads to undefined state of Rc0 */
6340 }
6341
6342 /* dccci */
6343 static void gen_dccci(DisasContext *ctx)
6344 {
6345 #if defined(CONFIG_USER_ONLY)
6346 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6347 #else
6348 if (unlikely(ctx->pr)) {
6349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6350 return;
6351 }
6352 /* interpreted as no-op */
6353 #endif
6354 }
6355
6356 /* dcread */
6357 static void gen_dcread(DisasContext *ctx)
6358 {
6359 #if defined(CONFIG_USER_ONLY)
6360 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6361 #else
6362 TCGv EA, val;
6363 if (unlikely(ctx->pr)) {
6364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6365 return;
6366 }
6367 gen_set_access_type(ctx, ACCESS_CACHE);
6368 EA = tcg_temp_new();
6369 gen_addr_reg_index(ctx, EA);
6370 val = tcg_temp_new();
6371 gen_qemu_ld32u(ctx, val, EA);
6372 tcg_temp_free(val);
6373 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6374 tcg_temp_free(EA);
6375 #endif
6376 }
6377
6378 /* icbt */
6379 static void gen_icbt_40x(DisasContext *ctx)
6380 {
6381 /* interpreted as no-op */
6382 /* XXX: specification say this is treated as a load by the MMU
6383 * but does not generate any exception
6384 */
6385 }
6386
6387 /* iccci */
6388 static void gen_iccci(DisasContext *ctx)
6389 {
6390 #if defined(CONFIG_USER_ONLY)
6391 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6392 #else
6393 if (unlikely(ctx->pr)) {
6394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6395 return;
6396 }
6397 /* interpreted as no-op */
6398 #endif
6399 }
6400
6401 /* icread */
6402 static void gen_icread(DisasContext *ctx)
6403 {
6404 #if defined(CONFIG_USER_ONLY)
6405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6406 #else
6407 if (unlikely(ctx->pr)) {
6408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6409 return;
6410 }
6411 /* interpreted as no-op */
6412 #endif
6413 }
6414
6415 /* rfci (supervisor only) */
6416 static void gen_rfci_40x(DisasContext *ctx)
6417 {
6418 #if defined(CONFIG_USER_ONLY)
6419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6420 #else
6421 if (unlikely(ctx->pr)) {
6422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6423 return;
6424 }
6425 /* Restore CPU state */
6426 gen_helper_40x_rfci(cpu_env);
6427 gen_sync_exception(ctx);
6428 #endif
6429 }
6430
6431 static void gen_rfci(DisasContext *ctx)
6432 {
6433 #if defined(CONFIG_USER_ONLY)
6434 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6435 #else
6436 if (unlikely(ctx->pr)) {
6437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6438 return;
6439 }
6440 /* Restore CPU state */
6441 gen_helper_rfci(cpu_env);
6442 gen_sync_exception(ctx);
6443 #endif
6444 }
6445
6446 /* BookE specific */
6447
6448 /* XXX: not implemented on 440 ? */
6449 static void gen_rfdi(DisasContext *ctx)
6450 {
6451 #if defined(CONFIG_USER_ONLY)
6452 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6453 #else
6454 if (unlikely(ctx->pr)) {
6455 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6456 return;
6457 }
6458 /* Restore CPU state */
6459 gen_helper_rfdi(cpu_env);
6460 gen_sync_exception(ctx);
6461 #endif
6462 }
6463
6464 /* XXX: not implemented on 440 ? */
6465 static void gen_rfmci(DisasContext *ctx)
6466 {
6467 #if defined(CONFIG_USER_ONLY)
6468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6469 #else
6470 if (unlikely(ctx->pr)) {
6471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6472 return;
6473 }
6474 /* Restore CPU state */
6475 gen_helper_rfmci(cpu_env);
6476 gen_sync_exception(ctx);
6477 #endif
6478 }
6479
6480 /* TLB management - PowerPC 405 implementation */
6481
6482 /* tlbre */
6483 static void gen_tlbre_40x(DisasContext *ctx)
6484 {
6485 #if defined(CONFIG_USER_ONLY)
6486 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6487 #else
6488 if (unlikely(ctx->pr)) {
6489 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6490 return;
6491 }
6492 switch (rB(ctx->opcode)) {
6493 case 0:
6494 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6495 cpu_gpr[rA(ctx->opcode)]);
6496 break;
6497 case 1:
6498 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6499 cpu_gpr[rA(ctx->opcode)]);
6500 break;
6501 default:
6502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6503 break;
6504 }
6505 #endif
6506 }
6507
6508 /* tlbsx - tlbsx. */
6509 static void gen_tlbsx_40x(DisasContext *ctx)
6510 {
6511 #if defined(CONFIG_USER_ONLY)
6512 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6513 #else
6514 TCGv t0;
6515 if (unlikely(ctx->pr)) {
6516 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6517 return;
6518 }
6519 t0 = tcg_temp_new();
6520 gen_addr_reg_index(ctx, t0);
6521 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6522 tcg_temp_free(t0);
6523 if (Rc(ctx->opcode)) {
6524 TCGLabel *l1 = gen_new_label();
6525 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6526 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6527 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6528 gen_set_label(l1);
6529 }
6530 #endif
6531 }
6532
6533 /* tlbwe */
6534 static void gen_tlbwe_40x(DisasContext *ctx)
6535 {
6536 #if defined(CONFIG_USER_ONLY)
6537 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6538 #else
6539 if (unlikely(ctx->pr)) {
6540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6541 return;
6542 }
6543 switch (rB(ctx->opcode)) {
6544 case 0:
6545 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6546 cpu_gpr[rS(ctx->opcode)]);
6547 break;
6548 case 1:
6549 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6550 cpu_gpr[rS(ctx->opcode)]);
6551 break;
6552 default:
6553 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6554 break;
6555 }
6556 #endif
6557 }
6558
6559 /* TLB management - PowerPC 440 implementation */
6560
6561 /* tlbre */
6562 static void gen_tlbre_440(DisasContext *ctx)
6563 {
6564 #if defined(CONFIG_USER_ONLY)
6565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6566 #else
6567 if (unlikely(ctx->pr)) {
6568 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6569 return;
6570 }
6571 switch (rB(ctx->opcode)) {
6572 case 0:
6573 case 1:
6574 case 2:
6575 {
6576 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6577 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6578 t0, cpu_gpr[rA(ctx->opcode)]);
6579 tcg_temp_free_i32(t0);
6580 }
6581 break;
6582 default:
6583 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6584 break;
6585 }
6586 #endif
6587 }
6588
6589 /* tlbsx - tlbsx. */
6590 static void gen_tlbsx_440(DisasContext *ctx)
6591 {
6592 #if defined(CONFIG_USER_ONLY)
6593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6594 #else
6595 TCGv t0;
6596 if (unlikely(ctx->pr)) {
6597 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6598 return;
6599 }
6600 t0 = tcg_temp_new();
6601 gen_addr_reg_index(ctx, t0);
6602 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6603 tcg_temp_free(t0);
6604 if (Rc(ctx->opcode)) {
6605 TCGLabel *l1 = gen_new_label();
6606 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6607 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6608 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6609 gen_set_label(l1);
6610 }
6611 #endif
6612 }
6613
6614 /* tlbwe */
6615 static void gen_tlbwe_440(DisasContext *ctx)
6616 {
6617 #if defined(CONFIG_USER_ONLY)
6618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6619 #else
6620 if (unlikely(ctx->pr)) {
6621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6622 return;
6623 }
6624 switch (rB(ctx->opcode)) {
6625 case 0:
6626 case 1:
6627 case 2:
6628 {
6629 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6630 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6631 cpu_gpr[rS(ctx->opcode)]);
6632 tcg_temp_free_i32(t0);
6633 }
6634 break;
6635 default:
6636 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6637 break;
6638 }
6639 #endif
6640 }
6641
6642 /* TLB management - PowerPC BookE 2.06 implementation */
6643
6644 /* tlbre */
6645 static void gen_tlbre_booke206(DisasContext *ctx)
6646 {
6647 #if defined(CONFIG_USER_ONLY)
6648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6649 #else
6650 if (unlikely(ctx->pr)) {
6651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6652 return;
6653 }
6654
6655 gen_helper_booke206_tlbre(cpu_env);
6656 #endif
6657 }
6658
6659 /* tlbsx - tlbsx. */
6660 static void gen_tlbsx_booke206(DisasContext *ctx)
6661 {
6662 #if defined(CONFIG_USER_ONLY)
6663 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6664 #else
6665 TCGv t0;
6666 if (unlikely(ctx->pr)) {
6667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6668 return;
6669 }
6670
6671 if (rA(ctx->opcode)) {
6672 t0 = tcg_temp_new();
6673 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6674 } else {
6675 t0 = tcg_const_tl(0);
6676 }
6677
6678 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6679 gen_helper_booke206_tlbsx(cpu_env, t0);
6680 tcg_temp_free(t0);
6681 #endif
6682 }
6683
6684 /* tlbwe */
6685 static void gen_tlbwe_booke206(DisasContext *ctx)
6686 {
6687 #if defined(CONFIG_USER_ONLY)
6688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6689 #else
6690 if (unlikely(ctx->pr)) {
6691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6692 return;
6693 }
6694 gen_update_nip(ctx, ctx->nip - 4);
6695 gen_helper_booke206_tlbwe(cpu_env);
6696 #endif
6697 }
6698
6699 static void gen_tlbivax_booke206(DisasContext *ctx)
6700 {
6701 #if defined(CONFIG_USER_ONLY)
6702 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6703 #else
6704 TCGv t0;
6705 if (unlikely(ctx->pr)) {
6706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6707 return;
6708 }
6709
6710 t0 = tcg_temp_new();
6711 gen_addr_reg_index(ctx, t0);
6712
6713 gen_helper_booke206_tlbivax(cpu_env, t0);
6714 tcg_temp_free(t0);
6715 #endif
6716 }
6717
6718 static void gen_tlbilx_booke206(DisasContext *ctx)
6719 {
6720 #if defined(CONFIG_USER_ONLY)
6721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6722 #else
6723 TCGv t0;
6724 if (unlikely(ctx->pr)) {
6725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6726 return;
6727 }
6728
6729 t0 = tcg_temp_new();
6730 gen_addr_reg_index(ctx, t0);
6731
6732 switch((ctx->opcode >> 21) & 0x3) {
6733 case 0:
6734 gen_helper_booke206_tlbilx0(cpu_env, t0);
6735 break;
6736 case 1:
6737 gen_helper_booke206_tlbilx1(cpu_env, t0);
6738 break;
6739 case 3:
6740 gen_helper_booke206_tlbilx3(cpu_env, t0);
6741 break;
6742 default:
6743 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6744 break;
6745 }
6746
6747 tcg_temp_free(t0);
6748 #endif
6749 }
6750
6751
6752 /* wrtee */
6753 static void gen_wrtee(DisasContext *ctx)
6754 {
6755 #if defined(CONFIG_USER_ONLY)
6756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6757 #else
6758 TCGv t0;
6759 if (unlikely(ctx->pr)) {
6760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6761 return;
6762 }
6763 t0 = tcg_temp_new();
6764 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6765 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6766 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6767 tcg_temp_free(t0);
6768 /* Stop translation to have a chance to raise an exception
6769 * if we just set msr_ee to 1
6770 */
6771 gen_stop_exception(ctx);
6772 #endif
6773 }
6774
6775 /* wrteei */
6776 static void gen_wrteei(DisasContext *ctx)
6777 {
6778 #if defined(CONFIG_USER_ONLY)
6779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6780 #else
6781 if (unlikely(ctx->pr)) {
6782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6783 return;
6784 }
6785 if (ctx->opcode & 0x00008000) {
6786 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6787 /* Stop translation to have a chance to raise an exception */
6788 gen_stop_exception(ctx);
6789 } else {
6790 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6791 }
6792 #endif
6793 }
6794
6795 /* PowerPC 440 specific instructions */
6796
6797 /* dlmzb */
6798 static void gen_dlmzb(DisasContext *ctx)
6799 {
6800 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6801 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6802 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6803 tcg_temp_free_i32(t0);
6804 }
6805
6806 /* mbar replaces eieio on 440 */
6807 static void gen_mbar(DisasContext *ctx)
6808 {
6809 /* interpreted as no-op */
6810 }
6811
6812 /* msync replaces sync on 440 */
6813 static void gen_msync_4xx(DisasContext *ctx)
6814 {
6815 /* interpreted as no-op */
6816 }
6817
6818 /* icbt */
6819 static void gen_icbt_440(DisasContext *ctx)
6820 {
6821 /* interpreted as no-op */
6822 /* XXX: specification say this is treated as a load by the MMU
6823 * but does not generate any exception
6824 */
6825 }
6826
6827 /* Embedded.Processor Control */
6828
6829 static void gen_msgclr(DisasContext *ctx)
6830 {
6831 #if defined(CONFIG_USER_ONLY)
6832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6833 #else
6834 if (unlikely(ctx->pr)) {
6835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6836 return;
6837 }
6838
6839 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6840 #endif
6841 }
6842
6843 static void gen_msgsnd(DisasContext *ctx)
6844 {
6845 #if defined(CONFIG_USER_ONLY)
6846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6847 #else
6848 if (unlikely(ctx->pr)) {
6849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6850 return;
6851 }
6852
6853 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6854 #endif
6855 }
6856
6857 /*** Altivec vector extension ***/
6858 /* Altivec registers moves */
6859
6860 static inline TCGv_ptr gen_avr_ptr(int reg)
6861 {
6862 TCGv_ptr r = tcg_temp_new_ptr();
6863 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6864 return r;
6865 }
6866
6867 #define GEN_VR_LDX(name, opc2, opc3) \
6868 static void glue(gen_, name)(DisasContext *ctx) \
6869 { \
6870 TCGv EA; \
6871 if (unlikely(!ctx->altivec_enabled)) { \
6872 gen_exception(ctx, POWERPC_EXCP_VPU); \
6873 return; \
6874 } \
6875 gen_set_access_type(ctx, ACCESS_INT); \
6876 EA = tcg_temp_new(); \
6877 gen_addr_reg_index(ctx, EA); \
6878 tcg_gen_andi_tl(EA, EA, ~0xf); \
6879 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6880 64-bit byteswap already. */ \
6881 if (ctx->le_mode) { \
6882 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6883 tcg_gen_addi_tl(EA, EA, 8); \
6884 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6885 } else { \
6886 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6887 tcg_gen_addi_tl(EA, EA, 8); \
6888 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6889 } \
6890 tcg_temp_free(EA); \
6891 }
6892
6893 #define GEN_VR_STX(name, opc2, opc3) \
6894 static void gen_st##name(DisasContext *ctx) \
6895 { \
6896 TCGv EA; \
6897 if (unlikely(!ctx->altivec_enabled)) { \
6898 gen_exception(ctx, POWERPC_EXCP_VPU); \
6899 return; \
6900 } \
6901 gen_set_access_type(ctx, ACCESS_INT); \
6902 EA = tcg_temp_new(); \
6903 gen_addr_reg_index(ctx, EA); \
6904 tcg_gen_andi_tl(EA, EA, ~0xf); \
6905 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6906 64-bit byteswap already. */ \
6907 if (ctx->le_mode) { \
6908 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6909 tcg_gen_addi_tl(EA, EA, 8); \
6910 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6911 } else { \
6912 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6913 tcg_gen_addi_tl(EA, EA, 8); \
6914 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6915 } \
6916 tcg_temp_free(EA); \
6917 }
6918
6919 #define GEN_VR_LVE(name, opc2, opc3, size) \
6920 static void gen_lve##name(DisasContext *ctx) \
6921 { \
6922 TCGv EA; \
6923 TCGv_ptr rs; \
6924 if (unlikely(!ctx->altivec_enabled)) { \
6925 gen_exception(ctx, POWERPC_EXCP_VPU); \
6926 return; \
6927 } \
6928 gen_set_access_type(ctx, ACCESS_INT); \
6929 EA = tcg_temp_new(); \
6930 gen_addr_reg_index(ctx, EA); \
6931 if (size > 1) { \
6932 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6933 } \
6934 rs = gen_avr_ptr(rS(ctx->opcode)); \
6935 gen_helper_lve##name(cpu_env, rs, EA); \
6936 tcg_temp_free(EA); \
6937 tcg_temp_free_ptr(rs); \
6938 }
6939
6940 #define GEN_VR_STVE(name, opc2, opc3, size) \
6941 static void gen_stve##name(DisasContext *ctx) \
6942 { \
6943 TCGv EA; \
6944 TCGv_ptr rs; \
6945 if (unlikely(!ctx->altivec_enabled)) { \
6946 gen_exception(ctx, POWERPC_EXCP_VPU); \
6947 return; \
6948 } \
6949 gen_set_access_type(ctx, ACCESS_INT); \
6950 EA = tcg_temp_new(); \
6951 gen_addr_reg_index(ctx, EA); \
6952 if (size > 1) { \
6953 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6954 } \
6955 rs = gen_avr_ptr(rS(ctx->opcode)); \
6956 gen_helper_stve##name(cpu_env, rs, EA); \
6957 tcg_temp_free(EA); \
6958 tcg_temp_free_ptr(rs); \
6959 }
6960
6961 GEN_VR_LDX(lvx, 0x07, 0x03);
6962 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6963 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6964
6965 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6966 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6967 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6968
6969 GEN_VR_STX(svx, 0x07, 0x07);
6970 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6971 GEN_VR_STX(svxl, 0x07, 0x0F);
6972
6973 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6974 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6975 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6976
6977 static void gen_lvsl(DisasContext *ctx)
6978 {
6979 TCGv_ptr rd;
6980 TCGv EA;
6981 if (unlikely(!ctx->altivec_enabled)) {
6982 gen_exception(ctx, POWERPC_EXCP_VPU);
6983 return;
6984 }
6985 EA = tcg_temp_new();
6986 gen_addr_reg_index(ctx, EA);
6987 rd = gen_avr_ptr(rD(ctx->opcode));
6988 gen_helper_lvsl(rd, EA);
6989 tcg_temp_free(EA);
6990 tcg_temp_free_ptr(rd);
6991 }
6992
6993 static void gen_lvsr(DisasContext *ctx)
6994 {
6995 TCGv_ptr rd;
6996 TCGv EA;
6997 if (unlikely(!ctx->altivec_enabled)) {
6998 gen_exception(ctx, POWERPC_EXCP_VPU);
6999 return;
7000 }
7001 EA = tcg_temp_new();
7002 gen_addr_reg_index(ctx, EA);
7003 rd = gen_avr_ptr(rD(ctx->opcode));
7004 gen_helper_lvsr(rd, EA);
7005 tcg_temp_free(EA);
7006 tcg_temp_free_ptr(rd);
7007 }
7008
7009 static void gen_mfvscr(DisasContext *ctx)
7010 {
7011 TCGv_i32 t;
7012 if (unlikely(!ctx->altivec_enabled)) {
7013 gen_exception(ctx, POWERPC_EXCP_VPU);
7014 return;
7015 }
7016 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
7017 t = tcg_temp_new_i32();
7018 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
7019 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
7020 tcg_temp_free_i32(t);
7021 }
7022
7023 static void gen_mtvscr(DisasContext *ctx)
7024 {
7025 TCGv_ptr p;
7026 if (unlikely(!ctx->altivec_enabled)) {
7027 gen_exception(ctx, POWERPC_EXCP_VPU);
7028 return;
7029 }
7030 p = gen_avr_ptr(rB(ctx->opcode));
7031 gen_helper_mtvscr(cpu_env, p);
7032 tcg_temp_free_ptr(p);
7033 }
7034
7035 /* Logical operations */
7036 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
7037 static void glue(gen_, name)(DisasContext *ctx) \
7038 { \
7039 if (unlikely(!ctx->altivec_enabled)) { \
7040 gen_exception(ctx, POWERPC_EXCP_VPU); \
7041 return; \
7042 } \
7043 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7044 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7045 }
7046
7047 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7048 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7049 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7050 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7051 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
7052 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7053 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7054 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7055
7056 #define GEN_VXFORM(name, opc2, opc3) \
7057 static void glue(gen_, name)(DisasContext *ctx) \
7058 { \
7059 TCGv_ptr ra, rb, rd; \
7060 if (unlikely(!ctx->altivec_enabled)) { \
7061 gen_exception(ctx, POWERPC_EXCP_VPU); \
7062 return; \
7063 } \
7064 ra = gen_avr_ptr(rA(ctx->opcode)); \
7065 rb = gen_avr_ptr(rB(ctx->opcode)); \
7066 rd = gen_avr_ptr(rD(ctx->opcode)); \
7067 gen_helper_##name (rd, ra, rb); \
7068 tcg_temp_free_ptr(ra); \
7069 tcg_temp_free_ptr(rb); \
7070 tcg_temp_free_ptr(rd); \
7071 }
7072
7073 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7074 static void glue(gen_, name)(DisasContext *ctx) \
7075 { \
7076 TCGv_ptr ra, rb, rd; \
7077 if (unlikely(!ctx->altivec_enabled)) { \
7078 gen_exception(ctx, POWERPC_EXCP_VPU); \
7079 return; \
7080 } \
7081 ra = gen_avr_ptr(rA(ctx->opcode)); \
7082 rb = gen_avr_ptr(rB(ctx->opcode)); \
7083 rd = gen_avr_ptr(rD(ctx->opcode)); \
7084 gen_helper_##name(cpu_env, rd, ra, rb); \
7085 tcg_temp_free_ptr(ra); \
7086 tcg_temp_free_ptr(rb); \
7087 tcg_temp_free_ptr(rd); \
7088 }
7089
7090 #define GEN_VXFORM3(name, opc2, opc3) \
7091 static void glue(gen_, name)(DisasContext *ctx) \
7092 { \
7093 TCGv_ptr ra, rb, rc, rd; \
7094 if (unlikely(!ctx->altivec_enabled)) { \
7095 gen_exception(ctx, POWERPC_EXCP_VPU); \
7096 return; \
7097 } \
7098 ra = gen_avr_ptr(rA(ctx->opcode)); \
7099 rb = gen_avr_ptr(rB(ctx->opcode)); \
7100 rc = gen_avr_ptr(rC(ctx->opcode)); \
7101 rd = gen_avr_ptr(rD(ctx->opcode)); \
7102 gen_helper_##name(rd, ra, rb, rc); \
7103 tcg_temp_free_ptr(ra); \
7104 tcg_temp_free_ptr(rb); \
7105 tcg_temp_free_ptr(rc); \
7106 tcg_temp_free_ptr(rd); \
7107 }
7108
7109 /*
7110 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7111 * an opcode bit. In general, these pairs come from different
7112 * versions of the ISA, so we must also support a pair of flags for
7113 * each instruction.
7114 */
7115 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7116 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7117 { \
7118 if ((Rc(ctx->opcode) == 0) && \
7119 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7120 gen_##name0(ctx); \
7121 } else if ((Rc(ctx->opcode) == 1) && \
7122 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7123 gen_##name1(ctx); \
7124 } else { \
7125 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7126 } \
7127 }
7128
7129 GEN_VXFORM(vaddubm, 0, 0);
7130 GEN_VXFORM(vadduhm, 0, 1);
7131 GEN_VXFORM(vadduwm, 0, 2);
7132 GEN_VXFORM(vaddudm, 0, 3);
7133 GEN_VXFORM(vsububm, 0, 16);
7134 GEN_VXFORM(vsubuhm, 0, 17);
7135 GEN_VXFORM(vsubuwm, 0, 18);
7136 GEN_VXFORM(vsubudm, 0, 19);
7137 GEN_VXFORM(vmaxub, 1, 0);
7138 GEN_VXFORM(vmaxuh, 1, 1);
7139 GEN_VXFORM(vmaxuw, 1, 2);
7140 GEN_VXFORM(vmaxud, 1, 3);
7141 GEN_VXFORM(vmaxsb, 1, 4);
7142 GEN_VXFORM(vmaxsh, 1, 5);
7143 GEN_VXFORM(vmaxsw, 1, 6);
7144 GEN_VXFORM(vmaxsd, 1, 7);
7145 GEN_VXFORM(vminub, 1, 8);
7146 GEN_VXFORM(vminuh, 1, 9);
7147 GEN_VXFORM(vminuw, 1, 10);
7148 GEN_VXFORM(vminud, 1, 11);
7149 GEN_VXFORM(vminsb, 1, 12);
7150 GEN_VXFORM(vminsh, 1, 13);
7151 GEN_VXFORM(vminsw, 1, 14);
7152 GEN_VXFORM(vminsd, 1, 15);
7153 GEN_VXFORM(vavgub, 1, 16);
7154 GEN_VXFORM(vavguh, 1, 17);
7155 GEN_VXFORM(vavguw, 1, 18);
7156 GEN_VXFORM(vavgsb, 1, 20);
7157 GEN_VXFORM(vavgsh, 1, 21);
7158 GEN_VXFORM(vavgsw, 1, 22);
7159 GEN_VXFORM(vmrghb, 6, 0);
7160 GEN_VXFORM(vmrghh, 6, 1);
7161 GEN_VXFORM(vmrghw, 6, 2);
7162 GEN_VXFORM(vmrglb, 6, 4);
7163 GEN_VXFORM(vmrglh, 6, 5);
7164 GEN_VXFORM(vmrglw, 6, 6);
7165
7166 static void gen_vmrgew(DisasContext *ctx)
7167 {
7168 TCGv_i64 tmp;
7169 int VT, VA, VB;
7170 if (unlikely(!ctx->altivec_enabled)) {
7171 gen_exception(ctx, POWERPC_EXCP_VPU);
7172 return;
7173 }
7174 VT = rD(ctx->opcode);
7175 VA = rA(ctx->opcode);
7176 VB = rB(ctx->opcode);
7177 tmp = tcg_temp_new_i64();
7178 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7179 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7180 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7181 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7182 tcg_temp_free_i64(tmp);
7183 }
7184
7185 static void gen_vmrgow(DisasContext *ctx)
7186 {
7187 int VT, VA, VB;
7188 if (unlikely(!ctx->altivec_enabled)) {
7189 gen_exception(ctx, POWERPC_EXCP_VPU);
7190 return;
7191 }
7192 VT = rD(ctx->opcode);
7193 VA = rA(ctx->opcode);
7194 VB = rB(ctx->opcode);
7195
7196 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7197 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7198 }
7199
7200 GEN_VXFORM(vmuloub, 4, 0);
7201 GEN_VXFORM(vmulouh, 4, 1);
7202 GEN_VXFORM(vmulouw, 4, 2);
7203 GEN_VXFORM(vmuluwm, 4, 2);
7204 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7205 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7206 GEN_VXFORM(vmulosb, 4, 4);
7207 GEN_VXFORM(vmulosh, 4, 5);
7208 GEN_VXFORM(vmulosw, 4, 6);
7209 GEN_VXFORM(vmuleub, 4, 8);
7210 GEN_VXFORM(vmuleuh, 4, 9);
7211 GEN_VXFORM(vmuleuw, 4, 10);
7212 GEN_VXFORM(vmulesb, 4, 12);
7213 GEN_VXFORM(vmulesh, 4, 13);
7214 GEN_VXFORM(vmulesw, 4, 14);
7215 GEN_VXFORM(vslb, 2, 4);
7216 GEN_VXFORM(vslh, 2, 5);
7217 GEN_VXFORM(vslw, 2, 6);
7218 GEN_VXFORM(vsld, 2, 23);
7219 GEN_VXFORM(vsrb, 2, 8);
7220 GEN_VXFORM(vsrh, 2, 9);
7221 GEN_VXFORM(vsrw, 2, 10);
7222 GEN_VXFORM(vsrd, 2, 27);
7223 GEN_VXFORM(vsrab, 2, 12);
7224 GEN_VXFORM(vsrah, 2, 13);
7225 GEN_VXFORM(vsraw, 2, 14);
7226 GEN_VXFORM(vsrad, 2, 15);
7227 GEN_VXFORM(vslo, 6, 16);
7228 GEN_VXFORM(vsro, 6, 17);
7229 GEN_VXFORM(vaddcuw, 0, 6);
7230 GEN_VXFORM(vsubcuw, 0, 22);
7231 GEN_VXFORM_ENV(vaddubs, 0, 8);
7232 GEN_VXFORM_ENV(vadduhs, 0, 9);
7233 GEN_VXFORM_ENV(vadduws, 0, 10);
7234 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7235 GEN_VXFORM_ENV(vaddshs, 0, 13);
7236 GEN_VXFORM_ENV(vaddsws, 0, 14);
7237 GEN_VXFORM_ENV(vsububs, 0, 24);
7238 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7239 GEN_VXFORM_ENV(vsubuws, 0, 26);
7240 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7241 GEN_VXFORM_ENV(vsubshs, 0, 29);
7242 GEN_VXFORM_ENV(vsubsws, 0, 30);
7243 GEN_VXFORM(vadduqm, 0, 4);
7244 GEN_VXFORM(vaddcuq, 0, 5);
7245 GEN_VXFORM3(vaddeuqm, 30, 0);
7246 GEN_VXFORM3(vaddecuq, 30, 0);
7247 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7248 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7249 GEN_VXFORM(vsubuqm, 0, 20);
7250 GEN_VXFORM(vsubcuq, 0, 21);
7251 GEN_VXFORM3(vsubeuqm, 31, 0);
7252 GEN_VXFORM3(vsubecuq, 31, 0);
7253 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7254 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7255 GEN_VXFORM(vrlb, 2, 0);
7256 GEN_VXFORM(vrlh, 2, 1);
7257 GEN_VXFORM(vrlw, 2, 2);
7258 GEN_VXFORM(vrld, 2, 3);
7259 GEN_VXFORM(vsl, 2, 7);
7260 GEN_VXFORM(vsr, 2, 11);
7261 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7262 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7263 GEN_VXFORM_ENV(vpkudum, 7, 17);
7264 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7265 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7266 GEN_VXFORM_ENV(vpkudus, 7, 19);
7267 GEN_VXFORM_ENV(vpkshus, 7, 4);
7268 GEN_VXFORM_ENV(vpkswus, 7, 5);
7269 GEN_VXFORM_ENV(vpksdus, 7, 21);
7270 GEN_VXFORM_ENV(vpkshss, 7, 6);
7271 GEN_VXFORM_ENV(vpkswss, 7, 7);
7272 GEN_VXFORM_ENV(vpksdss, 7, 23);
7273 GEN_VXFORM(vpkpx, 7, 12);
7274 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7275 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7276 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7277 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7278 GEN_VXFORM_ENV(vsumsws, 4, 30);
7279 GEN_VXFORM_ENV(vaddfp, 5, 0);
7280 GEN_VXFORM_ENV(vsubfp, 5, 1);
7281 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7282 GEN_VXFORM_ENV(vminfp, 5, 17);
7283
7284 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7285 static void glue(gen_, name)(DisasContext *ctx) \
7286 { \
7287 TCGv_ptr ra, rb, rd; \
7288 if (unlikely(!ctx->altivec_enabled)) { \
7289 gen_exception(ctx, POWERPC_EXCP_VPU); \
7290 return; \
7291 } \
7292 ra = gen_avr_ptr(rA(ctx->opcode)); \
7293 rb = gen_avr_ptr(rB(ctx->opcode)); \
7294 rd = gen_avr_ptr(rD(ctx->opcode)); \
7295 gen_helper_##opname(cpu_env, rd, ra, rb); \
7296 tcg_temp_free_ptr(ra); \
7297 tcg_temp_free_ptr(rb); \
7298 tcg_temp_free_ptr(rd); \
7299 }
7300
7301 #define GEN_VXRFORM(name, opc2, opc3) \
7302 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7303 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7304
7305 /*
7306 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7307 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7308 * come from different versions of the ISA, so we must also support a
7309 * pair of flags for each instruction.
7310 */
7311 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7312 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7313 { \
7314 if ((Rc(ctx->opcode) == 0) && \
7315 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7316 if (Rc21(ctx->opcode) == 0) { \
7317 gen_##name0(ctx); \
7318 } else { \
7319 gen_##name0##_(ctx); \
7320 } \
7321 } else if ((Rc(ctx->opcode) == 1) && \
7322 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7323 if (Rc21(ctx->opcode) == 0) { \
7324 gen_##name1(ctx); \
7325 } else { \
7326 gen_##name1##_(ctx); \
7327 } \
7328 } else { \
7329 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7330 } \
7331 }
7332
7333 GEN_VXRFORM(vcmpequb, 3, 0)
7334 GEN_VXRFORM(vcmpequh, 3, 1)
7335 GEN_VXRFORM(vcmpequw, 3, 2)
7336 GEN_VXRFORM(vcmpequd, 3, 3)
7337 GEN_VXRFORM(vcmpgtsb, 3, 12)
7338 GEN_VXRFORM(vcmpgtsh, 3, 13)
7339 GEN_VXRFORM(vcmpgtsw, 3, 14)
7340 GEN_VXRFORM(vcmpgtsd, 3, 15)
7341 GEN_VXRFORM(vcmpgtub, 3, 8)
7342 GEN_VXRFORM(vcmpgtuh, 3, 9)
7343 GEN_VXRFORM(vcmpgtuw, 3, 10)
7344 GEN_VXRFORM(vcmpgtud, 3, 11)
7345 GEN_VXRFORM(vcmpeqfp, 3, 3)
7346 GEN_VXRFORM(vcmpgefp, 3, 7)
7347 GEN_VXRFORM(vcmpgtfp, 3, 11)
7348 GEN_VXRFORM(vcmpbfp, 3, 15)
7349
7350 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7351 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7352 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7353 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7354 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7355 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7356
7357 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7358 static void glue(gen_, name)(DisasContext *ctx) \
7359 { \
7360 TCGv_ptr rd; \
7361 TCGv_i32 simm; \
7362 if (unlikely(!ctx->altivec_enabled)) { \
7363 gen_exception(ctx, POWERPC_EXCP_VPU); \
7364 return; \
7365 } \
7366 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7367 rd = gen_avr_ptr(rD(ctx->opcode)); \
7368 gen_helper_##name (rd, simm); \
7369 tcg_temp_free_i32(simm); \
7370 tcg_temp_free_ptr(rd); \
7371 }
7372
7373 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7374 GEN_VXFORM_SIMM(vspltish, 6, 13);
7375 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7376
7377 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7378 static void glue(gen_, name)(DisasContext *ctx) \
7379 { \
7380 TCGv_ptr rb, rd; \
7381 if (unlikely(!ctx->altivec_enabled)) { \
7382 gen_exception(ctx, POWERPC_EXCP_VPU); \
7383 return; \
7384 } \
7385 rb = gen_avr_ptr(rB(ctx->opcode)); \
7386 rd = gen_avr_ptr(rD(ctx->opcode)); \
7387 gen_helper_##name (rd, rb); \
7388 tcg_temp_free_ptr(rb); \
7389 tcg_temp_free_ptr(rd); \
7390 }
7391
7392 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7393 static void glue(gen_, name)(DisasContext *ctx) \
7394 { \
7395 TCGv_ptr rb, rd; \
7396 \
7397 if (unlikely(!ctx->altivec_enabled)) { \
7398 gen_exception(ctx, POWERPC_EXCP_VPU); \
7399 return; \
7400 } \
7401 rb = gen_avr_ptr(rB(ctx->opcode)); \
7402 rd = gen_avr_ptr(rD(ctx->opcode)); \
7403 gen_helper_##name(cpu_env, rd, rb); \
7404 tcg_temp_free_ptr(rb); \
7405 tcg_temp_free_ptr(rd); \
7406 }
7407
7408 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7409 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7410 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7411 GEN_VXFORM_NOA(vupklsb, 7, 10);
7412 GEN_VXFORM_NOA(vupklsh, 7, 11);
7413 GEN_VXFORM_NOA(vupklsw, 7, 27);
7414 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7415 GEN_VXFORM_NOA(vupklpx, 7, 15);
7416 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7417 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7418 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7419 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7420 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7421 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7422 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7423 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7424
7425 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7426 static void glue(gen_, name)(DisasContext *ctx) \
7427 { \
7428 TCGv_ptr rd; \
7429 TCGv_i32 simm; \
7430 if (unlikely(!ctx->altivec_enabled)) { \
7431 gen_exception(ctx, POWERPC_EXCP_VPU); \
7432 return; \
7433 } \
7434 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7435 rd = gen_avr_ptr(rD(ctx->opcode)); \
7436 gen_helper_##name (rd, simm); \
7437 tcg_temp_free_i32(simm); \
7438 tcg_temp_free_ptr(rd); \
7439 }
7440
7441 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7442 static void glue(gen_, name)(DisasContext *ctx) \
7443 { \
7444 TCGv_ptr rb, rd; \
7445 TCGv_i32 uimm; \
7446 if (unlikely(!ctx->altivec_enabled)) { \
7447 gen_exception(ctx, POWERPC_EXCP_VPU); \
7448 return; \
7449 } \
7450 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7451 rb = gen_avr_ptr(rB(ctx->opcode)); \
7452 rd = gen_avr_ptr(rD(ctx->opcode)); \
7453 gen_helper_##name (rd, rb, uimm); \
7454 tcg_temp_free_i32(uimm); \
7455 tcg_temp_free_ptr(rb); \
7456 tcg_temp_free_ptr(rd); \
7457 }
7458
7459 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7460 static void glue(gen_, name)(DisasContext *ctx) \
7461 { \
7462 TCGv_ptr rb, rd; \
7463 TCGv_i32 uimm; \
7464 \
7465 if (unlikely(!ctx->altivec_enabled)) { \
7466 gen_exception(ctx, POWERPC_EXCP_VPU); \
7467 return; \
7468 } \
7469 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7470 rb = gen_avr_ptr(rB(ctx->opcode)); \
7471 rd = gen_avr_ptr(rD(ctx->opcode)); \
7472 gen_helper_##name(cpu_env, rd, rb, uimm); \
7473 tcg_temp_free_i32(uimm); \
7474 tcg_temp_free_ptr(rb); \
7475 tcg_temp_free_ptr(rd); \
7476 }
7477
7478 GEN_VXFORM_UIMM(vspltb, 6, 8);
7479 GEN_VXFORM_UIMM(vsplth, 6, 9);
7480 GEN_VXFORM_UIMM(vspltw, 6, 10);
7481 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7482 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7483 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7484 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7485
7486 static void gen_vsldoi(DisasContext *ctx)
7487 {
7488 TCGv_ptr ra, rb, rd;
7489 TCGv_i32 sh;
7490 if (unlikely(!ctx->altivec_enabled)) {
7491 gen_exception(ctx, POWERPC_EXCP_VPU);
7492 return;
7493 }
7494 ra = gen_avr_ptr(rA(ctx->opcode));
7495 rb = gen_avr_ptr(rB(ctx->opcode));
7496 rd = gen_avr_ptr(rD(ctx->opcode));
7497 sh = tcg_const_i32(VSH(ctx->opcode));
7498 gen_helper_vsldoi (rd, ra, rb, sh);
7499 tcg_temp_free_ptr(ra);
7500 tcg_temp_free_ptr(rb);
7501 tcg_temp_free_ptr(rd);
7502 tcg_temp_free_i32(sh);
7503 }
7504
7505 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7506 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7507 { \
7508 TCGv_ptr ra, rb, rc, rd; \
7509 if (unlikely(!ctx->altivec_enabled)) { \
7510 gen_exception(ctx, POWERPC_EXCP_VPU); \
7511 return; \
7512 } \
7513 ra = gen_avr_ptr(rA(ctx->opcode)); \
7514 rb = gen_avr_ptr(rB(ctx->opcode)); \
7515 rc = gen_avr_ptr(rC(ctx->opcode)); \
7516 rd = gen_avr_ptr(rD(ctx->opcode)); \
7517 if (Rc(ctx->opcode)) { \
7518 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7519 } else { \
7520 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7521 } \
7522 tcg_temp_free_ptr(ra); \
7523 tcg_temp_free_ptr(rb); \
7524 tcg_temp_free_ptr(rc); \
7525 tcg_temp_free_ptr(rd); \
7526 }
7527
7528 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7529
7530 static void gen_vmladduhm(DisasContext *ctx)
7531 {
7532 TCGv_ptr ra, rb, rc, rd;
7533 if (unlikely(!ctx->altivec_enabled)) {
7534 gen_exception(ctx, POWERPC_EXCP_VPU);
7535 return;
7536 }
7537 ra = gen_avr_ptr(rA(ctx->opcode));
7538 rb = gen_avr_ptr(rB(ctx->opcode));
7539 rc = gen_avr_ptr(rC(ctx->opcode));
7540 rd = gen_avr_ptr(rD(ctx->opcode));
7541 gen_helper_vmladduhm(rd, ra, rb, rc);
7542 tcg_temp_free_ptr(ra);
7543 tcg_temp_free_ptr(rb);
7544 tcg_temp_free_ptr(rc);
7545 tcg_temp_free_ptr(rd);
7546 }
7547
7548 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7549 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7550 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7551 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7552 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7553
7554 GEN_VXFORM_NOA(vclzb, 1, 28)
7555 GEN_VXFORM_NOA(vclzh, 1, 29)
7556 GEN_VXFORM_NOA(vclzw, 1, 30)
7557 GEN_VXFORM_NOA(vclzd, 1, 31)
7558 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7559 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7560 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7561 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7562 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7563 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7564 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7565 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7566 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7567 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7568 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7569 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7570 GEN_VXFORM(vbpermq, 6, 21);
7571 GEN_VXFORM_NOA(vgbbd, 6, 20);
7572 GEN_VXFORM(vpmsumb, 4, 16)
7573 GEN_VXFORM(vpmsumh, 4, 17)
7574 GEN_VXFORM(vpmsumw, 4, 18)
7575 GEN_VXFORM(vpmsumd, 4, 19)
7576
7577 #define GEN_BCD(op) \
7578 static void gen_##op(DisasContext *ctx) \
7579 { \
7580 TCGv_ptr ra, rb, rd; \
7581 TCGv_i32 ps; \
7582 \
7583 if (unlikely(!ctx->altivec_enabled)) { \
7584 gen_exception(ctx, POWERPC_EXCP_VPU); \
7585 return; \
7586 } \
7587 \
7588 ra = gen_avr_ptr(rA(ctx->opcode)); \
7589 rb = gen_avr_ptr(rB(ctx->opcode)); \
7590 rd = gen_avr_ptr(rD(ctx->opcode)); \
7591 \
7592 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7593 \
7594 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7595 \
7596 tcg_temp_free_ptr(ra); \
7597 tcg_temp_free_ptr(rb); \
7598 tcg_temp_free_ptr(rd); \
7599 tcg_temp_free_i32(ps); \
7600 }
7601
7602 GEN_BCD(bcdadd)
7603 GEN_BCD(bcdsub)
7604
7605 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7606 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7607 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7608 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7609 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7610 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7611 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7612 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7613
7614 static void gen_vsbox(DisasContext *ctx)
7615 {
7616 TCGv_ptr ra, rd;
7617 if (unlikely(!ctx->altivec_enabled)) {
7618 gen_exception(ctx, POWERPC_EXCP_VPU);
7619 return;
7620 }
7621 ra = gen_avr_ptr(rA(ctx->opcode));
7622 rd = gen_avr_ptr(rD(ctx->opcode));
7623 gen_helper_vsbox(rd, ra);
7624 tcg_temp_free_ptr(ra);
7625 tcg_temp_free_ptr(rd);
7626 }
7627
7628 GEN_VXFORM(vcipher, 4, 20)
7629 GEN_VXFORM(vcipherlast, 4, 20)
7630 GEN_VXFORM(vncipher, 4, 21)
7631 GEN_VXFORM(vncipherlast, 4, 21)
7632
7633 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7634 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7635 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7636 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7637
7638 #define VSHASIGMA(op) \
7639 static void gen_##op(DisasContext *ctx) \
7640 { \
7641 TCGv_ptr ra, rd; \
7642 TCGv_i32 st_six; \
7643 if (unlikely(!ctx->altivec_enabled)) { \
7644 gen_exception(ctx, POWERPC_EXCP_VPU); \
7645 return; \
7646 } \
7647 ra = gen_avr_ptr(rA(ctx->opcode)); \
7648 rd = gen_avr_ptr(rD(ctx->opcode)); \
7649 st_six = tcg_const_i32(rB(ctx->opcode)); \
7650 gen_helper_##op(rd, ra, st_six); \
7651 tcg_temp_free_ptr(ra); \
7652 tcg_temp_free_ptr(rd); \
7653 tcg_temp_free_i32(st_six); \
7654 }
7655
7656 VSHASIGMA(vshasigmaw)
7657 VSHASIGMA(vshasigmad)
7658
7659 GEN_VXFORM3(vpermxor, 22, 0xFF)
7660 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7661 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7662
7663 /*** VSX extension ***/
7664
7665 static inline TCGv_i64 cpu_vsrh(int n)
7666 {
7667 if (n < 32) {
7668 return cpu_fpr[n];
7669 } else {
7670 return cpu_avrh[n-32];
7671 }
7672 }
7673
7674 static inline TCGv_i64 cpu_vsrl(int n)
7675 {
7676 if (n < 32) {
7677 return cpu_vsr[n];
7678 } else {
7679 return cpu_avrl[n-32];
7680 }
7681 }
7682
7683 #define VSX_LOAD_SCALAR(name, operation) \
7684 static void gen_##name(DisasContext *ctx) \
7685 { \
7686 TCGv EA; \
7687 if (unlikely(!ctx->vsx_enabled)) { \
7688 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7689 return; \
7690 } \
7691 gen_set_access_type(ctx, ACCESS_INT); \
7692 EA = tcg_temp_new(); \
7693 gen_addr_reg_index(ctx, EA); \
7694 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7695 /* NOTE: cpu_vsrl is undefined */ \
7696 tcg_temp_free(EA); \
7697 }
7698
7699 VSX_LOAD_SCALAR(lxsdx, ld64)
7700 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7701 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7702 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7703
7704 static void gen_lxvd2x(DisasContext *ctx)
7705 {
7706 TCGv EA;
7707 if (unlikely(!ctx->vsx_enabled)) {
7708 gen_exception(ctx, POWERPC_EXCP_VSXU);
7709 return;
7710 }
7711 gen_set_access_type(ctx, ACCESS_INT);
7712 EA = tcg_temp_new();
7713 gen_addr_reg_index(ctx, EA);
7714 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7715 tcg_gen_addi_tl(EA, EA, 8);
7716 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7717 tcg_temp_free(EA);
7718 }
7719
7720 static void gen_lxvdsx(DisasContext *ctx)
7721 {
7722 TCGv EA;
7723 if (unlikely(!ctx->vsx_enabled)) {
7724 gen_exception(ctx, POWERPC_EXCP_VSXU);
7725 return;
7726 }
7727 gen_set_access_type(ctx, ACCESS_INT);
7728 EA = tcg_temp_new();
7729 gen_addr_reg_index(ctx, EA);
7730 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7731 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7732 tcg_temp_free(EA);
7733 }
7734
7735 static void gen_lxvw4x(DisasContext *ctx)
7736 {
7737 TCGv EA;
7738 TCGv_i64 tmp;
7739 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7740 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7741 if (unlikely(!ctx->vsx_enabled)) {
7742 gen_exception(ctx, POWERPC_EXCP_VSXU);
7743 return;
7744 }
7745 gen_set_access_type(ctx, ACCESS_INT);
7746 EA = tcg_temp_new();
7747 tmp = tcg_temp_new_i64();
7748
7749 gen_addr_reg_index(ctx, EA);
7750 gen_qemu_ld32u_i64(ctx, tmp, EA);
7751 tcg_gen_addi_tl(EA, EA, 4);
7752 gen_qemu_ld32u_i64(ctx, xth, EA);
7753 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7754
7755 tcg_gen_addi_tl(EA, EA, 4);
7756 gen_qemu_ld32u_i64(ctx, tmp, EA);
7757 tcg_gen_addi_tl(EA, EA, 4);
7758 gen_qemu_ld32u_i64(ctx, xtl, EA);
7759 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7760
7761 tcg_temp_free(EA);
7762 tcg_temp_free_i64(tmp);
7763 }
7764
7765 #define VSX_STORE_SCALAR(name, operation) \
7766 static void gen_##name(DisasContext *ctx) \
7767 { \
7768 TCGv EA; \
7769 if (unlikely(!ctx->vsx_enabled)) { \
7770 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7771 return; \
7772 } \
7773 gen_set_access_type(ctx, ACCESS_INT); \
7774 EA = tcg_temp_new(); \
7775 gen_addr_reg_index(ctx, EA); \
7776 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7777 tcg_temp_free(EA); \
7778 }
7779
7780 VSX_STORE_SCALAR(stxsdx, st64)
7781 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7782 VSX_STORE_SCALAR(stxsspx, st32fs)
7783
7784 static void gen_stxvd2x(DisasContext *ctx)
7785 {
7786 TCGv EA;
7787 if (unlikely(!ctx->vsx_enabled)) {
7788 gen_exception(ctx, POWERPC_EXCP_VSXU);
7789 return;
7790 }
7791 gen_set_access_type(ctx, ACCESS_INT);
7792 EA = tcg_temp_new();
7793 gen_addr_reg_index(ctx, EA);
7794 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7795 tcg_gen_addi_tl(EA, EA, 8);
7796 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7797 tcg_temp_free(EA);
7798 }
7799
7800 static void gen_stxvw4x(DisasContext *ctx)
7801 {
7802 TCGv_i64 tmp;
7803 TCGv EA;
7804 if (unlikely(!ctx->vsx_enabled)) {
7805 gen_exception(ctx, POWERPC_EXCP_VSXU);
7806 return;
7807 }
7808 gen_set_access_type(ctx, ACCESS_INT);
7809 EA = tcg_temp_new();
7810 gen_addr_reg_index(ctx, EA);
7811 tmp = tcg_temp_new_i64();
7812
7813 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7814 gen_qemu_st32_i64(ctx, tmp, EA);
7815 tcg_gen_addi_tl(EA, EA, 4);
7816 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7817
7818 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7819 tcg_gen_addi_tl(EA, EA, 4);
7820 gen_qemu_st32_i64(ctx, tmp, EA);
7821 tcg_gen_addi_tl(EA, EA, 4);
7822 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7823
7824 tcg_temp_free(EA);
7825 tcg_temp_free_i64(tmp);
7826 }
7827
7828 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7829 static void gen_##name(DisasContext *ctx) \
7830 { \
7831 if (xS(ctx->opcode) < 32) { \
7832 if (unlikely(!ctx->fpu_enabled)) { \
7833 gen_exception(ctx, POWERPC_EXCP_FPU); \
7834 return; \
7835 } \
7836 } else { \
7837 if (unlikely(!ctx->altivec_enabled)) { \
7838 gen_exception(ctx, POWERPC_EXCP_VPU); \
7839 return; \
7840 } \
7841 } \
7842 TCGv_i64 tmp = tcg_temp_new_i64(); \
7843 tcg_gen_##tcgop1(tmp, source); \
7844 tcg_gen_##tcgop2(target, tmp); \
7845 tcg_temp_free_i64(tmp); \
7846 }
7847
7848
7849 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7850 cpu_vsrh(xS(ctx->opcode)))
7851 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7852 cpu_gpr[rA(ctx->opcode)])
7853 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7854 cpu_gpr[rA(ctx->opcode)])
7855
7856 #if defined(TARGET_PPC64)
7857 #define MV_VSRD(name, target, source) \
7858 static void gen_##name(DisasContext *ctx) \
7859 { \
7860 if (xS(ctx->opcode) < 32) { \
7861 if (unlikely(!ctx->fpu_enabled)) { \
7862 gen_exception(ctx, POWERPC_EXCP_FPU); \
7863 return; \
7864 } \
7865 } else { \
7866 if (unlikely(!ctx->altivec_enabled)) { \
7867 gen_exception(ctx, POWERPC_EXCP_VPU); \
7868 return; \
7869 } \
7870 } \
7871 tcg_gen_mov_i64(target, source); \
7872 }
7873
7874 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7875 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7876
7877 #endif
7878
7879 static void gen_xxpermdi(DisasContext *ctx)
7880 {
7881 if (unlikely(!ctx->vsx_enabled)) {
7882 gen_exception(ctx, POWERPC_EXCP_VSXU);
7883 return;
7884 }
7885
7886 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7887 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7888 TCGv_i64 xh, xl;
7889
7890 xh = tcg_temp_new_i64();
7891 xl = tcg_temp_new_i64();
7892
7893 if ((DM(ctx->opcode) & 2) == 0) {
7894 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7895 } else {
7896 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7897 }
7898 if ((DM(ctx->opcode) & 1) == 0) {
7899 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7900 } else {
7901 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7902 }
7903
7904 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7905 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7906
7907 tcg_temp_free_i64(xh);
7908 tcg_temp_free_i64(xl);
7909 } else {
7910 if ((DM(ctx->opcode) & 2) == 0) {
7911 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7912 } else {
7913 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7914 }
7915 if ((DM(ctx->opcode) & 1) == 0) {
7916 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7917 } else {
7918 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7919 }
7920 }
7921 }
7922
7923 #define OP_ABS 1
7924 #define OP_NABS 2
7925 #define OP_NEG 3
7926 #define OP_CPSGN 4
7927 #define SGN_MASK_DP 0x8000000000000000ull
7928 #define SGN_MASK_SP 0x8000000080000000ull
7929
7930 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7931 static void glue(gen_, name)(DisasContext * ctx) \
7932 { \
7933 TCGv_i64 xb, sgm; \
7934 if (unlikely(!ctx->vsx_enabled)) { \
7935 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7936 return; \
7937 } \
7938 xb = tcg_temp_new_i64(); \
7939 sgm = tcg_temp_new_i64(); \
7940 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7941 tcg_gen_movi_i64(sgm, sgn_mask); \
7942 switch (op) { \
7943 case OP_ABS: { \
7944 tcg_gen_andc_i64(xb, xb, sgm); \
7945 break; \
7946 } \
7947 case OP_NABS: { \
7948 tcg_gen_or_i64(xb, xb, sgm); \
7949 break; \
7950 } \
7951 case OP_NEG: { \
7952 tcg_gen_xor_i64(xb, xb, sgm); \
7953 break; \
7954 } \
7955 case OP_CPSGN: { \
7956 TCGv_i64 xa = tcg_temp_new_i64(); \
7957 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7958 tcg_gen_and_i64(xa, xa, sgm); \
7959 tcg_gen_andc_i64(xb, xb, sgm); \
7960 tcg_gen_or_i64(xb, xb, xa); \
7961 tcg_temp_free_i64(xa); \
7962 break; \
7963 } \
7964 } \
7965 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7966 tcg_temp_free_i64(xb); \
7967 tcg_temp_free_i64(sgm); \
7968 }
7969
7970 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7971 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7972 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7973 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7974
7975 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7976 static void glue(gen_, name)(DisasContext * ctx) \
7977 { \
7978 TCGv_i64 xbh, xbl, sgm; \
7979 if (unlikely(!ctx->vsx_enabled)) { \
7980 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7981 return; \
7982 } \
7983 xbh = tcg_temp_new_i64(); \
7984 xbl = tcg_temp_new_i64(); \
7985 sgm = tcg_temp_new_i64(); \
7986 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7987 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7988 tcg_gen_movi_i64(sgm, sgn_mask); \
7989 switch (op) { \
7990 case OP_ABS: { \
7991 tcg_gen_andc_i64(xbh, xbh, sgm); \
7992 tcg_gen_andc_i64(xbl, xbl, sgm); \
7993 break; \
7994 } \
7995 case OP_NABS: { \
7996 tcg_gen_or_i64(xbh, xbh, sgm); \
7997 tcg_gen_or_i64(xbl, xbl, sgm); \
7998 break; \
7999 } \
8000 case OP_NEG: { \
8001 tcg_gen_xor_i64(xbh, xbh, sgm); \
8002 tcg_gen_xor_i64(xbl, xbl, sgm); \
8003 break; \
8004 } \
8005 case OP_CPSGN: { \
8006 TCGv_i64 xah = tcg_temp_new_i64(); \
8007 TCGv_i64 xal = tcg_temp_new_i64(); \
8008 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
8009 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
8010 tcg_gen_and_i64(xah, xah, sgm); \
8011 tcg_gen_and_i64(xal, xal, sgm); \
8012 tcg_gen_andc_i64(xbh, xbh, sgm); \
8013 tcg_gen_andc_i64(xbl, xbl, sgm); \
8014 tcg_gen_or_i64(xbh, xbh, xah); \
8015 tcg_gen_or_i64(xbl, xbl, xal); \
8016 tcg_temp_free_i64(xah); \
8017 tcg_temp_free_i64(xal); \
8018 break; \
8019 } \
8020 } \
8021 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
8022 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
8023 tcg_temp_free_i64(xbh); \
8024 tcg_temp_free_i64(xbl); \
8025 tcg_temp_free_i64(sgm); \
8026 }
8027
8028 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
8029 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
8030 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
8031 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
8032 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
8033 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
8034 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
8035 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
8036
8037 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8038 static void gen_##name(DisasContext * ctx) \
8039 { \
8040 TCGv_i32 opc; \
8041 if (unlikely(!ctx->vsx_enabled)) { \
8042 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8043 return; \
8044 } \
8045 /* NIP cannot be restored if the memory exception comes from an helper */ \
8046 gen_update_nip(ctx, ctx->nip - 4); \
8047 opc = tcg_const_i32(ctx->opcode); \
8048 gen_helper_##name(cpu_env, opc); \
8049 tcg_temp_free_i32(opc); \
8050 }
8051
8052 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8053 static void gen_##name(DisasContext * ctx) \
8054 { \
8055 if (unlikely(!ctx->vsx_enabled)) { \
8056 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8057 return; \
8058 } \
8059 /* NIP cannot be restored if the exception comes */ \
8060 /* from a helper. */ \
8061 gen_update_nip(ctx, ctx->nip - 4); \
8062 \
8063 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8064 cpu_vsrh(xB(ctx->opcode))); \
8065 }
8066
8067 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8081 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8088 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8090 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8092 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8102 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8103 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8104
8105 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8106 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8107 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8108 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8109 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8110 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8111 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8112 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8113 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8114 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8115 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8116 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8117 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8118 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8119 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8120 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8121 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8122
8123 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8124 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8125 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8126 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8127 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8128 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8129 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8130 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8131 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8132 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8133 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8134 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8135 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8136 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8137 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8138 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8139 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8140 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8141 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8142 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8143 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8144 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8145 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8146 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8147 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8148 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8149 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8150 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8151 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8152 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8153 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8154 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8155 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8156 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8157 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8158 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8159
8160 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8161 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8162 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8163 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8164 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8165 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8166 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8167 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8168 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8169 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8170 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8171 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8172 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8173 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8174 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8175 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8176 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8177 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8178 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8179 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8180 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8181 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8182 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8183 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8184 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8185 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8186 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8187 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8188 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8189 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8190 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8191 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8192 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8193 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8194 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8195 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8196
8197 #define VSX_LOGICAL(name, tcg_op) \
8198 static void glue(gen_, name)(DisasContext * ctx) \
8199 { \
8200 if (unlikely(!ctx->vsx_enabled)) { \
8201 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8202 return; \
8203 } \
8204 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8205 cpu_vsrh(xB(ctx->opcode))); \
8206 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8207 cpu_vsrl(xB(ctx->opcode))); \
8208 }
8209
8210 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8211 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8212 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8213 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8214 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8215 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8216 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8217 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8218
8219 #define VSX_XXMRG(name, high) \
8220 static void glue(gen_, name)(DisasContext * ctx) \
8221 { \
8222 TCGv_i64 a0, a1, b0, b1; \
8223 if (unlikely(!ctx->vsx_enabled)) { \
8224 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8225 return; \
8226 } \
8227 a0 = tcg_temp_new_i64(); \
8228 a1 = tcg_temp_new_i64(); \
8229 b0 = tcg_temp_new_i64(); \
8230 b1 = tcg_temp_new_i64(); \
8231 if (high) { \
8232 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8233 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8234 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8235 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8236 } else { \
8237 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8238 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8239 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8240 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8241 } \
8242 tcg_gen_shri_i64(a0, a0, 32); \
8243 tcg_gen_shri_i64(b0, b0, 32); \
8244 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8245 b0, a0, 32, 32); \
8246 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8247 b1, a1, 32, 32); \
8248 tcg_temp_free_i64(a0); \
8249 tcg_temp_free_i64(a1); \
8250 tcg_temp_free_i64(b0); \
8251 tcg_temp_free_i64(b1); \
8252 }
8253
8254 VSX_XXMRG(xxmrghw, 1)
8255 VSX_XXMRG(xxmrglw, 0)
8256
8257 static void gen_xxsel(DisasContext * ctx)
8258 {
8259 TCGv_i64 a, b, c;
8260 if (unlikely(!ctx->vsx_enabled)) {
8261 gen_exception(ctx, POWERPC_EXCP_VSXU);
8262 return;
8263 }
8264 a = tcg_temp_new_i64();
8265 b = tcg_temp_new_i64();
8266 c = tcg_temp_new_i64();
8267
8268 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8269 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8270 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8271
8272 tcg_gen_and_i64(b, b, c);
8273 tcg_gen_andc_i64(a, a, c);
8274 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8275
8276 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8277 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8278 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8279
8280 tcg_gen_and_i64(b, b, c);
8281 tcg_gen_andc_i64(a, a, c);
8282 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8283
8284 tcg_temp_free_i64(a);
8285 tcg_temp_free_i64(b);
8286 tcg_temp_free_i64(c);
8287 }
8288
8289 static void gen_xxspltw(DisasContext *ctx)
8290 {
8291 TCGv_i64 b, b2;
8292 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8293 cpu_vsrl(xB(ctx->opcode)) :
8294 cpu_vsrh(xB(ctx->opcode));
8295
8296 if (unlikely(!ctx->vsx_enabled)) {
8297 gen_exception(ctx, POWERPC_EXCP_VSXU);
8298 return;
8299 }
8300
8301 b = tcg_temp_new_i64();
8302 b2 = tcg_temp_new_i64();
8303
8304 if (UIM(ctx->opcode) & 1) {
8305 tcg_gen_ext32u_i64(b, vsr);
8306 } else {
8307 tcg_gen_shri_i64(b, vsr, 32);
8308 }
8309
8310 tcg_gen_shli_i64(b2, b, 32);
8311 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8312 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8313
8314 tcg_temp_free_i64(b);
8315 tcg_temp_free_i64(b2);
8316 }
8317
8318 static void gen_xxsldwi(DisasContext *ctx)
8319 {
8320 TCGv_i64 xth, xtl;
8321 if (unlikely(!ctx->vsx_enabled)) {
8322 gen_exception(ctx, POWERPC_EXCP_VSXU);
8323 return;
8324 }
8325 xth = tcg_temp_new_i64();
8326 xtl = tcg_temp_new_i64();
8327
8328 switch (SHW(ctx->opcode)) {
8329 case 0: {
8330 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8331 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8332 break;
8333 }
8334 case 1: {
8335 TCGv_i64 t0 = tcg_temp_new_i64();
8336 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8337 tcg_gen_shli_i64(xth, xth, 32);
8338 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8339 tcg_gen_shri_i64(t0, t0, 32);
8340 tcg_gen_or_i64(xth, xth, t0);
8341 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8342 tcg_gen_shli_i64(xtl, xtl, 32);
8343 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8344 tcg_gen_shri_i64(t0, t0, 32);
8345 tcg_gen_or_i64(xtl, xtl, t0);
8346 tcg_temp_free_i64(t0);
8347 break;
8348 }
8349 case 2: {
8350 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8351 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8352 break;
8353 }
8354 case 3: {
8355 TCGv_i64 t0 = tcg_temp_new_i64();
8356 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8357 tcg_gen_shli_i64(xth, xth, 32);
8358 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8359 tcg_gen_shri_i64(t0, t0, 32);
8360 tcg_gen_or_i64(xth, xth, t0);
8361 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8362 tcg_gen_shli_i64(xtl, xtl, 32);
8363 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8364 tcg_gen_shri_i64(t0, t0, 32);
8365 tcg_gen_or_i64(xtl, xtl, t0);
8366 tcg_temp_free_i64(t0);
8367 break;
8368 }
8369 }
8370
8371 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8372 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8373
8374 tcg_temp_free_i64(xth);
8375 tcg_temp_free_i64(xtl);
8376 }
8377
8378 /*** Decimal Floating Point ***/
8379
8380 static inline TCGv_ptr gen_fprp_ptr(int reg)
8381 {
8382 TCGv_ptr r = tcg_temp_new_ptr();
8383 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8384 return r;
8385 }
8386
8387 #define GEN_DFP_T_A_B_Rc(name) \
8388 static void gen_##name(DisasContext *ctx) \
8389 { \
8390 TCGv_ptr rd, ra, rb; \
8391 if (unlikely(!ctx->fpu_enabled)) { \
8392 gen_exception(ctx, POWERPC_EXCP_FPU); \
8393 return; \
8394 } \
8395 gen_update_nip(ctx, ctx->nip - 4); \
8396 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8397 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8398 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8399 gen_helper_##name(cpu_env, rd, ra, rb); \
8400 if (unlikely(Rc(ctx->opcode) != 0)) { \
8401 gen_set_cr1_from_fpscr(ctx); \
8402 } \
8403 tcg_temp_free_ptr(rd); \
8404 tcg_temp_free_ptr(ra); \
8405 tcg_temp_free_ptr(rb); \
8406 }
8407
8408 #define GEN_DFP_BF_A_B(name) \
8409 static void gen_##name(DisasContext *ctx) \
8410 { \
8411 TCGv_ptr ra, rb; \
8412 if (unlikely(!ctx->fpu_enabled)) { \
8413 gen_exception(ctx, POWERPC_EXCP_FPU); \
8414 return; \
8415 } \
8416 gen_update_nip(ctx, ctx->nip - 4); \
8417 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8418 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8419 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8420 cpu_env, ra, rb); \
8421 tcg_temp_free_ptr(ra); \
8422 tcg_temp_free_ptr(rb); \
8423 }
8424
8425 #define GEN_DFP_BF_A_DCM(name) \
8426 static void gen_##name(DisasContext *ctx) \
8427 { \
8428 TCGv_ptr ra; \
8429 TCGv_i32 dcm; \
8430 if (unlikely(!ctx->fpu_enabled)) { \
8431 gen_exception(ctx, POWERPC_EXCP_FPU); \
8432 return; \
8433 } \
8434 gen_update_nip(ctx, ctx->nip - 4); \
8435 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8436 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8437 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8438 cpu_env, ra, dcm); \
8439 tcg_temp_free_ptr(ra); \
8440 tcg_temp_free_i32(dcm); \
8441 }
8442
8443 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8444 static void gen_##name(DisasContext *ctx) \
8445 { \
8446 TCGv_ptr rt, rb; \
8447 TCGv_i32 u32_1, u32_2; \
8448 if (unlikely(!ctx->fpu_enabled)) { \
8449 gen_exception(ctx, POWERPC_EXCP_FPU); \
8450 return; \
8451 } \
8452 gen_update_nip(ctx, ctx->nip - 4); \
8453 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8454 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8455 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8456 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8457 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8458 if (unlikely(Rc(ctx->opcode) != 0)) { \
8459 gen_set_cr1_from_fpscr(ctx); \
8460 } \
8461 tcg_temp_free_ptr(rt); \
8462 tcg_temp_free_ptr(rb); \
8463 tcg_temp_free_i32(u32_1); \
8464 tcg_temp_free_i32(u32_2); \
8465 }
8466
8467 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8468 static void gen_##name(DisasContext *ctx) \
8469 { \
8470 TCGv_ptr rt, ra, rb; \
8471 TCGv_i32 i32; \
8472 if (unlikely(!ctx->fpu_enabled)) { \
8473 gen_exception(ctx, POWERPC_EXCP_FPU); \
8474 return; \
8475 } \
8476 gen_update_nip(ctx, ctx->nip - 4); \
8477 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8478 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8479 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8480 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8481 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8482 if (unlikely(Rc(ctx->opcode) != 0)) { \
8483 gen_set_cr1_from_fpscr(ctx); \
8484 } \
8485 tcg_temp_free_ptr(rt); \
8486 tcg_temp_free_ptr(rb); \
8487 tcg_temp_free_ptr(ra); \
8488 tcg_temp_free_i32(i32); \
8489 }
8490
8491 #define GEN_DFP_T_B_Rc(name) \
8492 static void gen_##name(DisasContext *ctx) \
8493 { \
8494 TCGv_ptr rt, rb; \
8495 if (unlikely(!ctx->fpu_enabled)) { \
8496 gen_exception(ctx, POWERPC_EXCP_FPU); \
8497 return; \
8498 } \
8499 gen_update_nip(ctx, ctx->nip - 4); \
8500 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8501 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8502 gen_helper_##name(cpu_env, rt, rb); \
8503 if (unlikely(Rc(ctx->opcode) != 0)) { \
8504 gen_set_cr1_from_fpscr(ctx); \
8505 } \
8506 tcg_temp_free_ptr(rt); \
8507 tcg_temp_free_ptr(rb); \
8508 }
8509
8510 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8511 static void gen_##name(DisasContext *ctx) \
8512 { \
8513 TCGv_ptr rt, rs; \
8514 TCGv_i32 i32; \
8515 if (unlikely(!ctx->fpu_enabled)) { \
8516 gen_exception(ctx, POWERPC_EXCP_FPU); \
8517 return; \
8518 } \
8519 gen_update_nip(ctx, ctx->nip - 4); \
8520 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8521 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8522 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8523 gen_helper_##name(cpu_env, rt, rs, i32); \
8524 if (unlikely(Rc(ctx->opcode) != 0)) { \
8525 gen_set_cr1_from_fpscr(ctx); \
8526 } \
8527 tcg_temp_free_ptr(rt); \
8528 tcg_temp_free_ptr(rs); \
8529 tcg_temp_free_i32(i32); \
8530 }
8531
8532 GEN_DFP_T_A_B_Rc(dadd)
8533 GEN_DFP_T_A_B_Rc(daddq)
8534 GEN_DFP_T_A_B_Rc(dsub)
8535 GEN_DFP_T_A_B_Rc(dsubq)
8536 GEN_DFP_T_A_B_Rc(dmul)
8537 GEN_DFP_T_A_B_Rc(dmulq)
8538 GEN_DFP_T_A_B_Rc(ddiv)
8539 GEN_DFP_T_A_B_Rc(ddivq)
8540 GEN_DFP_BF_A_B(dcmpu)
8541 GEN_DFP_BF_A_B(dcmpuq)
8542 GEN_DFP_BF_A_B(dcmpo)
8543 GEN_DFP_BF_A_B(dcmpoq)
8544 GEN_DFP_BF_A_DCM(dtstdc)
8545 GEN_DFP_BF_A_DCM(dtstdcq)
8546 GEN_DFP_BF_A_DCM(dtstdg)
8547 GEN_DFP_BF_A_DCM(dtstdgq)
8548 GEN_DFP_BF_A_B(dtstex)
8549 GEN_DFP_BF_A_B(dtstexq)
8550 GEN_DFP_BF_A_B(dtstsf)
8551 GEN_DFP_BF_A_B(dtstsfq)
8552 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8553 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8554 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8555 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8556 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8557 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8558 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8559 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8560 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8561 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8562 GEN_DFP_T_B_Rc(dctdp)
8563 GEN_DFP_T_B_Rc(dctqpq)
8564 GEN_DFP_T_B_Rc(drsp)
8565 GEN_DFP_T_B_Rc(drdpq)
8566 GEN_DFP_T_B_Rc(dcffix)
8567 GEN_DFP_T_B_Rc(dcffixq)
8568 GEN_DFP_T_B_Rc(dctfix)
8569 GEN_DFP_T_B_Rc(dctfixq)
8570 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8571 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8572 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8573 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8574 GEN_DFP_T_B_Rc(dxex)
8575 GEN_DFP_T_B_Rc(dxexq)
8576 GEN_DFP_T_A_B_Rc(diex)
8577 GEN_DFP_T_A_B_Rc(diexq)
8578 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8579 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8580 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8581 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8582
8583 /*** SPE extension ***/
8584 /* Register moves */
8585
8586 static inline void gen_evmra(DisasContext *ctx)
8587 {
8588
8589 if (unlikely(!ctx->spe_enabled)) {
8590 gen_exception(ctx, POWERPC_EXCP_SPEU);
8591 return;
8592 }
8593
8594 TCGv_i64 tmp = tcg_temp_new_i64();
8595
8596 /* tmp := rA_lo + rA_hi << 32 */
8597 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8598
8599 /* spe_acc := tmp */
8600 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8601 tcg_temp_free_i64(tmp);
8602
8603 /* rD := rA */
8604 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8605 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8606 }
8607
8608 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8609 {
8610 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8611 }
8612
8613 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8614 {
8615 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8616 }
8617
8618 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8619 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8620 { \
8621 if (Rc(ctx->opcode)) \
8622 gen_##name1(ctx); \
8623 else \
8624 gen_##name0(ctx); \
8625 }
8626
8627 /* Handler for undefined SPE opcodes */
8628 static inline void gen_speundef(DisasContext *ctx)
8629 {
8630 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8631 }
8632
8633 /* SPE logic */
8634 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8635 static inline void gen_##name(DisasContext *ctx) \
8636 { \
8637 if (unlikely(!ctx->spe_enabled)) { \
8638 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8639 return; \
8640 } \
8641 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8642 cpu_gpr[rB(ctx->opcode)]); \
8643 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8644 cpu_gprh[rB(ctx->opcode)]); \
8645 }
8646
8647 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8648 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8649 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8650 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8651 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8652 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8653 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8654 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8655
8656 /* SPE logic immediate */
8657 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8658 static inline void gen_##name(DisasContext *ctx) \
8659 { \
8660 TCGv_i32 t0; \
8661 if (unlikely(!ctx->spe_enabled)) { \
8662 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8663 return; \
8664 } \
8665 t0 = tcg_temp_new_i32(); \
8666 \
8667 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8668 tcg_opi(t0, t0, rB(ctx->opcode)); \
8669 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8670 \
8671 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8672 tcg_opi(t0, t0, rB(ctx->opcode)); \
8673 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8674 \
8675 tcg_temp_free_i32(t0); \
8676 }
8677 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8678 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8679 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8680 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8681
8682 /* SPE arithmetic */
8683 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8684 static inline void gen_##name(DisasContext *ctx) \
8685 { \
8686 TCGv_i32 t0; \
8687 if (unlikely(!ctx->spe_enabled)) { \
8688 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8689 return; \
8690 } \
8691 t0 = tcg_temp_new_i32(); \
8692 \
8693 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8694 tcg_op(t0, t0); \
8695 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8696 \
8697 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8698 tcg_op(t0, t0); \
8699 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8700 \
8701 tcg_temp_free_i32(t0); \
8702 }
8703
8704 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8705 {
8706 TCGLabel *l1 = gen_new_label();
8707 TCGLabel *l2 = gen_new_label();
8708
8709 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8710 tcg_gen_neg_i32(ret, arg1);
8711 tcg_gen_br(l2);
8712 gen_set_label(l1);
8713 tcg_gen_mov_i32(ret, arg1);
8714 gen_set_label(l2);
8715 }
8716 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8717 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8718 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8719 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8720 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8721 {
8722 tcg_gen_addi_i32(ret, arg1, 0x8000);
8723 tcg_gen_ext16u_i32(ret, ret);
8724 }
8725 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8726 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8727 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8728
8729 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8730 static inline void gen_##name(DisasContext *ctx) \
8731 { \
8732 TCGv_i32 t0, t1; \
8733 if (unlikely(!ctx->spe_enabled)) { \
8734 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8735 return; \
8736 } \
8737 t0 = tcg_temp_new_i32(); \
8738 t1 = tcg_temp_new_i32(); \
8739 \
8740 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8741 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8742 tcg_op(t0, t0, t1); \
8743 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8744 \
8745 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8746 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8747 tcg_op(t0, t0, t1); \
8748 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8749 \
8750 tcg_temp_free_i32(t0); \
8751 tcg_temp_free_i32(t1); \
8752 }
8753
8754 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8755 {
8756 TCGLabel *l1 = gen_new_label();
8757 TCGLabel *l2 = gen_new_label();
8758 TCGv_i32 t0 = tcg_temp_local_new_i32();
8759
8760 /* No error here: 6 bits are used */
8761 tcg_gen_andi_i32(t0, arg2, 0x3F);
8762 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8763 tcg_gen_shr_i32(ret, arg1, t0);
8764 tcg_gen_br(l2);
8765 gen_set_label(l1);
8766 tcg_gen_movi_i32(ret, 0);
8767 gen_set_label(l2);
8768 tcg_temp_free_i32(t0);
8769 }
8770 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8771 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8772 {
8773 TCGLabel *l1 = gen_new_label();
8774 TCGLabel *l2 = gen_new_label();
8775 TCGv_i32 t0 = tcg_temp_local_new_i32();
8776
8777 /* No error here: 6 bits are used */
8778 tcg_gen_andi_i32(t0, arg2, 0x3F);
8779 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8780 tcg_gen_sar_i32(ret, arg1, t0);
8781 tcg_gen_br(l2);
8782 gen_set_label(l1);
8783 tcg_gen_movi_i32(ret, 0);
8784 gen_set_label(l2);
8785 tcg_temp_free_i32(t0);
8786 }
8787 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8788 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8789 {
8790 TCGLabel *l1 = gen_new_label();
8791 TCGLabel *l2 = gen_new_label();
8792 TCGv_i32 t0 = tcg_temp_local_new_i32();
8793
8794 /* No error here: 6 bits are used */
8795 tcg_gen_andi_i32(t0, arg2, 0x3F);
8796 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8797 tcg_gen_shl_i32(ret, arg1, t0);
8798 tcg_gen_br(l2);
8799 gen_set_label(l1);
8800 tcg_gen_movi_i32(ret, 0);
8801 gen_set_label(l2);
8802 tcg_temp_free_i32(t0);
8803 }
8804 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8805 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8806 {
8807 TCGv_i32 t0 = tcg_temp_new_i32();
8808 tcg_gen_andi_i32(t0, arg2, 0x1F);
8809 tcg_gen_rotl_i32(ret, arg1, t0);
8810 tcg_temp_free_i32(t0);
8811 }
8812 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8813 static inline void gen_evmergehi(DisasContext *ctx)
8814 {
8815 if (unlikely(!ctx->spe_enabled)) {
8816 gen_exception(ctx, POWERPC_EXCP_SPEU);
8817 return;
8818 }
8819 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8820 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8821 }
8822 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8823 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8824 {
8825 tcg_gen_sub_i32(ret, arg2, arg1);
8826 }
8827 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8828
8829 /* SPE arithmetic immediate */
8830 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8831 static inline void gen_##name(DisasContext *ctx) \
8832 { \
8833 TCGv_i32 t0; \
8834 if (unlikely(!ctx->spe_enabled)) { \
8835 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8836 return; \
8837 } \
8838 t0 = tcg_temp_new_i32(); \
8839 \
8840 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8841 tcg_op(t0, t0, rA(ctx->opcode)); \
8842 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8843 \
8844 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8845 tcg_op(t0, t0, rA(ctx->opcode)); \
8846 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8847 \
8848 tcg_temp_free_i32(t0); \
8849 }
8850 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8851 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8852
8853 /* SPE comparison */
8854 #define GEN_SPEOP_COMP(name, tcg_cond) \
8855 static inline void gen_##name(DisasContext *ctx) \
8856 { \
8857 if (unlikely(!ctx->spe_enabled)) { \
8858 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8859 return; \
8860 } \
8861 TCGLabel *l1 = gen_new_label(); \
8862 TCGLabel *l2 = gen_new_label(); \
8863 TCGLabel *l3 = gen_new_label(); \
8864 TCGLabel *l4 = gen_new_label(); \
8865 \
8866 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8867 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8868 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8869 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8870 \
8871 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8872 cpu_gpr[rB(ctx->opcode)], l1); \
8873 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8874 tcg_gen_br(l2); \
8875 gen_set_label(l1); \
8876 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8877 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8878 gen_set_label(l2); \
8879 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8880 cpu_gprh[rB(ctx->opcode)], l3); \
8881 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8882 ~(CRF_CH | CRF_CH_AND_CL)); \
8883 tcg_gen_br(l4); \
8884 gen_set_label(l3); \
8885 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8886 CRF_CH | CRF_CH_OR_CL); \
8887 gen_set_label(l4); \
8888 }
8889 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8890 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8891 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8892 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8893 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8894
8895 /* SPE misc */
8896 static inline void gen_brinc(DisasContext *ctx)
8897 {
8898 /* Note: brinc is usable even if SPE is disabled */
8899 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8900 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8901 }
8902 static inline void gen_evmergelo(DisasContext *ctx)
8903 {
8904 if (unlikely(!ctx->spe_enabled)) {
8905 gen_exception(ctx, POWERPC_EXCP_SPEU);
8906 return;
8907 }
8908 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8909 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8910 }
8911 static inline void gen_evmergehilo(DisasContext *ctx)
8912 {
8913 if (unlikely(!ctx->spe_enabled)) {
8914 gen_exception(ctx, POWERPC_EXCP_SPEU);
8915 return;
8916 }
8917 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8918 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8919 }
8920 static inline void gen_evmergelohi(DisasContext *ctx)
8921 {
8922 if (unlikely(!ctx->spe_enabled)) {
8923 gen_exception(ctx, POWERPC_EXCP_SPEU);
8924 return;
8925 }
8926 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8927 TCGv tmp = tcg_temp_new();
8928 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8929 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8930 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8931 tcg_temp_free(tmp);
8932 } else {
8933 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8934 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8935 }
8936 }
8937 static inline void gen_evsplati(DisasContext *ctx)
8938 {
8939 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8940
8941 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8942 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8943 }
8944 static inline void gen_evsplatfi(DisasContext *ctx)
8945 {
8946 uint64_t imm = rA(ctx->opcode) << 27;
8947
8948 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8949 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8950 }
8951
8952 static inline void gen_evsel(DisasContext *ctx)
8953 {
8954 TCGLabel *l1 = gen_new_label();
8955 TCGLabel *l2 = gen_new_label();
8956 TCGLabel *l3 = gen_new_label();
8957 TCGLabel *l4 = gen_new_label();
8958 TCGv_i32 t0 = tcg_temp_local_new_i32();
8959
8960 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8961 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8962 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8963 tcg_gen_br(l2);
8964 gen_set_label(l1);
8965 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8966 gen_set_label(l2);
8967 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8968 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8969 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8970 tcg_gen_br(l4);
8971 gen_set_label(l3);
8972 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8973 gen_set_label(l4);
8974 tcg_temp_free_i32(t0);
8975 }
8976
8977 static void gen_evsel0(DisasContext *ctx)
8978 {
8979 gen_evsel(ctx);
8980 }
8981
8982 static void gen_evsel1(DisasContext *ctx)
8983 {
8984 gen_evsel(ctx);
8985 }
8986
8987 static void gen_evsel2(DisasContext *ctx)
8988 {
8989 gen_evsel(ctx);
8990 }
8991
8992 static void gen_evsel3(DisasContext *ctx)
8993 {
8994 gen_evsel(ctx);
8995 }
8996
8997 /* Multiply */
8998
8999 static inline void gen_evmwumi(DisasContext *ctx)
9000 {
9001 TCGv_i64 t0, t1;
9002
9003 if (unlikely(!ctx->spe_enabled)) {
9004 gen_exception(ctx, POWERPC_EXCP_SPEU);
9005 return;
9006 }
9007
9008 t0 = tcg_temp_new_i64();
9009 t1 = tcg_temp_new_i64();
9010
9011 /* t0 := rA; t1 := rB */
9012 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9013 tcg_gen_ext32u_i64(t0, t0);
9014 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9015 tcg_gen_ext32u_i64(t1, t1);
9016
9017 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9018
9019 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9020
9021 tcg_temp_free_i64(t0);
9022 tcg_temp_free_i64(t1);
9023 }
9024
9025 static inline void gen_evmwumia(DisasContext *ctx)
9026 {
9027 TCGv_i64 tmp;
9028
9029 if (unlikely(!ctx->spe_enabled)) {
9030 gen_exception(ctx, POWERPC_EXCP_SPEU);
9031 return;
9032 }
9033
9034 gen_evmwumi(ctx); /* rD := rA * rB */
9035
9036 tmp = tcg_temp_new_i64();
9037
9038 /* acc := rD */
9039 gen_load_gpr64(tmp, rD(ctx->opcode));
9040 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9041 tcg_temp_free_i64(tmp);
9042 }
9043
9044 static inline void gen_evmwumiaa(DisasContext *ctx)
9045 {
9046 TCGv_i64 acc;
9047 TCGv_i64 tmp;
9048
9049 if (unlikely(!ctx->spe_enabled)) {
9050 gen_exception(ctx, POWERPC_EXCP_SPEU);
9051 return;
9052 }
9053
9054 gen_evmwumi(ctx); /* rD := rA * rB */
9055
9056 acc = tcg_temp_new_i64();
9057 tmp = tcg_temp_new_i64();
9058
9059 /* tmp := rD */
9060 gen_load_gpr64(tmp, rD(ctx->opcode));
9061
9062 /* Load acc */
9063 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9064
9065 /* acc := tmp + acc */
9066 tcg_gen_add_i64(acc, acc, tmp);
9067
9068 /* Store acc */
9069 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9070
9071 /* rD := acc */
9072 gen_store_gpr64(rD(ctx->opcode), acc);
9073
9074 tcg_temp_free_i64(acc);
9075 tcg_temp_free_i64(tmp);
9076 }
9077
9078 static inline void gen_evmwsmi(DisasContext *ctx)
9079 {
9080 TCGv_i64 t0, t1;
9081
9082 if (unlikely(!ctx->spe_enabled)) {
9083 gen_exception(ctx, POWERPC_EXCP_SPEU);
9084 return;
9085 }
9086
9087 t0 = tcg_temp_new_i64();
9088 t1 = tcg_temp_new_i64();
9089
9090 /* t0 := rA; t1 := rB */
9091 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9092 tcg_gen_ext32s_i64(t0, t0);
9093 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9094 tcg_gen_ext32s_i64(t1, t1);
9095
9096 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9097
9098 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9099
9100 tcg_temp_free_i64(t0);
9101 tcg_temp_free_i64(t1);
9102 }
9103
9104 static inline void gen_evmwsmia(DisasContext *ctx)
9105 {
9106 TCGv_i64 tmp;
9107
9108 gen_evmwsmi(ctx); /* rD := rA * rB */
9109
9110 tmp = tcg_temp_new_i64();
9111
9112 /* acc := rD */
9113 gen_load_gpr64(tmp, rD(ctx->opcode));
9114 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9115
9116 tcg_temp_free_i64(tmp);
9117 }
9118
9119 static inline void gen_evmwsmiaa(DisasContext *ctx)
9120 {
9121 TCGv_i64 acc = tcg_temp_new_i64();
9122 TCGv_i64 tmp = tcg_temp_new_i64();
9123
9124 gen_evmwsmi(ctx); /* rD := rA * rB */
9125
9126 acc = tcg_temp_new_i64();
9127 tmp = tcg_temp_new_i64();
9128
9129 /* tmp := rD */
9130 gen_load_gpr64(tmp, rD(ctx->opcode));
9131
9132 /* Load acc */
9133 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9134
9135 /* acc := tmp + acc */
9136 tcg_gen_add_i64(acc, acc, tmp);
9137
9138 /* Store acc */
9139 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9140
9141 /* rD := acc */
9142 gen_store_gpr64(rD(ctx->opcode), acc);
9143
9144 tcg_temp_free_i64(acc);
9145 tcg_temp_free_i64(tmp);
9146 }
9147
9148 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9149 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9150 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9151 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9152 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9153 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9154 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9155 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9156 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9157 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9158 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9159 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9160 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9161 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9162 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9163 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9164 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9165 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9166 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9167 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9168 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9169 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9170 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9171 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9172 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9173 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9174 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9175 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9176 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9177
9178 /* SPE load and stores */
9179 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9180 {
9181 target_ulong uimm = rB(ctx->opcode);
9182
9183 if (rA(ctx->opcode) == 0) {
9184 tcg_gen_movi_tl(EA, uimm << sh);
9185 } else {
9186 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9187 if (NARROW_MODE(ctx)) {
9188 tcg_gen_ext32u_tl(EA, EA);
9189 }
9190 }
9191 }
9192
9193 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9194 {
9195 TCGv_i64 t0 = tcg_temp_new_i64();
9196 gen_qemu_ld64(ctx, t0, addr);
9197 gen_store_gpr64(rD(ctx->opcode), t0);
9198 tcg_temp_free_i64(t0);
9199 }
9200
9201 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9202 {
9203 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9204 gen_addr_add(ctx, addr, addr, 4);
9205 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9206 }
9207
9208 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9209 {
9210 TCGv t0 = tcg_temp_new();
9211 gen_qemu_ld16u(ctx, t0, addr);
9212 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9213 gen_addr_add(ctx, addr, addr, 2);
9214 gen_qemu_ld16u(ctx, t0, addr);
9215 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9216 gen_addr_add(ctx, addr, addr, 2);
9217 gen_qemu_ld16u(ctx, t0, addr);
9218 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9219 gen_addr_add(ctx, addr, addr, 2);
9220 gen_qemu_ld16u(ctx, t0, addr);
9221 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9222 tcg_temp_free(t0);
9223 }
9224
9225 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9226 {
9227 TCGv t0 = tcg_temp_new();
9228 gen_qemu_ld16u(ctx, t0, addr);
9229 tcg_gen_shli_tl(t0, t0, 16);
9230 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9231 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9232 tcg_temp_free(t0);
9233 }
9234
9235 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9236 {
9237 TCGv t0 = tcg_temp_new();
9238 gen_qemu_ld16u(ctx, t0, addr);
9239 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9240 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9241 tcg_temp_free(t0);
9242 }
9243
9244 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9245 {
9246 TCGv t0 = tcg_temp_new();
9247 gen_qemu_ld16s(ctx, t0, addr);
9248 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9249 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9250 tcg_temp_free(t0);
9251 }
9252
9253 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9254 {
9255 TCGv t0 = tcg_temp_new();
9256 gen_qemu_ld16u(ctx, t0, addr);
9257 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9258 gen_addr_add(ctx, addr, addr, 2);
9259 gen_qemu_ld16u(ctx, t0, addr);
9260 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9261 tcg_temp_free(t0);
9262 }
9263
9264 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9265 {
9266 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9267 gen_addr_add(ctx, addr, addr, 2);
9268 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9269 }
9270
9271 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9272 {
9273 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9274 gen_addr_add(ctx, addr, addr, 2);
9275 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9276 }
9277
9278 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9279 {
9280 TCGv t0 = tcg_temp_new();
9281 gen_qemu_ld32u(ctx, t0, addr);
9282 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9283 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9284 tcg_temp_free(t0);
9285 }
9286
9287 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9288 {
9289 TCGv t0 = tcg_temp_new();
9290 gen_qemu_ld16u(ctx, t0, addr);
9291 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9292 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9293 gen_addr_add(ctx, addr, addr, 2);
9294 gen_qemu_ld16u(ctx, t0, addr);
9295 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9296 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9297 tcg_temp_free(t0);
9298 }
9299
9300 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9301 {
9302 TCGv_i64 t0 = tcg_temp_new_i64();
9303 gen_load_gpr64(t0, rS(ctx->opcode));
9304 gen_qemu_st64(ctx, t0, addr);
9305 tcg_temp_free_i64(t0);
9306 }
9307
9308 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9309 {
9310 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9311 gen_addr_add(ctx, addr, addr, 4);
9312 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9313 }
9314
9315 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9316 {
9317 TCGv t0 = tcg_temp_new();
9318 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9319 gen_qemu_st16(ctx, t0, addr);
9320 gen_addr_add(ctx, addr, addr, 2);
9321 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9322 gen_addr_add(ctx, addr, addr, 2);
9323 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9324 gen_qemu_st16(ctx, t0, addr);
9325 tcg_temp_free(t0);
9326 gen_addr_add(ctx, addr, addr, 2);
9327 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9328 }
9329
9330 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9331 {
9332 TCGv t0 = tcg_temp_new();
9333 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9334 gen_qemu_st16(ctx, t0, addr);
9335 gen_addr_add(ctx, addr, addr, 2);
9336 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9337 gen_qemu_st16(ctx, t0, addr);
9338 tcg_temp_free(t0);
9339 }
9340
9341 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9342 {
9343 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9344 gen_addr_add(ctx, addr, addr, 2);
9345 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9346 }
9347
9348 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9349 {
9350 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9351 }
9352
9353 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9354 {
9355 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9356 }
9357
9358 #define GEN_SPEOP_LDST(name, opc2, sh) \
9359 static void glue(gen_, name)(DisasContext *ctx) \
9360 { \
9361 TCGv t0; \
9362 if (unlikely(!ctx->spe_enabled)) { \
9363 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9364 return; \
9365 } \
9366 gen_set_access_type(ctx, ACCESS_INT); \
9367 t0 = tcg_temp_new(); \
9368 if (Rc(ctx->opcode)) { \
9369 gen_addr_spe_imm_index(ctx, t0, sh); \
9370 } else { \
9371 gen_addr_reg_index(ctx, t0); \
9372 } \
9373 gen_op_##name(ctx, t0); \
9374 tcg_temp_free(t0); \
9375 }
9376
9377 GEN_SPEOP_LDST(evldd, 0x00, 3);
9378 GEN_SPEOP_LDST(evldw, 0x01, 3);
9379 GEN_SPEOP_LDST(evldh, 0x02, 3);
9380 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9381 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9382 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9383 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9384 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9385 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9386 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9387 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9388
9389 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9390 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9391 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9392 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9393 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9394 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9395 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9396
9397 /* Multiply and add - TODO */
9398 #if 0
9399 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9400 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9401 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9402 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9403 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9404 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9405 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9406 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9407 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9408 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9409 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9410 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9411
9412 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9413 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9414 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9415 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9416 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9417 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9418 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9419 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9420 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9421 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9422 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9423 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9424
9425 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9426 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9427 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9428 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9429 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9430
9431 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9432 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9433 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9434 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9435 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9436 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9437 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9438 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9439 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9440 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9441 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9442 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9443
9444 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9445 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9446 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9447 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9448
9449 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9450 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9451 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9452 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9453 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9454 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9455 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9456 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9457 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9458 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9459 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9460 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9461
9462 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9463 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9464 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9465 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9466 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9467 #endif
9468
9469 /*** SPE floating-point extension ***/
9470 #define GEN_SPEFPUOP_CONV_32_32(name) \
9471 static inline void gen_##name(DisasContext *ctx) \
9472 { \
9473 TCGv_i32 t0 = tcg_temp_new_i32(); \
9474 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9475 gen_helper_##name(t0, cpu_env, t0); \
9476 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9477 tcg_temp_free_i32(t0); \
9478 }
9479 #define GEN_SPEFPUOP_CONV_32_64(name) \
9480 static inline void gen_##name(DisasContext *ctx) \
9481 { \
9482 TCGv_i64 t0 = tcg_temp_new_i64(); \
9483 TCGv_i32 t1 = tcg_temp_new_i32(); \
9484 gen_load_gpr64(t0, rB(ctx->opcode)); \
9485 gen_helper_##name(t1, cpu_env, t0); \
9486 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9487 tcg_temp_free_i64(t0); \
9488 tcg_temp_free_i32(t1); \
9489 }
9490 #define GEN_SPEFPUOP_CONV_64_32(name) \
9491 static inline void gen_##name(DisasContext *ctx) \
9492 { \
9493 TCGv_i64 t0 = tcg_temp_new_i64(); \
9494 TCGv_i32 t1 = tcg_temp_new_i32(); \
9495 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9496 gen_helper_##name(t0, cpu_env, t1); \
9497 gen_store_gpr64(rD(ctx->opcode), t0); \
9498 tcg_temp_free_i64(t0); \
9499 tcg_temp_free_i32(t1); \
9500 }
9501 #define GEN_SPEFPUOP_CONV_64_64(name) \
9502 static inline void gen_##name(DisasContext *ctx) \
9503 { \
9504 TCGv_i64 t0 = tcg_temp_new_i64(); \
9505 gen_load_gpr64(t0, rB(ctx->opcode)); \
9506 gen_helper_##name(t0, cpu_env, t0); \
9507 gen_store_gpr64(rD(ctx->opcode), t0); \
9508 tcg_temp_free_i64(t0); \
9509 }
9510 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9511 static inline void gen_##name(DisasContext *ctx) \
9512 { \
9513 TCGv_i32 t0, t1; \
9514 if (unlikely(!ctx->spe_enabled)) { \
9515 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9516 return; \
9517 } \
9518 t0 = tcg_temp_new_i32(); \
9519 t1 = tcg_temp_new_i32(); \
9520 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9521 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9522 gen_helper_##name(t0, cpu_env, t0, t1); \
9523 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9524 \
9525 tcg_temp_free_i32(t0); \
9526 tcg_temp_free_i32(t1); \
9527 }
9528 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9529 static inline void gen_##name(DisasContext *ctx) \
9530 { \
9531 TCGv_i64 t0, t1; \
9532 if (unlikely(!ctx->spe_enabled)) { \
9533 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9534 return; \
9535 } \
9536 t0 = tcg_temp_new_i64(); \
9537 t1 = tcg_temp_new_i64(); \
9538 gen_load_gpr64(t0, rA(ctx->opcode)); \
9539 gen_load_gpr64(t1, rB(ctx->opcode)); \
9540 gen_helper_##name(t0, cpu_env, t0, t1); \
9541 gen_store_gpr64(rD(ctx->opcode), t0); \
9542 tcg_temp_free_i64(t0); \
9543 tcg_temp_free_i64(t1); \
9544 }
9545 #define GEN_SPEFPUOP_COMP_32(name) \
9546 static inline void gen_##name(DisasContext *ctx) \
9547 { \
9548 TCGv_i32 t0, t1; \
9549 if (unlikely(!ctx->spe_enabled)) { \
9550 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9551 return; \
9552 } \
9553 t0 = tcg_temp_new_i32(); \
9554 t1 = tcg_temp_new_i32(); \
9555 \
9556 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9557 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9558 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9559 \
9560 tcg_temp_free_i32(t0); \
9561 tcg_temp_free_i32(t1); \
9562 }
9563 #define GEN_SPEFPUOP_COMP_64(name) \
9564 static inline void gen_##name(DisasContext *ctx) \
9565 { \
9566 TCGv_i64 t0, t1; \
9567 if (unlikely(!ctx->spe_enabled)) { \
9568 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9569 return; \
9570 } \
9571 t0 = tcg_temp_new_i64(); \
9572 t1 = tcg_temp_new_i64(); \
9573 gen_load_gpr64(t0, rA(ctx->opcode)); \
9574 gen_load_gpr64(t1, rB(ctx->opcode)); \
9575 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9576 tcg_temp_free_i64(t0); \
9577 tcg_temp_free_i64(t1); \
9578 }
9579
9580 /* Single precision floating-point vectors operations */
9581 /* Arithmetic */
9582 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9583 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9584 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9585 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9586 static inline void gen_evfsabs(DisasContext *ctx)
9587 {
9588 if (unlikely(!ctx->spe_enabled)) {
9589 gen_exception(ctx, POWERPC_EXCP_SPEU);
9590 return;
9591 }
9592 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9593 ~0x80000000);
9594 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9595 ~0x80000000);
9596 }
9597 static inline void gen_evfsnabs(DisasContext *ctx)
9598 {
9599 if (unlikely(!ctx->spe_enabled)) {
9600 gen_exception(ctx, POWERPC_EXCP_SPEU);
9601 return;
9602 }
9603 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9604 0x80000000);
9605 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9606 0x80000000);
9607 }
9608 static inline void gen_evfsneg(DisasContext *ctx)
9609 {
9610 if (unlikely(!ctx->spe_enabled)) {
9611 gen_exception(ctx, POWERPC_EXCP_SPEU);
9612 return;
9613 }
9614 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9615 0x80000000);
9616 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9617 0x80000000);
9618 }
9619
9620 /* Conversion */
9621 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9622 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9623 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9624 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9625 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9626 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9627 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9628 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9629 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9630 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9631
9632 /* Comparison */
9633 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9634 GEN_SPEFPUOP_COMP_64(evfscmplt);
9635 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9636 GEN_SPEFPUOP_COMP_64(evfststgt);
9637 GEN_SPEFPUOP_COMP_64(evfststlt);
9638 GEN_SPEFPUOP_COMP_64(evfststeq);
9639
9640 /* Opcodes definitions */
9641 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9642 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9643 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9644 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9645 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9646 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9647 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9648 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9649 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9650 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9651 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9652 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9653 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9654 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9655
9656 /* Single precision floating-point operations */
9657 /* Arithmetic */
9658 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9659 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9660 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9661 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9662 static inline void gen_efsabs(DisasContext *ctx)
9663 {
9664 if (unlikely(!ctx->spe_enabled)) {
9665 gen_exception(ctx, POWERPC_EXCP_SPEU);
9666 return;
9667 }
9668 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9669 }
9670 static inline void gen_efsnabs(DisasContext *ctx)
9671 {
9672 if (unlikely(!ctx->spe_enabled)) {
9673 gen_exception(ctx, POWERPC_EXCP_SPEU);
9674 return;
9675 }
9676 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9677 }
9678 static inline void gen_efsneg(DisasContext *ctx)
9679 {
9680 if (unlikely(!ctx->spe_enabled)) {
9681 gen_exception(ctx, POWERPC_EXCP_SPEU);
9682 return;
9683 }
9684 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9685 }
9686
9687 /* Conversion */
9688 GEN_SPEFPUOP_CONV_32_32(efscfui);
9689 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9690 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9691 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9692 GEN_SPEFPUOP_CONV_32_32(efsctui);
9693 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9694 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9695 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9696 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9697 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9698 GEN_SPEFPUOP_CONV_32_64(efscfd);
9699
9700 /* Comparison */
9701 GEN_SPEFPUOP_COMP_32(efscmpgt);
9702 GEN_SPEFPUOP_COMP_32(efscmplt);
9703 GEN_SPEFPUOP_COMP_32(efscmpeq);
9704 GEN_SPEFPUOP_COMP_32(efststgt);
9705 GEN_SPEFPUOP_COMP_32(efststlt);
9706 GEN_SPEFPUOP_COMP_32(efststeq);
9707
9708 /* Opcodes definitions */
9709 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9710 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9711 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9712 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9713 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9714 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9715 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9716 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9717 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9718 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9719 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9720 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9721 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9722 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9723
9724 /* Double precision floating-point operations */
9725 /* Arithmetic */
9726 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9727 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9728 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9729 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9730 static inline void gen_efdabs(DisasContext *ctx)
9731 {
9732 if (unlikely(!ctx->spe_enabled)) {
9733 gen_exception(ctx, POWERPC_EXCP_SPEU);
9734 return;
9735 }
9736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9737 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9738 ~0x80000000);
9739 }
9740 static inline void gen_efdnabs(DisasContext *ctx)
9741 {
9742 if (unlikely(!ctx->spe_enabled)) {
9743 gen_exception(ctx, POWERPC_EXCP_SPEU);
9744 return;
9745 }
9746 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9747 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9748 0x80000000);
9749 }
9750 static inline void gen_efdneg(DisasContext *ctx)
9751 {
9752 if (unlikely(!ctx->spe_enabled)) {
9753 gen_exception(ctx, POWERPC_EXCP_SPEU);
9754 return;
9755 }
9756 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9757 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9758 0x80000000);
9759 }
9760
9761 /* Conversion */
9762 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9763 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9764 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9765 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9766 GEN_SPEFPUOP_CONV_32_64(efdctui);
9767 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9768 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9769 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9770 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9771 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9772 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9773 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9774 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9775 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9776 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9777
9778 /* Comparison */
9779 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9780 GEN_SPEFPUOP_COMP_64(efdcmplt);
9781 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9782 GEN_SPEFPUOP_COMP_64(efdtstgt);
9783 GEN_SPEFPUOP_COMP_64(efdtstlt);
9784 GEN_SPEFPUOP_COMP_64(efdtsteq);
9785
9786 /* Opcodes definitions */
9787 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9788 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9789 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9790 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9791 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9792 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9793 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9794 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9795 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9796 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9797 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9798 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9799 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9800 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9801 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9802 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9803
9804 static void gen_tbegin(DisasContext *ctx)
9805 {
9806 if (unlikely(!ctx->tm_enabled)) {
9807 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9808 return;
9809 }
9810 gen_helper_tbegin(cpu_env);
9811 }
9812
9813 #define GEN_TM_NOOP(name) \
9814 static inline void gen_##name(DisasContext *ctx) \
9815 { \
9816 if (unlikely(!ctx->tm_enabled)) { \
9817 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9818 return; \
9819 } \
9820 /* Because tbegin always fails in QEMU, these user \
9821 * space instructions all have a simple implementation: \
9822 * \
9823 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9824 * = 0b0 || 0b00 || 0b0 \
9825 */ \
9826 tcg_gen_movi_i32(cpu_crf[0], 0); \
9827 }
9828
9829 GEN_TM_NOOP(tend);
9830 GEN_TM_NOOP(tabort);
9831 GEN_TM_NOOP(tabortwc);
9832 GEN_TM_NOOP(tabortwci);
9833 GEN_TM_NOOP(tabortdc);
9834 GEN_TM_NOOP(tabortdci);
9835 GEN_TM_NOOP(tsr);
9836
9837 static void gen_tcheck(DisasContext *ctx)
9838 {
9839 if (unlikely(!ctx->tm_enabled)) {
9840 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9841 return;
9842 }
9843 /* Because tbegin always fails, the tcheck implementation
9844 * is simple:
9845 *
9846 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9847 * = 0b1 || 0b00 || 0b0
9848 */
9849 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9850 }
9851
9852 #if defined(CONFIG_USER_ONLY)
9853 #define GEN_TM_PRIV_NOOP(name) \
9854 static inline void gen_##name(DisasContext *ctx) \
9855 { \
9856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9857 }
9858
9859 #else
9860
9861 #define GEN_TM_PRIV_NOOP(name) \
9862 static inline void gen_##name(DisasContext *ctx) \
9863 { \
9864 if (unlikely(ctx->pr)) { \
9865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9866 return; \
9867 } \
9868 if (unlikely(!ctx->tm_enabled)) { \
9869 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9870 return; \
9871 } \
9872 /* Because tbegin always fails, the implementation is \
9873 * simple: \
9874 * \
9875 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9876 * = 0b0 || 0b00 | 0b0 \
9877 */ \
9878 tcg_gen_movi_i32(cpu_crf[0], 0); \
9879 }
9880
9881 #endif
9882
9883 GEN_TM_PRIV_NOOP(treclaim);
9884 GEN_TM_PRIV_NOOP(trechkpt);
9885
9886 static opcode_t opcodes[] = {
9887 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9888 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9889 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9890 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9891 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9892 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9893 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9894 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9895 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9896 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9897 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9898 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9899 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9900 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9901 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9902 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9903 #if defined(TARGET_PPC64)
9904 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9905 #endif
9906 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9907 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9908 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9909 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9910 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9911 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9912 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9913 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9914 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9915 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9916 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9917 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9918 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9919 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9920 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9921 #if defined(TARGET_PPC64)
9922 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9923 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9924 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9925 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9926 #endif
9927 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9928 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9929 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9930 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9931 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9932 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9933 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9934 #if defined(TARGET_PPC64)
9935 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9936 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9937 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9938 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9939 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9940 #endif
9941 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9942 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9943 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9944 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9945 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9946 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9947 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9948 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9949 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9950 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9951 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9952 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9953 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9954 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9955 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9956 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9957 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9958 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9959 #if defined(TARGET_PPC64)
9960 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9961 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9962 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9963 #endif
9964 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9965 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9966 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9967 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9968 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9969 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9970 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9971 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9972 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9973 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9974 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9975 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9976 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9977 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9978 #if defined(TARGET_PPC64)
9979 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9980 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9981 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9982 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9983 #endif
9984 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9985 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9986 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9987 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9988 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9989 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9990 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9991 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9992 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9993 #if defined(TARGET_PPC64)
9994 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9995 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9996 #endif
9997 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9998 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9999 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
10000 #if defined(TARGET_PPC64)
10001 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
10002 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
10003 #endif
10004 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
10005 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
10006 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
10007 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
10008 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
10009 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
10010 #if defined(TARGET_PPC64)
10011 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
10012 #endif
10013 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
10014 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
10015 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
10016 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
10017 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
10018 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
10019 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
10020 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
10021 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
10022 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
10023 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
10024 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
10025 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
10026 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
10027 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
10028 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
10029 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
10030 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
10031 #if defined(TARGET_PPC64)
10032 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
10033 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10034 PPC_SEGMENT_64B),
10035 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10036 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10037 PPC_SEGMENT_64B),
10038 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10039 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10040 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
10041 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
10042 #endif
10043 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10044 /* XXX Those instructions will need to be handled differently for
10045 * different ISA versions */
10046 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10047 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
10048 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10049 #if defined(TARGET_PPC64)
10050 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
10051 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10052 #endif
10053 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10054 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10055 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10056 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10057 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10058 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10059 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10060 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10061 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10062 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10063 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10064 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10065 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10066 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10067 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10068 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10069 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10070 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10071 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10072 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10073 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10074 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10075 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10076 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10077 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10078 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10079 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10080 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10081 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10082 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10083 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10084 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10085 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10086 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10087 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10088 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10089 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10090 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10091 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10092 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10093 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10094 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10095 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10096 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10097 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10098 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10099 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10100 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10101 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10102 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10103 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10104 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10105 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10106 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10107 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10108 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10109 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10110 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10111 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10112 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10113 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10114 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10115 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10116 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10117 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10118 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10119 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10120 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10121 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10122 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10123 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10124 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10125 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10126 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10127 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10128 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10129 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10130 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10131 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10132 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10133 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10134 PPC_NONE, PPC2_BOOKE206),
10135 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10136 PPC_NONE, PPC2_BOOKE206),
10137 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10138 PPC_NONE, PPC2_BOOKE206),
10139 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10140 PPC_NONE, PPC2_BOOKE206),
10141 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10142 PPC_NONE, PPC2_BOOKE206),
10143 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10144 PPC_NONE, PPC2_PRCNTL),
10145 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10146 PPC_NONE, PPC2_PRCNTL),
10147 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10148 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10149 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10150 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10151 PPC_BOOKE, PPC2_BOOKE206),
10152 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10153 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10154 PPC_BOOKE, PPC2_BOOKE206),
10155 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10156 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10157 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10158 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10159 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10160 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10161 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10162 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10163 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10164
10165 #undef GEN_INT_ARITH_ADD
10166 #undef GEN_INT_ARITH_ADD_CONST
10167 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10168 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10169 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10170 add_ca, compute_ca, compute_ov) \
10171 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10172 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10173 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10174 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10175 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10176 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10177 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10178 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10179 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10180 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10181 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10182
10183 #undef GEN_INT_ARITH_DIVW
10184 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10185 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10186 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10187 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10188 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10189 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10190 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10191 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10192 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10193 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10194
10195 #if defined(TARGET_PPC64)
10196 #undef GEN_INT_ARITH_DIVD
10197 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10198 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10199 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10200 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10201 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10202 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10203
10204 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10205 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10206 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10207 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10208
10209 #undef GEN_INT_ARITH_MUL_HELPER
10210 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10211 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10212 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10213 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10214 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10215 #endif
10216
10217 #undef GEN_INT_ARITH_SUBF
10218 #undef GEN_INT_ARITH_SUBF_CONST
10219 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10220 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10221 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10222 add_ca, compute_ca, compute_ov) \
10223 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10224 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10225 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10226 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10227 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10228 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10229 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10230 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10231 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10232 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10233 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10234
10235 #undef GEN_LOGICAL1
10236 #undef GEN_LOGICAL2
10237 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10238 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10239 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10240 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10241 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10242 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10243 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10244 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10245 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10246 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10247 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10248 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10249 #if defined(TARGET_PPC64)
10250 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10251 #endif
10252
10253 #if defined(TARGET_PPC64)
10254 #undef GEN_PPC64_R2
10255 #undef GEN_PPC64_R4
10256 #define GEN_PPC64_R2(name, opc1, opc2) \
10257 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10258 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10259 PPC_64B)
10260 #define GEN_PPC64_R4(name, opc1, opc2) \
10261 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10262 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10263 PPC_64B), \
10264 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10265 PPC_64B), \
10266 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10267 PPC_64B)
10268 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10269 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10270 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10271 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10272 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10273 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10274 #endif
10275
10276 #undef _GEN_FLOAT_ACB
10277 #undef GEN_FLOAT_ACB
10278 #undef _GEN_FLOAT_AB
10279 #undef GEN_FLOAT_AB
10280 #undef _GEN_FLOAT_AC
10281 #undef GEN_FLOAT_AC
10282 #undef GEN_FLOAT_B
10283 #undef GEN_FLOAT_BS
10284 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10285 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10286 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10287 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10288 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10289 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10290 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10291 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10292 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10293 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10294 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10295 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10296 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10297 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10298 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10299 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10300 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10301 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10302 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10303
10304 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10305 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10306 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10307 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10308 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10309 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10310 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10311 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10312 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10313 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10314 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10315 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10316 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10317 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10318 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10319 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10320 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10321 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10322 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10323 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10324 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10325 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10326 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10327 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10328 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10329 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10330 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10331 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10332 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10333 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10334 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10335
10336 #undef GEN_LD
10337 #undef GEN_LDU
10338 #undef GEN_LDUX
10339 #undef GEN_LDX_E
10340 #undef GEN_LDS
10341 #define GEN_LD(name, ldop, opc, type) \
10342 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10343 #define GEN_LDU(name, ldop, opc, type) \
10344 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10345 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10346 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10347 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10348 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10349 #define GEN_LDS(name, ldop, op, type) \
10350 GEN_LD(name, ldop, op | 0x20, type) \
10351 GEN_LDU(name, ldop, op | 0x21, type) \
10352 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10353 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10354
10355 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10356 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10357 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10358 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10359 #if defined(TARGET_PPC64)
10360 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10361 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10362 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10363 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10364 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10365 #endif
10366 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10367 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10368
10369 #undef GEN_ST
10370 #undef GEN_STU
10371 #undef GEN_STUX
10372 #undef GEN_STX_E
10373 #undef GEN_STS
10374 #define GEN_ST(name, stop, opc, type) \
10375 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10376 #define GEN_STU(name, stop, opc, type) \
10377 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10378 #define GEN_STUX(name, stop, opc2, opc3, type) \
10379 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10380 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10381 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10382 #define GEN_STS(name, stop, op, type) \
10383 GEN_ST(name, stop, op | 0x20, type) \
10384 GEN_STU(name, stop, op | 0x21, type) \
10385 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10386 GEN_STX(name, stop, 0x17, op | 0x00, type)
10387
10388 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10389 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10390 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10391 #if defined(TARGET_PPC64)
10392 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10393 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10394 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10395 #endif
10396 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10397 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10398
10399 #undef GEN_LDF
10400 #undef GEN_LDUF
10401 #undef GEN_LDUXF
10402 #undef GEN_LDXF
10403 #undef GEN_LDFS
10404 #define GEN_LDF(name, ldop, opc, type) \
10405 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10406 #define GEN_LDUF(name, ldop, opc, type) \
10407 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10408 #define GEN_LDUXF(name, ldop, opc, type) \
10409 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10410 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10411 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10412 #define GEN_LDFS(name, ldop, op, type) \
10413 GEN_LDF(name, ldop, op | 0x20, type) \
10414 GEN_LDUF(name, ldop, op | 0x21, type) \
10415 GEN_LDUXF(name, ldop, op | 0x01, type) \
10416 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10417
10418 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10419 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10420 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10421 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10422 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10423 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10424
10425 #undef GEN_STF
10426 #undef GEN_STUF
10427 #undef GEN_STUXF
10428 #undef GEN_STXF
10429 #undef GEN_STFS
10430 #define GEN_STF(name, stop, opc, type) \
10431 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10432 #define GEN_STUF(name, stop, opc, type) \
10433 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10434 #define GEN_STUXF(name, stop, opc, type) \
10435 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10436 #define GEN_STXF(name, stop, opc2, opc3, type) \
10437 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10438 #define GEN_STFS(name, stop, op, type) \
10439 GEN_STF(name, stop, op | 0x20, type) \
10440 GEN_STUF(name, stop, op | 0x21, type) \
10441 GEN_STUXF(name, stop, op | 0x01, type) \
10442 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10443
10444 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10445 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10446 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10447 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10448 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10449
10450 #undef GEN_CRLOGIC
10451 #define GEN_CRLOGIC(name, tcg_op, opc) \
10452 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10453 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10454 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10455 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10456 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10457 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10458 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10459 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10460 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10461
10462 #undef GEN_MAC_HANDLER
10463 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10464 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10465 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10466 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10467 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10468 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10469 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10470 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10471 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10472 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10473 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10474 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10475 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10476 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10477 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10478 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10479 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10480 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10481 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10482 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10483 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10484 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10485 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10486 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10487 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10488 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10489 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10490 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10491 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10492 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10493 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10494 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10495 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10496 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10497 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10498 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10499 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10500 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10501 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10502 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10503 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10504 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10505 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10506 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10507
10508 #undef GEN_VR_LDX
10509 #undef GEN_VR_STX
10510 #undef GEN_VR_LVE
10511 #undef GEN_VR_STVE
10512 #define GEN_VR_LDX(name, opc2, opc3) \
10513 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10514 #define GEN_VR_STX(name, opc2, opc3) \
10515 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10516 #define GEN_VR_LVE(name, opc2, opc3) \
10517 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10518 #define GEN_VR_STVE(name, opc2, opc3) \
10519 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10520 GEN_VR_LDX(lvx, 0x07, 0x03),
10521 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10522 GEN_VR_LVE(bx, 0x07, 0x00),
10523 GEN_VR_LVE(hx, 0x07, 0x01),
10524 GEN_VR_LVE(wx, 0x07, 0x02),
10525 GEN_VR_STX(svx, 0x07, 0x07),
10526 GEN_VR_STX(svxl, 0x07, 0x0F),
10527 GEN_VR_STVE(bx, 0x07, 0x04),
10528 GEN_VR_STVE(hx, 0x07, 0x05),
10529 GEN_VR_STVE(wx, 0x07, 0x06),
10530
10531 #undef GEN_VX_LOGICAL
10532 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10533 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10534
10535 #undef GEN_VX_LOGICAL_207
10536 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10537 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10538
10539 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10540 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10541 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10542 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10543 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10544 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10545 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10546 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10547
10548 #undef GEN_VXFORM
10549 #define GEN_VXFORM(name, opc2, opc3) \
10550 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10551
10552 #undef GEN_VXFORM_207
10553 #define GEN_VXFORM_207(name, opc2, opc3) \
10554 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10555
10556 #undef GEN_VXFORM_DUAL
10557 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10558 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10559
10560 #undef GEN_VXRFORM_DUAL
10561 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10562 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10563 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10564
10565 GEN_VXFORM(vaddubm, 0, 0),
10566 GEN_VXFORM(vadduhm, 0, 1),
10567 GEN_VXFORM(vadduwm, 0, 2),
10568 GEN_VXFORM_207(vaddudm, 0, 3),
10569 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10570 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10571 GEN_VXFORM(vsubuwm, 0, 18),
10572 GEN_VXFORM_207(vsubudm, 0, 19),
10573 GEN_VXFORM(vmaxub, 1, 0),
10574 GEN_VXFORM(vmaxuh, 1, 1),
10575 GEN_VXFORM(vmaxuw, 1, 2),
10576 GEN_VXFORM_207(vmaxud, 1, 3),
10577 GEN_VXFORM(vmaxsb, 1, 4),
10578 GEN_VXFORM(vmaxsh, 1, 5),
10579 GEN_VXFORM(vmaxsw, 1, 6),
10580 GEN_VXFORM_207(vmaxsd, 1, 7),
10581 GEN_VXFORM(vminub, 1, 8),
10582 GEN_VXFORM(vminuh, 1, 9),
10583 GEN_VXFORM(vminuw, 1, 10),
10584 GEN_VXFORM_207(vminud, 1, 11),
10585 GEN_VXFORM(vminsb, 1, 12),
10586 GEN_VXFORM(vminsh, 1, 13),
10587 GEN_VXFORM(vminsw, 1, 14),
10588 GEN_VXFORM_207(vminsd, 1, 15),
10589 GEN_VXFORM(vavgub, 1, 16),
10590 GEN_VXFORM(vavguh, 1, 17),
10591 GEN_VXFORM(vavguw, 1, 18),
10592 GEN_VXFORM(vavgsb, 1, 20),
10593 GEN_VXFORM(vavgsh, 1, 21),
10594 GEN_VXFORM(vavgsw, 1, 22),
10595 GEN_VXFORM(vmrghb, 6, 0),
10596 GEN_VXFORM(vmrghh, 6, 1),
10597 GEN_VXFORM(vmrghw, 6, 2),
10598 GEN_VXFORM(vmrglb, 6, 4),
10599 GEN_VXFORM(vmrglh, 6, 5),
10600 GEN_VXFORM(vmrglw, 6, 6),
10601 GEN_VXFORM_207(vmrgew, 6, 30),
10602 GEN_VXFORM_207(vmrgow, 6, 26),
10603 GEN_VXFORM(vmuloub, 4, 0),
10604 GEN_VXFORM(vmulouh, 4, 1),
10605 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10606 GEN_VXFORM(vmulosb, 4, 4),
10607 GEN_VXFORM(vmulosh, 4, 5),
10608 GEN_VXFORM_207(vmulosw, 4, 6),
10609 GEN_VXFORM(vmuleub, 4, 8),
10610 GEN_VXFORM(vmuleuh, 4, 9),
10611 GEN_VXFORM_207(vmuleuw, 4, 10),
10612 GEN_VXFORM(vmulesb, 4, 12),
10613 GEN_VXFORM(vmulesh, 4, 13),
10614 GEN_VXFORM_207(vmulesw, 4, 14),
10615 GEN_VXFORM(vslb, 2, 4),
10616 GEN_VXFORM(vslh, 2, 5),
10617 GEN_VXFORM(vslw, 2, 6),
10618 GEN_VXFORM_207(vsld, 2, 23),
10619 GEN_VXFORM(vsrb, 2, 8),
10620 GEN_VXFORM(vsrh, 2, 9),
10621 GEN_VXFORM(vsrw, 2, 10),
10622 GEN_VXFORM_207(vsrd, 2, 27),
10623 GEN_VXFORM(vsrab, 2, 12),
10624 GEN_VXFORM(vsrah, 2, 13),
10625 GEN_VXFORM(vsraw, 2, 14),
10626 GEN_VXFORM_207(vsrad, 2, 15),
10627 GEN_VXFORM(vslo, 6, 16),
10628 GEN_VXFORM(vsro, 6, 17),
10629 GEN_VXFORM(vaddcuw, 0, 6),
10630 GEN_VXFORM(vsubcuw, 0, 22),
10631 GEN_VXFORM(vaddubs, 0, 8),
10632 GEN_VXFORM(vadduhs, 0, 9),
10633 GEN_VXFORM(vadduws, 0, 10),
10634 GEN_VXFORM(vaddsbs, 0, 12),
10635 GEN_VXFORM(vaddshs, 0, 13),
10636 GEN_VXFORM(vaddsws, 0, 14),
10637 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10638 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10639 GEN_VXFORM(vsubuws, 0, 26),
10640 GEN_VXFORM(vsubsbs, 0, 28),
10641 GEN_VXFORM(vsubshs, 0, 29),
10642 GEN_VXFORM(vsubsws, 0, 30),
10643 GEN_VXFORM_207(vadduqm, 0, 4),
10644 GEN_VXFORM_207(vaddcuq, 0, 5),
10645 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10646 GEN_VXFORM_207(vsubuqm, 0, 20),
10647 GEN_VXFORM_207(vsubcuq, 0, 21),
10648 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10649 GEN_VXFORM(vrlb, 2, 0),
10650 GEN_VXFORM(vrlh, 2, 1),
10651 GEN_VXFORM(vrlw, 2, 2),
10652 GEN_VXFORM_207(vrld, 2, 3),
10653 GEN_VXFORM(vsl, 2, 7),
10654 GEN_VXFORM(vsr, 2, 11),
10655 GEN_VXFORM(vpkuhum, 7, 0),
10656 GEN_VXFORM(vpkuwum, 7, 1),
10657 GEN_VXFORM_207(vpkudum, 7, 17),
10658 GEN_VXFORM(vpkuhus, 7, 2),
10659 GEN_VXFORM(vpkuwus, 7, 3),
10660 GEN_VXFORM_207(vpkudus, 7, 19),
10661 GEN_VXFORM(vpkshus, 7, 4),
10662 GEN_VXFORM(vpkswus, 7, 5),
10663 GEN_VXFORM_207(vpksdus, 7, 21),
10664 GEN_VXFORM(vpkshss, 7, 6),
10665 GEN_VXFORM(vpkswss, 7, 7),
10666 GEN_VXFORM_207(vpksdss, 7, 23),
10667 GEN_VXFORM(vpkpx, 7, 12),
10668 GEN_VXFORM(vsum4ubs, 4, 24),
10669 GEN_VXFORM(vsum4sbs, 4, 28),
10670 GEN_VXFORM(vsum4shs, 4, 25),
10671 GEN_VXFORM(vsum2sws, 4, 26),
10672 GEN_VXFORM(vsumsws, 4, 30),
10673 GEN_VXFORM(vaddfp, 5, 0),
10674 GEN_VXFORM(vsubfp, 5, 1),
10675 GEN_VXFORM(vmaxfp, 5, 16),
10676 GEN_VXFORM(vminfp, 5, 17),
10677
10678 #undef GEN_VXRFORM1
10679 #undef GEN_VXRFORM
10680 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10681 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10682 #define GEN_VXRFORM(name, opc2, opc3) \
10683 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10684 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10685 GEN_VXRFORM(vcmpequb, 3, 0)
10686 GEN_VXRFORM(vcmpequh, 3, 1)
10687 GEN_VXRFORM(vcmpequw, 3, 2)
10688 GEN_VXRFORM(vcmpgtsb, 3, 12)
10689 GEN_VXRFORM(vcmpgtsh, 3, 13)
10690 GEN_VXRFORM(vcmpgtsw, 3, 14)
10691 GEN_VXRFORM(vcmpgtub, 3, 8)
10692 GEN_VXRFORM(vcmpgtuh, 3, 9)
10693 GEN_VXRFORM(vcmpgtuw, 3, 10)
10694 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10695 GEN_VXRFORM(vcmpgefp, 3, 7)
10696 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10697 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10698
10699 #undef GEN_VXFORM_SIMM
10700 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10701 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10702 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10703 GEN_VXFORM_SIMM(vspltish, 6, 13),
10704 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10705
10706 #undef GEN_VXFORM_NOA
10707 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10708 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10709 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10710 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10711 GEN_VXFORM_207(vupkhsw, 7, 25),
10712 GEN_VXFORM_NOA(vupklsb, 7, 10),
10713 GEN_VXFORM_NOA(vupklsh, 7, 11),
10714 GEN_VXFORM_207(vupklsw, 7, 27),
10715 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10716 GEN_VXFORM_NOA(vupklpx, 7, 15),
10717 GEN_VXFORM_NOA(vrefp, 5, 4),
10718 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10719 GEN_VXFORM_NOA(vexptefp, 5, 6),
10720 GEN_VXFORM_NOA(vlogefp, 5, 7),
10721 GEN_VXFORM_NOA(vrfim, 5, 11),
10722 GEN_VXFORM_NOA(vrfin, 5, 8),
10723 GEN_VXFORM_NOA(vrfip, 5, 10),
10724 GEN_VXFORM_NOA(vrfiz, 5, 9),
10725
10726 #undef GEN_VXFORM_UIMM
10727 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10728 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10729 GEN_VXFORM_UIMM(vspltb, 6, 8),
10730 GEN_VXFORM_UIMM(vsplth, 6, 9),
10731 GEN_VXFORM_UIMM(vspltw, 6, 10),
10732 GEN_VXFORM_UIMM(vcfux, 5, 12),
10733 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10734 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10735 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10736
10737 #undef GEN_VAFORM_PAIRED
10738 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10739 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10740 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10741 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10742 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10743 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10744 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10745 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10746
10747 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10748 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10749 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10750 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10751
10752 GEN_VXFORM_207(vbpermq, 6, 21),
10753 GEN_VXFORM_207(vgbbd, 6, 20),
10754 GEN_VXFORM_207(vpmsumb, 4, 16),
10755 GEN_VXFORM_207(vpmsumh, 4, 17),
10756 GEN_VXFORM_207(vpmsumw, 4, 18),
10757 GEN_VXFORM_207(vpmsumd, 4, 19),
10758
10759 GEN_VXFORM_207(vsbox, 4, 23),
10760
10761 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10762 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10763
10764 GEN_VXFORM_207(vshasigmaw, 1, 26),
10765 GEN_VXFORM_207(vshasigmad, 1, 27),
10766
10767 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10768
10769 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10770 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10771 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10772 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10773 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10774 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10775 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10776
10777 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10778 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10779 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10780 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10781 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10782
10783 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10784 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10785 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10786 #if defined(TARGET_PPC64)
10787 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10788 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10789 #endif
10790
10791 #undef GEN_XX2FORM
10792 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10793 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10794 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10795
10796 #undef GEN_XX3FORM
10797 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10798 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10799 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10800 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10801 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10802
10803 #undef GEN_XX2IFORM
10804 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10805 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10806 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10807 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10808 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10809
10810 #undef GEN_XX3_RC_FORM
10811 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10812 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10813 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10814 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10815 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10816 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10817 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10818 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10819 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10820
10821 #undef GEN_XX3FORM_DM
10822 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10823 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10824 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10825 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10826 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10827 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10828 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10829 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10830 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10831 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10832 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10833 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10834 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10835 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10836 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10837 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10838 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10839
10840 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10841 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10842 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10843 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10844
10845 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10846 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10847 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10848 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10849 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10850 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10851 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10852 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10853
10854 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10855 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10856 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10857 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10858 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10859 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10860 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10861 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10862 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10863 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10864 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10865 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10866 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10867 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10868 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10869 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10870 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10871 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10872 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10873 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10874 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10875 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10876 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10877 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10878 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10879 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10880 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10881 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10882 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10883 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10884 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10885 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10886 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10887 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10888 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10889 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10890
10891 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10892 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10893 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10894 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10895 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10896 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10897 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10898 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10899 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10900 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10901 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10902 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10903 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10904 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10905 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10906 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10907 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10908 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10909
10910 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10911 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10912 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10913 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10914 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10915 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10916 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10917 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10918 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10919 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10920 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10921 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10922 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10923 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10924 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10925 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10926 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10927 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10928 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10929 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10930 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10931 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10932 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10933 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10934 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10935 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10936 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10937 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10938 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10939 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10940 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10941 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10942 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10943 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10944 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10945 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10946
10947 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10948 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10949 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10950 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10951 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10952 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10953 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10954 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10955 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10956 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10957 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10958 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10959 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10960 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10961 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10962 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10963 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10964 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10965 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10966 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10967 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10968 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10969 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10970 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10971 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10972 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10973 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10974 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10975 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10976 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10977 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10978 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10979 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10980 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10981 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10982 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10983
10984 #undef VSX_LOGICAL
10985 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10986 GEN_XX3FORM(name, opc2, opc3, fl2)
10987
10988 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10989 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10990 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10991 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10992 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10993 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10994 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10995 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10996 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10997 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10998 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10999 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
11000
11001 #define GEN_XXSEL_ROW(opc3) \
11002 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
11003 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
11004 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
11005 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
11006 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
11007 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
11008 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
11009 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
11010
11011 GEN_XXSEL_ROW(0x00)
11012 GEN_XXSEL_ROW(0x01)
11013 GEN_XXSEL_ROW(0x02)
11014 GEN_XXSEL_ROW(0x03)
11015 GEN_XXSEL_ROW(0x04)
11016 GEN_XXSEL_ROW(0x05)
11017 GEN_XXSEL_ROW(0x06)
11018 GEN_XXSEL_ROW(0x07)
11019 GEN_XXSEL_ROW(0x08)
11020 GEN_XXSEL_ROW(0x09)
11021 GEN_XXSEL_ROW(0x0A)
11022 GEN_XXSEL_ROW(0x0B)
11023 GEN_XXSEL_ROW(0x0C)
11024 GEN_XXSEL_ROW(0x0D)
11025 GEN_XXSEL_ROW(0x0E)
11026 GEN_XXSEL_ROW(0x0F)
11027 GEN_XXSEL_ROW(0x10)
11028 GEN_XXSEL_ROW(0x11)
11029 GEN_XXSEL_ROW(0x12)
11030 GEN_XXSEL_ROW(0x13)
11031 GEN_XXSEL_ROW(0x14)
11032 GEN_XXSEL_ROW(0x15)
11033 GEN_XXSEL_ROW(0x16)
11034 GEN_XXSEL_ROW(0x17)
11035 GEN_XXSEL_ROW(0x18)
11036 GEN_XXSEL_ROW(0x19)
11037 GEN_XXSEL_ROW(0x1A)
11038 GEN_XXSEL_ROW(0x1B)
11039 GEN_XXSEL_ROW(0x1C)
11040 GEN_XXSEL_ROW(0x1D)
11041 GEN_XXSEL_ROW(0x1E)
11042 GEN_XXSEL_ROW(0x1F)
11043
11044 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11045
11046 #undef GEN_DFP_T_A_B_Rc
11047 #undef GEN_DFP_BF_A_B
11048 #undef GEN_DFP_BF_A_DCM
11049 #undef GEN_DFP_T_B_U32_U32_Rc
11050 #undef GEN_DFP_T_A_B_I32_Rc
11051 #undef GEN_DFP_T_B_Rc
11052 #undef GEN_DFP_T_FPR_I32_Rc
11053
11054 #define _GEN_DFP_LONG(name, op1, op2, mask) \
11055 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11056
11057 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11058 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11059 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11060
11061 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11062 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11063 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11064 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11065 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11066
11067 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11068 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11069
11070 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11071 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11072 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11073
11074 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11075 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11076 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11077 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11078 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11079
11080 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11081 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11082
11083 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11084 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11085
11086 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11087 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11088
11089 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11090 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11091
11092 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11093 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11094
11095 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11096 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11097
11098 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11099 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11100
11101 #define GEN_DFP_BF_A_B(name, op1, op2) \
11102 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11103
11104 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11105 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11106
11107 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11108 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11109
11110 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11111 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11112
11113 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11114 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11115
11116 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11117 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11118
11119 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11120 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11121
11122 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11123 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11124
11125 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11126 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11127
11128 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11129 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11130
11131 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11132 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11133
11134 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11135 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11136
11137 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11138 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11139
11140 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11141 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11142
11143 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11144 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11145
11146 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11147 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11148
11149 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11150 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11151
11152 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11153 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11154
11155 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11156 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11157 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11158 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11159 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11160 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11161 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11162 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11163 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11164 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11165 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11166 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11167 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11168 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11169 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11170 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11171 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11172 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11173 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11174 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11175 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11176 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11177 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11178 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11179 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11180 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11181 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11182 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11183 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11184 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11185 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11186 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11187 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11188 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11189 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11190 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11191 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11192 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11193 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11194 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11195 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11196 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11197 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11198 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11199 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11200 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11201 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11202 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11203 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11204 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11205
11206 #undef GEN_SPE
11207 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11208 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11209 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11210 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11211 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11212 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11213 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11214 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11215 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11216 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11217 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11218 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11219 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11220 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11221 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11222 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11223 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11224 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11225 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11226 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11227 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11228 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11229 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11230 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11231 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11232 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11233 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11234 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11235 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11236 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11237 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11238
11239 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11240 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11241 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11242 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11243 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11244 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11245 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11246 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11247 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11248 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11249 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11250 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11251 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11252 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11253
11254 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11255 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11256 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11257 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11258 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11259 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11260 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11261 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11262 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11263 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11264 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11265 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11266 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11267 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11268
11269 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11270 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11271 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11272 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11273 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11274 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11275 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11276 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11277 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11278 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11279 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11280 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11281 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11282 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11283 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11284 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11285
11286 #undef GEN_SPEOP_LDST
11287 #define GEN_SPEOP_LDST(name, opc2, sh) \
11288 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11289 GEN_SPEOP_LDST(evldd, 0x00, 3),
11290 GEN_SPEOP_LDST(evldw, 0x01, 3),
11291 GEN_SPEOP_LDST(evldh, 0x02, 3),
11292 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11293 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11294 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11295 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11296 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11297 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11298 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11299 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11300
11301 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11302 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11303 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11304 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11305 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11306 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11307 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11308
11309 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11310 PPC_NONE, PPC2_TM),
11311 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11312 PPC_NONE, PPC2_TM),
11313 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11314 PPC_NONE, PPC2_TM),
11315 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11316 PPC_NONE, PPC2_TM),
11317 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11318 PPC_NONE, PPC2_TM),
11319 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11320 PPC_NONE, PPC2_TM),
11321 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11322 PPC_NONE, PPC2_TM),
11323 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11324 PPC_NONE, PPC2_TM),
11325 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11326 PPC_NONE, PPC2_TM),
11327 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11328 PPC_NONE, PPC2_TM),
11329 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11330 PPC_NONE, PPC2_TM),
11331 };
11332
11333 #include "helper_regs.h"
11334 #include "translate_init.c"
11335
11336 /*****************************************************************************/
11337 /* Misc PowerPC helpers */
11338 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11339 int flags)
11340 {
11341 #define RGPL 4
11342 #define RFPL 4
11343
11344 PowerPCCPU *cpu = POWERPC_CPU(cs);
11345 CPUPPCState *env = &cpu->env;
11346 int i;
11347
11348 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11349 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11350 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11351 cs->cpu_index);
11352 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11353 TARGET_FMT_lx " iidx %d didx %d\n",
11354 env->msr, env->spr[SPR_HID0],
11355 env->hflags, env->immu_idx, env->dmmu_idx);
11356 #if !defined(NO_TIMER_DUMP)
11357 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11358 #if !defined(CONFIG_USER_ONLY)
11359 " DECR %08" PRIu32
11360 #endif
11361 "\n",
11362 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11363 #if !defined(CONFIG_USER_ONLY)
11364 , cpu_ppc_load_decr(env)
11365 #endif
11366 );
11367 #endif
11368 for (i = 0; i < 32; i++) {
11369 if ((i & (RGPL - 1)) == 0)
11370 cpu_fprintf(f, "GPR%02d", i);
11371 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11372 if ((i & (RGPL - 1)) == (RGPL - 1))
11373 cpu_fprintf(f, "\n");
11374 }
11375 cpu_fprintf(f, "CR ");
11376 for (i = 0; i < 8; i++)
11377 cpu_fprintf(f, "%01x", env->crf[i]);
11378 cpu_fprintf(f, " [");
11379 for (i = 0; i < 8; i++) {
11380 char a = '-';
11381 if (env->crf[i] & 0x08)
11382 a = 'L';
11383 else if (env->crf[i] & 0x04)
11384 a = 'G';
11385 else if (env->crf[i] & 0x02)
11386 a = 'E';
11387 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11388 }
11389 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11390 env->reserve_addr);
11391 for (i = 0; i < 32; i++) {
11392 if ((i & (RFPL - 1)) == 0)
11393 cpu_fprintf(f, "FPR%02d", i);
11394 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11395 if ((i & (RFPL - 1)) == (RFPL - 1))
11396 cpu_fprintf(f, "\n");
11397 }
11398 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11399 #if !defined(CONFIG_USER_ONLY)
11400 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11401 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11402 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11403 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11404
11405 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11406 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11407 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11408 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11409
11410 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11411 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11412 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11413 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11414
11415 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11416 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11417 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11418 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11419 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11420
11421 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11422 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11423 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11424 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11425
11426 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11427 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11428 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11429 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11430
11431 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11432 " EPR " TARGET_FMT_lx "\n",
11433 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11434 env->spr[SPR_BOOKE_EPR]);
11435
11436 /* FSL-specific */
11437 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11438 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11439 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11440 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11441
11442 /*
11443 * IVORs are left out as they are large and do not change often --
11444 * they can be read with "p $ivor0", "p $ivor1", etc.
11445 */
11446 }
11447
11448 #if defined(TARGET_PPC64)
11449 if (env->flags & POWERPC_FLAG_CFAR) {
11450 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11451 }
11452 #endif
11453
11454 switch (env->mmu_model) {
11455 case POWERPC_MMU_32B:
11456 case POWERPC_MMU_601:
11457 case POWERPC_MMU_SOFT_6xx:
11458 case POWERPC_MMU_SOFT_74xx:
11459 #if defined(TARGET_PPC64)
11460 case POWERPC_MMU_64B:
11461 case POWERPC_MMU_2_03:
11462 case POWERPC_MMU_2_06:
11463 case POWERPC_MMU_2_06a:
11464 case POWERPC_MMU_2_07:
11465 case POWERPC_MMU_2_07a:
11466 #endif
11467 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11468 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11469 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11470 break;
11471 case POWERPC_MMU_BOOKE206:
11472 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11473 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11474 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11475 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11476
11477 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11478 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11479 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11480 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11481
11482 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11483 " TLB1CFG " TARGET_FMT_lx "\n",
11484 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11485 env->spr[SPR_BOOKE_TLB1CFG]);
11486 break;
11487 default:
11488 break;
11489 }
11490 #endif
11491
11492 #undef RGPL
11493 #undef RFPL
11494 }
11495
11496 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11497 fprintf_function cpu_fprintf, int flags)
11498 {
11499 #if defined(DO_PPC_STATISTICS)
11500 PowerPCCPU *cpu = POWERPC_CPU(cs);
11501 opc_handler_t **t1, **t2, **t3, *handler;
11502 int op1, op2, op3;
11503
11504 t1 = cpu->env.opcodes;
11505 for (op1 = 0; op1 < 64; op1++) {
11506 handler = t1[op1];
11507 if (is_indirect_opcode(handler)) {
11508 t2 = ind_table(handler);
11509 for (op2 = 0; op2 < 32; op2++) {
11510 handler = t2[op2];
11511 if (is_indirect_opcode(handler)) {
11512 t3 = ind_table(handler);
11513 for (op3 = 0; op3 < 32; op3++) {
11514 handler = t3[op3];
11515 if (handler->count == 0)
11516 continue;
11517 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11518 "%016" PRIx64 " %" PRId64 "\n",
11519 op1, op2, op3, op1, (op3 << 5) | op2,
11520 handler->oname,
11521 handler->count, handler->count);
11522 }
11523 } else {
11524 if (handler->count == 0)
11525 continue;
11526 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11527 "%016" PRIx64 " %" PRId64 "\n",
11528 op1, op2, op1, op2, handler->oname,
11529 handler->count, handler->count);
11530 }
11531 }
11532 } else {
11533 if (handler->count == 0)
11534 continue;
11535 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11536 " %" PRId64 "\n",
11537 op1, op1, handler->oname,
11538 handler->count, handler->count);
11539 }
11540 }
11541 #endif
11542 }
11543
11544 /*****************************************************************************/
11545 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11546 {
11547 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11548 CPUState *cs = CPU(cpu);
11549 DisasContext ctx, *ctxp = &ctx;
11550 opc_handler_t **table, *handler;
11551 target_ulong pc_start;
11552 int num_insns;
11553 int max_insns;
11554
11555 pc_start = tb->pc;
11556 ctx.nip = pc_start;
11557 ctx.tb = tb;
11558 ctx.exception = POWERPC_EXCP_NONE;
11559 ctx.spr_cb = env->spr_cb;
11560 ctx.pr = msr_pr;
11561 ctx.mem_idx = env->dmmu_idx;
11562 #if !defined(CONFIG_USER_ONLY)
11563 ctx.hv = msr_hv || !env->has_hv_mode;
11564 #endif
11565 ctx.insns_flags = env->insns_flags;
11566 ctx.insns_flags2 = env->insns_flags2;
11567 ctx.access_type = -1;
11568 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11569 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11570 #if defined(TARGET_PPC64)
11571 ctx.sf_mode = msr_is_64bit(env, env->msr);
11572 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11573 #endif
11574 if (env->mmu_model == POWERPC_MMU_32B ||
11575 env->mmu_model == POWERPC_MMU_601 ||
11576 (env->mmu_model & POWERPC_MMU_64B))
11577 ctx.lazy_tlb_flush = true;
11578
11579 ctx.fpu_enabled = msr_fp;
11580 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11581 ctx.spe_enabled = msr_spe;
11582 else
11583 ctx.spe_enabled = 0;
11584 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11585 ctx.altivec_enabled = msr_vr;
11586 else
11587 ctx.altivec_enabled = 0;
11588 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11589 ctx.vsx_enabled = msr_vsx;
11590 } else {
11591 ctx.vsx_enabled = 0;
11592 }
11593 #if defined(TARGET_PPC64)
11594 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11595 ctx.tm_enabled = msr_tm;
11596 } else {
11597 ctx.tm_enabled = 0;
11598 }
11599 #endif
11600 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11601 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11602 else
11603 ctx.singlestep_enabled = 0;
11604 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11605 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11606 if (unlikely(cs->singlestep_enabled)) {
11607 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11608 }
11609 #if defined (DO_SINGLE_STEP) && 0
11610 /* Single step trace mode */
11611 msr_se = 1;
11612 #endif
11613 num_insns = 0;
11614 max_insns = tb->cflags & CF_COUNT_MASK;
11615 if (max_insns == 0) {
11616 max_insns = CF_COUNT_MASK;
11617 }
11618 if (max_insns > TCG_MAX_INSNS) {
11619 max_insns = TCG_MAX_INSNS;
11620 }
11621
11622 gen_tb_start(tb);
11623 tcg_clear_temp_count();
11624 /* Set env in case of segfault during code fetch */
11625 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11626 tcg_gen_insn_start(ctx.nip);
11627 num_insns++;
11628
11629 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11630 gen_debug_exception(ctxp);
11631 /* The address covered by the breakpoint must be included in
11632 [tb->pc, tb->pc + tb->size) in order to for it to be
11633 properly cleared -- thus we increment the PC here so that
11634 the logic setting tb->size below does the right thing. */
11635 ctx.nip += 4;
11636 break;
11637 }
11638
11639 LOG_DISAS("----------------\n");
11640 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11641 ctx.nip, ctx.mem_idx, (int)msr_ir);
11642 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11643 gen_io_start();
11644 if (unlikely(need_byteswap(&ctx))) {
11645 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11646 } else {
11647 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11648 }
11649 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11650 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11651 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11652 ctx.nip += 4;
11653 table = env->opcodes;
11654 handler = table[opc1(ctx.opcode)];
11655 if (is_indirect_opcode(handler)) {
11656 table = ind_table(handler);
11657 handler = table[opc2(ctx.opcode)];
11658 if (is_indirect_opcode(handler)) {
11659 table = ind_table(handler);
11660 handler = table[opc3(ctx.opcode)];
11661 }
11662 }
11663 /* Is opcode *REALLY* valid ? */
11664 if (unlikely(handler->handler == &gen_invalid)) {
11665 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11666 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11667 opc1(ctx.opcode), opc2(ctx.opcode),
11668 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11669 } else {
11670 uint32_t inval;
11671
11672 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11673 inval = handler->inval2;
11674 } else {
11675 inval = handler->inval1;
11676 }
11677
11678 if (unlikely((ctx.opcode & inval) != 0)) {
11679 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11680 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11681 ctx.opcode & inval, opc1(ctx.opcode),
11682 opc2(ctx.opcode), opc3(ctx.opcode),
11683 ctx.opcode, ctx.nip - 4);
11684 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11685 break;
11686 }
11687 }
11688 (*(handler->handler))(&ctx);
11689 #if defined(DO_PPC_STATISTICS)
11690 handler->count++;
11691 #endif
11692 /* Check trace mode exceptions */
11693 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11694 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11695 ctx.exception != POWERPC_SYSCALL &&
11696 ctx.exception != POWERPC_EXCP_TRAP &&
11697 ctx.exception != POWERPC_EXCP_BRANCH)) {
11698 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11699 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11700 (cs->singlestep_enabled) ||
11701 singlestep ||
11702 num_insns >= max_insns)) {
11703 /* if we reach a page boundary or are single stepping, stop
11704 * generation
11705 */
11706 break;
11707 }
11708 if (tcg_check_temp_count()) {
11709 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11710 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11711 ctx.opcode);
11712 exit(1);
11713 }
11714 }
11715 if (tb->cflags & CF_LAST_IO)
11716 gen_io_end();
11717 if (ctx.exception == POWERPC_EXCP_NONE) {
11718 gen_goto_tb(&ctx, 0, ctx.nip);
11719 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11720 if (unlikely(cs->singlestep_enabled)) {
11721 gen_debug_exception(ctxp);
11722 }
11723 /* Generate the return instruction */
11724 tcg_gen_exit_tb(0);
11725 }
11726 gen_tb_end(tb, num_insns);
11727
11728 tb->size = ctx.nip - pc_start;
11729 tb->icount = num_insns;
11730
11731 #if defined(DEBUG_DISAS)
11732 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11733 && qemu_log_in_addr_range(pc_start)) {
11734 int flags;
11735 flags = env->bfd_mach;
11736 flags |= ctx.le_mode << 16;
11737 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11738 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11739 qemu_log("\n");
11740 }
11741 #endif
11742 }
11743
11744 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11745 target_ulong *data)
11746 {
11747 env->nip = data[0];
11748 }
QEmu