2 * QEMU Sparc Sun4c interrupt controller emulation
4 * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 //#define DEBUG_IRQ_COUNT
34 #define DPRINTF(fmt, ...) \
35 do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...)
41 * Registers of interrupt controller in sun4c.
47 typedef struct Sun4c_INTCTLState
{
49 #ifdef DEBUG_IRQ_COUNT
52 qemu_irq cpu_irqs
[MAX_PILS
];
53 const uint32_t *intbit_to_level
;
61 static void sun4c_check_interrupts(void *opaque
);
63 static uint32_t sun4c_intctl_mem_readb(void *opaque
, target_phys_addr_t addr
)
65 Sun4c_INTCTLState
*s
= opaque
;
69 DPRINTF("read reg 0x" TARGET_FMT_plx
" = %x\n", addr
, ret
);
74 static void sun4c_intctl_mem_writeb(void *opaque
, target_phys_addr_t addr
,
77 Sun4c_INTCTLState
*s
= opaque
;
79 DPRINTF("write reg 0x" TARGET_FMT_plx
" = %x\n", addr
, val
);
82 sun4c_check_interrupts(s
);
85 static CPUReadMemoryFunc
*sun4c_intctl_mem_read
[3] = {
86 sun4c_intctl_mem_readb
,
91 static CPUWriteMemoryFunc
*sun4c_intctl_mem_write
[3] = {
92 sun4c_intctl_mem_writeb
,
97 void sun4c_pic_info(Monitor
*mon
, void *opaque
)
99 Sun4c_INTCTLState
*s
= opaque
;
101 monitor_printf(mon
, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
105 void sun4c_irq_info(Monitor
*mon
, void *opaque
)
107 #ifndef DEBUG_IRQ_COUNT
108 monitor_printf(mon
, "irq statistic code not compiled.\n");
110 Sun4c_INTCTLState
*s
= opaque
;
113 monitor_printf(mon
, "IRQ statistics:\n");
114 count
= s
->irq_count
;
116 monitor_printf(mon
, " %" PRId64
"\n", count
);
120 static const uint32_t intbit_to_level
[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
122 static void sun4c_check_interrupts(void *opaque
)
124 Sun4c_INTCTLState
*s
= opaque
;
125 uint32_t pil_pending
;
129 if (s
->pending
&& !(s
->reg
& 0x80000000)) {
130 for (i
= 0; i
< 8; i
++) {
131 if (s
->pending
& (1 << i
))
132 pil_pending
|= 1 << intbit_to_level
[i
];
136 for (i
= 0; i
< MAX_PILS
; i
++) {
137 if (pil_pending
& (1 << i
)) {
138 if (!(s
->pil_out
& (1 << i
)))
139 qemu_irq_raise(s
->cpu_irqs
[i
]);
141 if (s
->pil_out
& (1 << i
))
142 qemu_irq_lower(s
->cpu_irqs
[i
]);
145 s
->pil_out
= pil_pending
;
149 * "irq" here is the bit number in the system interrupt register
151 static void sun4c_set_irq(void *opaque
, int irq
, int level
)
153 Sun4c_INTCTLState
*s
= opaque
;
154 uint32_t mask
= 1 << irq
;
155 uint32_t pil
= intbit_to_level
[irq
];
157 DPRINTF("Set irq %d -> pil %d level %d\n", irq
, pil
,
161 #ifdef DEBUG_IRQ_COUNT
168 sun4c_check_interrupts(s
);
172 static void sun4c_intctl_save(QEMUFile
*f
, void *opaque
)
174 Sun4c_INTCTLState
*s
= opaque
;
176 qemu_put_8s(f
, &s
->reg
);
177 qemu_put_8s(f
, &s
->pending
);
180 static int sun4c_intctl_load(QEMUFile
*f
, void *opaque
, int version_id
)
182 Sun4c_INTCTLState
*s
= opaque
;
187 qemu_get_8s(f
, &s
->reg
);
188 qemu_get_8s(f
, &s
->pending
);
193 static void sun4c_intctl_reset(void *opaque
)
195 Sun4c_INTCTLState
*s
= opaque
;
201 DeviceState
*sun4c_intctl_init(target_phys_addr_t addr
, qemu_irq
*parent_irq
)
207 dev
= qdev_create(NULL
, "sun4c_intctl");
210 s
= sysbus_from_qdev(dev
);
212 for (i
= 0; i
< MAX_PILS
; i
++) {
213 sysbus_connect_irq(s
, i
, parent_irq
[i
]);
215 sysbus_mmio_map(s
, 0, addr
);
220 static void sun4c_intctl_init1(SysBusDevice
*dev
)
222 Sun4c_INTCTLState
*s
= FROM_SYSBUS(Sun4c_INTCTLState
, dev
);
226 io_memory
= cpu_register_io_memory(sun4c_intctl_mem_read
,
227 sun4c_intctl_mem_write
, s
);
228 sysbus_init_mmio(dev
, INTCTL_SIZE
, io_memory
);
229 qdev_init_gpio_in(&dev
->qdev
, sun4c_set_irq
, 8);
231 for (i
= 0; i
< MAX_PILS
; i
++) {
232 sysbus_init_irq(dev
, &s
->cpu_irqs
[i
]);
234 register_savevm("sun4c_intctl", -1, 1, sun4c_intctl_save
,
235 sun4c_intctl_load
, s
);
236 qemu_register_reset(sun4c_intctl_reset
, s
);
237 sun4c_intctl_reset(s
);
240 static SysBusDeviceInfo sun4c_intctl_info
= {
241 .init
= sun4c_intctl_init1
,
242 .qdev
.name
= "sun4c_intctl",
243 .qdev
.size
= sizeof(Sun4c_INTCTLState
),
246 static void sun4c_intctl_register_devices(void)
248 sysbus_register_withprop(&sun4c_intctl_info
);
251 device_init(sun4c_intctl_register_devices
)