4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40 #define PREFIX_VEX 0x20
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
60 //#define MACRO_TEST 1
62 /* global register indexes */
63 static TCGv_ptr cpu_env
;
65 static TCGv cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
, cpu_cc_srcT
;
66 static TCGv_i32 cpu_cc_op
;
67 static TCGv cpu_regs
[CPU_NB_REGS
];
70 /* local register indexes (only used inside old micro ops) */
71 static TCGv cpu_tmp0
, cpu_tmp4
;
72 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
73 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
74 static TCGv_i64 cpu_tmp1_i64
;
76 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
78 #include "exec/gen-icount.h"
81 static int x86_64_hregs
;
84 typedef struct DisasContext
{
85 /* current insn context */
86 int override
; /* -1 if no override */
90 target_ulong pc
; /* pc = eip + cs_base */
91 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
92 static state change (stop translation) */
93 /* current block context */
94 target_ulong cs_base
; /* base of CS segment */
95 int pe
; /* protected mode */
96 int code32
; /* 32 bit code segment */
98 int lma
; /* long mode active */
99 int code64
; /* 64 bit code segment */
102 int vex_l
; /* vex vector length */
103 int vex_v
; /* vex vvvv register, without 1's compliment. */
104 int ss32
; /* 32 bit stack segment */
105 CCOp cc_op
; /* current CC operation */
107 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
108 int f_st
; /* currently unused */
109 int vm86
; /* vm86 mode */
112 int tf
; /* TF cpu flag */
113 int singlestep_enabled
; /* "hardware" single step enabled */
114 int jmp_opt
; /* use direct block chaining for direct jumps */
115 int mem_index
; /* select memory access functions */
116 uint64_t flags
; /* all execution flags */
117 struct TranslationBlock
*tb
;
118 int popl_esp_hack
; /* for correct popl with esp base handling */
119 int rip_offset
; /* only used in x86_64, but left for simplicity */
121 int cpuid_ext_features
;
122 int cpuid_ext2_features
;
123 int cpuid_ext3_features
;
124 int cpuid_7_0_ebx_features
;
127 static void gen_eob(DisasContext
*s
);
128 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
129 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
130 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
);
132 /* i386 arith/logic operations */
152 OP_SHL1
, /* undocumented */
168 /* I386 int registers */
169 OR_EAX
, /* MUST be even numbered */
178 OR_TMP0
= 16, /* temporary operand register */
180 OR_A0
, /* temporary register used when doing address evaluation */
190 /* Bit set if the global variable is live after setting CC_OP to X. */
191 static const uint8_t cc_op_live
[CC_OP_NB
] = {
192 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
193 [CC_OP_EFLAGS
] = USES_CC_SRC
,
194 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
196 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
197 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
198 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
199 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
200 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
202 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_BMILGB
... CC_OP_BMILGQ
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_ADCX
] = USES_CC_DST
| USES_CC_SRC
,
206 [CC_OP_ADOX
] = USES_CC_SRC
| USES_CC_SRC2
,
207 [CC_OP_ADCOX
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
211 static void set_cc_op(DisasContext
*s
, CCOp op
)
215 if (s
->cc_op
== op
) {
219 /* Discard CC computation that will no longer be used. */
220 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
221 if (dead
& USES_CC_DST
) {
222 tcg_gen_discard_tl(cpu_cc_dst
);
224 if (dead
& USES_CC_SRC
) {
225 tcg_gen_discard_tl(cpu_cc_src
);
227 if (dead
& USES_CC_SRC2
) {
228 tcg_gen_discard_tl(cpu_cc_src2
);
230 if (dead
& USES_CC_SRCT
) {
231 tcg_gen_discard_tl(cpu_cc_srcT
);
234 if (op
== CC_OP_DYNAMIC
) {
235 /* The DYNAMIC setting is translator only, and should never be
236 stored. Thus we always consider it clean. */
237 s
->cc_op_dirty
= false;
239 /* Discard any computed CC_OP value (see shifts). */
240 if (s
->cc_op
== CC_OP_DYNAMIC
) {
241 tcg_gen_discard_i32(cpu_cc_op
);
243 s
->cc_op_dirty
= true;
248 static void gen_update_cc_op(DisasContext
*s
)
250 if (s
->cc_op_dirty
) {
251 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
252 s
->cc_op_dirty
= false;
258 #define NB_OP_SIZES 4
260 #else /* !TARGET_X86_64 */
262 #define NB_OP_SIZES 3
264 #endif /* !TARGET_X86_64 */
266 #if defined(HOST_WORDS_BIGENDIAN)
267 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
268 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
269 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
270 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
271 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
273 #define REG_B_OFFSET 0
274 #define REG_H_OFFSET 1
275 #define REG_W_OFFSET 0
276 #define REG_L_OFFSET 0
277 #define REG_LH_OFFSET 4
280 /* In instruction encodings for byte register accesses the
281 * register number usually indicates "low 8 bits of register N";
282 * however there are some special cases where N 4..7 indicates
283 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
284 * true for this special case, false otherwise.
286 static inline bool byte_reg_is_xH(int reg
)
292 if (reg
>= 8 || x86_64_hregs
) {
299 /* Select the size of a push/pop operation. */
300 static inline TCGMemOp
mo_pushpop(DisasContext
*s
, TCGMemOp ot
)
303 return ot
== MO_16
? MO_16
: MO_64
;
309 /* Select only size 64 else 32. Used for SSE operand sizes. */
310 static inline TCGMemOp
mo_64_32(TCGMemOp ot
)
313 return ot
== MO_64
? MO_64
: MO_32
;
319 /* Select size 8 if lsb of B is clear, else OT. Used for decoding
320 byte vs word opcodes. */
321 static inline TCGMemOp
mo_b_d(int b
, TCGMemOp ot
)
323 return b
& 1 ? ot
: MO_8
;
326 /* Select size 8 if lsb of B is clear, else OT capped at 32.
327 Used for decoding operand size of port opcodes. */
328 static inline TCGMemOp
mo_b_d32(int b
, TCGMemOp ot
)
330 return b
& 1 ? (ot
== MO_16
? MO_16
: MO_32
) : MO_8
;
333 static void gen_op_mov_reg_v(TCGMemOp ot
, int reg
, TCGv t0
)
337 if (!byte_reg_is_xH(reg
)) {
338 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
340 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
344 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
347 /* For x86_64, this sets the higher half of register to zero.
348 For i386, this is equivalent to a mov. */
349 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
353 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
361 static inline void gen_op_mov_reg_T0(TCGMemOp ot
, int reg
)
363 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
366 static inline void gen_op_mov_reg_T1(TCGMemOp ot
, int reg
)
368 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
371 static inline void gen_op_mov_reg_A0(TCGMemOp size
, int reg
)
373 gen_op_mov_reg_v(size
, reg
, cpu_A0
);
376 static inline void gen_op_mov_v_reg(TCGMemOp ot
, TCGv t0
, int reg
)
378 if (ot
== MO_8
&& byte_reg_is_xH(reg
)) {
379 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
380 tcg_gen_ext8u_tl(t0
, t0
);
382 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
386 static inline void gen_op_mov_TN_reg(TCGMemOp ot
, int t_index
, int reg
)
388 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
391 static inline void gen_op_movl_A0_reg(int reg
)
393 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
396 static inline void gen_op_addl_A0_im(int32_t val
)
398 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
400 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
405 static inline void gen_op_addq_A0_im(int64_t val
)
407 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
411 static void gen_add_A0_im(DisasContext
*s
, int val
)
415 gen_op_addq_A0_im(val
);
418 gen_op_addl_A0_im(val
);
421 static inline void gen_op_addl_T0_T1(void)
423 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
426 static inline void gen_op_jmp_T0(void)
428 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
431 static inline void gen_op_add_reg_im(TCGMemOp size
, int reg
, int32_t val
)
433 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
434 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
437 static inline void gen_op_add_reg_T0(TCGMemOp size
, int reg
)
439 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
440 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
443 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
445 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
447 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
448 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
449 /* For x86_64, this sets the higher half of register to zero.
450 For i386, this is equivalent to a nop. */
451 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
454 static inline void gen_op_movl_A0_seg(int reg
)
456 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
459 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
461 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
464 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
465 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
467 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
468 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
471 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
476 static inline void gen_op_movq_A0_seg(int reg
)
478 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
481 static inline void gen_op_addq_A0_seg(int reg
)
483 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
484 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
487 static inline void gen_op_movq_A0_reg(int reg
)
489 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
492 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
494 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
496 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
497 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
501 static inline void gen_op_ld_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
503 tcg_gen_qemu_ld_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
506 static inline void gen_op_st_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
508 tcg_gen_qemu_st_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
511 static inline void gen_op_st_rm_T0_A0(DisasContext
*s
, int idx
, int d
)
514 gen_op_st_v(s
, idx
, cpu_T
[0], cpu_A0
);
516 gen_op_mov_reg_T0(idx
, d
);
520 static inline void gen_jmp_im(target_ulong pc
)
522 tcg_gen_movi_tl(cpu_tmp0
, pc
);
523 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
526 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
530 override
= s
->override
;
535 gen_op_movq_A0_seg(override
);
536 gen_op_addq_A0_reg_sN(0, R_ESI
);
538 gen_op_movq_A0_reg(R_ESI
);
544 if (s
->addseg
&& override
< 0)
547 gen_op_movl_A0_seg(override
);
548 gen_op_addl_A0_reg_sN(0, R_ESI
);
550 gen_op_movl_A0_reg(R_ESI
);
554 /* 16 address, always override */
557 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESI
]);
558 gen_op_addl_A0_seg(s
, override
);
565 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
570 gen_op_movq_A0_reg(R_EDI
);
575 gen_op_movl_A0_seg(R_ES
);
576 gen_op_addl_A0_reg_sN(0, R_EDI
);
578 gen_op_movl_A0_reg(R_EDI
);
582 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_EDI
]);
583 gen_op_addl_A0_seg(s
, R_ES
);
590 static inline void gen_op_movl_T0_Dshift(TCGMemOp ot
)
592 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
593 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
596 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, TCGMemOp size
, bool sign
)
601 tcg_gen_ext8s_tl(dst
, src
);
603 tcg_gen_ext8u_tl(dst
, src
);
608 tcg_gen_ext16s_tl(dst
, src
);
610 tcg_gen_ext16u_tl(dst
, src
);
616 tcg_gen_ext32s_tl(dst
, src
);
618 tcg_gen_ext32u_tl(dst
, src
);
627 static void gen_extu(TCGMemOp ot
, TCGv reg
)
629 gen_ext_tl(reg
, reg
, ot
, false);
632 static void gen_exts(TCGMemOp ot
, TCGv reg
)
634 gen_ext_tl(reg
, reg
, ot
, true);
637 static inline void gen_op_jnz_ecx(TCGMemOp size
, int label1
)
639 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
640 gen_extu(size
, cpu_tmp0
);
641 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
644 static inline void gen_op_jz_ecx(TCGMemOp size
, int label1
)
646 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
647 gen_extu(size
, cpu_tmp0
);
648 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
651 static void gen_helper_in_func(TCGMemOp ot
, TCGv v
, TCGv_i32 n
)
655 gen_helper_inb(v
, n
);
658 gen_helper_inw(v
, n
);
661 gen_helper_inl(v
, n
);
668 static void gen_helper_out_func(TCGMemOp ot
, TCGv_i32 v
, TCGv_i32 n
)
672 gen_helper_outb(v
, n
);
675 gen_helper_outw(v
, n
);
678 gen_helper_outl(v
, n
);
685 static void gen_check_io(DisasContext
*s
, TCGMemOp ot
, target_ulong cur_eip
,
689 target_ulong next_eip
;
692 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
696 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
699 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
702 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
705 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
711 if(s
->flags
& HF_SVMI_MASK
) {
716 svm_flags
|= (1 << (4 + ot
));
717 next_eip
= s
->pc
- s
->cs_base
;
718 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
719 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
720 tcg_const_i32(svm_flags
),
721 tcg_const_i32(next_eip
- cur_eip
));
725 static inline void gen_movs(DisasContext
*s
, TCGMemOp ot
)
727 gen_string_movl_A0_ESI(s
);
728 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
729 gen_string_movl_A0_EDI(s
);
730 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
731 gen_op_movl_T0_Dshift(ot
);
732 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
733 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
736 static void gen_op_update1_cc(void)
738 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
741 static void gen_op_update2_cc(void)
743 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
744 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
747 static void gen_op_update3_cc(TCGv reg
)
749 tcg_gen_mov_tl(cpu_cc_src2
, reg
);
750 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
751 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
754 static inline void gen_op_testl_T0_T1_cc(void)
756 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
759 static void gen_op_update_neg_cc(void)
761 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
762 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
763 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
766 /* compute all eflags to cc_src */
767 static void gen_compute_eflags(DisasContext
*s
)
769 TCGv zero
, dst
, src1
, src2
;
772 if (s
->cc_op
== CC_OP_EFLAGS
) {
775 if (s
->cc_op
== CC_OP_CLR
) {
776 tcg_gen_movi_tl(cpu_cc_src
, CC_Z
);
777 set_cc_op(s
, CC_OP_EFLAGS
);
786 /* Take care to not read values that are not live. */
787 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
788 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
);
790 zero
= tcg_const_tl(0);
791 if (dead
& USES_CC_DST
) {
794 if (dead
& USES_CC_SRC
) {
797 if (dead
& USES_CC_SRC2
) {
803 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, src2
, cpu_cc_op
);
804 set_cc_op(s
, CC_OP_EFLAGS
);
811 typedef struct CCPrepare
{
821 /* compute eflags.C to reg */
822 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
828 case CC_OP_SUBB
... CC_OP_SUBQ
:
829 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
830 size
= s
->cc_op
- CC_OP_SUBB
;
831 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
832 /* If no temporary was used, be careful not to alias t1 and t0. */
833 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
834 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
838 case CC_OP_ADDB
... CC_OP_ADDQ
:
839 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
840 size
= s
->cc_op
- CC_OP_ADDB
;
841 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
842 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
844 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
845 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
847 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
849 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
851 case CC_OP_INCB
... CC_OP_INCQ
:
852 case CC_OP_DECB
... CC_OP_DECQ
:
853 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
854 .mask
= -1, .no_setcond
= true };
856 case CC_OP_SHLB
... CC_OP_SHLQ
:
857 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
858 size
= s
->cc_op
- CC_OP_SHLB
;
859 shift
= (8 << size
) - 1;
860 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
861 .mask
= (target_ulong
)1 << shift
};
863 case CC_OP_MULB
... CC_OP_MULQ
:
864 return (CCPrepare
) { .cond
= TCG_COND_NE
,
865 .reg
= cpu_cc_src
, .mask
= -1 };
867 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
868 size
= s
->cc_op
- CC_OP_BMILGB
;
869 t0
= gen_ext_tl(reg
, cpu_cc_src
, size
, false);
870 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
874 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_dst
,
875 .mask
= -1, .no_setcond
= true };
878 case CC_OP_SARB
... CC_OP_SARQ
:
880 return (CCPrepare
) { .cond
= TCG_COND_NE
,
881 .reg
= cpu_cc_src
, .mask
= CC_C
};
884 /* The need to compute only C from CC_OP_DYNAMIC is important
885 in efficiently implementing e.g. INC at the start of a TB. */
887 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
,
888 cpu_cc_src2
, cpu_cc_op
);
889 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
890 .mask
= -1, .no_setcond
= true };
894 /* compute eflags.P to reg */
895 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
897 gen_compute_eflags(s
);
898 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
902 /* compute eflags.S to reg */
903 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
907 gen_compute_eflags(s
);
913 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
916 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
919 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
920 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
921 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
926 /* compute eflags.O to reg */
927 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
932 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src2
,
933 .mask
= -1, .no_setcond
= true };
935 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
937 gen_compute_eflags(s
);
938 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
943 /* compute eflags.Z to reg */
944 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
948 gen_compute_eflags(s
);
954 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
957 return (CCPrepare
) { .cond
= TCG_COND_ALWAYS
, .mask
= -1 };
960 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
961 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
962 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
967 /* perform a conditional store into register 'reg' according to jump opcode
968 value 'b'. In the fast case, T0 is guaranted not to be used. */
969 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
971 int inv
, jcc_op
, cond
;
977 jcc_op
= (b
>> 1) & 7;
980 case CC_OP_SUBB
... CC_OP_SUBQ
:
981 /* We optimize relational operators for the cmp/jcc case. */
982 size
= s
->cc_op
- CC_OP_SUBB
;
985 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
986 gen_extu(size
, cpu_tmp4
);
987 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
988 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
989 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
998 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
999 gen_exts(size
, cpu_tmp4
);
1000 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1001 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
1002 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1012 /* This actually generates good code for JC, JZ and JS. */
1015 cc
= gen_prepare_eflags_o(s
, reg
);
1018 cc
= gen_prepare_eflags_c(s
, reg
);
1021 cc
= gen_prepare_eflags_z(s
, reg
);
1024 gen_compute_eflags(s
);
1025 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1026 .mask
= CC_Z
| CC_C
};
1029 cc
= gen_prepare_eflags_s(s
, reg
);
1032 cc
= gen_prepare_eflags_p(s
, reg
);
1035 gen_compute_eflags(s
);
1036 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1039 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1040 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1041 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1046 gen_compute_eflags(s
);
1047 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1050 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1051 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1052 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1053 .mask
= CC_S
| CC_Z
};
1060 cc
.cond
= tcg_invert_cond(cc
.cond
);
1065 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1067 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1069 if (cc
.no_setcond
) {
1070 if (cc
.cond
== TCG_COND_EQ
) {
1071 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1073 tcg_gen_mov_tl(reg
, cc
.reg
);
1078 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1079 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1080 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1081 tcg_gen_andi_tl(reg
, reg
, 1);
1084 if (cc
.mask
!= -1) {
1085 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1089 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1091 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1095 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1097 gen_setcc1(s
, JCC_B
<< 1, reg
);
1100 /* generate a conditional jump to label 'l1' according to jump opcode
1101 value 'b'. In the fast case, T0 is guaranted not to be used. */
1102 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1104 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1106 if (cc
.mask
!= -1) {
1107 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1111 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1113 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1117 /* Generate a conditional jump to label 'l1' according to jump opcode
1118 value 'b'. In the fast case, T0 is guaranted not to be used.
1119 A translation block must end soon. */
1120 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1122 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1124 gen_update_cc_op(s
);
1125 if (cc
.mask
!= -1) {
1126 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1129 set_cc_op(s
, CC_OP_DYNAMIC
);
1131 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1133 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1137 /* XXX: does not work with gdbstub "ice" single step - not a
1139 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1143 l1
= gen_new_label();
1144 l2
= gen_new_label();
1145 gen_op_jnz_ecx(s
->aflag
, l1
);
1147 gen_jmp_tb(s
, next_eip
, 1);
1152 static inline void gen_stos(DisasContext
*s
, TCGMemOp ot
)
1154 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
1155 gen_string_movl_A0_EDI(s
);
1156 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1157 gen_op_movl_T0_Dshift(ot
);
1158 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1161 static inline void gen_lods(DisasContext
*s
, TCGMemOp ot
)
1163 gen_string_movl_A0_ESI(s
);
1164 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1165 gen_op_mov_reg_T0(ot
, R_EAX
);
1166 gen_op_movl_T0_Dshift(ot
);
1167 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1170 static inline void gen_scas(DisasContext
*s
, TCGMemOp ot
)
1172 gen_string_movl_A0_EDI(s
);
1173 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1174 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1175 gen_op_movl_T0_Dshift(ot
);
1176 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1179 static inline void gen_cmps(DisasContext
*s
, TCGMemOp ot
)
1181 gen_string_movl_A0_EDI(s
);
1182 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1183 gen_string_movl_A0_ESI(s
);
1184 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1185 gen_op_movl_T0_Dshift(ot
);
1186 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1187 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1190 static inline void gen_ins(DisasContext
*s
, TCGMemOp ot
)
1194 gen_string_movl_A0_EDI(s
);
1195 /* Note: we must do this dummy write first to be restartable in
1196 case of page fault. */
1197 tcg_gen_movi_tl(cpu_T
[0], 0);
1198 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1199 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1200 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1201 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1202 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1203 gen_op_movl_T0_Dshift(ot
);
1204 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1209 static inline void gen_outs(DisasContext
*s
, TCGMemOp ot
)
1213 gen_string_movl_A0_ESI(s
);
1214 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1216 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1217 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1218 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1219 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1221 gen_op_movl_T0_Dshift(ot
);
1222 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1227 /* same method as Valgrind : we generate jumps to current or next
1229 #define GEN_REPZ(op) \
1230 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1231 target_ulong cur_eip, target_ulong next_eip) \
1234 gen_update_cc_op(s); \
1235 l2 = gen_jz_ecx_string(s, next_eip); \
1236 gen_ ## op(s, ot); \
1237 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1238 /* a loop would cause two single step exceptions if ECX = 1 \
1239 before rep string_insn */ \
1241 gen_op_jz_ecx(s->aflag, l2); \
1242 gen_jmp(s, cur_eip); \
1245 #define GEN_REPZ2(op) \
1246 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1247 target_ulong cur_eip, \
1248 target_ulong next_eip, \
1252 gen_update_cc_op(s); \
1253 l2 = gen_jz_ecx_string(s, next_eip); \
1254 gen_ ## op(s, ot); \
1255 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1256 gen_update_cc_op(s); \
1257 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1259 gen_op_jz_ecx(s->aflag, l2); \
1260 gen_jmp(s, cur_eip); \
1271 static void gen_helper_fp_arith_ST0_FT0(int op
)
1275 gen_helper_fadd_ST0_FT0(cpu_env
);
1278 gen_helper_fmul_ST0_FT0(cpu_env
);
1281 gen_helper_fcom_ST0_FT0(cpu_env
);
1284 gen_helper_fcom_ST0_FT0(cpu_env
);
1287 gen_helper_fsub_ST0_FT0(cpu_env
);
1290 gen_helper_fsubr_ST0_FT0(cpu_env
);
1293 gen_helper_fdiv_ST0_FT0(cpu_env
);
1296 gen_helper_fdivr_ST0_FT0(cpu_env
);
1301 /* NOTE the exception in "r" op ordering */
1302 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1304 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1307 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1310 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1313 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1316 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1319 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1322 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1327 /* if d == OR_TMP0, it means memory operand (address in A0) */
1328 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
)
1331 gen_op_mov_TN_reg(ot
, 0, d
);
1333 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1337 gen_compute_eflags_c(s1
, cpu_tmp4
);
1338 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1339 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1340 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1341 gen_op_update3_cc(cpu_tmp4
);
1342 set_cc_op(s1
, CC_OP_ADCB
+ ot
);
1345 gen_compute_eflags_c(s1
, cpu_tmp4
);
1346 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1347 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1348 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1349 gen_op_update3_cc(cpu_tmp4
);
1350 set_cc_op(s1
, CC_OP_SBBB
+ ot
);
1353 gen_op_addl_T0_T1();
1354 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1355 gen_op_update2_cc();
1356 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1359 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1360 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1361 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1362 gen_op_update2_cc();
1363 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1367 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1368 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1369 gen_op_update1_cc();
1370 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1373 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1374 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1375 gen_op_update1_cc();
1376 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1379 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1380 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1381 gen_op_update1_cc();
1382 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1385 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1386 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1387 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1388 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1393 /* if d == OR_TMP0, it means memory operand (address in A0) */
1394 static void gen_inc(DisasContext
*s1
, TCGMemOp ot
, int d
, int c
)
1397 gen_op_mov_TN_reg(ot
, 0, d
);
1399 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1401 gen_compute_eflags_c(s1
, cpu_cc_src
);
1403 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1404 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1406 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1407 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1409 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1410 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1413 static void gen_shift_flags(DisasContext
*s
, TCGMemOp ot
, TCGv result
,
1414 TCGv shm1
, TCGv count
, bool is_right
)
1416 TCGv_i32 z32
, s32
, oldop
;
1419 /* Store the results into the CC variables. If we know that the
1420 variable must be dead, store unconditionally. Otherwise we'll
1421 need to not disrupt the current contents. */
1422 z_tl
= tcg_const_tl(0);
1423 if (cc_op_live
[s
->cc_op
] & USES_CC_DST
) {
1424 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_dst
, count
, z_tl
,
1425 result
, cpu_cc_dst
);
1427 tcg_gen_mov_tl(cpu_cc_dst
, result
);
1429 if (cc_op_live
[s
->cc_op
] & USES_CC_SRC
) {
1430 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_src
, count
, z_tl
,
1433 tcg_gen_mov_tl(cpu_cc_src
, shm1
);
1435 tcg_temp_free(z_tl
);
1437 /* Get the two potential CC_OP values into temporaries. */
1438 tcg_gen_movi_i32(cpu_tmp2_i32
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1439 if (s
->cc_op
== CC_OP_DYNAMIC
) {
1442 tcg_gen_movi_i32(cpu_tmp3_i32
, s
->cc_op
);
1443 oldop
= cpu_tmp3_i32
;
1446 /* Conditionally store the CC_OP value. */
1447 z32
= tcg_const_i32(0);
1448 s32
= tcg_temp_new_i32();
1449 tcg_gen_trunc_tl_i32(s32
, count
);
1450 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, s32
, z32
, cpu_tmp2_i32
, oldop
);
1451 tcg_temp_free_i32(z32
);
1452 tcg_temp_free_i32(s32
);
1454 /* The CC_OP value is no longer predictable. */
1455 set_cc_op(s
, CC_OP_DYNAMIC
);
1458 static void gen_shift_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1459 int is_right
, int is_arith
)
1461 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1464 if (op1
== OR_TMP0
) {
1465 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1467 gen_op_mov_TN_reg(ot
, 0, op1
);
1470 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1471 tcg_gen_subi_tl(cpu_tmp0
, cpu_T
[1], 1);
1475 gen_exts(ot
, cpu_T
[0]);
1476 tcg_gen_sar_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1477 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1479 gen_extu(ot
, cpu_T
[0]);
1480 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1481 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1484 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1485 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1489 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1491 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, cpu_T
[1], is_right
);
1494 static void gen_shift_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1495 int is_right
, int is_arith
)
1497 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1501 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1503 gen_op_mov_TN_reg(ot
, 0, op1
);
1509 gen_exts(ot
, cpu_T
[0]);
1510 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1511 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1513 gen_extu(ot
, cpu_T
[0]);
1514 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1515 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1518 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1519 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1524 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1526 /* update eflags if non zero shift */
1528 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1529 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1530 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1534 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1537 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1539 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1542 static void gen_rot_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
, int is_right
)
1544 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1548 if (op1
== OR_TMP0
) {
1549 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1551 gen_op_mov_TN_reg(ot
, 0, op1
);
1554 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1558 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1559 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
1560 tcg_gen_muli_tl(cpu_T
[0], cpu_T
[0], 0x01010101);
1563 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1564 tcg_gen_deposit_tl(cpu_T
[0], cpu_T
[0], cpu_T
[0], 16, 16);
1567 #ifdef TARGET_X86_64
1569 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1570 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
1572 tcg_gen_rotr_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1574 tcg_gen_rotl_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1576 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1581 tcg_gen_rotr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1583 tcg_gen_rotl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1589 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1591 /* We'll need the flags computed into CC_SRC. */
1592 gen_compute_eflags(s
);
1594 /* The value that was "rotated out" is now present at the other end
1595 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1596 since we've computed the flags into CC_SRC, these variables are
1599 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1600 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1601 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1603 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1604 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1606 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1607 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1609 /* Now conditionally store the new CC_OP value. If the shift count
1610 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1611 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1612 exactly as we computed above. */
1613 t0
= tcg_const_i32(0);
1614 t1
= tcg_temp_new_i32();
1615 tcg_gen_trunc_tl_i32(t1
, cpu_T
[1]);
1616 tcg_gen_movi_i32(cpu_tmp2_i32
, CC_OP_ADCOX
);
1617 tcg_gen_movi_i32(cpu_tmp3_i32
, CC_OP_EFLAGS
);
1618 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, t1
, t0
,
1619 cpu_tmp2_i32
, cpu_tmp3_i32
);
1620 tcg_temp_free_i32(t0
);
1621 tcg_temp_free_i32(t1
);
1623 /* The CC_OP value is no longer predictable. */
1624 set_cc_op(s
, CC_OP_DYNAMIC
);
1627 static void gen_rot_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1630 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1634 if (op1
== OR_TMP0
) {
1635 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1637 gen_op_mov_TN_reg(ot
, 0, op1
);
1643 #ifdef TARGET_X86_64
1645 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1647 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1649 tcg_gen_rotli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1651 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1656 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], op2
);
1658 tcg_gen_rotli_tl(cpu_T
[0], cpu_T
[0], op2
);
1669 shift
= mask
+ 1 - shift
;
1671 gen_extu(ot
, cpu_T
[0]);
1672 tcg_gen_shli_tl(cpu_tmp0
, cpu_T
[0], shift
);
1673 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], mask
+ 1 - shift
);
1674 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
1680 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1683 /* Compute the flags into CC_SRC. */
1684 gen_compute_eflags(s
);
1686 /* The value that was "rotated out" is now present at the other end
1687 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1688 since we've computed the flags into CC_SRC, these variables are
1691 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1692 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1693 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1695 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1696 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1698 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1699 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1700 set_cc_op(s
, CC_OP_ADCOX
);
1704 /* XXX: add faster immediate = 1 case */
1705 static void gen_rotc_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1708 gen_compute_eflags(s
);
1709 assert(s
->cc_op
== CC_OP_EFLAGS
);
1713 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1715 gen_op_mov_TN_reg(ot
, 0, op1
);
1720 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1723 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1726 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1728 #ifdef TARGET_X86_64
1730 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1739 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1742 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1745 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1747 #ifdef TARGET_X86_64
1749 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1757 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1760 /* XXX: add faster immediate case */
1761 static void gen_shiftd_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1762 bool is_right
, TCGv count_in
)
1764 target_ulong mask
= (ot
== MO_64
? 63 : 31);
1768 if (op1
== OR_TMP0
) {
1769 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1771 gen_op_mov_TN_reg(ot
, 0, op1
);
1774 count
= tcg_temp_new();
1775 tcg_gen_andi_tl(count
, count_in
, mask
);
1779 /* Note: we implement the Intel behaviour for shift count > 16.
1780 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1781 portion by constructing it as a 32-bit value. */
1783 tcg_gen_deposit_tl(cpu_tmp0
, cpu_T
[0], cpu_T
[1], 16, 16);
1784 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1785 tcg_gen_mov_tl(cpu_T
[0], cpu_tmp0
);
1787 tcg_gen_deposit_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1], 16, 16);
1790 #ifdef TARGET_X86_64
1792 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1793 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1795 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1796 tcg_gen_shr_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1797 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], count
);
1799 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1800 tcg_gen_shl_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1801 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], count
);
1802 tcg_gen_shri_i64(cpu_tmp0
, cpu_tmp0
, 32);
1803 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], 32);
1808 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1810 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1812 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1813 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], count
);
1814 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1816 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1818 /* Only needed if count > 16, for Intel behaviour. */
1819 tcg_gen_subfi_tl(cpu_tmp4
, 33, count
);
1820 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[1], cpu_tmp4
);
1821 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, cpu_tmp4
);
1824 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1825 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], count
);
1826 tcg_gen_shr_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1828 tcg_gen_movi_tl(cpu_tmp4
, 0);
1829 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[1], count
, cpu_tmp4
,
1830 cpu_tmp4
, cpu_T
[1]);
1831 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1836 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1838 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, count
, is_right
);
1839 tcg_temp_free(count
);
1842 static void gen_shift(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int s
)
1845 gen_op_mov_TN_reg(ot
, 1, s
);
1848 gen_rot_rm_T1(s1
, ot
, d
, 0);
1851 gen_rot_rm_T1(s1
, ot
, d
, 1);
1855 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1858 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1861 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1864 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1867 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1872 static void gen_shifti(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int c
)
1876 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1879 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1883 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1886 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1889 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1892 /* currently not optimized */
1893 tcg_gen_movi_tl(cpu_T
[1], c
);
1894 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1899 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
1906 int mod
, rm
, code
, override
, must_add_seg
;
1909 override
= s
->override
;
1910 must_add_seg
= s
->addseg
;
1913 mod
= (modrm
>> 6) & 3;
1926 code
= cpu_ldub_code(env
, s
->pc
++);
1927 scale
= (code
>> 6) & 3;
1928 index
= ((code
>> 3) & 7) | REX_X(s
);
1930 index
= -1; /* no index */
1938 if ((base
& 7) == 5) {
1940 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1942 if (CODE64(s
) && !havesib
) {
1943 disp
+= s
->pc
+ s
->rip_offset
;
1950 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
1954 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1959 /* For correct popl handling with esp. */
1960 if (base
== R_ESP
&& s
->popl_esp_hack
) {
1961 disp
+= s
->popl_esp_hack
;
1964 /* Compute the address, with a minimum number of TCG ops. */
1968 sum
= cpu_regs
[index
];
1970 tcg_gen_shli_tl(cpu_A0
, cpu_regs
[index
], scale
);
1974 tcg_gen_add_tl(cpu_A0
, sum
, cpu_regs
[base
]);
1977 } else if (base
>= 0) {
1978 sum
= cpu_regs
[base
];
1980 if (TCGV_IS_UNUSED(sum
)) {
1981 tcg_gen_movi_tl(cpu_A0
, disp
);
1983 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
1988 if (base
== R_EBP
|| base
== R_ESP
) {
1995 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
1996 offsetof(CPUX86State
, segs
[override
].base
));
1998 if (s
->aflag
== MO_32
) {
1999 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2001 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2005 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2008 if (s
->aflag
== MO_32
) {
2009 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2017 disp
= cpu_lduw_code(env
, s
->pc
);
2019 tcg_gen_movi_tl(cpu_A0
, disp
);
2020 rm
= 0; /* avoid SS override */
2027 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2031 disp
= (int16_t)cpu_lduw_code(env
, s
->pc
);
2039 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_ESI
]);
2042 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_EDI
]);
2045 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_ESI
]);
2048 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_EDI
]);
2051 sum
= cpu_regs
[R_ESI
];
2054 sum
= cpu_regs
[R_EDI
];
2057 sum
= cpu_regs
[R_EBP
];
2061 sum
= cpu_regs
[R_EBX
];
2064 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
2065 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2069 if (rm
== 2 || rm
== 3 || rm
== 6) {
2075 gen_op_addl_A0_seg(s
, override
);
2084 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2086 int mod
, rm
, base
, code
;
2088 mod
= (modrm
>> 6) & 3;
2099 code
= cpu_ldub_code(env
, s
->pc
++);
2141 /* used for LEA and MOV AX, mem */
2142 static void gen_add_A0_ds_seg(DisasContext
*s
)
2144 int override
, must_add_seg
;
2145 must_add_seg
= s
->addseg
;
2147 if (s
->override
>= 0) {
2148 override
= s
->override
;
2152 #ifdef TARGET_X86_64
2154 gen_op_addq_A0_seg(override
);
2158 gen_op_addl_A0_seg(s
, override
);
2163 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2165 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2166 TCGMemOp ot
, int reg
, int is_store
)
2170 mod
= (modrm
>> 6) & 3;
2171 rm
= (modrm
& 7) | REX_B(s
);
2175 gen_op_mov_TN_reg(ot
, 0, reg
);
2176 gen_op_mov_reg_T0(ot
, rm
);
2178 gen_op_mov_TN_reg(ot
, 0, rm
);
2180 gen_op_mov_reg_T0(ot
, reg
);
2183 gen_lea_modrm(env
, s
, modrm
);
2186 gen_op_mov_TN_reg(ot
, 0, reg
);
2187 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2189 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
2191 gen_op_mov_reg_T0(ot
, reg
);
2196 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
)
2202 ret
= cpu_ldub_code(env
, s
->pc
);
2206 ret
= cpu_lduw_code(env
, s
->pc
);
2210 #ifdef TARGET_X86_64
2213 ret
= cpu_ldl_code(env
, s
->pc
);
2222 static inline int insn_const_size(TCGMemOp ot
)
2231 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2233 TranslationBlock
*tb
;
2236 pc
= s
->cs_base
+ eip
;
2238 /* NOTE: we handle the case where the TB spans two pages here */
2239 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2240 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2241 /* jump to same page: we can use a direct jump */
2242 tcg_gen_goto_tb(tb_num
);
2244 tcg_gen_exit_tb((uintptr_t)tb
+ tb_num
);
2246 /* jump to another page: currently not optimized */
2252 static inline void gen_jcc(DisasContext
*s
, int b
,
2253 target_ulong val
, target_ulong next_eip
)
2258 l1
= gen_new_label();
2261 gen_goto_tb(s
, 0, next_eip
);
2264 gen_goto_tb(s
, 1, val
);
2265 s
->is_jmp
= DISAS_TB_JUMP
;
2267 l1
= gen_new_label();
2268 l2
= gen_new_label();
2271 gen_jmp_im(next_eip
);
2281 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
, int b
,
2286 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2288 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2289 if (cc
.mask
!= -1) {
2290 TCGv t0
= tcg_temp_new();
2291 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2295 cc
.reg2
= tcg_const_tl(cc
.imm
);
2298 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2299 cpu_T
[0], cpu_regs
[reg
]);
2300 gen_op_mov_reg_T0(ot
, reg
);
2302 if (cc
.mask
!= -1) {
2303 tcg_temp_free(cc
.reg
);
2306 tcg_temp_free(cc
.reg2
);
2310 static inline void gen_op_movl_T0_seg(int seg_reg
)
2312 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2313 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2316 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2318 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2319 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2320 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2321 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2322 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2323 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2326 /* move T0 to seg_reg and compute if the CPU state may change. Never
2327 call this function with seg_reg == R_CS */
2328 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2330 if (s
->pe
&& !s
->vm86
) {
2331 /* XXX: optimize by finding processor state dynamically */
2332 gen_update_cc_op(s
);
2333 gen_jmp_im(cur_eip
);
2334 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2335 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2336 /* abort translation because the addseg value may change or
2337 because ss32 may change. For R_SS, translation must always
2338 stop as a special handling must be done to disable hardware
2339 interrupts for the next instruction */
2340 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2341 s
->is_jmp
= DISAS_TB_JUMP
;
2343 gen_op_movl_seg_T0_vm(seg_reg
);
2344 if (seg_reg
== R_SS
)
2345 s
->is_jmp
= DISAS_TB_JUMP
;
2349 static inline int svm_is_rep(int prefixes
)
2351 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2355 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2356 uint32_t type
, uint64_t param
)
2358 /* no SVM activated; fast case */
2359 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2361 gen_update_cc_op(s
);
2362 gen_jmp_im(pc_start
- s
->cs_base
);
2363 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2364 tcg_const_i64(param
));
2368 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2370 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2373 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2375 #ifdef TARGET_X86_64
2377 gen_op_add_reg_im(MO_64
, R_ESP
, addend
);
2381 gen_op_add_reg_im(MO_32
, R_ESP
, addend
);
2383 gen_op_add_reg_im(MO_16
, R_ESP
, addend
);
2387 /* generate a push. It depends on ss32, addseg and dflag */
2388 static void gen_push_T0(DisasContext
*s
)
2390 #ifdef TARGET_X86_64
2392 gen_op_movq_A0_reg(R_ESP
);
2393 if (s
->dflag
!= MO_16
) {
2394 gen_op_addq_A0_im(-8);
2395 gen_op_st_v(s
, MO_64
, cpu_T
[0], cpu_A0
);
2397 gen_op_addq_A0_im(-2);
2398 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
2400 gen_op_mov_reg_A0(MO_64
, R_ESP
);
2404 gen_op_movl_A0_reg(R_ESP
);
2405 gen_op_addl_A0_im(-1 << s
->dflag
);
2408 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2409 gen_op_addl_A0_seg(s
, R_SS
);
2412 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2413 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2414 gen_op_addl_A0_seg(s
, R_SS
);
2416 gen_op_st_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2417 if (s
->ss32
&& !s
->addseg
)
2418 gen_op_mov_reg_A0(MO_32
, R_ESP
);
2420 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2424 /* generate a push. It depends on ss32, addseg and dflag */
2425 /* slower version for T1, only used for call Ev */
2426 static void gen_push_T1(DisasContext
*s
)
2428 #ifdef TARGET_X86_64
2430 gen_op_movq_A0_reg(R_ESP
);
2431 if (s
->dflag
!= MO_16
) {
2432 gen_op_addq_A0_im(-8);
2433 gen_op_st_v(s
, MO_64
, cpu_T
[1], cpu_A0
);
2435 gen_op_addq_A0_im(-2);
2436 gen_op_st_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
2438 gen_op_mov_reg_A0(MO_64
, R_ESP
);
2442 gen_op_movl_A0_reg(R_ESP
);
2443 gen_op_addl_A0_im(-1 << s
->dflag
);
2446 gen_op_addl_A0_seg(s
, R_SS
);
2449 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2450 gen_op_addl_A0_seg(s
, R_SS
);
2452 gen_op_st_v(s
, s
->dflag
, cpu_T
[1], cpu_A0
);
2454 if (s
->ss32
&& !s
->addseg
)
2455 gen_op_mov_reg_A0(MO_32
, R_ESP
);
2457 gen_stack_update(s
, -1 << s
->dflag
);
2461 /* two step pop is necessary for precise exceptions */
2462 static void gen_pop_T0(DisasContext
*s
)
2464 #ifdef TARGET_X86_64
2466 gen_op_movq_A0_reg(R_ESP
);
2467 gen_op_ld_v(s
, mo_pushpop(s
, s
->dflag
), cpu_T
[0], cpu_A0
);
2471 gen_op_movl_A0_reg(R_ESP
);
2474 gen_op_addl_A0_seg(s
, R_SS
);
2476 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2477 gen_op_addl_A0_seg(s
, R_SS
);
2479 gen_op_ld_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2483 static void gen_pop_update(DisasContext
*s
)
2485 gen_stack_update(s
, 1 << mo_pushpop(s
, s
->dflag
));
2488 static void gen_stack_A0(DisasContext
*s
)
2490 gen_op_movl_A0_reg(R_ESP
);
2492 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2493 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2495 gen_op_addl_A0_seg(s
, R_SS
);
2498 /* NOTE: wrap around in 16 bit not fully handled */
2499 static void gen_pusha(DisasContext
*s
)
2502 gen_op_movl_A0_reg(R_ESP
);
2503 gen_op_addl_A0_im(-8 << s
->dflag
);
2505 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2506 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2508 gen_op_addl_A0_seg(s
, R_SS
);
2509 for(i
= 0;i
< 8; i
++) {
2510 gen_op_mov_TN_reg(MO_32
, 0, 7 - i
);
2511 gen_op_st_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2512 gen_op_addl_A0_im(1 << s
->dflag
);
2514 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2517 /* NOTE: wrap around in 16 bit not fully handled */
2518 static void gen_popa(DisasContext
*s
)
2521 gen_op_movl_A0_reg(R_ESP
);
2523 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2524 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2525 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 8 << s
->dflag
);
2527 gen_op_addl_A0_seg(s
, R_SS
);
2528 for(i
= 0;i
< 8; i
++) {
2529 /* ESP is not reloaded */
2531 gen_op_ld_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2532 gen_op_mov_reg_T0(s
->dflag
, 7 - i
);
2534 gen_op_addl_A0_im(1 << s
->dflag
);
2536 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2539 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2541 TCGMemOp ot
= mo_pushpop(s
, s
->dflag
);
2542 int opsize
= 1 << ot
;
2545 #ifdef TARGET_X86_64
2547 gen_op_movl_A0_reg(R_ESP
);
2548 gen_op_addq_A0_im(-opsize
);
2549 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2552 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2553 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2555 /* XXX: must save state */
2556 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2557 tcg_const_i32((ot
== MO_64
)),
2560 gen_op_mov_reg_T1(ot
, R_EBP
);
2561 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2562 gen_op_mov_reg_T1(MO_64
, R_ESP
);
2566 gen_op_movl_A0_reg(R_ESP
);
2567 gen_op_addl_A0_im(-opsize
);
2569 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2570 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2572 gen_op_addl_A0_seg(s
, R_SS
);
2574 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2575 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2577 /* XXX: must save state */
2578 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2579 tcg_const_i32(s
->dflag
- 1),
2582 gen_op_mov_reg_T1(ot
, R_EBP
);
2583 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2584 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2588 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2590 gen_update_cc_op(s
);
2591 gen_jmp_im(cur_eip
);
2592 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2593 s
->is_jmp
= DISAS_TB_JUMP
;
2596 /* an interrupt is different from an exception because of the
2598 static void gen_interrupt(DisasContext
*s
, int intno
,
2599 target_ulong cur_eip
, target_ulong next_eip
)
2601 gen_update_cc_op(s
);
2602 gen_jmp_im(cur_eip
);
2603 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2604 tcg_const_i32(next_eip
- cur_eip
));
2605 s
->is_jmp
= DISAS_TB_JUMP
;
2608 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2610 gen_update_cc_op(s
);
2611 gen_jmp_im(cur_eip
);
2612 gen_helper_debug(cpu_env
);
2613 s
->is_jmp
= DISAS_TB_JUMP
;
2616 /* generate a generic end of block. Trace exception is also generated
2618 static void gen_eob(DisasContext
*s
)
2620 gen_update_cc_op(s
);
2621 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2622 gen_helper_reset_inhibit_irq(cpu_env
);
2624 if (s
->tb
->flags
& HF_RF_MASK
) {
2625 gen_helper_reset_rf(cpu_env
);
2627 if (s
->singlestep_enabled
) {
2628 gen_helper_debug(cpu_env
);
2630 gen_helper_single_step(cpu_env
);
2634 s
->is_jmp
= DISAS_TB_JUMP
;
2637 /* generate a jump to eip. No segment change must happen before as a
2638 direct call to the next block may occur */
2639 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2641 gen_update_cc_op(s
);
2642 set_cc_op(s
, CC_OP_DYNAMIC
);
2644 gen_goto_tb(s
, tb_num
, eip
);
2645 s
->is_jmp
= DISAS_TB_JUMP
;
2652 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2654 gen_jmp_tb(s
, eip
, 0);
2657 static inline void gen_ldq_env_A0(DisasContext
*s
, int offset
)
2659 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2660 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2663 static inline void gen_stq_env_A0(DisasContext
*s
, int offset
)
2665 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2666 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2669 static inline void gen_ldo_env_A0(DisasContext
*s
, int offset
)
2671 int mem_index
= s
->mem_index
;
2672 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2673 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2674 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2675 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2676 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2679 static inline void gen_sto_env_A0(DisasContext
*s
, int offset
)
2681 int mem_index
= s
->mem_index
;
2682 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2683 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2684 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2685 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2686 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2689 static inline void gen_op_movo(int d_offset
, int s_offset
)
2691 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2692 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2693 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2694 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2697 static inline void gen_op_movq(int d_offset
, int s_offset
)
2699 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2700 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2703 static inline void gen_op_movl(int d_offset
, int s_offset
)
2705 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2706 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2709 static inline void gen_op_movq_env_0(int d_offset
)
2711 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2712 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2715 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2716 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2717 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2718 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2719 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2720 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2722 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2723 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2726 #define SSE_SPECIAL ((void *)1)
2727 #define SSE_DUMMY ((void *)2)
2729 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2730 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2731 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2733 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2734 /* 3DNow! extensions */
2735 [0x0e] = { SSE_DUMMY
}, /* femms */
2736 [0x0f] = { SSE_DUMMY
}, /* pf... */
2737 /* pure SSE operations */
2738 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2739 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2740 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2741 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2742 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2743 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2744 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2745 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2747 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2748 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2749 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2750 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2751 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2752 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2753 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2754 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2755 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2756 [0x51] = SSE_FOP(sqrt
),
2757 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2758 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2759 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2760 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2761 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2762 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2763 [0x58] = SSE_FOP(add
),
2764 [0x59] = SSE_FOP(mul
),
2765 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2766 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2767 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2768 [0x5c] = SSE_FOP(sub
),
2769 [0x5d] = SSE_FOP(min
),
2770 [0x5e] = SSE_FOP(div
),
2771 [0x5f] = SSE_FOP(max
),
2773 [0xc2] = SSE_FOP(cmpeq
),
2774 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2775 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2777 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2778 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2779 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2781 /* MMX ops and their SSE extensions */
2782 [0x60] = MMX_OP2(punpcklbw
),
2783 [0x61] = MMX_OP2(punpcklwd
),
2784 [0x62] = MMX_OP2(punpckldq
),
2785 [0x63] = MMX_OP2(packsswb
),
2786 [0x64] = MMX_OP2(pcmpgtb
),
2787 [0x65] = MMX_OP2(pcmpgtw
),
2788 [0x66] = MMX_OP2(pcmpgtl
),
2789 [0x67] = MMX_OP2(packuswb
),
2790 [0x68] = MMX_OP2(punpckhbw
),
2791 [0x69] = MMX_OP2(punpckhwd
),
2792 [0x6a] = MMX_OP2(punpckhdq
),
2793 [0x6b] = MMX_OP2(packssdw
),
2794 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2795 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2796 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2797 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2798 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2799 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2800 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2801 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2802 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2803 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2804 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2805 [0x74] = MMX_OP2(pcmpeqb
),
2806 [0x75] = MMX_OP2(pcmpeqw
),
2807 [0x76] = MMX_OP2(pcmpeql
),
2808 [0x77] = { SSE_DUMMY
}, /* emms */
2809 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2810 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2811 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2812 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2813 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2814 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2815 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2816 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2817 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2818 [0xd1] = MMX_OP2(psrlw
),
2819 [0xd2] = MMX_OP2(psrld
),
2820 [0xd3] = MMX_OP2(psrlq
),
2821 [0xd4] = MMX_OP2(paddq
),
2822 [0xd5] = MMX_OP2(pmullw
),
2823 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2824 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2825 [0xd8] = MMX_OP2(psubusb
),
2826 [0xd9] = MMX_OP2(psubusw
),
2827 [0xda] = MMX_OP2(pminub
),
2828 [0xdb] = MMX_OP2(pand
),
2829 [0xdc] = MMX_OP2(paddusb
),
2830 [0xdd] = MMX_OP2(paddusw
),
2831 [0xde] = MMX_OP2(pmaxub
),
2832 [0xdf] = MMX_OP2(pandn
),
2833 [0xe0] = MMX_OP2(pavgb
),
2834 [0xe1] = MMX_OP2(psraw
),
2835 [0xe2] = MMX_OP2(psrad
),
2836 [0xe3] = MMX_OP2(pavgw
),
2837 [0xe4] = MMX_OP2(pmulhuw
),
2838 [0xe5] = MMX_OP2(pmulhw
),
2839 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2840 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2841 [0xe8] = MMX_OP2(psubsb
),
2842 [0xe9] = MMX_OP2(psubsw
),
2843 [0xea] = MMX_OP2(pminsw
),
2844 [0xeb] = MMX_OP2(por
),
2845 [0xec] = MMX_OP2(paddsb
),
2846 [0xed] = MMX_OP2(paddsw
),
2847 [0xee] = MMX_OP2(pmaxsw
),
2848 [0xef] = MMX_OP2(pxor
),
2849 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2850 [0xf1] = MMX_OP2(psllw
),
2851 [0xf2] = MMX_OP2(pslld
),
2852 [0xf3] = MMX_OP2(psllq
),
2853 [0xf4] = MMX_OP2(pmuludq
),
2854 [0xf5] = MMX_OP2(pmaddwd
),
2855 [0xf6] = MMX_OP2(psadbw
),
2856 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
2857 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
2858 [0xf8] = MMX_OP2(psubb
),
2859 [0xf9] = MMX_OP2(psubw
),
2860 [0xfa] = MMX_OP2(psubl
),
2861 [0xfb] = MMX_OP2(psubq
),
2862 [0xfc] = MMX_OP2(paddb
),
2863 [0xfd] = MMX_OP2(paddw
),
2864 [0xfe] = MMX_OP2(paddl
),
2867 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
2868 [0 + 2] = MMX_OP2(psrlw
),
2869 [0 + 4] = MMX_OP2(psraw
),
2870 [0 + 6] = MMX_OP2(psllw
),
2871 [8 + 2] = MMX_OP2(psrld
),
2872 [8 + 4] = MMX_OP2(psrad
),
2873 [8 + 6] = MMX_OP2(pslld
),
2874 [16 + 2] = MMX_OP2(psrlq
),
2875 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2876 [16 + 6] = MMX_OP2(psllq
),
2877 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2880 static const SSEFunc_0_epi sse_op_table3ai
[] = {
2881 gen_helper_cvtsi2ss
,
2885 #ifdef TARGET_X86_64
2886 static const SSEFunc_0_epl sse_op_table3aq
[] = {
2887 gen_helper_cvtsq2ss
,
2892 static const SSEFunc_i_ep sse_op_table3bi
[] = {
2893 gen_helper_cvttss2si
,
2894 gen_helper_cvtss2si
,
2895 gen_helper_cvttsd2si
,
2899 #ifdef TARGET_X86_64
2900 static const SSEFunc_l_ep sse_op_table3bq
[] = {
2901 gen_helper_cvttss2sq
,
2902 gen_helper_cvtss2sq
,
2903 gen_helper_cvttsd2sq
,
2908 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
2919 static const SSEFunc_0_epp sse_op_table5
[256] = {
2920 [0x0c] = gen_helper_pi2fw
,
2921 [0x0d] = gen_helper_pi2fd
,
2922 [0x1c] = gen_helper_pf2iw
,
2923 [0x1d] = gen_helper_pf2id
,
2924 [0x8a] = gen_helper_pfnacc
,
2925 [0x8e] = gen_helper_pfpnacc
,
2926 [0x90] = gen_helper_pfcmpge
,
2927 [0x94] = gen_helper_pfmin
,
2928 [0x96] = gen_helper_pfrcp
,
2929 [0x97] = gen_helper_pfrsqrt
,
2930 [0x9a] = gen_helper_pfsub
,
2931 [0x9e] = gen_helper_pfadd
,
2932 [0xa0] = gen_helper_pfcmpgt
,
2933 [0xa4] = gen_helper_pfmax
,
2934 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2935 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2936 [0xaa] = gen_helper_pfsubr
,
2937 [0xae] = gen_helper_pfacc
,
2938 [0xb0] = gen_helper_pfcmpeq
,
2939 [0xb4] = gen_helper_pfmul
,
2940 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
2941 [0xb7] = gen_helper_pmulhrw_mmx
,
2942 [0xbb] = gen_helper_pswapd
,
2943 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
2946 struct SSEOpHelper_epp
{
2947 SSEFunc_0_epp op
[2];
2951 struct SSEOpHelper_eppi
{
2952 SSEFunc_0_eppi op
[2];
2956 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2957 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2958 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2959 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2960 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
2961 CPUID_EXT_PCLMULQDQ }
2962 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
2964 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
2965 [0x00] = SSSE3_OP(pshufb
),
2966 [0x01] = SSSE3_OP(phaddw
),
2967 [0x02] = SSSE3_OP(phaddd
),
2968 [0x03] = SSSE3_OP(phaddsw
),
2969 [0x04] = SSSE3_OP(pmaddubsw
),
2970 [0x05] = SSSE3_OP(phsubw
),
2971 [0x06] = SSSE3_OP(phsubd
),
2972 [0x07] = SSSE3_OP(phsubsw
),
2973 [0x08] = SSSE3_OP(psignb
),
2974 [0x09] = SSSE3_OP(psignw
),
2975 [0x0a] = SSSE3_OP(psignd
),
2976 [0x0b] = SSSE3_OP(pmulhrsw
),
2977 [0x10] = SSE41_OP(pblendvb
),
2978 [0x14] = SSE41_OP(blendvps
),
2979 [0x15] = SSE41_OP(blendvpd
),
2980 [0x17] = SSE41_OP(ptest
),
2981 [0x1c] = SSSE3_OP(pabsb
),
2982 [0x1d] = SSSE3_OP(pabsw
),
2983 [0x1e] = SSSE3_OP(pabsd
),
2984 [0x20] = SSE41_OP(pmovsxbw
),
2985 [0x21] = SSE41_OP(pmovsxbd
),
2986 [0x22] = SSE41_OP(pmovsxbq
),
2987 [0x23] = SSE41_OP(pmovsxwd
),
2988 [0x24] = SSE41_OP(pmovsxwq
),
2989 [0x25] = SSE41_OP(pmovsxdq
),
2990 [0x28] = SSE41_OP(pmuldq
),
2991 [0x29] = SSE41_OP(pcmpeqq
),
2992 [0x2a] = SSE41_SPECIAL
, /* movntqda */
2993 [0x2b] = SSE41_OP(packusdw
),
2994 [0x30] = SSE41_OP(pmovzxbw
),
2995 [0x31] = SSE41_OP(pmovzxbd
),
2996 [0x32] = SSE41_OP(pmovzxbq
),
2997 [0x33] = SSE41_OP(pmovzxwd
),
2998 [0x34] = SSE41_OP(pmovzxwq
),
2999 [0x35] = SSE41_OP(pmovzxdq
),
3000 [0x37] = SSE42_OP(pcmpgtq
),
3001 [0x38] = SSE41_OP(pminsb
),
3002 [0x39] = SSE41_OP(pminsd
),
3003 [0x3a] = SSE41_OP(pminuw
),
3004 [0x3b] = SSE41_OP(pminud
),
3005 [0x3c] = SSE41_OP(pmaxsb
),
3006 [0x3d] = SSE41_OP(pmaxsd
),
3007 [0x3e] = SSE41_OP(pmaxuw
),
3008 [0x3f] = SSE41_OP(pmaxud
),
3009 [0x40] = SSE41_OP(pmulld
),
3010 [0x41] = SSE41_OP(phminposuw
),
3011 [0xdb] = AESNI_OP(aesimc
),
3012 [0xdc] = AESNI_OP(aesenc
),
3013 [0xdd] = AESNI_OP(aesenclast
),
3014 [0xde] = AESNI_OP(aesdec
),
3015 [0xdf] = AESNI_OP(aesdeclast
),
3018 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3019 [0x08] = SSE41_OP(roundps
),
3020 [0x09] = SSE41_OP(roundpd
),
3021 [0x0a] = SSE41_OP(roundss
),
3022 [0x0b] = SSE41_OP(roundsd
),
3023 [0x0c] = SSE41_OP(blendps
),
3024 [0x0d] = SSE41_OP(blendpd
),
3025 [0x0e] = SSE41_OP(pblendw
),
3026 [0x0f] = SSSE3_OP(palignr
),
3027 [0x14] = SSE41_SPECIAL
, /* pextrb */
3028 [0x15] = SSE41_SPECIAL
, /* pextrw */
3029 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3030 [0x17] = SSE41_SPECIAL
, /* extractps */
3031 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3032 [0x21] = SSE41_SPECIAL
, /* insertps */
3033 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3034 [0x40] = SSE41_OP(dpps
),
3035 [0x41] = SSE41_OP(dppd
),
3036 [0x42] = SSE41_OP(mpsadbw
),
3037 [0x44] = PCLMULQDQ_OP(pclmulqdq
),
3038 [0x60] = SSE42_OP(pcmpestrm
),
3039 [0x61] = SSE42_OP(pcmpestri
),
3040 [0x62] = SSE42_OP(pcmpistrm
),
3041 [0x63] = SSE42_OP(pcmpistri
),
3042 [0xdf] = AESNI_OP(aeskeygenassist
),
3045 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3046 target_ulong pc_start
, int rex_r
)
3048 int b1
, op1_offset
, op2_offset
, is_xmm
, val
;
3049 int modrm
, mod
, rm
, reg
;
3050 SSEFunc_0_epp sse_fn_epp
;
3051 SSEFunc_0_eppi sse_fn_eppi
;
3052 SSEFunc_0_ppi sse_fn_ppi
;
3053 SSEFunc_0_eppt sse_fn_eppt
;
3057 if (s
->prefix
& PREFIX_DATA
)
3059 else if (s
->prefix
& PREFIX_REPZ
)
3061 else if (s
->prefix
& PREFIX_REPNZ
)
3065 sse_fn_epp
= sse_op_table1
[b
][b1
];
3069 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3079 /* simple MMX/SSE operation */
3080 if (s
->flags
& HF_TS_MASK
) {
3081 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3084 if (s
->flags
& HF_EM_MASK
) {
3086 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3089 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3090 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3093 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3096 gen_helper_emms(cpu_env
);
3101 gen_helper_emms(cpu_env
);
3104 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3105 the static cpu state) */
3107 gen_helper_enter_mmx(cpu_env
);
3110 modrm
= cpu_ldub_code(env
, s
->pc
++);
3111 reg
= ((modrm
>> 3) & 7);
3114 mod
= (modrm
>> 6) & 3;
3115 if (sse_fn_epp
== SSE_SPECIAL
) {
3118 case 0x0e7: /* movntq */
3121 gen_lea_modrm(env
, s
, modrm
);
3122 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3124 case 0x1e7: /* movntdq */
3125 case 0x02b: /* movntps */
3126 case 0x12b: /* movntps */
3129 gen_lea_modrm(env
, s
, modrm
);
3130 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3132 case 0x3f0: /* lddqu */
3135 gen_lea_modrm(env
, s
, modrm
);
3136 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3138 case 0x22b: /* movntss */
3139 case 0x32b: /* movntsd */
3142 gen_lea_modrm(env
, s
, modrm
);
3144 gen_stq_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3146 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3147 xmm_regs
[reg
].XMM_L(0)));
3148 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3151 case 0x6e: /* movd mm, ea */
3152 #ifdef TARGET_X86_64
3153 if (s
->dflag
== MO_64
) {
3154 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3155 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3159 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3160 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3161 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3162 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3163 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3166 case 0x16e: /* movd xmm, ea */
3167 #ifdef TARGET_X86_64
3168 if (s
->dflag
== MO_64
) {
3169 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3170 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3171 offsetof(CPUX86State
,xmm_regs
[reg
]));
3172 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3176 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3177 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3178 offsetof(CPUX86State
,xmm_regs
[reg
]));
3179 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3180 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3183 case 0x6f: /* movq mm, ea */
3185 gen_lea_modrm(env
, s
, modrm
);
3186 gen_ldq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3189 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3190 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3191 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3192 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3195 case 0x010: /* movups */
3196 case 0x110: /* movupd */
3197 case 0x028: /* movaps */
3198 case 0x128: /* movapd */
3199 case 0x16f: /* movdqa xmm, ea */
3200 case 0x26f: /* movdqu xmm, ea */
3202 gen_lea_modrm(env
, s
, modrm
);
3203 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3205 rm
= (modrm
& 7) | REX_B(s
);
3206 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3207 offsetof(CPUX86State
,xmm_regs
[rm
]));
3210 case 0x210: /* movss xmm, ea */
3212 gen_lea_modrm(env
, s
, modrm
);
3213 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3214 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3215 tcg_gen_movi_tl(cpu_T
[0], 0);
3216 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3217 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3218 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3220 rm
= (modrm
& 7) | REX_B(s
);
3221 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3222 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3225 case 0x310: /* movsd xmm, ea */
3227 gen_lea_modrm(env
, s
, modrm
);
3228 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3229 xmm_regs
[reg
].XMM_Q(0)));
3230 tcg_gen_movi_tl(cpu_T
[0], 0);
3231 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3232 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3234 rm
= (modrm
& 7) | REX_B(s
);
3235 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3236 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3239 case 0x012: /* movlps */
3240 case 0x112: /* movlpd */
3242 gen_lea_modrm(env
, s
, modrm
);
3243 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3244 xmm_regs
[reg
].XMM_Q(0)));
3247 rm
= (modrm
& 7) | REX_B(s
);
3248 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3249 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3252 case 0x212: /* movsldup */
3254 gen_lea_modrm(env
, s
, modrm
);
3255 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3257 rm
= (modrm
& 7) | REX_B(s
);
3258 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3259 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3260 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3261 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3263 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3264 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3265 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3266 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3268 case 0x312: /* movddup */
3270 gen_lea_modrm(env
, s
, modrm
);
3271 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3272 xmm_regs
[reg
].XMM_Q(0)));
3274 rm
= (modrm
& 7) | REX_B(s
);
3275 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3276 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3278 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3279 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3281 case 0x016: /* movhps */
3282 case 0x116: /* movhpd */
3284 gen_lea_modrm(env
, s
, modrm
);
3285 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3286 xmm_regs
[reg
].XMM_Q(1)));
3289 rm
= (modrm
& 7) | REX_B(s
);
3290 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3291 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3294 case 0x216: /* movshdup */
3296 gen_lea_modrm(env
, s
, modrm
);
3297 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3299 rm
= (modrm
& 7) | REX_B(s
);
3300 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3301 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3302 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3303 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3305 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3306 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3307 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3308 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3313 int bit_index
, field_length
;
3315 if (b1
== 1 && reg
!= 0)
3317 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3318 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3319 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3320 offsetof(CPUX86State
,xmm_regs
[reg
]));
3322 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3323 tcg_const_i32(bit_index
),
3324 tcg_const_i32(field_length
));
3326 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3327 tcg_const_i32(bit_index
),
3328 tcg_const_i32(field_length
));
3331 case 0x7e: /* movd ea, mm */
3332 #ifdef TARGET_X86_64
3333 if (s
->dflag
== MO_64
) {
3334 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3335 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3336 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3340 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3341 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3342 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3345 case 0x17e: /* movd ea, xmm */
3346 #ifdef TARGET_X86_64
3347 if (s
->dflag
== MO_64
) {
3348 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3349 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3350 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3354 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3355 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3356 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3359 case 0x27e: /* movq xmm, ea */
3361 gen_lea_modrm(env
, s
, modrm
);
3362 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3363 xmm_regs
[reg
].XMM_Q(0)));
3365 rm
= (modrm
& 7) | REX_B(s
);
3366 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3367 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3369 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3371 case 0x7f: /* movq ea, mm */
3373 gen_lea_modrm(env
, s
, modrm
);
3374 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3377 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3378 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3381 case 0x011: /* movups */
3382 case 0x111: /* movupd */
3383 case 0x029: /* movaps */
3384 case 0x129: /* movapd */
3385 case 0x17f: /* movdqa ea, xmm */
3386 case 0x27f: /* movdqu ea, xmm */
3388 gen_lea_modrm(env
, s
, modrm
);
3389 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3391 rm
= (modrm
& 7) | REX_B(s
);
3392 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3393 offsetof(CPUX86State
,xmm_regs
[reg
]));
3396 case 0x211: /* movss ea, xmm */
3398 gen_lea_modrm(env
, s
, modrm
);
3399 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3400 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3402 rm
= (modrm
& 7) | REX_B(s
);
3403 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3404 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3407 case 0x311: /* movsd ea, xmm */
3409 gen_lea_modrm(env
, s
, modrm
);
3410 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3411 xmm_regs
[reg
].XMM_Q(0)));
3413 rm
= (modrm
& 7) | REX_B(s
);
3414 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3415 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3418 case 0x013: /* movlps */
3419 case 0x113: /* movlpd */
3421 gen_lea_modrm(env
, s
, modrm
);
3422 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3423 xmm_regs
[reg
].XMM_Q(0)));
3428 case 0x017: /* movhps */
3429 case 0x117: /* movhpd */
3431 gen_lea_modrm(env
, s
, modrm
);
3432 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3433 xmm_regs
[reg
].XMM_Q(1)));
3438 case 0x71: /* shift mm, im */
3441 case 0x171: /* shift xmm, im */
3447 val
= cpu_ldub_code(env
, s
->pc
++);
3449 tcg_gen_movi_tl(cpu_T
[0], val
);
3450 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3451 tcg_gen_movi_tl(cpu_T
[0], 0);
3452 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3453 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3455 tcg_gen_movi_tl(cpu_T
[0], val
);
3456 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3457 tcg_gen_movi_tl(cpu_T
[0], 0);
3458 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3459 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3461 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3462 (((modrm
>> 3)) & 7)][b1
];
3467 rm
= (modrm
& 7) | REX_B(s
);
3468 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3471 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3473 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3474 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3475 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3477 case 0x050: /* movmskps */
3478 rm
= (modrm
& 7) | REX_B(s
);
3479 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3480 offsetof(CPUX86State
,xmm_regs
[rm
]));
3481 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3482 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3484 case 0x150: /* movmskpd */
3485 rm
= (modrm
& 7) | REX_B(s
);
3486 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3487 offsetof(CPUX86State
,xmm_regs
[rm
]));
3488 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3489 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3491 case 0x02a: /* cvtpi2ps */
3492 case 0x12a: /* cvtpi2pd */
3493 gen_helper_enter_mmx(cpu_env
);
3495 gen_lea_modrm(env
, s
, modrm
);
3496 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3497 gen_ldq_env_A0(s
, op2_offset
);
3500 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3502 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3503 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3504 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3507 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3511 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3515 case 0x22a: /* cvtsi2ss */
3516 case 0x32a: /* cvtsi2sd */
3517 ot
= mo_64_32(s
->dflag
);
3518 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3519 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3520 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3522 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3523 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3524 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3526 #ifdef TARGET_X86_64
3527 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3528 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3534 case 0x02c: /* cvttps2pi */
3535 case 0x12c: /* cvttpd2pi */
3536 case 0x02d: /* cvtps2pi */
3537 case 0x12d: /* cvtpd2pi */
3538 gen_helper_enter_mmx(cpu_env
);
3540 gen_lea_modrm(env
, s
, modrm
);
3541 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3542 gen_ldo_env_A0(s
, op2_offset
);
3544 rm
= (modrm
& 7) | REX_B(s
);
3545 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3547 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3548 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3549 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3552 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3555 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3558 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3561 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3565 case 0x22c: /* cvttss2si */
3566 case 0x32c: /* cvttsd2si */
3567 case 0x22d: /* cvtss2si */
3568 case 0x32d: /* cvtsd2si */
3569 ot
= mo_64_32(s
->dflag
);
3571 gen_lea_modrm(env
, s
, modrm
);
3573 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_Q(0)));
3575 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3576 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3578 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3580 rm
= (modrm
& 7) | REX_B(s
);
3581 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3583 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3585 SSEFunc_i_ep sse_fn_i_ep
=
3586 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3587 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3588 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3590 #ifdef TARGET_X86_64
3591 SSEFunc_l_ep sse_fn_l_ep
=
3592 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3593 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3598 gen_op_mov_reg_T0(ot
, reg
);
3600 case 0xc4: /* pinsrw */
3603 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
3604 val
= cpu_ldub_code(env
, s
->pc
++);
3607 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3608 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3611 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3612 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3615 case 0xc5: /* pextrw */
3619 ot
= mo_64_32(s
->dflag
);
3620 val
= cpu_ldub_code(env
, s
->pc
++);
3623 rm
= (modrm
& 7) | REX_B(s
);
3624 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3625 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3629 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3630 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3632 reg
= ((modrm
>> 3) & 7) | rex_r
;
3633 gen_op_mov_reg_T0(ot
, reg
);
3635 case 0x1d6: /* movq ea, xmm */
3637 gen_lea_modrm(env
, s
, modrm
);
3638 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3639 xmm_regs
[reg
].XMM_Q(0)));
3641 rm
= (modrm
& 7) | REX_B(s
);
3642 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3643 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3644 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3647 case 0x2d6: /* movq2dq */
3648 gen_helper_enter_mmx(cpu_env
);
3650 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3651 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3652 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3654 case 0x3d6: /* movdq2q */
3655 gen_helper_enter_mmx(cpu_env
);
3656 rm
= (modrm
& 7) | REX_B(s
);
3657 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3658 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3660 case 0xd7: /* pmovmskb */
3665 rm
= (modrm
& 7) | REX_B(s
);
3666 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3667 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3670 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3671 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3673 reg
= ((modrm
>> 3) & 7) | rex_r
;
3674 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3680 if ((b
& 0xf0) == 0xf0) {
3683 modrm
= cpu_ldub_code(env
, s
->pc
++);
3685 reg
= ((modrm
>> 3) & 7) | rex_r
;
3686 mod
= (modrm
>> 6) & 3;
3691 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3695 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3699 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3701 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3703 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3704 gen_lea_modrm(env
, s
, modrm
);
3706 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3707 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3708 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3709 gen_ldq_env_A0(s
, op2_offset
+
3710 offsetof(XMMReg
, XMM_Q(0)));
3712 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3713 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3714 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
3715 s
->mem_index
, MO_LEUL
);
3716 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3717 offsetof(XMMReg
, XMM_L(0)));
3719 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3720 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
3721 s
->mem_index
, MO_LEUW
);
3722 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3723 offsetof(XMMReg
, XMM_W(0)));
3725 case 0x2a: /* movntqda */
3726 gen_ldo_env_A0(s
, op1_offset
);
3729 gen_ldo_env_A0(s
, op2_offset
);
3733 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3735 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3737 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3738 gen_lea_modrm(env
, s
, modrm
);
3739 gen_ldq_env_A0(s
, op2_offset
);
3742 if (sse_fn_epp
== SSE_SPECIAL
) {
3746 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3747 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3748 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3751 set_cc_op(s
, CC_OP_EFLAGS
);
3758 /* Various integer extensions at 0f 38 f[0-f]. */
3759 b
= modrm
| (b1
<< 8);
3760 modrm
= cpu_ldub_code(env
, s
->pc
++);
3761 reg
= ((modrm
>> 3) & 7) | rex_r
;
3764 case 0x3f0: /* crc32 Gd,Eb */
3765 case 0x3f1: /* crc32 Gd,Ey */
3767 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
)) {
3770 if ((b
& 0xff) == 0xf0) {
3772 } else if (s
->dflag
!= MO_64
) {
3773 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3778 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[reg
]);
3779 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3780 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3781 cpu_T
[0], tcg_const_i32(8 << ot
));
3783 ot
= mo_64_32(s
->dflag
);
3784 gen_op_mov_reg_T0(ot
, reg
);
3787 case 0x1f0: /* crc32 or movbe */
3789 /* For these insns, the f3 prefix is supposed to have priority
3790 over the 66 prefix, but that's not what we implement above
3792 if (s
->prefix
& PREFIX_REPNZ
) {
3796 case 0x0f0: /* movbe Gy,My */
3797 case 0x0f1: /* movbe My,Gy */
3798 if (!(s
->cpuid_ext_features
& CPUID_EXT_MOVBE
)) {
3801 if (s
->dflag
!= MO_64
) {
3802 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3807 gen_lea_modrm(env
, s
, modrm
);
3809 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
3810 s
->mem_index
, ot
| MO_BE
);
3811 gen_op_mov_reg_T0(ot
, reg
);
3813 tcg_gen_qemu_st_tl(cpu_regs
[reg
], cpu_A0
,
3814 s
->mem_index
, ot
| MO_BE
);
3818 case 0x0f2: /* andn Gy, By, Ey */
3819 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3820 || !(s
->prefix
& PREFIX_VEX
)
3824 ot
= mo_64_32(s
->dflag
);
3825 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3826 tcg_gen_andc_tl(cpu_T
[0], cpu_regs
[s
->vex_v
], cpu_T
[0]);
3827 gen_op_mov_reg_T0(ot
, reg
);
3828 gen_op_update1_cc();
3829 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3832 case 0x0f7: /* bextr Gy, Ey, By */
3833 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3834 || !(s
->prefix
& PREFIX_VEX
)
3838 ot
= mo_64_32(s
->dflag
);
3842 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3843 /* Extract START, and shift the operand.
3844 Shifts larger than operand size get zeros. */
3845 tcg_gen_ext8u_tl(cpu_A0
, cpu_regs
[s
->vex_v
]);
3846 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3848 bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3849 zero
= tcg_const_tl(0);
3850 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_T
[0], cpu_A0
, bound
,
3852 tcg_temp_free(zero
);
3854 /* Extract the LEN into a mask. Lengths larger than
3855 operand size get all ones. */
3856 tcg_gen_shri_tl(cpu_A0
, cpu_regs
[s
->vex_v
], 8);
3857 tcg_gen_ext8u_tl(cpu_A0
, cpu_A0
);
3858 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_A0
, cpu_A0
, bound
,
3860 tcg_temp_free(bound
);
3861 tcg_gen_movi_tl(cpu_T
[1], 1);
3862 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_A0
);
3863 tcg_gen_subi_tl(cpu_T
[1], cpu_T
[1], 1);
3864 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3866 gen_op_mov_reg_T0(ot
, reg
);
3867 gen_op_update1_cc();
3868 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3872 case 0x0f5: /* bzhi Gy, Ey, By */
3873 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3874 || !(s
->prefix
& PREFIX_VEX
)
3878 ot
= mo_64_32(s
->dflag
);
3879 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3880 tcg_gen_ext8u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3882 TCGv bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3883 /* Note that since we're using BMILG (in order to get O
3884 cleared) we need to store the inverse into C. */
3885 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_cc_src
,
3887 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_T
[1], cpu_T
[1],
3888 bound
, bound
, cpu_T
[1]);
3889 tcg_temp_free(bound
);
3891 tcg_gen_movi_tl(cpu_A0
, -1);
3892 tcg_gen_shl_tl(cpu_A0
, cpu_A0
, cpu_T
[1]);
3893 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3894 gen_op_mov_reg_T0(ot
, reg
);
3895 gen_op_update1_cc();
3896 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
3899 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3900 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3901 || !(s
->prefix
& PREFIX_VEX
)
3905 ot
= mo_64_32(s
->dflag
);
3906 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3909 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3910 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EDX
]);
3911 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
3912 cpu_tmp2_i32
, cpu_tmp3_i32
);
3913 tcg_gen_extu_i32_tl(cpu_regs
[s
->vex_v
], cpu_tmp2_i32
);
3914 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp3_i32
);
3916 #ifdef TARGET_X86_64
3918 tcg_gen_mulu2_i64(cpu_regs
[s
->vex_v
], cpu_regs
[reg
],
3919 cpu_T
[0], cpu_regs
[R_EDX
]);
3925 case 0x3f5: /* pdep Gy, By, Ey */
3926 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3927 || !(s
->prefix
& PREFIX_VEX
)
3931 ot
= mo_64_32(s
->dflag
);
3932 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3933 /* Note that by zero-extending the mask operand, we
3934 automatically handle zero-extending the result. */
3936 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3938 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3940 gen_helper_pdep(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3943 case 0x2f5: /* pext Gy, By, Ey */
3944 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3945 || !(s
->prefix
& PREFIX_VEX
)
3949 ot
= mo_64_32(s
->dflag
);
3950 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3951 /* Note that by zero-extending the mask operand, we
3952 automatically handle zero-extending the result. */
3954 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3956 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3958 gen_helper_pext(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3961 case 0x1f6: /* adcx Gy, Ey */
3962 case 0x2f6: /* adox Gy, Ey */
3963 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_ADX
)) {
3966 TCGv carry_in
, carry_out
, zero
;
3969 ot
= mo_64_32(s
->dflag
);
3970 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3972 /* Re-use the carry-out from a previous round. */
3973 TCGV_UNUSED(carry_in
);
3974 carry_out
= (b
== 0x1f6 ? cpu_cc_dst
: cpu_cc_src2
);
3978 carry_in
= cpu_cc_dst
;
3979 end_op
= CC_OP_ADCX
;
3981 end_op
= CC_OP_ADCOX
;
3986 end_op
= CC_OP_ADCOX
;
3988 carry_in
= cpu_cc_src2
;
3989 end_op
= CC_OP_ADOX
;
3993 end_op
= CC_OP_ADCOX
;
3994 carry_in
= carry_out
;
3997 end_op
= (b
== 0x1f6 ? CC_OP_ADCX
: CC_OP_ADOX
);
4000 /* If we can't reuse carry-out, get it out of EFLAGS. */
4001 if (TCGV_IS_UNUSED(carry_in
)) {
4002 if (s
->cc_op
!= CC_OP_ADCX
&& s
->cc_op
!= CC_OP_ADOX
) {
4003 gen_compute_eflags(s
);
4005 carry_in
= cpu_tmp0
;
4006 tcg_gen_shri_tl(carry_in
, cpu_cc_src
,
4007 ctz32(b
== 0x1f6 ? CC_C
: CC_O
));
4008 tcg_gen_andi_tl(carry_in
, carry_in
, 1);
4012 #ifdef TARGET_X86_64
4014 /* If we know TL is 64-bit, and we want a 32-bit
4015 result, just do everything in 64-bit arithmetic. */
4016 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_regs
[reg
]);
4017 tcg_gen_ext32u_i64(cpu_T
[0], cpu_T
[0]);
4018 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_regs
[reg
]);
4019 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], carry_in
);
4020 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_T
[0]);
4021 tcg_gen_shri_i64(carry_out
, cpu_T
[0], 32);
4025 /* Otherwise compute the carry-out in two steps. */
4026 zero
= tcg_const_tl(0);
4027 tcg_gen_add2_tl(cpu_T
[0], carry_out
,
4030 tcg_gen_add2_tl(cpu_regs
[reg
], carry_out
,
4031 cpu_regs
[reg
], carry_out
,
4033 tcg_temp_free(zero
);
4036 set_cc_op(s
, end_op
);
4040 case 0x1f7: /* shlx Gy, Ey, By */
4041 case 0x2f7: /* sarx Gy, Ey, By */
4042 case 0x3f7: /* shrx Gy, Ey, By */
4043 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4044 || !(s
->prefix
& PREFIX_VEX
)
4048 ot
= mo_64_32(s
->dflag
);
4049 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4051 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 63);
4053 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 31);
4056 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4057 } else if (b
== 0x2f7) {
4059 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4061 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4064 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4066 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4068 gen_op_mov_reg_T0(ot
, reg
);
4074 case 0x3f3: /* Group 17 */
4075 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
4076 || !(s
->prefix
& PREFIX_VEX
)
4080 ot
= mo_64_32(s
->dflag
);
4081 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4084 case 1: /* blsr By,Ey */
4085 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[0]);
4086 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4087 gen_op_mov_reg_T0(ot
, s
->vex_v
);
4088 gen_op_update2_cc();
4089 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4092 case 2: /* blsmsk By,Ey */
4093 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4094 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4095 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4096 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4097 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4100 case 3: /* blsi By, Ey */
4101 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4102 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4103 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4104 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4105 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4121 modrm
= cpu_ldub_code(env
, s
->pc
++);
4123 reg
= ((modrm
>> 3) & 7) | rex_r
;
4124 mod
= (modrm
>> 6) & 3;
4129 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4133 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4136 if (sse_fn_eppi
== SSE_SPECIAL
) {
4137 ot
= mo_64_32(s
->dflag
);
4138 rm
= (modrm
& 7) | REX_B(s
);
4140 gen_lea_modrm(env
, s
, modrm
);
4141 reg
= ((modrm
>> 3) & 7) | rex_r
;
4142 val
= cpu_ldub_code(env
, s
->pc
++);
4144 case 0x14: /* pextrb */
4145 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4146 xmm_regs
[reg
].XMM_B(val
& 15)));
4148 gen_op_mov_reg_T0(ot
, rm
);
4150 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4151 s
->mem_index
, MO_UB
);
4154 case 0x15: /* pextrw */
4155 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4156 xmm_regs
[reg
].XMM_W(val
& 7)));
4158 gen_op_mov_reg_T0(ot
, rm
);
4160 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4161 s
->mem_index
, MO_LEUW
);
4165 if (ot
== MO_32
) { /* pextrd */
4166 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4167 offsetof(CPUX86State
,
4168 xmm_regs
[reg
].XMM_L(val
& 3)));
4170 tcg_gen_extu_i32_tl(cpu_regs
[rm
], cpu_tmp2_i32
);
4172 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
4173 s
->mem_index
, MO_LEUL
);
4175 } else { /* pextrq */
4176 #ifdef TARGET_X86_64
4177 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4178 offsetof(CPUX86State
,
4179 xmm_regs
[reg
].XMM_Q(val
& 1)));
4181 tcg_gen_mov_i64(cpu_regs
[rm
], cpu_tmp1_i64
);
4183 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
4184 s
->mem_index
, MO_LEQ
);
4191 case 0x17: /* extractps */
4192 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4193 xmm_regs
[reg
].XMM_L(val
& 3)));
4195 gen_op_mov_reg_T0(ot
, rm
);
4197 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4198 s
->mem_index
, MO_LEUL
);
4201 case 0x20: /* pinsrb */
4203 gen_op_mov_TN_reg(MO_32
, 0, rm
);
4205 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
4206 s
->mem_index
, MO_UB
);
4208 tcg_gen_st8_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4209 xmm_regs
[reg
].XMM_B(val
& 15)));
4211 case 0x21: /* insertps */
4213 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4214 offsetof(CPUX86State
,xmm_regs
[rm
]
4215 .XMM_L((val
>> 6) & 3)));
4217 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4218 s
->mem_index
, MO_LEUL
);
4220 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4221 offsetof(CPUX86State
,xmm_regs
[reg
]
4222 .XMM_L((val
>> 4) & 3)));
4224 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4225 cpu_env
, offsetof(CPUX86State
,
4226 xmm_regs
[reg
].XMM_L(0)));
4228 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4229 cpu_env
, offsetof(CPUX86State
,
4230 xmm_regs
[reg
].XMM_L(1)));
4232 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4233 cpu_env
, offsetof(CPUX86State
,
4234 xmm_regs
[reg
].XMM_L(2)));
4236 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4237 cpu_env
, offsetof(CPUX86State
,
4238 xmm_regs
[reg
].XMM_L(3)));
4241 if (ot
== MO_32
) { /* pinsrd */
4243 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[rm
]);
4245 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4246 s
->mem_index
, MO_LEUL
);
4248 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4249 offsetof(CPUX86State
,
4250 xmm_regs
[reg
].XMM_L(val
& 3)));
4251 } else { /* pinsrq */
4252 #ifdef TARGET_X86_64
4254 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4256 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
4257 s
->mem_index
, MO_LEQ
);
4259 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4260 offsetof(CPUX86State
,
4261 xmm_regs
[reg
].XMM_Q(val
& 1)));
4272 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4274 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4276 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4277 gen_lea_modrm(env
, s
, modrm
);
4278 gen_ldo_env_A0(s
, op2_offset
);
4281 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4283 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4285 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4286 gen_lea_modrm(env
, s
, modrm
);
4287 gen_ldq_env_A0(s
, op2_offset
);
4290 val
= cpu_ldub_code(env
, s
->pc
++);
4292 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4293 set_cc_op(s
, CC_OP_EFLAGS
);
4295 if (s
->dflag
== MO_64
) {
4296 /* The helper must use entire 64-bit gp registers */
4301 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4302 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4303 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4307 /* Various integer extensions at 0f 3a f[0-f]. */
4308 b
= modrm
| (b1
<< 8);
4309 modrm
= cpu_ldub_code(env
, s
->pc
++);
4310 reg
= ((modrm
>> 3) & 7) | rex_r
;
4313 case 0x3f0: /* rorx Gy,Ey, Ib */
4314 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4315 || !(s
->prefix
& PREFIX_VEX
)
4319 ot
= mo_64_32(s
->dflag
);
4320 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4321 b
= cpu_ldub_code(env
, s
->pc
++);
4323 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], b
& 63);
4325 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4326 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, b
& 31);
4327 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4329 gen_op_mov_reg_T0(ot
, reg
);
4341 /* generic MMX or SSE operation */
4343 case 0x70: /* pshufx insn */
4344 case 0xc6: /* pshufx insn */
4345 case 0xc2: /* compare insns */
4352 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4354 gen_lea_modrm(env
, s
, modrm
);
4355 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4356 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4358 /* specific case for SSE single instructions */
4361 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
4362 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4365 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
4369 gen_ldo_env_A0(s
, op2_offset
);
4372 rm
= (modrm
& 7) | REX_B(s
);
4373 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4376 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4378 gen_lea_modrm(env
, s
, modrm
);
4379 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4380 gen_ldq_env_A0(s
, op2_offset
);
4383 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4387 case 0x0f: /* 3DNow! data insns */
4388 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4390 val
= cpu_ldub_code(env
, s
->pc
++);
4391 sse_fn_epp
= sse_op_table5
[val
];
4395 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4396 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4397 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4399 case 0x70: /* pshufx insn */
4400 case 0xc6: /* pshufx insn */
4401 val
= cpu_ldub_code(env
, s
->pc
++);
4402 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4403 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4404 /* XXX: introduce a new table? */
4405 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4406 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4410 val
= cpu_ldub_code(env
, s
->pc
++);
4413 sse_fn_epp
= sse_op_table4
[val
][b1
];
4415 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4416 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4417 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4420 /* maskmov : we must prepare A0 */
4423 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EDI
]);
4424 gen_extu(s
->aflag
, cpu_A0
);
4425 gen_add_A0_ds_seg(s
);
4427 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4428 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4429 /* XXX: introduce a new table? */
4430 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4431 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4434 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4435 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4436 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4439 if (b
== 0x2e || b
== 0x2f) {
4440 set_cc_op(s
, CC_OP_EFLAGS
);
4445 /* convert one instruction. s->is_jmp is set if the translation must
4446 be stopped. Return the next pc value */
4447 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4448 target_ulong pc_start
)
4452 TCGMemOp ot
, aflag
, dflag
;
4453 int modrm
, reg
, rm
, mod
, op
, opreg
, val
;
4454 target_ulong next_eip
, tval
;
4457 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4458 tcg_gen_debug_insn_start(pc_start
);
4465 #ifdef TARGET_X86_64
4470 s
->rip_offset
= 0; /* for relative ip address */
4474 b
= cpu_ldub_code(env
, s
->pc
);
4476 /* Collect prefixes. */
4479 prefixes
|= PREFIX_REPZ
;
4482 prefixes
|= PREFIX_REPNZ
;
4485 prefixes
|= PREFIX_LOCK
;
4506 prefixes
|= PREFIX_DATA
;
4509 prefixes
|= PREFIX_ADR
;
4511 #ifdef TARGET_X86_64
4515 rex_w
= (b
>> 3) & 1;
4516 rex_r
= (b
& 0x4) << 1;
4517 s
->rex_x
= (b
& 0x2) << 2;
4518 REX_B(s
) = (b
& 0x1) << 3;
4519 x86_64_hregs
= 1; /* select uniform byte register addressing */
4524 case 0xc5: /* 2-byte VEX */
4525 case 0xc4: /* 3-byte VEX */
4526 /* VEX prefixes cannot be used except in 32-bit mode.
4527 Otherwise the instruction is LES or LDS. */
4528 if (s
->code32
&& !s
->vm86
) {
4529 static const int pp_prefix
[4] = {
4530 0, PREFIX_DATA
, PREFIX_REPZ
, PREFIX_REPNZ
4532 int vex3
, vex2
= cpu_ldub_code(env
, s
->pc
);
4534 if (!CODE64(s
) && (vex2
& 0xc0) != 0xc0) {
4535 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4536 otherwise the instruction is LES or LDS. */
4541 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4542 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
4543 | PREFIX_LOCK
| PREFIX_DATA
)) {
4546 #ifdef TARGET_X86_64
4551 rex_r
= (~vex2
>> 4) & 8;
4554 b
= cpu_ldub_code(env
, s
->pc
++);
4556 #ifdef TARGET_X86_64
4557 s
->rex_x
= (~vex2
>> 3) & 8;
4558 s
->rex_b
= (~vex2
>> 2) & 8;
4560 vex3
= cpu_ldub_code(env
, s
->pc
++);
4561 rex_w
= (vex3
>> 7) & 1;
4562 switch (vex2
& 0x1f) {
4563 case 0x01: /* Implied 0f leading opcode bytes. */
4564 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4566 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4569 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4572 default: /* Reserved for future use. */
4576 s
->vex_v
= (~vex3
>> 3) & 0xf;
4577 s
->vex_l
= (vex3
>> 2) & 1;
4578 prefixes
|= pp_prefix
[vex3
& 3] | PREFIX_VEX
;
4583 /* Post-process prefixes. */
4585 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4586 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4587 over 0x66 if both are present. */
4588 dflag
= (rex_w
> 0 ? MO_64
: prefixes
& PREFIX_DATA
? MO_16
: MO_32
);
4589 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4590 aflag
= (prefixes
& PREFIX_ADR
? MO_32
: MO_64
);
4592 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4593 if (s
->code32
^ ((prefixes
& PREFIX_DATA
) != 0)) {
4598 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4599 if (s
->code32
^ ((prefixes
& PREFIX_ADR
) != 0)) {
4606 s
->prefix
= prefixes
;
4610 /* lock generation */
4611 if (prefixes
& PREFIX_LOCK
)
4614 /* now check op code */
4618 /**************************/
4619 /* extended op code */
4620 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4623 /**************************/
4638 ot
= mo_b_d(b
, dflag
);
4641 case 0: /* OP Ev, Gv */
4642 modrm
= cpu_ldub_code(env
, s
->pc
++);
4643 reg
= ((modrm
>> 3) & 7) | rex_r
;
4644 mod
= (modrm
>> 6) & 3;
4645 rm
= (modrm
& 7) | REX_B(s
);
4647 gen_lea_modrm(env
, s
, modrm
);
4649 } else if (op
== OP_XORL
&& rm
== reg
) {
4651 /* xor reg, reg optimisation */
4652 set_cc_op(s
, CC_OP_CLR
);
4653 tcg_gen_movi_tl(cpu_T
[0], 0);
4654 gen_op_mov_reg_T0(ot
, reg
);
4659 gen_op_mov_TN_reg(ot
, 1, reg
);
4660 gen_op(s
, op
, ot
, opreg
);
4662 case 1: /* OP Gv, Ev */
4663 modrm
= cpu_ldub_code(env
, s
->pc
++);
4664 mod
= (modrm
>> 6) & 3;
4665 reg
= ((modrm
>> 3) & 7) | rex_r
;
4666 rm
= (modrm
& 7) | REX_B(s
);
4668 gen_lea_modrm(env
, s
, modrm
);
4669 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4670 } else if (op
== OP_XORL
&& rm
== reg
) {
4673 gen_op_mov_TN_reg(ot
, 1, rm
);
4675 gen_op(s
, op
, ot
, reg
);
4677 case 2: /* OP A, Iv */
4678 val
= insn_get(env
, s
, ot
);
4679 tcg_gen_movi_tl(cpu_T
[1], val
);
4680 gen_op(s
, op
, ot
, OR_EAX
);
4689 case 0x80: /* GRP1 */
4695 ot
= mo_b_d(b
, dflag
);
4697 modrm
= cpu_ldub_code(env
, s
->pc
++);
4698 mod
= (modrm
>> 6) & 3;
4699 rm
= (modrm
& 7) | REX_B(s
);
4700 op
= (modrm
>> 3) & 7;
4706 s
->rip_offset
= insn_const_size(ot
);
4707 gen_lea_modrm(env
, s
, modrm
);
4718 val
= insn_get(env
, s
, ot
);
4721 val
= (int8_t)insn_get(env
, s
, MO_8
);
4724 tcg_gen_movi_tl(cpu_T
[1], val
);
4725 gen_op(s
, op
, ot
, opreg
);
4729 /**************************/
4730 /* inc, dec, and other misc arith */
4731 case 0x40 ... 0x47: /* inc Gv */
4733 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4735 case 0x48 ... 0x4f: /* dec Gv */
4737 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4739 case 0xf6: /* GRP3 */
4741 ot
= mo_b_d(b
, dflag
);
4743 modrm
= cpu_ldub_code(env
, s
->pc
++);
4744 mod
= (modrm
>> 6) & 3;
4745 rm
= (modrm
& 7) | REX_B(s
);
4746 op
= (modrm
>> 3) & 7;
4749 s
->rip_offset
= insn_const_size(ot
);
4750 gen_lea_modrm(env
, s
, modrm
);
4751 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4753 gen_op_mov_TN_reg(ot
, 0, rm
);
4758 val
= insn_get(env
, s
, ot
);
4759 tcg_gen_movi_tl(cpu_T
[1], val
);
4760 gen_op_testl_T0_T1_cc();
4761 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4764 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4766 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4768 gen_op_mov_reg_T0(ot
, rm
);
4772 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4774 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4776 gen_op_mov_reg_T0(ot
, rm
);
4778 gen_op_update_neg_cc();
4779 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4784 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4785 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4786 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4787 /* XXX: use 32 bit mul which could be faster */
4788 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4789 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4790 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4791 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4792 set_cc_op(s
, CC_OP_MULB
);
4795 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4796 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4797 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4798 /* XXX: use 32 bit mul which could be faster */
4799 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4800 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4801 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4802 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4803 gen_op_mov_reg_T0(MO_16
, R_EDX
);
4804 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4805 set_cc_op(s
, CC_OP_MULW
);
4809 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4810 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4811 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4812 cpu_tmp2_i32
, cpu_tmp3_i32
);
4813 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4814 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4815 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4816 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4817 set_cc_op(s
, CC_OP_MULL
);
4819 #ifdef TARGET_X86_64
4821 tcg_gen_mulu2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4822 cpu_T
[0], cpu_regs
[R_EAX
]);
4823 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4824 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4825 set_cc_op(s
, CC_OP_MULQ
);
4833 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4834 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4835 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4836 /* XXX: use 32 bit mul which could be faster */
4837 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4838 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4839 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4840 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4841 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4842 set_cc_op(s
, CC_OP_MULB
);
4845 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4846 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4847 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4848 /* XXX: use 32 bit mul which could be faster */
4849 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4850 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4851 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4852 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4853 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4854 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4855 gen_op_mov_reg_T0(MO_16
, R_EDX
);
4856 set_cc_op(s
, CC_OP_MULW
);
4860 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4861 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4862 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4863 cpu_tmp2_i32
, cpu_tmp3_i32
);
4864 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4865 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4866 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
4867 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4868 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
4869 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
4870 set_cc_op(s
, CC_OP_MULL
);
4872 #ifdef TARGET_X86_64
4874 tcg_gen_muls2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4875 cpu_T
[0], cpu_regs
[R_EAX
]);
4876 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4877 tcg_gen_sari_tl(cpu_cc_src
, cpu_regs
[R_EAX
], 63);
4878 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_regs
[R_EDX
]);
4879 set_cc_op(s
, CC_OP_MULQ
);
4887 gen_jmp_im(pc_start
- s
->cs_base
);
4888 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4891 gen_jmp_im(pc_start
- s
->cs_base
);
4892 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4896 gen_jmp_im(pc_start
- s
->cs_base
);
4897 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4899 #ifdef TARGET_X86_64
4901 gen_jmp_im(pc_start
- s
->cs_base
);
4902 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4910 gen_jmp_im(pc_start
- s
->cs_base
);
4911 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4914 gen_jmp_im(pc_start
- s
->cs_base
);
4915 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4919 gen_jmp_im(pc_start
- s
->cs_base
);
4920 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4922 #ifdef TARGET_X86_64
4924 gen_jmp_im(pc_start
- s
->cs_base
);
4925 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4935 case 0xfe: /* GRP4 */
4936 case 0xff: /* GRP5 */
4937 ot
= mo_b_d(b
, dflag
);
4939 modrm
= cpu_ldub_code(env
, s
->pc
++);
4940 mod
= (modrm
>> 6) & 3;
4941 rm
= (modrm
& 7) | REX_B(s
);
4942 op
= (modrm
>> 3) & 7;
4943 if (op
>= 2 && b
== 0xfe) {
4947 if (op
== 2 || op
== 4) {
4948 /* operand size for jumps is 64 bit */
4950 } else if (op
== 3 || op
== 5) {
4951 ot
= dflag
!= MO_16
? MO_32
+ (rex_w
== 1) : MO_16
;
4952 } else if (op
== 6) {
4953 /* default push size is 64 bit */
4954 ot
= mo_pushpop(s
, dflag
);
4958 gen_lea_modrm(env
, s
, modrm
);
4959 if (op
>= 2 && op
!= 3 && op
!= 5)
4960 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4962 gen_op_mov_TN_reg(ot
, 0, rm
);
4966 case 0: /* inc Ev */
4971 gen_inc(s
, ot
, opreg
, 1);
4973 case 1: /* dec Ev */
4978 gen_inc(s
, ot
, opreg
, -1);
4980 case 2: /* call Ev */
4981 /* XXX: optimize if memory (no 'and' is necessary) */
4982 if (dflag
== MO_16
) {
4983 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4985 next_eip
= s
->pc
- s
->cs_base
;
4986 tcg_gen_movi_tl(cpu_T
[1], next_eip
);
4991 case 3: /* lcall Ev */
4992 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4993 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
4994 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4996 if (s
->pe
&& !s
->vm86
) {
4997 gen_update_cc_op(s
);
4998 gen_jmp_im(pc_start
- s
->cs_base
);
4999 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5000 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5001 tcg_const_i32(dflag
- 1),
5002 tcg_const_i32(s
->pc
- pc_start
));
5004 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5005 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5006 tcg_const_i32(dflag
- 1),
5007 tcg_const_i32(s
->pc
- s
->cs_base
));
5011 case 4: /* jmp Ev */
5012 if (dflag
== MO_16
) {
5013 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5018 case 5: /* ljmp Ev */
5019 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5020 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5021 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5023 if (s
->pe
&& !s
->vm86
) {
5024 gen_update_cc_op(s
);
5025 gen_jmp_im(pc_start
- s
->cs_base
);
5026 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5027 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5028 tcg_const_i32(s
->pc
- pc_start
));
5030 gen_op_movl_seg_T0_vm(R_CS
);
5031 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
5036 case 6: /* push Ev */
5044 case 0x84: /* test Ev, Gv */
5046 ot
= mo_b_d(b
, dflag
);
5048 modrm
= cpu_ldub_code(env
, s
->pc
++);
5049 reg
= ((modrm
>> 3) & 7) | rex_r
;
5051 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5052 gen_op_mov_TN_reg(ot
, 1, reg
);
5053 gen_op_testl_T0_T1_cc();
5054 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5057 case 0xa8: /* test eAX, Iv */
5059 ot
= mo_b_d(b
, dflag
);
5060 val
= insn_get(env
, s
, ot
);
5062 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
5063 tcg_gen_movi_tl(cpu_T
[1], val
);
5064 gen_op_testl_T0_T1_cc();
5065 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5068 case 0x98: /* CWDE/CBW */
5070 #ifdef TARGET_X86_64
5072 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5073 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5074 gen_op_mov_reg_T0(MO_64
, R_EAX
);
5078 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5079 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5080 gen_op_mov_reg_T0(MO_32
, R_EAX
);
5083 gen_op_mov_TN_reg(MO_8
, 0, R_EAX
);
5084 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5085 gen_op_mov_reg_T0(MO_16
, R_EAX
);
5091 case 0x99: /* CDQ/CWD */
5093 #ifdef TARGET_X86_64
5095 gen_op_mov_TN_reg(MO_64
, 0, R_EAX
);
5096 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
5097 gen_op_mov_reg_T0(MO_64
, R_EDX
);
5101 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5102 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5103 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
5104 gen_op_mov_reg_T0(MO_32
, R_EDX
);
5107 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5108 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5109 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
5110 gen_op_mov_reg_T0(MO_16
, R_EDX
);
5116 case 0x1af: /* imul Gv, Ev */
5117 case 0x69: /* imul Gv, Ev, I */
5120 modrm
= cpu_ldub_code(env
, s
->pc
++);
5121 reg
= ((modrm
>> 3) & 7) | rex_r
;
5123 s
->rip_offset
= insn_const_size(ot
);
5126 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5128 val
= insn_get(env
, s
, ot
);
5129 tcg_gen_movi_tl(cpu_T
[1], val
);
5130 } else if (b
== 0x6b) {
5131 val
= (int8_t)insn_get(env
, s
, MO_8
);
5132 tcg_gen_movi_tl(cpu_T
[1], val
);
5134 gen_op_mov_TN_reg(ot
, 1, reg
);
5137 #ifdef TARGET_X86_64
5139 tcg_gen_muls2_i64(cpu_regs
[reg
], cpu_T
[1], cpu_T
[0], cpu_T
[1]);
5140 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5141 tcg_gen_sari_tl(cpu_cc_src
, cpu_cc_dst
, 63);
5142 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[1]);
5146 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5147 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5148 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
5149 cpu_tmp2_i32
, cpu_tmp3_i32
);
5150 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
5151 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
5152 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5153 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
5154 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
5157 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5158 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5159 /* XXX: use 32 bit mul which could be faster */
5160 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5161 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5162 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5163 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5164 gen_op_mov_reg_T0(ot
, reg
);
5167 set_cc_op(s
, CC_OP_MULB
+ ot
);
5170 case 0x1c1: /* xadd Ev, Gv */
5171 ot
= mo_b_d(b
, dflag
);
5172 modrm
= cpu_ldub_code(env
, s
->pc
++);
5173 reg
= ((modrm
>> 3) & 7) | rex_r
;
5174 mod
= (modrm
>> 6) & 3;
5176 rm
= (modrm
& 7) | REX_B(s
);
5177 gen_op_mov_TN_reg(ot
, 0, reg
);
5178 gen_op_mov_TN_reg(ot
, 1, rm
);
5179 gen_op_addl_T0_T1();
5180 gen_op_mov_reg_T1(ot
, reg
);
5181 gen_op_mov_reg_T0(ot
, rm
);
5183 gen_lea_modrm(env
, s
, modrm
);
5184 gen_op_mov_TN_reg(ot
, 0, reg
);
5185 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5186 gen_op_addl_T0_T1();
5187 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5188 gen_op_mov_reg_T1(ot
, reg
);
5190 gen_op_update2_cc();
5191 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5194 case 0x1b1: /* cmpxchg Ev, Gv */
5197 TCGv t0
, t1
, t2
, a0
;
5199 ot
= mo_b_d(b
, dflag
);
5200 modrm
= cpu_ldub_code(env
, s
->pc
++);
5201 reg
= ((modrm
>> 3) & 7) | rex_r
;
5202 mod
= (modrm
>> 6) & 3;
5203 t0
= tcg_temp_local_new();
5204 t1
= tcg_temp_local_new();
5205 t2
= tcg_temp_local_new();
5206 a0
= tcg_temp_local_new();
5207 gen_op_mov_v_reg(ot
, t1
, reg
);
5209 rm
= (modrm
& 7) | REX_B(s
);
5210 gen_op_mov_v_reg(ot
, t0
, rm
);
5212 gen_lea_modrm(env
, s
, modrm
);
5213 tcg_gen_mov_tl(a0
, cpu_A0
);
5214 gen_op_ld_v(s
, ot
, t0
, a0
);
5215 rm
= 0; /* avoid warning */
5217 label1
= gen_new_label();
5218 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5221 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5222 label2
= gen_new_label();
5224 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5226 gen_set_label(label1
);
5227 gen_op_mov_reg_v(ot
, rm
, t1
);
5229 /* perform no-op store cycle like physical cpu; must be
5230 before changing accumulator to ensure idempotency if
5231 the store faults and the instruction is restarted */
5232 gen_op_st_v(s
, ot
, t0
, a0
);
5233 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5235 gen_set_label(label1
);
5236 gen_op_st_v(s
, ot
, t1
, a0
);
5238 gen_set_label(label2
);
5239 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5240 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5241 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5242 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5249 case 0x1c7: /* cmpxchg8b */
5250 modrm
= cpu_ldub_code(env
, s
->pc
++);
5251 mod
= (modrm
>> 6) & 3;
5252 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5254 #ifdef TARGET_X86_64
5255 if (dflag
== MO_64
) {
5256 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5258 gen_jmp_im(pc_start
- s
->cs_base
);
5259 gen_update_cc_op(s
);
5260 gen_lea_modrm(env
, s
, modrm
);
5261 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5265 if (!(s
->cpuid_features
& CPUID_CX8
))
5267 gen_jmp_im(pc_start
- s
->cs_base
);
5268 gen_update_cc_op(s
);
5269 gen_lea_modrm(env
, s
, modrm
);
5270 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5272 set_cc_op(s
, CC_OP_EFLAGS
);
5275 /**************************/
5277 case 0x50 ... 0x57: /* push */
5278 gen_op_mov_TN_reg(MO_32
, 0, (b
& 7) | REX_B(s
));
5281 case 0x58 ... 0x5f: /* pop */
5282 ot
= mo_pushpop(s
, dflag
);
5284 /* NOTE: order is important for pop %sp */
5286 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5288 case 0x60: /* pusha */
5293 case 0x61: /* popa */
5298 case 0x68: /* push Iv */
5300 ot
= mo_pushpop(s
, dflag
);
5302 val
= insn_get(env
, s
, ot
);
5304 val
= (int8_t)insn_get(env
, s
, MO_8
);
5305 tcg_gen_movi_tl(cpu_T
[0], val
);
5308 case 0x8f: /* pop Ev */
5309 ot
= mo_pushpop(s
, dflag
);
5310 modrm
= cpu_ldub_code(env
, s
->pc
++);
5311 mod
= (modrm
>> 6) & 3;
5314 /* NOTE: order is important for pop %sp */
5316 rm
= (modrm
& 7) | REX_B(s
);
5317 gen_op_mov_reg_T0(ot
, rm
);
5319 /* NOTE: order is important too for MMU exceptions */
5320 s
->popl_esp_hack
= 1 << ot
;
5321 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5322 s
->popl_esp_hack
= 0;
5326 case 0xc8: /* enter */
5329 val
= cpu_lduw_code(env
, s
->pc
);
5331 level
= cpu_ldub_code(env
, s
->pc
++);
5332 gen_enter(s
, val
, level
);
5335 case 0xc9: /* leave */
5336 /* XXX: exception not precise (ESP is updated before potential exception) */
5338 gen_op_mov_TN_reg(MO_64
, 0, R_EBP
);
5339 gen_op_mov_reg_T0(MO_64
, R_ESP
);
5340 } else if (s
->ss32
) {
5341 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
5342 gen_op_mov_reg_T0(MO_32
, R_ESP
);
5344 gen_op_mov_TN_reg(MO_16
, 0, R_EBP
);
5345 gen_op_mov_reg_T0(MO_16
, R_ESP
);
5348 ot
= mo_pushpop(s
, dflag
);
5349 gen_op_mov_reg_T0(ot
, R_EBP
);
5352 case 0x06: /* push es */
5353 case 0x0e: /* push cs */
5354 case 0x16: /* push ss */
5355 case 0x1e: /* push ds */
5358 gen_op_movl_T0_seg(b
>> 3);
5361 case 0x1a0: /* push fs */
5362 case 0x1a8: /* push gs */
5363 gen_op_movl_T0_seg((b
>> 3) & 7);
5366 case 0x07: /* pop es */
5367 case 0x17: /* pop ss */
5368 case 0x1f: /* pop ds */
5373 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5376 /* if reg == SS, inhibit interrupts/trace. */
5377 /* If several instructions disable interrupts, only the
5379 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5380 gen_helper_set_inhibit_irq(cpu_env
);
5384 gen_jmp_im(s
->pc
- s
->cs_base
);
5388 case 0x1a1: /* pop fs */
5389 case 0x1a9: /* pop gs */
5391 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5394 gen_jmp_im(s
->pc
- s
->cs_base
);
5399 /**************************/
5402 case 0x89: /* mov Gv, Ev */
5403 ot
= mo_b_d(b
, dflag
);
5404 modrm
= cpu_ldub_code(env
, s
->pc
++);
5405 reg
= ((modrm
>> 3) & 7) | rex_r
;
5407 /* generate a generic store */
5408 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5411 case 0xc7: /* mov Ev, Iv */
5412 ot
= mo_b_d(b
, dflag
);
5413 modrm
= cpu_ldub_code(env
, s
->pc
++);
5414 mod
= (modrm
>> 6) & 3;
5416 s
->rip_offset
= insn_const_size(ot
);
5417 gen_lea_modrm(env
, s
, modrm
);
5419 val
= insn_get(env
, s
, ot
);
5420 tcg_gen_movi_tl(cpu_T
[0], val
);
5422 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5424 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5428 case 0x8b: /* mov Ev, Gv */
5429 ot
= mo_b_d(b
, dflag
);
5430 modrm
= cpu_ldub_code(env
, s
->pc
++);
5431 reg
= ((modrm
>> 3) & 7) | rex_r
;
5433 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5434 gen_op_mov_reg_T0(ot
, reg
);
5436 case 0x8e: /* mov seg, Gv */
5437 modrm
= cpu_ldub_code(env
, s
->pc
++);
5438 reg
= (modrm
>> 3) & 7;
5439 if (reg
>= 6 || reg
== R_CS
)
5441 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
5442 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5444 /* if reg == SS, inhibit interrupts/trace */
5445 /* If several instructions disable interrupts, only the
5447 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5448 gen_helper_set_inhibit_irq(cpu_env
);
5452 gen_jmp_im(s
->pc
- s
->cs_base
);
5456 case 0x8c: /* mov Gv, seg */
5457 modrm
= cpu_ldub_code(env
, s
->pc
++);
5458 reg
= (modrm
>> 3) & 7;
5459 mod
= (modrm
>> 6) & 3;
5462 gen_op_movl_T0_seg(reg
);
5463 ot
= mod
== 3 ? dflag
: MO_16
;
5464 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5467 case 0x1b6: /* movzbS Gv, Eb */
5468 case 0x1b7: /* movzwS Gv, Eb */
5469 case 0x1be: /* movsbS Gv, Eb */
5470 case 0x1bf: /* movswS Gv, Eb */
5475 /* d_ot is the size of destination */
5477 /* ot is the size of source */
5478 ot
= (b
& 1) + MO_8
;
5479 /* s_ot is the sign+size of source */
5480 s_ot
= b
& 8 ? MO_SIGN
| ot
: ot
;
5482 modrm
= cpu_ldub_code(env
, s
->pc
++);
5483 reg
= ((modrm
>> 3) & 7) | rex_r
;
5484 mod
= (modrm
>> 6) & 3;
5485 rm
= (modrm
& 7) | REX_B(s
);
5488 gen_op_mov_TN_reg(ot
, 0, rm
);
5491 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5494 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5497 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5501 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5504 gen_op_mov_reg_T0(d_ot
, reg
);
5506 gen_lea_modrm(env
, s
, modrm
);
5507 gen_op_ld_v(s
, s_ot
, cpu_T
[0], cpu_A0
);
5508 gen_op_mov_reg_T0(d_ot
, reg
);
5513 case 0x8d: /* lea */
5515 modrm
= cpu_ldub_code(env
, s
->pc
++);
5516 mod
= (modrm
>> 6) & 3;
5519 reg
= ((modrm
>> 3) & 7) | rex_r
;
5520 /* we must ensure that no segment is added */
5524 gen_lea_modrm(env
, s
, modrm
);
5526 gen_op_mov_reg_A0(ot
, reg
);
5529 case 0xa0: /* mov EAX, Ov */
5531 case 0xa2: /* mov Ov, EAX */
5534 target_ulong offset_addr
;
5536 ot
= mo_b_d(b
, dflag
);
5538 #ifdef TARGET_X86_64
5540 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5545 offset_addr
= insn_get(env
, s
, s
->aflag
);
5548 tcg_gen_movi_tl(cpu_A0
, offset_addr
);
5549 gen_add_A0_ds_seg(s
);
5551 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5552 gen_op_mov_reg_T0(ot
, R_EAX
);
5554 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5555 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5559 case 0xd7: /* xlat */
5560 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EBX
]);
5561 tcg_gen_ext8u_tl(cpu_T
[0], cpu_regs
[R_EAX
]);
5562 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5563 gen_extu(s
->aflag
, cpu_A0
);
5564 gen_add_A0_ds_seg(s
);
5565 gen_op_ld_v(s
, MO_8
, cpu_T
[0], cpu_A0
);
5566 gen_op_mov_reg_T0(MO_8
, R_EAX
);
5568 case 0xb0 ... 0xb7: /* mov R, Ib */
5569 val
= insn_get(env
, s
, MO_8
);
5570 tcg_gen_movi_tl(cpu_T
[0], val
);
5571 gen_op_mov_reg_T0(MO_8
, (b
& 7) | REX_B(s
));
5573 case 0xb8 ... 0xbf: /* mov R, Iv */
5574 #ifdef TARGET_X86_64
5575 if (dflag
== MO_64
) {
5578 tmp
= cpu_ldq_code(env
, s
->pc
);
5580 reg
= (b
& 7) | REX_B(s
);
5581 tcg_gen_movi_tl(cpu_T
[0], tmp
);
5582 gen_op_mov_reg_T0(MO_64
, reg
);
5587 val
= insn_get(env
, s
, ot
);
5588 reg
= (b
& 7) | REX_B(s
);
5589 tcg_gen_movi_tl(cpu_T
[0], val
);
5590 gen_op_mov_reg_T0(ot
, reg
);
5594 case 0x91 ... 0x97: /* xchg R, EAX */
5597 reg
= (b
& 7) | REX_B(s
);
5601 case 0x87: /* xchg Ev, Gv */
5602 ot
= mo_b_d(b
, dflag
);
5603 modrm
= cpu_ldub_code(env
, s
->pc
++);
5604 reg
= ((modrm
>> 3) & 7) | rex_r
;
5605 mod
= (modrm
>> 6) & 3;
5607 rm
= (modrm
& 7) | REX_B(s
);
5609 gen_op_mov_TN_reg(ot
, 0, reg
);
5610 gen_op_mov_TN_reg(ot
, 1, rm
);
5611 gen_op_mov_reg_T0(ot
, rm
);
5612 gen_op_mov_reg_T1(ot
, reg
);
5614 gen_lea_modrm(env
, s
, modrm
);
5615 gen_op_mov_TN_reg(ot
, 0, reg
);
5616 /* for xchg, lock is implicit */
5617 if (!(prefixes
& PREFIX_LOCK
))
5619 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5620 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5621 if (!(prefixes
& PREFIX_LOCK
))
5622 gen_helper_unlock();
5623 gen_op_mov_reg_T1(ot
, reg
);
5626 case 0xc4: /* les Gv */
5627 /* In CODE64 this is VEX3; see above. */
5630 case 0xc5: /* lds Gv */
5631 /* In CODE64 this is VEX2; see above. */
5634 case 0x1b2: /* lss Gv */
5637 case 0x1b4: /* lfs Gv */
5640 case 0x1b5: /* lgs Gv */
5643 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
5644 modrm
= cpu_ldub_code(env
, s
->pc
++);
5645 reg
= ((modrm
>> 3) & 7) | rex_r
;
5646 mod
= (modrm
>> 6) & 3;
5649 gen_lea_modrm(env
, s
, modrm
);
5650 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5651 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5652 /* load the segment first to handle exceptions properly */
5653 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5654 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5655 /* then put the data */
5656 gen_op_mov_reg_T1(ot
, reg
);
5658 gen_jmp_im(s
->pc
- s
->cs_base
);
5663 /************************/
5671 ot
= mo_b_d(b
, dflag
);
5672 modrm
= cpu_ldub_code(env
, s
->pc
++);
5673 mod
= (modrm
>> 6) & 3;
5674 op
= (modrm
>> 3) & 7;
5680 gen_lea_modrm(env
, s
, modrm
);
5683 opreg
= (modrm
& 7) | REX_B(s
);
5688 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5691 shift
= cpu_ldub_code(env
, s
->pc
++);
5693 gen_shifti(s
, op
, ot
, opreg
, shift
);
5708 case 0x1a4: /* shld imm */
5712 case 0x1a5: /* shld cl */
5716 case 0x1ac: /* shrd imm */
5720 case 0x1ad: /* shrd cl */
5725 modrm
= cpu_ldub_code(env
, s
->pc
++);
5726 mod
= (modrm
>> 6) & 3;
5727 rm
= (modrm
& 7) | REX_B(s
);
5728 reg
= ((modrm
>> 3) & 7) | rex_r
;
5730 gen_lea_modrm(env
, s
, modrm
);
5735 gen_op_mov_TN_reg(ot
, 1, reg
);
5738 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5739 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5742 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5746 /************************/
5749 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5750 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5751 /* XXX: what to do if illegal op ? */
5752 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5755 modrm
= cpu_ldub_code(env
, s
->pc
++);
5756 mod
= (modrm
>> 6) & 3;
5758 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5761 gen_lea_modrm(env
, s
, modrm
);
5763 case 0x00 ... 0x07: /* fxxxs */
5764 case 0x10 ... 0x17: /* fixxxl */
5765 case 0x20 ... 0x27: /* fxxxl */
5766 case 0x30 ... 0x37: /* fixxx */
5773 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5774 s
->mem_index
, MO_LEUL
);
5775 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5778 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5779 s
->mem_index
, MO_LEUL
);
5780 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5783 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5784 s
->mem_index
, MO_LEQ
);
5785 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5789 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5790 s
->mem_index
, MO_LESW
);
5791 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5795 gen_helper_fp_arith_ST0_FT0(op1
);
5797 /* fcomp needs pop */
5798 gen_helper_fpop(cpu_env
);
5802 case 0x08: /* flds */
5803 case 0x0a: /* fsts */
5804 case 0x0b: /* fstps */
5805 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5806 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5807 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5812 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5813 s
->mem_index
, MO_LEUL
);
5814 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5817 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5818 s
->mem_index
, MO_LEUL
);
5819 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5822 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5823 s
->mem_index
, MO_LEQ
);
5824 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5828 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5829 s
->mem_index
, MO_LESW
);
5830 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5835 /* XXX: the corresponding CPUID bit must be tested ! */
5838 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5839 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5840 s
->mem_index
, MO_LEUL
);
5843 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5844 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5845 s
->mem_index
, MO_LEQ
);
5849 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5850 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5851 s
->mem_index
, MO_LEUW
);
5854 gen_helper_fpop(cpu_env
);
5859 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5860 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5861 s
->mem_index
, MO_LEUL
);
5864 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5865 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5866 s
->mem_index
, MO_LEUL
);
5869 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5870 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5871 s
->mem_index
, MO_LEQ
);
5875 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5876 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5877 s
->mem_index
, MO_LEUW
);
5881 gen_helper_fpop(cpu_env
);
5885 case 0x0c: /* fldenv mem */
5886 gen_update_cc_op(s
);
5887 gen_jmp_im(pc_start
- s
->cs_base
);
5888 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5890 case 0x0d: /* fldcw mem */
5891 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5892 s
->mem_index
, MO_LEUW
);
5893 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5895 case 0x0e: /* fnstenv mem */
5896 gen_update_cc_op(s
);
5897 gen_jmp_im(pc_start
- s
->cs_base
);
5898 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5900 case 0x0f: /* fnstcw mem */
5901 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5902 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5903 s
->mem_index
, MO_LEUW
);
5905 case 0x1d: /* fldt mem */
5906 gen_update_cc_op(s
);
5907 gen_jmp_im(pc_start
- s
->cs_base
);
5908 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5910 case 0x1f: /* fstpt mem */
5911 gen_update_cc_op(s
);
5912 gen_jmp_im(pc_start
- s
->cs_base
);
5913 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5914 gen_helper_fpop(cpu_env
);
5916 case 0x2c: /* frstor mem */
5917 gen_update_cc_op(s
);
5918 gen_jmp_im(pc_start
- s
->cs_base
);
5919 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5921 case 0x2e: /* fnsave mem */
5922 gen_update_cc_op(s
);
5923 gen_jmp_im(pc_start
- s
->cs_base
);
5924 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5926 case 0x2f: /* fnstsw mem */
5927 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5928 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5929 s
->mem_index
, MO_LEUW
);
5931 case 0x3c: /* fbld */
5932 gen_update_cc_op(s
);
5933 gen_jmp_im(pc_start
- s
->cs_base
);
5934 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5936 case 0x3e: /* fbstp */
5937 gen_update_cc_op(s
);
5938 gen_jmp_im(pc_start
- s
->cs_base
);
5939 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5940 gen_helper_fpop(cpu_env
);
5942 case 0x3d: /* fildll */
5943 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5944 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5946 case 0x3f: /* fistpll */
5947 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5948 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5949 gen_helper_fpop(cpu_env
);
5955 /* register float ops */
5959 case 0x08: /* fld sti */
5960 gen_helper_fpush(cpu_env
);
5961 gen_helper_fmov_ST0_STN(cpu_env
,
5962 tcg_const_i32((opreg
+ 1) & 7));
5964 case 0x09: /* fxchg sti */
5965 case 0x29: /* fxchg4 sti, undocumented op */
5966 case 0x39: /* fxchg7 sti, undocumented op */
5967 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5969 case 0x0a: /* grp d9/2 */
5972 /* check exceptions (FreeBSD FPU probe) */
5973 gen_update_cc_op(s
);
5974 gen_jmp_im(pc_start
- s
->cs_base
);
5975 gen_helper_fwait(cpu_env
);
5981 case 0x0c: /* grp d9/4 */
5984 gen_helper_fchs_ST0(cpu_env
);
5987 gen_helper_fabs_ST0(cpu_env
);
5990 gen_helper_fldz_FT0(cpu_env
);
5991 gen_helper_fcom_ST0_FT0(cpu_env
);
5994 gen_helper_fxam_ST0(cpu_env
);
6000 case 0x0d: /* grp d9/5 */
6004 gen_helper_fpush(cpu_env
);
6005 gen_helper_fld1_ST0(cpu_env
);
6008 gen_helper_fpush(cpu_env
);
6009 gen_helper_fldl2t_ST0(cpu_env
);
6012 gen_helper_fpush(cpu_env
);
6013 gen_helper_fldl2e_ST0(cpu_env
);
6016 gen_helper_fpush(cpu_env
);
6017 gen_helper_fldpi_ST0(cpu_env
);
6020 gen_helper_fpush(cpu_env
);
6021 gen_helper_fldlg2_ST0(cpu_env
);
6024 gen_helper_fpush(cpu_env
);
6025 gen_helper_fldln2_ST0(cpu_env
);
6028 gen_helper_fpush(cpu_env
);
6029 gen_helper_fldz_ST0(cpu_env
);
6036 case 0x0e: /* grp d9/6 */
6039 gen_helper_f2xm1(cpu_env
);
6042 gen_helper_fyl2x(cpu_env
);
6045 gen_helper_fptan(cpu_env
);
6047 case 3: /* fpatan */
6048 gen_helper_fpatan(cpu_env
);
6050 case 4: /* fxtract */
6051 gen_helper_fxtract(cpu_env
);
6053 case 5: /* fprem1 */
6054 gen_helper_fprem1(cpu_env
);
6056 case 6: /* fdecstp */
6057 gen_helper_fdecstp(cpu_env
);
6060 case 7: /* fincstp */
6061 gen_helper_fincstp(cpu_env
);
6065 case 0x0f: /* grp d9/7 */
6068 gen_helper_fprem(cpu_env
);
6070 case 1: /* fyl2xp1 */
6071 gen_helper_fyl2xp1(cpu_env
);
6074 gen_helper_fsqrt(cpu_env
);
6076 case 3: /* fsincos */
6077 gen_helper_fsincos(cpu_env
);
6079 case 5: /* fscale */
6080 gen_helper_fscale(cpu_env
);
6082 case 4: /* frndint */
6083 gen_helper_frndint(cpu_env
);
6086 gen_helper_fsin(cpu_env
);
6090 gen_helper_fcos(cpu_env
);
6094 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6095 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6096 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6102 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6104 gen_helper_fpop(cpu_env
);
6106 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6107 gen_helper_fp_arith_ST0_FT0(op1
);
6111 case 0x02: /* fcom */
6112 case 0x22: /* fcom2, undocumented op */
6113 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6114 gen_helper_fcom_ST0_FT0(cpu_env
);
6116 case 0x03: /* fcomp */
6117 case 0x23: /* fcomp3, undocumented op */
6118 case 0x32: /* fcomp5, undocumented op */
6119 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6120 gen_helper_fcom_ST0_FT0(cpu_env
);
6121 gen_helper_fpop(cpu_env
);
6123 case 0x15: /* da/5 */
6125 case 1: /* fucompp */
6126 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6127 gen_helper_fucom_ST0_FT0(cpu_env
);
6128 gen_helper_fpop(cpu_env
);
6129 gen_helper_fpop(cpu_env
);
6137 case 0: /* feni (287 only, just do nop here) */
6139 case 1: /* fdisi (287 only, just do nop here) */
6142 gen_helper_fclex(cpu_env
);
6144 case 3: /* fninit */
6145 gen_helper_fninit(cpu_env
);
6147 case 4: /* fsetpm (287 only, just do nop here) */
6153 case 0x1d: /* fucomi */
6154 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6157 gen_update_cc_op(s
);
6158 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6159 gen_helper_fucomi_ST0_FT0(cpu_env
);
6160 set_cc_op(s
, CC_OP_EFLAGS
);
6162 case 0x1e: /* fcomi */
6163 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6166 gen_update_cc_op(s
);
6167 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6168 gen_helper_fcomi_ST0_FT0(cpu_env
);
6169 set_cc_op(s
, CC_OP_EFLAGS
);
6171 case 0x28: /* ffree sti */
6172 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6174 case 0x2a: /* fst sti */
6175 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6177 case 0x2b: /* fstp sti */
6178 case 0x0b: /* fstp1 sti, undocumented op */
6179 case 0x3a: /* fstp8 sti, undocumented op */
6180 case 0x3b: /* fstp9 sti, undocumented op */
6181 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6182 gen_helper_fpop(cpu_env
);
6184 case 0x2c: /* fucom st(i) */
6185 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6186 gen_helper_fucom_ST0_FT0(cpu_env
);
6188 case 0x2d: /* fucomp st(i) */
6189 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6190 gen_helper_fucom_ST0_FT0(cpu_env
);
6191 gen_helper_fpop(cpu_env
);
6193 case 0x33: /* de/3 */
6195 case 1: /* fcompp */
6196 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6197 gen_helper_fcom_ST0_FT0(cpu_env
);
6198 gen_helper_fpop(cpu_env
);
6199 gen_helper_fpop(cpu_env
);
6205 case 0x38: /* ffreep sti, undocumented op */
6206 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6207 gen_helper_fpop(cpu_env
);
6209 case 0x3c: /* df/4 */
6212 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6213 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6214 gen_op_mov_reg_T0(MO_16
, R_EAX
);
6220 case 0x3d: /* fucomip */
6221 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6224 gen_update_cc_op(s
);
6225 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6226 gen_helper_fucomi_ST0_FT0(cpu_env
);
6227 gen_helper_fpop(cpu_env
);
6228 set_cc_op(s
, CC_OP_EFLAGS
);
6230 case 0x3e: /* fcomip */
6231 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6234 gen_update_cc_op(s
);
6235 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6236 gen_helper_fcomi_ST0_FT0(cpu_env
);
6237 gen_helper_fpop(cpu_env
);
6238 set_cc_op(s
, CC_OP_EFLAGS
);
6240 case 0x10 ... 0x13: /* fcmovxx */
6244 static const uint8_t fcmov_cc
[8] = {
6251 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6254 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6255 l1
= gen_new_label();
6256 gen_jcc1_noeob(s
, op1
, l1
);
6257 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6266 /************************/
6269 case 0xa4: /* movsS */
6271 ot
= mo_b_d(b
, dflag
);
6272 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6273 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6279 case 0xaa: /* stosS */
6281 ot
= mo_b_d(b
, dflag
);
6282 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6283 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6288 case 0xac: /* lodsS */
6290 ot
= mo_b_d(b
, dflag
);
6291 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6292 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6297 case 0xae: /* scasS */
6299 ot
= mo_b_d(b
, dflag
);
6300 if (prefixes
& PREFIX_REPNZ
) {
6301 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6302 } else if (prefixes
& PREFIX_REPZ
) {
6303 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6309 case 0xa6: /* cmpsS */
6311 ot
= mo_b_d(b
, dflag
);
6312 if (prefixes
& PREFIX_REPNZ
) {
6313 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6314 } else if (prefixes
& PREFIX_REPZ
) {
6315 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6320 case 0x6c: /* insS */
6322 ot
= mo_b_d32(b
, dflag
);
6323 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6324 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6325 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6326 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6327 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6331 gen_jmp(s
, s
->pc
- s
->cs_base
);
6335 case 0x6e: /* outsS */
6337 ot
= mo_b_d32(b
, dflag
);
6338 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6339 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6340 svm_is_rep(prefixes
) | 4);
6341 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6342 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6346 gen_jmp(s
, s
->pc
- s
->cs_base
);
6351 /************************/
6356 ot
= mo_b_d32(b
, dflag
);
6357 val
= cpu_ldub_code(env
, s
->pc
++);
6358 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6359 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6362 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6363 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6364 gen_op_mov_reg_T1(ot
, R_EAX
);
6367 gen_jmp(s
, s
->pc
- s
->cs_base
);
6372 ot
= mo_b_d32(b
, dflag
);
6373 val
= cpu_ldub_code(env
, s
->pc
++);
6374 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6375 svm_is_rep(prefixes
));
6376 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6380 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6381 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6382 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6385 gen_jmp(s
, s
->pc
- s
->cs_base
);
6390 ot
= mo_b_d32(b
, dflag
);
6391 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6392 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6393 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6396 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6397 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6398 gen_op_mov_reg_T1(ot
, R_EAX
);
6401 gen_jmp(s
, s
->pc
- s
->cs_base
);
6406 ot
= mo_b_d32(b
, dflag
);
6407 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6408 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6409 svm_is_rep(prefixes
));
6410 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6414 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6415 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6416 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6419 gen_jmp(s
, s
->pc
- s
->cs_base
);
6423 /************************/
6425 case 0xc2: /* ret im */
6426 val
= cpu_ldsw_code(env
, s
->pc
);
6429 if (CODE64(s
) && dflag
!= MO_16
) {
6432 gen_stack_update(s
, val
+ (1 << dflag
));
6433 if (dflag
== MO_16
) {
6434 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
6439 case 0xc3: /* ret */
6442 if (dflag
== MO_16
) {
6443 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
6448 case 0xca: /* lret im */
6449 val
= cpu_ldsw_code(env
, s
->pc
);
6452 if (s
->pe
&& !s
->vm86
) {
6453 gen_update_cc_op(s
);
6454 gen_jmp_im(pc_start
- s
->cs_base
);
6455 gen_helper_lret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6456 tcg_const_i32(val
));
6460 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6461 /* NOTE: keeping EIP updated is not a problem in case of
6465 gen_op_addl_A0_im(1 << dflag
);
6466 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6467 gen_op_movl_seg_T0_vm(R_CS
);
6468 /* add stack offset */
6469 gen_stack_update(s
, val
+ (2 << dflag
));
6473 case 0xcb: /* lret */
6476 case 0xcf: /* iret */
6477 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6480 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6481 set_cc_op(s
, CC_OP_EFLAGS
);
6482 } else if (s
->vm86
) {
6484 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6486 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6487 set_cc_op(s
, CC_OP_EFLAGS
);
6490 gen_update_cc_op(s
);
6491 gen_jmp_im(pc_start
- s
->cs_base
);
6492 gen_helper_iret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6493 tcg_const_i32(s
->pc
- s
->cs_base
));
6494 set_cc_op(s
, CC_OP_EFLAGS
);
6498 case 0xe8: /* call im */
6500 if (dflag
!= MO_16
) {
6501 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6503 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6505 next_eip
= s
->pc
- s
->cs_base
;
6507 if (dflag
== MO_16
) {
6509 } else if (!CODE64(s
)) {
6512 tcg_gen_movi_tl(cpu_T
[0], next_eip
);
6517 case 0x9a: /* lcall im */
6519 unsigned int selector
, offset
;
6524 offset
= insn_get(env
, s
, ot
);
6525 selector
= insn_get(env
, s
, MO_16
);
6527 tcg_gen_movi_tl(cpu_T
[0], selector
);
6528 tcg_gen_movi_tl(cpu_T
[1], offset
);
6531 case 0xe9: /* jmp im */
6532 if (dflag
!= MO_16
) {
6533 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6535 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6537 tval
+= s
->pc
- s
->cs_base
;
6538 if (dflag
== MO_16
) {
6540 } else if (!CODE64(s
)) {
6545 case 0xea: /* ljmp im */
6547 unsigned int selector
, offset
;
6552 offset
= insn_get(env
, s
, ot
);
6553 selector
= insn_get(env
, s
, MO_16
);
6555 tcg_gen_movi_tl(cpu_T
[0], selector
);
6556 tcg_gen_movi_tl(cpu_T
[1], offset
);
6559 case 0xeb: /* jmp Jb */
6560 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6561 tval
+= s
->pc
- s
->cs_base
;
6562 if (dflag
== MO_16
) {
6567 case 0x70 ... 0x7f: /* jcc Jb */
6568 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6570 case 0x180 ... 0x18f: /* jcc Jv */
6571 if (dflag
!= MO_16
) {
6572 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6574 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6577 next_eip
= s
->pc
- s
->cs_base
;
6579 if (dflag
== MO_16
) {
6582 gen_jcc(s
, b
, tval
, next_eip
);
6585 case 0x190 ... 0x19f: /* setcc Gv */
6586 modrm
= cpu_ldub_code(env
, s
->pc
++);
6587 gen_setcc1(s
, b
, cpu_T
[0]);
6588 gen_ldst_modrm(env
, s
, modrm
, MO_8
, OR_TMP0
, 1);
6590 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6591 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6595 modrm
= cpu_ldub_code(env
, s
->pc
++);
6596 reg
= ((modrm
>> 3) & 7) | rex_r
;
6597 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6600 /************************/
6602 case 0x9c: /* pushf */
6603 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6604 if (s
->vm86
&& s
->iopl
!= 3) {
6605 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6607 gen_update_cc_op(s
);
6608 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6612 case 0x9d: /* popf */
6613 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6614 if (s
->vm86
&& s
->iopl
!= 3) {
6615 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6619 if (dflag
!= MO_16
) {
6620 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6621 tcg_const_i32((TF_MASK
| AC_MASK
|
6626 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6627 tcg_const_i32((TF_MASK
| AC_MASK
|
6629 IF_MASK
| IOPL_MASK
)
6633 if (s
->cpl
<= s
->iopl
) {
6634 if (dflag
!= MO_16
) {
6635 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6636 tcg_const_i32((TF_MASK
|
6642 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6643 tcg_const_i32((TF_MASK
|
6651 if (dflag
!= MO_16
) {
6652 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6653 tcg_const_i32((TF_MASK
| AC_MASK
|
6654 ID_MASK
| NT_MASK
)));
6656 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6657 tcg_const_i32((TF_MASK
| AC_MASK
|
6664 set_cc_op(s
, CC_OP_EFLAGS
);
6665 /* abort translation because TF/AC flag may change */
6666 gen_jmp_im(s
->pc
- s
->cs_base
);
6670 case 0x9e: /* sahf */
6671 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6673 gen_op_mov_TN_reg(MO_8
, 0, R_AH
);
6674 gen_compute_eflags(s
);
6675 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6676 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6677 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6679 case 0x9f: /* lahf */
6680 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6682 gen_compute_eflags(s
);
6683 /* Note: gen_compute_eflags() only gives the condition codes */
6684 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6685 gen_op_mov_reg_T0(MO_8
, R_AH
);
6687 case 0xf5: /* cmc */
6688 gen_compute_eflags(s
);
6689 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6691 case 0xf8: /* clc */
6692 gen_compute_eflags(s
);
6693 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6695 case 0xf9: /* stc */
6696 gen_compute_eflags(s
);
6697 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6699 case 0xfc: /* cld */
6700 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6701 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6703 case 0xfd: /* std */
6704 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6705 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6708 /************************/
6709 /* bit operations */
6710 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6712 modrm
= cpu_ldub_code(env
, s
->pc
++);
6713 op
= (modrm
>> 3) & 7;
6714 mod
= (modrm
>> 6) & 3;
6715 rm
= (modrm
& 7) | REX_B(s
);
6718 gen_lea_modrm(env
, s
, modrm
);
6719 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6721 gen_op_mov_TN_reg(ot
, 0, rm
);
6724 val
= cpu_ldub_code(env
, s
->pc
++);
6725 tcg_gen_movi_tl(cpu_T
[1], val
);
6730 case 0x1a3: /* bt Gv, Ev */
6733 case 0x1ab: /* bts */
6736 case 0x1b3: /* btr */
6739 case 0x1bb: /* btc */
6743 modrm
= cpu_ldub_code(env
, s
->pc
++);
6744 reg
= ((modrm
>> 3) & 7) | rex_r
;
6745 mod
= (modrm
>> 6) & 3;
6746 rm
= (modrm
& 7) | REX_B(s
);
6747 gen_op_mov_TN_reg(MO_32
, 1, reg
);
6749 gen_lea_modrm(env
, s
, modrm
);
6750 /* specific case: we need to add a displacement */
6751 gen_exts(ot
, cpu_T
[1]);
6752 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6753 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6754 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6755 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6757 gen_op_mov_TN_reg(ot
, 0, rm
);
6760 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6763 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6764 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6767 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6768 tcg_gen_movi_tl(cpu_tmp0
, 1);
6769 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6770 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6773 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6774 tcg_gen_movi_tl(cpu_tmp0
, 1);
6775 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6776 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6777 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6781 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6782 tcg_gen_movi_tl(cpu_tmp0
, 1);
6783 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6784 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6787 set_cc_op(s
, CC_OP_SARB
+ ot
);
6790 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
6792 gen_op_mov_reg_T0(ot
, rm
);
6794 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6795 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6798 case 0x1bc: /* bsf / tzcnt */
6799 case 0x1bd: /* bsr / lzcnt */
6801 modrm
= cpu_ldub_code(env
, s
->pc
++);
6802 reg
= ((modrm
>> 3) & 7) | rex_r
;
6803 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
6804 gen_extu(ot
, cpu_T
[0]);
6806 /* Note that lzcnt and tzcnt are in different extensions. */
6807 if ((prefixes
& PREFIX_REPZ
)
6809 ? s
->cpuid_ext3_features
& CPUID_EXT3_ABM
6810 : s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)) {
6812 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
6814 /* For lzcnt, reduce the target_ulong result by the
6815 number of zeros that we expect to find at the top. */
6816 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6817 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- size
);
6819 /* For tzcnt, a zero input must return the operand size:
6820 force all bits outside the operand size to 1. */
6821 target_ulong mask
= (target_ulong
)-2 << (size
- 1);
6822 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], mask
);
6823 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6825 /* For lzcnt/tzcnt, C and Z bits are defined and are
6826 related to the result. */
6827 gen_op_update1_cc();
6828 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
6830 /* For bsr/bsf, only the Z bit is defined and it is related
6831 to the input and not the result. */
6832 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
6833 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6835 /* For bsr, return the bit index of the first 1 bit,
6836 not the count of leading zeros. */
6837 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6838 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- 1);
6840 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6842 /* ??? The manual says that the output is undefined when the
6843 input is zero, but real hardware leaves it unchanged, and
6844 real programs appear to depend on that. */
6845 tcg_gen_movi_tl(cpu_tmp0
, 0);
6846 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[0], cpu_cc_dst
, cpu_tmp0
,
6847 cpu_regs
[reg
], cpu_T
[0]);
6849 gen_op_mov_reg_T0(ot
, reg
);
6851 /************************/
6853 case 0x27: /* daa */
6856 gen_update_cc_op(s
);
6857 gen_helper_daa(cpu_env
);
6858 set_cc_op(s
, CC_OP_EFLAGS
);
6860 case 0x2f: /* das */
6863 gen_update_cc_op(s
);
6864 gen_helper_das(cpu_env
);
6865 set_cc_op(s
, CC_OP_EFLAGS
);
6867 case 0x37: /* aaa */
6870 gen_update_cc_op(s
);
6871 gen_helper_aaa(cpu_env
);
6872 set_cc_op(s
, CC_OP_EFLAGS
);
6874 case 0x3f: /* aas */
6877 gen_update_cc_op(s
);
6878 gen_helper_aas(cpu_env
);
6879 set_cc_op(s
, CC_OP_EFLAGS
);
6881 case 0xd4: /* aam */
6884 val
= cpu_ldub_code(env
, s
->pc
++);
6886 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6888 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6889 set_cc_op(s
, CC_OP_LOGICB
);
6892 case 0xd5: /* aad */
6895 val
= cpu_ldub_code(env
, s
->pc
++);
6896 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6897 set_cc_op(s
, CC_OP_LOGICB
);
6899 /************************/
6901 case 0x90: /* nop */
6902 /* XXX: correct lock test for all insn */
6903 if (prefixes
& PREFIX_LOCK
) {
6906 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6908 goto do_xchg_reg_eax
;
6910 if (prefixes
& PREFIX_REPZ
) {
6911 gen_update_cc_op(s
);
6912 gen_jmp_im(pc_start
- s
->cs_base
);
6913 gen_helper_pause(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6914 s
->is_jmp
= DISAS_TB_JUMP
;
6917 case 0x9b: /* fwait */
6918 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6919 (HF_MP_MASK
| HF_TS_MASK
)) {
6920 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6922 gen_update_cc_op(s
);
6923 gen_jmp_im(pc_start
- s
->cs_base
);
6924 gen_helper_fwait(cpu_env
);
6927 case 0xcc: /* int3 */
6928 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6930 case 0xcd: /* int N */
6931 val
= cpu_ldub_code(env
, s
->pc
++);
6932 if (s
->vm86
&& s
->iopl
!= 3) {
6933 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6935 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6938 case 0xce: /* into */
6941 gen_update_cc_op(s
);
6942 gen_jmp_im(pc_start
- s
->cs_base
);
6943 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6946 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6947 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6949 gen_debug(s
, pc_start
- s
->cs_base
);
6953 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6957 case 0xfa: /* cli */
6959 if (s
->cpl
<= s
->iopl
) {
6960 gen_helper_cli(cpu_env
);
6962 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6966 gen_helper_cli(cpu_env
);
6968 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6972 case 0xfb: /* sti */
6974 if (s
->cpl
<= s
->iopl
) {
6976 gen_helper_sti(cpu_env
);
6977 /* interruptions are enabled only the first insn after sti */
6978 /* If several instructions disable interrupts, only the
6980 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6981 gen_helper_set_inhibit_irq(cpu_env
);
6982 /* give a chance to handle pending irqs */
6983 gen_jmp_im(s
->pc
- s
->cs_base
);
6986 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6992 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6996 case 0x62: /* bound */
7000 modrm
= cpu_ldub_code(env
, s
->pc
++);
7001 reg
= (modrm
>> 3) & 7;
7002 mod
= (modrm
>> 6) & 3;
7005 gen_op_mov_TN_reg(ot
, 0, reg
);
7006 gen_lea_modrm(env
, s
, modrm
);
7007 gen_jmp_im(pc_start
- s
->cs_base
);
7008 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7010 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
7012 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
7015 case 0x1c8 ... 0x1cf: /* bswap reg */
7016 reg
= (b
& 7) | REX_B(s
);
7017 #ifdef TARGET_X86_64
7018 if (dflag
== MO_64
) {
7019 gen_op_mov_TN_reg(MO_64
, 0, reg
);
7020 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
7021 gen_op_mov_reg_T0(MO_64
, reg
);
7025 gen_op_mov_TN_reg(MO_32
, 0, reg
);
7026 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
7027 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
7028 gen_op_mov_reg_T0(MO_32
, reg
);
7031 case 0xd6: /* salc */
7034 gen_compute_eflags_c(s
, cpu_T
[0]);
7035 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
7036 gen_op_mov_reg_T0(MO_8
, R_EAX
);
7038 case 0xe0: /* loopnz */
7039 case 0xe1: /* loopz */
7040 case 0xe2: /* loop */
7041 case 0xe3: /* jecxz */
7045 tval
= (int8_t)insn_get(env
, s
, MO_8
);
7046 next_eip
= s
->pc
- s
->cs_base
;
7048 if (dflag
== MO_16
) {
7052 l1
= gen_new_label();
7053 l2
= gen_new_label();
7054 l3
= gen_new_label();
7057 case 0: /* loopnz */
7059 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7060 gen_op_jz_ecx(s
->aflag
, l3
);
7061 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7064 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7065 gen_op_jnz_ecx(s
->aflag
, l1
);
7069 gen_op_jz_ecx(s
->aflag
, l1
);
7074 gen_jmp_im(next_eip
);
7083 case 0x130: /* wrmsr */
7084 case 0x132: /* rdmsr */
7086 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7088 gen_update_cc_op(s
);
7089 gen_jmp_im(pc_start
- s
->cs_base
);
7091 gen_helper_rdmsr(cpu_env
);
7093 gen_helper_wrmsr(cpu_env
);
7097 case 0x131: /* rdtsc */
7098 gen_update_cc_op(s
);
7099 gen_jmp_im(pc_start
- s
->cs_base
);
7102 gen_helper_rdtsc(cpu_env
);
7105 gen_jmp(s
, s
->pc
- s
->cs_base
);
7108 case 0x133: /* rdpmc */
7109 gen_update_cc_op(s
);
7110 gen_jmp_im(pc_start
- s
->cs_base
);
7111 gen_helper_rdpmc(cpu_env
);
7113 case 0x134: /* sysenter */
7114 /* For Intel SYSENTER is valid on 64-bit */
7115 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7118 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7120 gen_update_cc_op(s
);
7121 gen_jmp_im(pc_start
- s
->cs_base
);
7122 gen_helper_sysenter(cpu_env
);
7126 case 0x135: /* sysexit */
7127 /* For Intel SYSEXIT is valid on 64-bit */
7128 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7131 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7133 gen_update_cc_op(s
);
7134 gen_jmp_im(pc_start
- s
->cs_base
);
7135 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
- 1));
7139 #ifdef TARGET_X86_64
7140 case 0x105: /* syscall */
7141 /* XXX: is it usable in real mode ? */
7142 gen_update_cc_op(s
);
7143 gen_jmp_im(pc_start
- s
->cs_base
);
7144 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7147 case 0x107: /* sysret */
7149 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7151 gen_update_cc_op(s
);
7152 gen_jmp_im(pc_start
- s
->cs_base
);
7153 gen_helper_sysret(cpu_env
, tcg_const_i32(dflag
- 1));
7154 /* condition codes are modified only in long mode */
7156 set_cc_op(s
, CC_OP_EFLAGS
);
7162 case 0x1a2: /* cpuid */
7163 gen_update_cc_op(s
);
7164 gen_jmp_im(pc_start
- s
->cs_base
);
7165 gen_helper_cpuid(cpu_env
);
7167 case 0xf4: /* hlt */
7169 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7171 gen_update_cc_op(s
);
7172 gen_jmp_im(pc_start
- s
->cs_base
);
7173 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7174 s
->is_jmp
= DISAS_TB_JUMP
;
7178 modrm
= cpu_ldub_code(env
, s
->pc
++);
7179 mod
= (modrm
>> 6) & 3;
7180 op
= (modrm
>> 3) & 7;
7183 if (!s
->pe
|| s
->vm86
)
7185 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7186 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7187 ot
= mod
== 3 ? dflag
: MO_16
;
7188 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7191 if (!s
->pe
|| s
->vm86
)
7194 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7196 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7197 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7198 gen_jmp_im(pc_start
- s
->cs_base
);
7199 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7200 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7204 if (!s
->pe
|| s
->vm86
)
7206 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7207 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7208 ot
= mod
== 3 ? dflag
: MO_16
;
7209 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7212 if (!s
->pe
|| s
->vm86
)
7215 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7217 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7218 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7219 gen_jmp_im(pc_start
- s
->cs_base
);
7220 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7221 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7226 if (!s
->pe
|| s
->vm86
)
7228 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7229 gen_update_cc_op(s
);
7231 gen_helper_verr(cpu_env
, cpu_T
[0]);
7233 gen_helper_verw(cpu_env
, cpu_T
[0]);
7235 set_cc_op(s
, CC_OP_EFLAGS
);
7242 modrm
= cpu_ldub_code(env
, s
->pc
++);
7243 mod
= (modrm
>> 6) & 3;
7244 op
= (modrm
>> 3) & 7;
7250 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7251 gen_lea_modrm(env
, s
, modrm
);
7252 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7253 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7254 gen_add_A0_im(s
, 2);
7255 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7256 if (dflag
== MO_16
) {
7257 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7259 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7264 case 0: /* monitor */
7265 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7268 gen_update_cc_op(s
);
7269 gen_jmp_im(pc_start
- s
->cs_base
);
7270 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EAX
]);
7271 gen_extu(s
->aflag
, cpu_A0
);
7272 gen_add_A0_ds_seg(s
);
7273 gen_helper_monitor(cpu_env
, cpu_A0
);
7276 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7279 gen_update_cc_op(s
);
7280 gen_jmp_im(pc_start
- s
->cs_base
);
7281 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7285 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7289 gen_helper_clac(cpu_env
);
7290 gen_jmp_im(s
->pc
- s
->cs_base
);
7294 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7298 gen_helper_stac(cpu_env
);
7299 gen_jmp_im(s
->pc
- s
->cs_base
);
7306 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7307 gen_lea_modrm(env
, s
, modrm
);
7308 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7309 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7310 gen_add_A0_im(s
, 2);
7311 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7312 if (dflag
== MO_16
) {
7313 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7315 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7321 gen_update_cc_op(s
);
7322 gen_jmp_im(pc_start
- s
->cs_base
);
7325 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7328 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7331 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
- 1),
7332 tcg_const_i32(s
->pc
- pc_start
));
7334 s
->is_jmp
= DISAS_TB_JUMP
;
7337 case 1: /* VMMCALL */
7338 if (!(s
->flags
& HF_SVME_MASK
))
7340 gen_helper_vmmcall(cpu_env
);
7342 case 2: /* VMLOAD */
7343 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7346 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7349 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7352 case 3: /* VMSAVE */
7353 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7356 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7359 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7363 if ((!(s
->flags
& HF_SVME_MASK
) &&
7364 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7368 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7371 gen_helper_stgi(cpu_env
);
7375 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7378 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7381 gen_helper_clgi(cpu_env
);
7384 case 6: /* SKINIT */
7385 if ((!(s
->flags
& HF_SVME_MASK
) &&
7386 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7389 gen_helper_skinit(cpu_env
);
7391 case 7: /* INVLPGA */
7392 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7395 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7398 gen_helper_invlpga(cpu_env
,
7399 tcg_const_i32(s
->aflag
- 1));
7405 } else if (s
->cpl
!= 0) {
7406 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7408 gen_svm_check_intercept(s
, pc_start
,
7409 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7410 gen_lea_modrm(env
, s
, modrm
);
7411 gen_op_ld_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
7412 gen_add_A0_im(s
, 2);
7413 gen_op_ld_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7414 if (dflag
== MO_16
) {
7415 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7418 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7419 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7421 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7422 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7427 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7428 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7429 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7431 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7433 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 1);
7437 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7439 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7440 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7441 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7442 gen_jmp_im(s
->pc
- s
->cs_base
);
7447 if (mod
!= 3) { /* invlpg */
7449 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7451 gen_update_cc_op(s
);
7452 gen_jmp_im(pc_start
- s
->cs_base
);
7453 gen_lea_modrm(env
, s
, modrm
);
7454 gen_helper_invlpg(cpu_env
, cpu_A0
);
7455 gen_jmp_im(s
->pc
- s
->cs_base
);
7460 case 0: /* swapgs */
7461 #ifdef TARGET_X86_64
7464 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7466 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7467 offsetof(CPUX86State
,segs
[R_GS
].base
));
7468 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7469 offsetof(CPUX86State
,kernelgsbase
));
7470 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7471 offsetof(CPUX86State
,segs
[R_GS
].base
));
7472 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7473 offsetof(CPUX86State
,kernelgsbase
));
7481 case 1: /* rdtscp */
7482 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7484 gen_update_cc_op(s
);
7485 gen_jmp_im(pc_start
- s
->cs_base
);
7488 gen_helper_rdtscp(cpu_env
);
7491 gen_jmp(s
, s
->pc
- s
->cs_base
);
7503 case 0x108: /* invd */
7504 case 0x109: /* wbinvd */
7506 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7508 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7512 case 0x63: /* arpl or movslS (x86_64) */
7513 #ifdef TARGET_X86_64
7516 /* d_ot is the size of destination */
7519 modrm
= cpu_ldub_code(env
, s
->pc
++);
7520 reg
= ((modrm
>> 3) & 7) | rex_r
;
7521 mod
= (modrm
>> 6) & 3;
7522 rm
= (modrm
& 7) | REX_B(s
);
7525 gen_op_mov_TN_reg(MO_32
, 0, rm
);
7527 if (d_ot
== MO_64
) {
7528 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7530 gen_op_mov_reg_T0(d_ot
, reg
);
7532 gen_lea_modrm(env
, s
, modrm
);
7533 gen_op_ld_v(s
, MO_32
| MO_SIGN
, cpu_T
[0], cpu_A0
);
7534 gen_op_mov_reg_T0(d_ot
, reg
);
7540 TCGv t0
, t1
, t2
, a0
;
7542 if (!s
->pe
|| s
->vm86
)
7544 t0
= tcg_temp_local_new();
7545 t1
= tcg_temp_local_new();
7546 t2
= tcg_temp_local_new();
7548 modrm
= cpu_ldub_code(env
, s
->pc
++);
7549 reg
= (modrm
>> 3) & 7;
7550 mod
= (modrm
>> 6) & 3;
7553 gen_lea_modrm(env
, s
, modrm
);
7554 gen_op_ld_v(s
, ot
, t0
, cpu_A0
);
7555 a0
= tcg_temp_local_new();
7556 tcg_gen_mov_tl(a0
, cpu_A0
);
7558 gen_op_mov_v_reg(ot
, t0
, rm
);
7561 gen_op_mov_v_reg(ot
, t1
, reg
);
7562 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7563 tcg_gen_andi_tl(t1
, t1
, 3);
7564 tcg_gen_movi_tl(t2
, 0);
7565 label1
= gen_new_label();
7566 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7567 tcg_gen_andi_tl(t0
, t0
, ~3);
7568 tcg_gen_or_tl(t0
, t0
, t1
);
7569 tcg_gen_movi_tl(t2
, CC_Z
);
7570 gen_set_label(label1
);
7572 gen_op_st_v(s
, ot
, t0
, a0
);
7575 gen_op_mov_reg_v(ot
, rm
, t0
);
7577 gen_compute_eflags(s
);
7578 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7579 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7585 case 0x102: /* lar */
7586 case 0x103: /* lsl */
7590 if (!s
->pe
|| s
->vm86
)
7592 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
7593 modrm
= cpu_ldub_code(env
, s
->pc
++);
7594 reg
= ((modrm
>> 3) & 7) | rex_r
;
7595 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7596 t0
= tcg_temp_local_new();
7597 gen_update_cc_op(s
);
7599 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7601 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7603 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7604 label1
= gen_new_label();
7605 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7606 gen_op_mov_reg_v(ot
, reg
, t0
);
7607 gen_set_label(label1
);
7608 set_cc_op(s
, CC_OP_EFLAGS
);
7613 modrm
= cpu_ldub_code(env
, s
->pc
++);
7614 mod
= (modrm
>> 6) & 3;
7615 op
= (modrm
>> 3) & 7;
7617 case 0: /* prefetchnta */
7618 case 1: /* prefetchnt0 */
7619 case 2: /* prefetchnt0 */
7620 case 3: /* prefetchnt0 */
7623 gen_lea_modrm(env
, s
, modrm
);
7624 /* nothing more to do */
7626 default: /* nop (multi byte) */
7627 gen_nop_modrm(env
, s
, modrm
);
7631 case 0x119 ... 0x11f: /* nop (multi byte) */
7632 modrm
= cpu_ldub_code(env
, s
->pc
++);
7633 gen_nop_modrm(env
, s
, modrm
);
7635 case 0x120: /* mov reg, crN */
7636 case 0x122: /* mov crN, reg */
7638 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7640 modrm
= cpu_ldub_code(env
, s
->pc
++);
7641 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7642 * AMD documentation (24594.pdf) and testing of
7643 * intel 386 and 486 processors all show that the mod bits
7644 * are assumed to be 1's, regardless of actual values.
7646 rm
= (modrm
& 7) | REX_B(s
);
7647 reg
= ((modrm
>> 3) & 7) | rex_r
;
7652 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7653 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7662 gen_update_cc_op(s
);
7663 gen_jmp_im(pc_start
- s
->cs_base
);
7665 gen_op_mov_TN_reg(ot
, 0, rm
);
7666 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7668 gen_jmp_im(s
->pc
- s
->cs_base
);
7671 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7672 gen_op_mov_reg_T0(ot
, rm
);
7680 case 0x121: /* mov reg, drN */
7681 case 0x123: /* mov drN, reg */
7683 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7685 modrm
= cpu_ldub_code(env
, s
->pc
++);
7686 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7687 * AMD documentation (24594.pdf) and testing of
7688 * intel 386 and 486 processors all show that the mod bits
7689 * are assumed to be 1's, regardless of actual values.
7691 rm
= (modrm
& 7) | REX_B(s
);
7692 reg
= ((modrm
>> 3) & 7) | rex_r
;
7697 /* XXX: do it dynamically with CR4.DE bit */
7698 if (reg
== 4 || reg
== 5 || reg
>= 8)
7701 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7702 gen_op_mov_TN_reg(ot
, 0, rm
);
7703 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7704 gen_jmp_im(s
->pc
- s
->cs_base
);
7707 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7708 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7709 gen_op_mov_reg_T0(ot
, rm
);
7713 case 0x106: /* clts */
7715 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7717 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7718 gen_helper_clts(cpu_env
);
7719 /* abort block because static cpu state changed */
7720 gen_jmp_im(s
->pc
- s
->cs_base
);
7724 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7725 case 0x1c3: /* MOVNTI reg, mem */
7726 if (!(s
->cpuid_features
& CPUID_SSE2
))
7728 ot
= mo_64_32(dflag
);
7729 modrm
= cpu_ldub_code(env
, s
->pc
++);
7730 mod
= (modrm
>> 6) & 3;
7733 reg
= ((modrm
>> 3) & 7) | rex_r
;
7734 /* generate a generic store */
7735 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7738 modrm
= cpu_ldub_code(env
, s
->pc
++);
7739 mod
= (modrm
>> 6) & 3;
7740 op
= (modrm
>> 3) & 7;
7742 case 0: /* fxsave */
7743 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7744 (s
->prefix
& PREFIX_LOCK
))
7746 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7747 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7750 gen_lea_modrm(env
, s
, modrm
);
7751 gen_update_cc_op(s
);
7752 gen_jmp_im(pc_start
- s
->cs_base
);
7753 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7755 case 1: /* fxrstor */
7756 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7757 (s
->prefix
& PREFIX_LOCK
))
7759 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7760 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7763 gen_lea_modrm(env
, s
, modrm
);
7764 gen_update_cc_op(s
);
7765 gen_jmp_im(pc_start
- s
->cs_base
);
7766 gen_helper_fxrstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7768 case 2: /* ldmxcsr */
7769 case 3: /* stmxcsr */
7770 if (s
->flags
& HF_TS_MASK
) {
7771 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7774 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7777 gen_lea_modrm(env
, s
, modrm
);
7779 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
7780 s
->mem_index
, MO_LEUL
);
7781 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7783 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7784 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7787 case 5: /* lfence */
7788 case 6: /* mfence */
7789 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7792 case 7: /* sfence / clflush */
7793 if ((modrm
& 0xc7) == 0xc0) {
7795 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7796 if (!(s
->cpuid_features
& CPUID_SSE
))
7800 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7802 gen_lea_modrm(env
, s
, modrm
);
7809 case 0x10d: /* 3DNow! prefetch(w) */
7810 modrm
= cpu_ldub_code(env
, s
->pc
++);
7811 mod
= (modrm
>> 6) & 3;
7814 gen_lea_modrm(env
, s
, modrm
);
7815 /* ignore for now */
7817 case 0x1aa: /* rsm */
7818 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7819 if (!(s
->flags
& HF_SMM_MASK
))
7821 gen_update_cc_op(s
);
7822 gen_jmp_im(s
->pc
- s
->cs_base
);
7823 gen_helper_rsm(cpu_env
);
7826 case 0x1b8: /* SSE4.2 popcnt */
7827 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7830 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7833 modrm
= cpu_ldub_code(env
, s
->pc
++);
7834 reg
= ((modrm
>> 3) & 7) | rex_r
;
7836 if (s
->prefix
& PREFIX_DATA
) {
7839 ot
= mo_64_32(dflag
);
7842 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7843 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7844 gen_op_mov_reg_T0(ot
, reg
);
7846 set_cc_op(s
, CC_OP_EFLAGS
);
7848 case 0x10e ... 0x10f:
7849 /* 3DNow! instructions, ignore prefixes */
7850 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7851 case 0x110 ... 0x117:
7852 case 0x128 ... 0x12f:
7853 case 0x138 ... 0x13a:
7854 case 0x150 ... 0x179:
7855 case 0x17c ... 0x17f:
7857 case 0x1c4 ... 0x1c6:
7858 case 0x1d0 ... 0x1fe:
7859 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7864 /* lock generation */
7865 if (s
->prefix
& PREFIX_LOCK
)
7866 gen_helper_unlock();
7869 if (s
->prefix
& PREFIX_LOCK
)
7870 gen_helper_unlock();
7871 /* XXX: ensure that no lock was generated */
7872 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7876 void optimize_flags_init(void)
7878 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7879 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7880 offsetof(CPUX86State
, cc_op
), "cc_op");
7881 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7883 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7885 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src2
),
7888 #ifdef TARGET_X86_64
7889 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7890 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
7891 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7892 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
7893 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7894 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
7895 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7896 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
7897 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7898 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
7899 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7900 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
7901 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7902 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
7903 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7904 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
7905 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7906 offsetof(CPUX86State
, regs
[8]), "r8");
7907 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7908 offsetof(CPUX86State
, regs
[9]), "r9");
7909 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7910 offsetof(CPUX86State
, regs
[10]), "r10");
7911 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7912 offsetof(CPUX86State
, regs
[11]), "r11");
7913 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7914 offsetof(CPUX86State
, regs
[12]), "r12");
7915 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7916 offsetof(CPUX86State
, regs
[13]), "r13");
7917 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7918 offsetof(CPUX86State
, regs
[14]), "r14");
7919 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7920 offsetof(CPUX86State
, regs
[15]), "r15");
7922 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7923 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
7924 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7925 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
7926 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7927 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
7928 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7929 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
7930 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7931 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
7932 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7933 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
7934 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7935 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
7936 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7937 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
7941 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7942 basic block 'tb'. If search_pc is TRUE, also generate PC
7943 information for each intermediate instruction. */
7944 static inline void gen_intermediate_code_internal(X86CPU
*cpu
,
7945 TranslationBlock
*tb
,
7948 CPUState
*cs
= CPU(cpu
);
7949 CPUX86State
*env
= &cpu
->env
;
7950 DisasContext dc1
, *dc
= &dc1
;
7951 target_ulong pc_ptr
;
7952 uint16_t *gen_opc_end
;
7956 target_ulong pc_start
;
7957 target_ulong cs_base
;
7961 /* generate intermediate code */
7963 cs_base
= tb
->cs_base
;
7966 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7967 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7968 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7969 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7971 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7972 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7973 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7974 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7975 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
7976 dc
->cc_op
= CC_OP_DYNAMIC
;
7977 dc
->cc_op_dirty
= false;
7978 dc
->cs_base
= cs_base
;
7980 dc
->popl_esp_hack
= 0;
7981 /* select memory access functions */
7983 if (flags
& HF_SOFTMMU_MASK
) {
7984 dc
->mem_index
= cpu_mmu_index(env
);
7986 dc
->cpuid_features
= env
->features
[FEAT_1_EDX
];
7987 dc
->cpuid_ext_features
= env
->features
[FEAT_1_ECX
];
7988 dc
->cpuid_ext2_features
= env
->features
[FEAT_8000_0001_EDX
];
7989 dc
->cpuid_ext3_features
= env
->features
[FEAT_8000_0001_ECX
];
7990 dc
->cpuid_7_0_ebx_features
= env
->features
[FEAT_7_0_EBX
];
7991 #ifdef TARGET_X86_64
7992 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7993 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7996 dc
->jmp_opt
= !(dc
->tf
|| cs
->singlestep_enabled
||
7997 (flags
& HF_INHIBIT_IRQ_MASK
)
7998 #ifndef CONFIG_SOFTMMU
7999 || (flags
& HF_SOFTMMU_MASK
)
8003 /* check addseg logic */
8004 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
8005 printf("ERROR addseg\n");
8008 cpu_T
[0] = tcg_temp_new();
8009 cpu_T
[1] = tcg_temp_new();
8010 cpu_A0
= tcg_temp_new();
8012 cpu_tmp0
= tcg_temp_new();
8013 cpu_tmp1_i64
= tcg_temp_new_i64();
8014 cpu_tmp2_i32
= tcg_temp_new_i32();
8015 cpu_tmp3_i32
= tcg_temp_new_i32();
8016 cpu_tmp4
= tcg_temp_new();
8017 cpu_ptr0
= tcg_temp_new_ptr();
8018 cpu_ptr1
= tcg_temp_new_ptr();
8019 cpu_cc_srcT
= tcg_temp_local_new();
8021 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
8023 dc
->is_jmp
= DISAS_NEXT
;
8027 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8029 max_insns
= CF_COUNT_MASK
;
8033 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
8034 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8035 if (bp
->pc
== pc_ptr
&&
8036 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
8037 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
8043 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8047 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8049 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
8050 gen_opc_cc_op
[lj
] = dc
->cc_op
;
8051 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
8052 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
8054 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8057 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
8059 /* stop translation if indicated */
8062 /* if single step mode, we generate only one instruction and
8063 generate an exception */
8064 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8065 the flag and abort the translation to give the irqs a
8066 change to be happen */
8067 if (dc
->tf
|| dc
->singlestep_enabled
||
8068 (flags
& HF_INHIBIT_IRQ_MASK
)) {
8069 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8073 /* if too long translation, stop generation too */
8074 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
8075 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8076 num_insns
>= max_insns
) {
8077 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8082 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8087 if (tb
->cflags
& CF_LAST_IO
)
8089 gen_tb_end(tb
, num_insns
);
8090 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8091 /* we don't forget to fill the last values */
8093 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8096 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8100 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8102 qemu_log("----------------\n");
8103 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8104 #ifdef TARGET_X86_64
8109 disas_flags
= !dc
->code32
;
8110 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8116 tb
->size
= pc_ptr
- pc_start
;
8117 tb
->icount
= num_insns
;
8121 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8123 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, false);
8126 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8128 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, true);
8131 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8135 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8137 qemu_log("RESTORE:\n");
8138 for(i
= 0;i
<= pc_pos
; i
++) {
8139 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8140 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8141 tcg_ctx
.gen_opc_pc
[i
]);
8144 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8145 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8146 (uint32_t)tb
->cs_base
);
8149 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8150 cc_op
= gen_opc_cc_op
[pc_pos
];
8151 if (cc_op
!= CC_OP_DYNAMIC
)