ppc/pnv: change pnv_phb4_update_regions() to use PnvPHB4
[qemu.git] / hw / pci-host / pnv_phb4.c
blob034721f159159747c70a003128e05c313a7b8932
1 /*
2 * QEMU PowerPC PowerNV (POWER9) PHB4 model
4 * Copyright (c) 2018-2020, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9 #include "qemu/osdep.h"
10 #include "qemu/log.h"
11 #include "qapi/visitor.h"
12 #include "qapi/error.h"
13 #include "qemu-common.h"
14 #include "monitor/monitor.h"
15 #include "target/ppc/cpu.h"
16 #include "hw/pci-host/pnv_phb4_regs.h"
17 #include "hw/pci-host/pnv_phb4.h"
18 #include "hw/pci/pcie_host.h"
19 #include "hw/pci/pcie_port.h"
20 #include "hw/ppc/pnv.h"
21 #include "hw/ppc/pnv_xscom.h"
22 #include "hw/irq.h"
23 #include "hw/qdev-properties.h"
24 #include "qom/object.h"
25 #include "sysemu/sysemu.h"
26 #include "trace.h"
28 #define phb_error(phb, fmt, ...) \
29 qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \
30 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)
32 #define phb_pec_error(pec, fmt, ...) \
33 qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \
34 (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
37 * QEMU version of the GETFIELD/SETFIELD macros
39 * These are common with the PnvXive model.
41 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word)
43 return (word & mask) >> ctz64(mask);
46 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
47 uint64_t value)
49 return (word & ~mask) | ((value << ctz64(mask)) & mask);
52 static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb)
54 PCIHostState *pci = PCI_HOST_BRIDGE(phb);
55 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
56 uint8_t bus, devfn;
58 if (!(addr >> 63)) {
59 return NULL;
61 bus = (addr >> 52) & 0xff;
62 devfn = (addr >> 44) & 0xff;
64 /* We don't access the root complex this way */
65 if (bus == 0 && devfn == 0) {
66 return NULL;
68 return pci_find_device(pci->bus, bus, devfn);
72 * The CONFIG_DATA register expects little endian accesses, but as the
73 * region is big endian, we have to swap the value.
75 static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off,
76 unsigned size, uint64_t val)
78 uint32_t cfg_addr, limit;
79 PCIDevice *pdev;
81 pdev = pnv_phb4_find_cfg_dev(phb);
82 if (!pdev) {
83 return;
85 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc;
86 cfg_addr |= off;
87 limit = pci_config_size(pdev);
88 if (limit <= cfg_addr) {
90 * conventional pci device can be behind pcie-to-pci bridge.
91 * 256 <= addr < 4K has no effects.
93 return;
95 switch (size) {
96 case 1:
97 break;
98 case 2:
99 val = bswap16(val);
100 break;
101 case 4:
102 val = bswap32(val);
103 break;
104 default:
105 g_assert_not_reached();
107 pci_host_config_write_common(pdev, cfg_addr, limit, val, size);
110 static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off,
111 unsigned size)
113 uint32_t cfg_addr, limit;
114 PCIDevice *pdev;
115 uint64_t val;
117 pdev = pnv_phb4_find_cfg_dev(phb);
118 if (!pdev) {
119 return ~0ull;
121 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc;
122 cfg_addr |= off;
123 limit = pci_config_size(pdev);
124 if (limit <= cfg_addr) {
126 * conventional pci device can be behind pcie-to-pci bridge.
127 * 256 <= addr < 4K has no effects.
129 return ~0ull;
131 val = pci_host_config_read_common(pdev, cfg_addr, limit, size);
132 switch (size) {
133 case 1:
134 return val;
135 case 2:
136 return bswap16(val);
137 case 4:
138 return bswap32(val);
139 default:
140 g_assert_not_reached();
145 * Root complex register accesses are memory mapped.
147 static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
148 unsigned size, uint64_t val)
150 PCIHostState *pci = PCI_HOST_BRIDGE(phb);
151 PCIDevice *pdev;
153 if (size != 4) {
154 phb_error(phb, "rc_config_write invalid size %d\n", size);
155 return;
158 pdev = pci_find_device(pci->bus, 0, 0);
159 if (!pdev) {
160 phb_error(phb, "rc_config_write device not found\n");
161 return;
164 pci_host_config_write_common(pdev, off, PHB_RC_CONFIG_SIZE,
165 bswap32(val), 4);
168 static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off,
169 unsigned size)
171 PCIHostState *pci = PCI_HOST_BRIDGE(phb);
172 PCIDevice *pdev;
173 uint64_t val;
175 if (size != 4) {
176 phb_error(phb, "rc_config_read invalid size %d\n", size);
177 return ~0ull;
180 pdev = pci_find_device(pci->bus, 0, 0);
181 if (!pdev) {
182 phb_error(phb, "rc_config_read device not found\n");
183 return ~0ull;
186 val = pci_host_config_read_common(pdev, off, PHB_RC_CONFIG_SIZE, 4);
187 return bswap32(val);
190 static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index)
192 uint64_t base, start, size, mbe0, mbe1;
193 MemoryRegion *parent;
194 char name[64];
196 /* Unmap first */
197 if (memory_region_is_mapped(&phb->mr_mmio[index])) {
198 /* Should we destroy it in RCU friendly way... ? */
199 memory_region_del_subregion(phb->mr_mmio[index].container,
200 &phb->mr_mmio[index]);
203 /* Get table entry */
204 mbe0 = phb->ioda_MBT[(index << 1)];
205 mbe1 = phb->ioda_MBT[(index << 1) + 1];
207 if (!(mbe0 & IODA3_MBT0_ENABLE)) {
208 return;
211 /* Grab geometry from registers */
212 base = GETFIELD(IODA3_MBT0_BASE_ADDR, mbe0) << 12;
213 size = GETFIELD(IODA3_MBT1_MASK, mbe1) << 12;
214 size |= 0xff00000000000000ull;
215 size = ~size + 1;
217 /* Calculate PCI side start address based on M32/M64 window type */
218 if (mbe0 & IODA3_MBT0_TYPE_M32) {
219 start = phb->regs[PHB_M32_START_ADDR >> 3];
220 if ((start + size) > 0x100000000ull) {
221 phb_error(phb, "M32 set beyond 4GB boundary !");
222 size = 0x100000000 - start;
224 } else {
225 start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]);
228 /* TODO: Figure out how to implemet/decode AOMASK */
230 /* Check if it matches an enabled MMIO region in the PEC stack */
231 if (memory_region_is_mapped(&phb->stack->mmbar0) &&
232 base >= phb->stack->mmio0_base &&
233 (base + size) <= (phb->stack->mmio0_base + phb->stack->mmio0_size)) {
234 parent = &phb->stack->mmbar0;
235 base -= phb->stack->mmio0_base;
236 } else if (memory_region_is_mapped(&phb->stack->mmbar1) &&
237 base >= phb->stack->mmio1_base &&
238 (base + size) <= (phb->stack->mmio1_base + phb->stack->mmio1_size)) {
239 parent = &phb->stack->mmbar1;
240 base -= phb->stack->mmio1_base;
241 } else {
242 phb_error(phb, "PHB MBAR %d out of parent bounds", index);
243 return;
246 /* Create alias (better name ?) */
247 snprintf(name, sizeof(name), "phb4-mbar%d", index);
248 memory_region_init_alias(&phb->mr_mmio[index], OBJECT(phb), name,
249 &phb->pci_mmio, start, size);
250 memory_region_add_subregion(parent, base, &phb->mr_mmio[index]);
253 static void pnv_phb4_check_all_mbt(PnvPHB4 *phb)
255 uint64_t i;
256 uint32_t num_windows = phb->big_phb ? PNV_PHB4_MAX_MMIO_WINDOWS :
257 PNV_PHB4_MIN_MMIO_WINDOWS;
259 for (i = 0; i < num_windows; i++) {
260 pnv_phb4_check_mbt(phb, i);
264 static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb,
265 unsigned *out_table, unsigned *out_idx)
267 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3];
268 unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg);
269 unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg);
270 unsigned int mask;
271 uint64_t *tptr = NULL;
273 switch (table) {
274 case IODA3_TBL_LIST:
275 tptr = phb->ioda_LIST;
276 mask = 7;
277 break;
278 case IODA3_TBL_MIST:
279 tptr = phb->ioda_MIST;
280 mask = phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> 1);
281 mask -= 1;
282 break;
283 case IODA3_TBL_RCAM:
284 mask = phb->big_phb ? 127 : 63;
285 break;
286 case IODA3_TBL_MRT:
287 mask = phb->big_phb ? 15 : 7;
288 break;
289 case IODA3_TBL_PESTA:
290 case IODA3_TBL_PESTB:
291 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1);
292 mask -= 1;
293 break;
294 case IODA3_TBL_TVT:
295 tptr = phb->ioda_TVT;
296 mask = phb->big_phb ? PNV_PHB4_MAX_TVEs : (PNV_PHB4_MAX_TVEs >> 1);
297 mask -= 1;
298 break;
299 case IODA3_TBL_TCR:
300 case IODA3_TBL_TDR:
301 mask = phb->big_phb ? 1023 : 511;
302 break;
303 case IODA3_TBL_MBT:
304 tptr = phb->ioda_MBT;
305 mask = phb->big_phb ? PNV_PHB4_MAX_MBEs : (PNV_PHB4_MAX_MBEs >> 1);
306 mask -= 1;
307 break;
308 case IODA3_TBL_MDT:
309 tptr = phb->ioda_MDT;
310 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1);
311 mask -= 1;
312 break;
313 case IODA3_TBL_PEEV:
314 tptr = phb->ioda_PEEV;
315 mask = phb->big_phb ? PNV_PHB4_MAX_PEEVs : (PNV_PHB4_MAX_PEEVs >> 1);
316 mask -= 1;
317 break;
318 default:
319 phb_error(phb, "invalid IODA table %d", table);
320 return NULL;
322 index &= mask;
323 if (out_idx) {
324 *out_idx = index;
326 if (out_table) {
327 *out_table = table;
329 if (tptr) {
330 tptr += index;
332 if (adreg & PHB_IODA_AD_AUTOINC) {
333 index = (index + 1) & mask;
334 adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index);
337 phb->regs[PHB_IODA_ADDR >> 3] = adreg;
338 return tptr;
341 static uint64_t pnv_phb4_ioda_read(PnvPHB4 *phb)
343 unsigned table, idx;
344 uint64_t *tptr;
346 tptr = pnv_phb4_ioda_access(phb, &table, &idx);
347 if (!tptr) {
348 /* Special PESTA case */
349 if (table == IODA3_TBL_PESTA) {
350 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 1)) << 63;
351 } else if (table == IODA3_TBL_PESTB) {
352 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 2)) << 62;
354 /* Return 0 on unsupported tables, not ff's */
355 return 0;
357 return *tptr;
360 static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val)
362 unsigned table, idx;
363 uint64_t *tptr;
365 tptr = pnv_phb4_ioda_access(phb, &table, &idx);
366 if (!tptr) {
367 /* Special PESTA case */
368 if (table == IODA3_TBL_PESTA) {
369 phb->ioda_PEST_AB[idx] &= ~1;
370 phb->ioda_PEST_AB[idx] |= (val >> 63) & 1;
371 } else if (table == IODA3_TBL_PESTB) {
372 phb->ioda_PEST_AB[idx] &= ~2;
373 phb->ioda_PEST_AB[idx] |= (val >> 62) & 2;
375 return;
378 /* Handle side effects */
379 switch (table) {
380 case IODA3_TBL_LIST:
381 break;
382 case IODA3_TBL_MIST: {
383 /* Special mask for MIST partial write */
384 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3];
385 uint32_t mmask = GETFIELD(PHB_IODA_AD_MIST_PWV, adreg);
386 uint64_t v = *tptr;
387 if (mmask == 0) {
388 mmask = 0xf;
390 if (mmask & 8) {
391 v &= 0x0000ffffffffffffull;
392 v |= 0xcfff000000000000ull & val;
394 if (mmask & 4) {
395 v &= 0xffff0000ffffffffull;
396 v |= 0x0000cfff00000000ull & val;
398 if (mmask & 2) {
399 v &= 0xffffffff0000ffffull;
400 v |= 0x00000000cfff0000ull & val;
402 if (mmask & 1) {
403 v &= 0xffffffffffff0000ull;
404 v |= 0x000000000000cfffull & val;
406 *tptr = v;
407 break;
409 case IODA3_TBL_MBT:
410 *tptr = val;
412 /* Copy accross the valid bit to the other half */
413 phb->ioda_MBT[idx ^ 1] &= 0x7fffffffffffffffull;
414 phb->ioda_MBT[idx ^ 1] |= 0x8000000000000000ull & val;
416 /* Update mappings */
417 pnv_phb4_check_mbt(phb, idx >> 1);
418 break;
419 default:
420 *tptr = val;
424 static void pnv_phb4_rtc_invalidate(PnvPHB4 *phb, uint64_t val)
426 PnvPhb4DMASpace *ds;
428 /* Always invalidate all for now ... */
429 QLIST_FOREACH(ds, &phb->dma_spaces, list) {
430 ds->pe_num = PHB_INVALID_PE;
434 static void pnv_phb4_update_msi_regions(PnvPhb4DMASpace *ds)
436 uint64_t cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3];
438 if (cfg & PHB_PHB4C_32BIT_MSI_EN) {
439 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) {
440 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr),
441 0xffff0000, &ds->msi32_mr);
443 } else {
444 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) {
445 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr),
446 &ds->msi32_mr);
450 if (cfg & PHB_PHB4C_64BIT_MSI_EN) {
451 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) {
452 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr),
453 (1ull << 60), &ds->msi64_mr);
455 } else {
456 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) {
457 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr),
458 &ds->msi64_mr);
463 static void pnv_phb4_update_all_msi_regions(PnvPHB4 *phb)
465 PnvPhb4DMASpace *ds;
467 QLIST_FOREACH(ds, &phb->dma_spaces, list) {
468 pnv_phb4_update_msi_regions(ds);
472 static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
474 int shift, flags, i, lsi_base;
475 XiveSource *xsrc = &phb->xsrc;
477 /* The XIVE source characteristics can be set at run time */
478 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PGSZ_64K) {
479 shift = XIVE_ESB_64K;
480 } else {
481 shift = XIVE_ESB_4K;
483 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_STORE_EOI) {
484 flags = XIVE_SRC_STORE_EOI;
485 } else {
486 flags = 0;
489 phb->xsrc.esb_shift = shift;
490 phb->xsrc.esb_flags = flags;
492 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
493 lsi_base <<= 3;
495 /* TODO: handle reset values of PHB_LSI_SRC_ID */
496 if (!lsi_base) {
497 return;
500 /* TODO: need a xive_source_irq_reset_lsi() */
501 bitmap_zero(xsrc->lsi_map, xsrc->nr_irqs);
503 for (i = 0; i < xsrc->nr_irqs; i++) {
504 bool msi = (i < lsi_base || i >= (lsi_base + 8));
505 if (!msi) {
506 xive_source_irq_set_lsi(xsrc, i);
511 static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,
512 unsigned size)
514 PnvPHB4 *phb = PNV_PHB4(opaque);
515 bool changed;
517 /* Special case outbound configuration data */
518 if ((off & 0xfffc) == PHB_CONFIG_DATA) {
519 pnv_phb4_config_write(phb, off & 0x3, size, val);
520 return;
523 /* Special case RC configuration space */
524 if ((off & 0xf800) == PHB_RC_CONFIG_BASE) {
525 pnv_phb4_rc_config_write(phb, off & 0x7ff, size, val);
526 return;
529 /* Other registers are 64-bit only */
530 if (size != 8 || off & 0x7) {
531 phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d",
532 off, size);
533 return;
536 /* Handle masking */
537 switch (off) {
538 case PHB_LSI_SOURCE_ID:
539 val &= PHB_LSI_SRC_ID;
540 break;
541 case PHB_M64_UPPER_BITS:
542 val &= 0xff00000000000000ull;
543 break;
544 /* TCE Kill */
545 case PHB_TCE_KILL:
546 /* Clear top 3 bits which HW does to indicate successful queuing */
547 val &= ~(PHB_TCE_KILL_ALL | PHB_TCE_KILL_PE | PHB_TCE_KILL_ONE);
548 break;
549 case PHB_Q_DMA_R:
551 * This is enough logic to make SW happy but we aren't
552 * actually quiescing the DMAs
554 if (val & PHB_Q_DMA_R_AUTORESET) {
555 val = 0;
556 } else {
557 val &= PHB_Q_DMA_R_QUIESCE_DMA;
559 break;
560 /* LEM stuff */
561 case PHB_LEM_FIR_AND_MASK:
562 phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val;
563 return;
564 case PHB_LEM_FIR_OR_MASK:
565 phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val;
566 return;
567 case PHB_LEM_ERROR_AND_MASK:
568 phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val;
569 return;
570 case PHB_LEM_ERROR_OR_MASK:
571 phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val;
572 return;
573 case PHB_LEM_WOF:
574 val = 0;
575 break;
576 /* TODO: More regs ..., maybe create a table with masks... */
578 /* Read only registers */
579 case PHB_CPU_LOADSTORE_STATUS:
580 case PHB_ETU_ERR_SUMMARY:
581 case PHB_PHB4_GEN_CAP:
582 case PHB_PHB4_TCE_CAP:
583 case PHB_PHB4_IRQ_CAP:
584 case PHB_PHB4_EEH_CAP:
585 return;
588 /* Record whether it changed */
589 changed = phb->regs[off >> 3] != val;
591 /* Store in register cache first */
592 phb->regs[off >> 3] = val;
594 /* Handle side effects */
595 switch (off) {
596 case PHB_PHB4_CONFIG:
597 if (changed) {
598 pnv_phb4_update_all_msi_regions(phb);
600 break;
601 case PHB_M32_START_ADDR:
602 case PHB_M64_UPPER_BITS:
603 if (changed) {
604 pnv_phb4_check_all_mbt(phb);
606 break;
608 /* IODA table accesses */
609 case PHB_IODA_DATA0:
610 pnv_phb4_ioda_write(phb, val);
611 break;
613 /* RTC invalidation */
614 case PHB_RTC_INVALIDATE:
615 pnv_phb4_rtc_invalidate(phb, val);
616 break;
618 /* PHB Control (Affects XIVE source) */
619 case PHB_CTRLR:
620 case PHB_LSI_SOURCE_ID:
621 pnv_phb4_update_xsrc(phb);
622 break;
624 /* Silent simple writes */
625 case PHB_ASN_CMPM:
626 case PHB_CONFIG_ADDRESS:
627 case PHB_IODA_ADDR:
628 case PHB_TCE_KILL:
629 case PHB_TCE_SPEC_CTL:
630 case PHB_PEST_BAR:
631 case PHB_PELTV_BAR:
632 case PHB_RTT_BAR:
633 case PHB_LEM_FIR_ACCUM:
634 case PHB_LEM_ERROR_MASK:
635 case PHB_LEM_ACTION0:
636 case PHB_LEM_ACTION1:
637 case PHB_TCE_TAG_ENABLE:
638 case PHB_INT_NOTIFY_ADDR:
639 case PHB_INT_NOTIFY_INDEX:
640 case PHB_DMARD_SYNC:
641 break;
643 /* Noise on anything else */
644 default:
645 qemu_log_mask(LOG_UNIMP, "phb4: reg_write 0x%"PRIx64"=%"PRIx64"\n",
646 off, val);
650 static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size)
652 PnvPHB4 *phb = PNV_PHB4(opaque);
653 uint64_t val;
655 if ((off & 0xfffc) == PHB_CONFIG_DATA) {
656 return pnv_phb4_config_read(phb, off & 0x3, size);
659 /* Special case RC configuration space */
660 if ((off & 0xf800) == PHB_RC_CONFIG_BASE) {
661 return pnv_phb4_rc_config_read(phb, off & 0x7ff, size);
664 /* Other registers are 64-bit only */
665 if (size != 8 || off & 0x7) {
666 phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d",
667 off, size);
668 return ~0ull;
671 /* Default read from cache */
672 val = phb->regs[off >> 3];
674 switch (off) {
675 case PHB_VERSION:
676 return phb->version;
678 /* Read-only */
679 case PHB_PHB4_GEN_CAP:
680 return 0xe4b8000000000000ull;
681 case PHB_PHB4_TCE_CAP:
682 return phb->big_phb ? 0x4008440000000400ull : 0x2008440000000200ull;
683 case PHB_PHB4_IRQ_CAP:
684 return phb->big_phb ? 0x0800000000001000ull : 0x0800000000000800ull;
685 case PHB_PHB4_EEH_CAP:
686 return phb->big_phb ? 0x2000000000000000ull : 0x1000000000000000ull;
688 /* IODA table accesses */
689 case PHB_IODA_DATA0:
690 return pnv_phb4_ioda_read(phb);
692 /* Link training always appears trained */
693 case PHB_PCIE_DLP_TRAIN_CTL:
694 /* TODO: Do something sensible with speed ? */
695 return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;
697 /* DMA read sync: make it look like it's complete */
698 case PHB_DMARD_SYNC:
699 return PHB_DMARD_SYNC_COMPLETE;
701 /* Silent simple reads */
702 case PHB_LSI_SOURCE_ID:
703 case PHB_CPU_LOADSTORE_STATUS:
704 case PHB_ASN_CMPM:
705 case PHB_PHB4_CONFIG:
706 case PHB_M32_START_ADDR:
707 case PHB_CONFIG_ADDRESS:
708 case PHB_IODA_ADDR:
709 case PHB_RTC_INVALIDATE:
710 case PHB_TCE_KILL:
711 case PHB_TCE_SPEC_CTL:
712 case PHB_PEST_BAR:
713 case PHB_PELTV_BAR:
714 case PHB_RTT_BAR:
715 case PHB_M64_UPPER_BITS:
716 case PHB_CTRLR:
717 case PHB_LEM_FIR_ACCUM:
718 case PHB_LEM_ERROR_MASK:
719 case PHB_LEM_ACTION0:
720 case PHB_LEM_ACTION1:
721 case PHB_TCE_TAG_ENABLE:
722 case PHB_INT_NOTIFY_ADDR:
723 case PHB_INT_NOTIFY_INDEX:
724 case PHB_Q_DMA_R:
725 case PHB_ETU_ERR_SUMMARY:
726 break;
728 /* Noise on anything else */
729 default:
730 qemu_log_mask(LOG_UNIMP, "phb4: reg_read 0x%"PRIx64"=%"PRIx64"\n",
731 off, val);
733 return val;
736 static const MemoryRegionOps pnv_phb4_reg_ops = {
737 .read = pnv_phb4_reg_read,
738 .write = pnv_phb4_reg_write,
739 .valid.min_access_size = 1,
740 .valid.max_access_size = 8,
741 .impl.min_access_size = 1,
742 .impl.max_access_size = 8,
743 .endianness = DEVICE_BIG_ENDIAN,
746 static uint64_t pnv_phb4_xscom_read(void *opaque, hwaddr addr, unsigned size)
748 PnvPHB4 *phb = PNV_PHB4(opaque);
749 uint32_t reg = addr >> 3;
750 uint64_t val;
751 hwaddr offset;
753 switch (reg) {
754 case PHB_SCOM_HV_IND_ADDR:
755 return phb->scom_hv_ind_addr_reg;
757 case PHB_SCOM_HV_IND_DATA:
758 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) {
759 phb_error(phb, "Invalid indirect address");
760 return ~0ull;
762 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8;
763 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg);
764 val = pnv_phb4_reg_read(phb, offset, size);
765 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) {
766 offset += size;
767 offset &= 0x3fff;
768 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR,
769 phb->scom_hv_ind_addr_reg,
770 offset);
772 return val;
773 case PHB_SCOM_ETU_LEM_FIR:
774 case PHB_SCOM_ETU_LEM_FIR_AND:
775 case PHB_SCOM_ETU_LEM_FIR_OR:
776 case PHB_SCOM_ETU_LEM_FIR_MSK:
777 case PHB_SCOM_ETU_LEM_ERR_MSK_AND:
778 case PHB_SCOM_ETU_LEM_ERR_MSK_OR:
779 case PHB_SCOM_ETU_LEM_ACT0:
780 case PHB_SCOM_ETU_LEM_ACT1:
781 case PHB_SCOM_ETU_LEM_WOF:
782 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM;
783 return pnv_phb4_reg_read(phb, offset, size);
784 case PHB_SCOM_ETU_PMON_CONFIG:
785 case PHB_SCOM_ETU_PMON_CTR0:
786 case PHB_SCOM_ETU_PMON_CTR1:
787 case PHB_SCOM_ETU_PMON_CTR2:
788 case PHB_SCOM_ETU_PMON_CTR3:
789 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG;
790 return pnv_phb4_reg_read(phb, offset, size);
792 default:
793 qemu_log_mask(LOG_UNIMP, "phb4: xscom_read 0x%"HWADDR_PRIx"\n", addr);
794 return ~0ull;
798 static void pnv_phb4_xscom_write(void *opaque, hwaddr addr,
799 uint64_t val, unsigned size)
801 PnvPHB4 *phb = PNV_PHB4(opaque);
802 uint32_t reg = addr >> 3;
803 hwaddr offset;
805 switch (reg) {
806 case PHB_SCOM_HV_IND_ADDR:
807 phb->scom_hv_ind_addr_reg = val & 0xe000000000001fff;
808 break;
809 case PHB_SCOM_HV_IND_DATA:
810 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) {
811 phb_error(phb, "Invalid indirect address");
812 break;
814 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8;
815 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg);
816 pnv_phb4_reg_write(phb, offset, val, size);
817 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) {
818 offset += size;
819 offset &= 0x3fff;
820 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR,
821 phb->scom_hv_ind_addr_reg,
822 offset);
824 break;
825 case PHB_SCOM_ETU_LEM_FIR:
826 case PHB_SCOM_ETU_LEM_FIR_AND:
827 case PHB_SCOM_ETU_LEM_FIR_OR:
828 case PHB_SCOM_ETU_LEM_FIR_MSK:
829 case PHB_SCOM_ETU_LEM_ERR_MSK_AND:
830 case PHB_SCOM_ETU_LEM_ERR_MSK_OR:
831 case PHB_SCOM_ETU_LEM_ACT0:
832 case PHB_SCOM_ETU_LEM_ACT1:
833 case PHB_SCOM_ETU_LEM_WOF:
834 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM;
835 pnv_phb4_reg_write(phb, offset, val, size);
836 break;
837 case PHB_SCOM_ETU_PMON_CONFIG:
838 case PHB_SCOM_ETU_PMON_CTR0:
839 case PHB_SCOM_ETU_PMON_CTR1:
840 case PHB_SCOM_ETU_PMON_CTR2:
841 case PHB_SCOM_ETU_PMON_CTR3:
842 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG;
843 pnv_phb4_reg_write(phb, offset, val, size);
844 break;
845 default:
846 qemu_log_mask(LOG_UNIMP, "phb4: xscom_write 0x%"HWADDR_PRIx
847 "=%"PRIx64"\n", addr, val);
851 const MemoryRegionOps pnv_phb4_xscom_ops = {
852 .read = pnv_phb4_xscom_read,
853 .write = pnv_phb4_xscom_write,
854 .valid.min_access_size = 8,
855 .valid.max_access_size = 8,
856 .impl.min_access_size = 8,
857 .impl.max_access_size = 8,
858 .endianness = DEVICE_BIG_ENDIAN,
861 static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr,
862 unsigned size)
864 PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
865 uint32_t reg = addr >> 3;
867 /* TODO: add list of allowed registers and error out if not */
868 return stack->nest_regs[reg];
871 static void pnv_phb4_update_regions(PnvPHB4 *phb)
873 /* Unmap first always */
874 if (memory_region_is_mapped(&phb->mr_regs)) {
875 memory_region_del_subregion(&phb->phbbar, &phb->mr_regs);
877 if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) {
878 memory_region_del_subregion(&phb->intbar, &phb->xsrc.esb_mmio);
881 /* Map registers if enabled */
882 if (memory_region_is_mapped(&phb->phbbar)) {
883 memory_region_add_subregion(&phb->phbbar, 0, &phb->mr_regs);
886 /* Map ESB if enabled */
887 if (memory_region_is_mapped(&phb->intbar)) {
888 memory_region_add_subregion(&phb->intbar, 0, &phb->xsrc.esb_mmio);
891 /* Check/update m32 */
892 pnv_phb4_check_all_mbt(phb);
895 static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack)
897 PnvPhb4PecState *pec = stack->pec;
898 PnvPHB4 *phb = stack->phb;
899 MemoryRegion *sysmem = get_system_memory();
900 uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN];
901 uint64_t bar, mask, size;
902 char name[64];
905 * NOTE: This will really not work well if those are remapped
906 * after the PHB has created its sub regions. We could do better
907 * if we had a way to resize regions but we don't really care
908 * that much in practice as the stuff below really only happens
909 * once early during boot
912 /* Handle unmaps */
913 if (memory_region_is_mapped(&stack->mmbar0) &&
914 !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
915 memory_region_del_subregion(sysmem, &stack->mmbar0);
917 if (memory_region_is_mapped(&stack->mmbar1) &&
918 !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
919 memory_region_del_subregion(sysmem, &stack->mmbar1);
921 if (memory_region_is_mapped(&phb->phbbar) &&
922 !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
923 memory_region_del_subregion(sysmem, &phb->phbbar);
925 if (memory_region_is_mapped(&phb->intbar) &&
926 !(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
927 memory_region_del_subregion(sysmem, &phb->intbar);
930 /* Update PHB */
931 pnv_phb4_update_regions(phb);
933 /* Handle maps */
934 if (!memory_region_is_mapped(&stack->mmbar0) &&
935 (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
936 bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8;
937 mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK];
938 size = ((~mask) >> 8) + 1;
939 snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0",
940 pec->chip_id, pec->index, stack->stack_no);
941 memory_region_init(&stack->mmbar0, OBJECT(stack), name, size);
942 memory_region_add_subregion(sysmem, bar, &stack->mmbar0);
943 stack->mmio0_base = bar;
944 stack->mmio0_size = size;
946 if (!memory_region_is_mapped(&stack->mmbar1) &&
947 (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
948 bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8;
949 mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK];
950 size = ((~mask) >> 8) + 1;
951 snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1",
952 pec->chip_id, pec->index, stack->stack_no);
953 memory_region_init(&stack->mmbar1, OBJECT(stack), name, size);
954 memory_region_add_subregion(sysmem, bar, &stack->mmbar1);
955 stack->mmio1_base = bar;
956 stack->mmio1_size = size;
958 if (!memory_region_is_mapped(&phb->phbbar) &&
959 (bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
960 bar = stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8;
961 size = PNV_PHB4_NUM_REGS << 3;
962 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d",
963 pec->chip_id, pec->index, stack->stack_no);
964 memory_region_init(&phb->phbbar, OBJECT(phb), name, size);
965 memory_region_add_subregion(sysmem, bar, &phb->phbbar);
967 if (!memory_region_is_mapped(&phb->intbar) &&
968 (bar_en & PEC_NEST_STK_BAR_EN_INT)) {
969 bar = stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8;
970 size = PNV_PHB4_MAX_INTs << 16;
971 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-int",
972 stack->pec->chip_id, stack->pec->index, stack->stack_no);
973 memory_region_init(&phb->intbar, OBJECT(phb), name, size);
974 memory_region_add_subregion(sysmem, bar, &phb->intbar);
977 /* Update PHB */
978 pnv_phb4_update_regions(phb);
981 static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
982 uint64_t val, unsigned size)
984 PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
985 PnvPhb4PecState *pec = stack->pec;
986 uint32_t reg = addr >> 3;
988 switch (reg) {
989 case PEC_NEST_STK_PCI_NEST_FIR:
990 stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
991 break;
992 case PEC_NEST_STK_PCI_NEST_FIR_CLR:
993 stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
994 break;
995 case PEC_NEST_STK_PCI_NEST_FIR_SET:
996 stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
997 break;
998 case PEC_NEST_STK_PCI_NEST_FIR_MSK:
999 stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
1000 break;
1001 case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
1002 stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
1003 break;
1004 case PEC_NEST_STK_PCI_NEST_FIR_MSKS:
1005 stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val;
1006 break;
1007 case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
1008 case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
1009 stack->nest_regs[reg] = val;
1010 break;
1011 case PEC_NEST_STK_PCI_NEST_FIR_WOF:
1012 stack->nest_regs[reg] = 0;
1013 break;
1014 case PEC_NEST_STK_ERR_REPORT_0:
1015 case PEC_NEST_STK_ERR_REPORT_1:
1016 case PEC_NEST_STK_PBCQ_GNRL_STATUS:
1017 /* Flag error ? */
1018 break;
1019 case PEC_NEST_STK_PBCQ_MODE:
1020 stack->nest_regs[reg] = val & 0xff00000000000000ull;
1021 break;
1022 case PEC_NEST_STK_MMIO_BAR0:
1023 case PEC_NEST_STK_MMIO_BAR0_MASK:
1024 case PEC_NEST_STK_MMIO_BAR1:
1025 case PEC_NEST_STK_MMIO_BAR1_MASK:
1026 if (stack->nest_regs[PEC_NEST_STK_BAR_EN] &
1027 (PEC_NEST_STK_BAR_EN_MMIO0 |
1028 PEC_NEST_STK_BAR_EN_MMIO1)) {
1029 phb_pec_error(pec, "Changing enabled BAR unsupported\n");
1031 stack->nest_regs[reg] = val & 0xffffffffff000000ull;
1032 break;
1033 case PEC_NEST_STK_PHB_REGS_BAR:
1034 if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
1035 phb_pec_error(pec, "Changing enabled BAR unsupported\n");
1037 stack->nest_regs[reg] = val & 0xffffffffffc00000ull;
1038 break;
1039 case PEC_NEST_STK_INT_BAR:
1040 if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
1041 phb_pec_error(pec, "Changing enabled BAR unsupported\n");
1043 stack->nest_regs[reg] = val & 0xfffffff000000000ull;
1044 break;
1045 case PEC_NEST_STK_BAR_EN:
1046 stack->nest_regs[reg] = val & 0xf000000000000000ull;
1047 pnv_pec_stk_update_map(stack);
1048 break;
1049 case PEC_NEST_STK_DATA_FRZ_TYPE:
1050 case PEC_NEST_STK_PBCQ_TUN_BAR:
1051 /* Not used for now */
1052 stack->nest_regs[reg] = val;
1053 break;
1054 default:
1055 qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
1056 "=%"PRIx64"\n", addr, val);
1060 static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = {
1061 .read = pnv_pec_stk_nest_xscom_read,
1062 .write = pnv_pec_stk_nest_xscom_write,
1063 .valid.min_access_size = 8,
1064 .valid.max_access_size = 8,
1065 .impl.min_access_size = 8,
1066 .impl.max_access_size = 8,
1067 .endianness = DEVICE_BIG_ENDIAN,
1070 static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr,
1071 unsigned size)
1073 PnvPHB4 *phb = PNV_PHB4(opaque);
1074 uint32_t reg = addr >> 3;
1076 /* TODO: add list of allowed registers and error out if not */
1077 return phb->pci_regs[reg];
1080 static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr,
1081 uint64_t val, unsigned size)
1083 PnvPHB4 *phb = PNV_PHB4(opaque);
1084 uint32_t reg = addr >> 3;
1086 switch (reg) {
1087 case PEC_PCI_STK_PCI_FIR:
1088 phb->pci_regs[reg] = val;
1089 break;
1090 case PEC_PCI_STK_PCI_FIR_CLR:
1091 phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
1092 break;
1093 case PEC_PCI_STK_PCI_FIR_SET:
1094 phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
1095 break;
1096 case PEC_PCI_STK_PCI_FIR_MSK:
1097 phb->pci_regs[reg] = val;
1098 break;
1099 case PEC_PCI_STK_PCI_FIR_MSKC:
1100 phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
1101 break;
1102 case PEC_PCI_STK_PCI_FIR_MSKS:
1103 phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
1104 break;
1105 case PEC_PCI_STK_PCI_FIR_ACT0:
1106 case PEC_PCI_STK_PCI_FIR_ACT1:
1107 phb->pci_regs[reg] = val;
1108 break;
1109 case PEC_PCI_STK_PCI_FIR_WOF:
1110 phb->pci_regs[reg] = 0;
1111 break;
1112 case PEC_PCI_STK_ETU_RESET:
1113 phb->pci_regs[reg] = val & 0x8000000000000000ull;
1114 /* TODO: Implement reset */
1115 break;
1116 case PEC_PCI_STK_PBAIB_ERR_REPORT:
1117 break;
1118 case PEC_PCI_STK_PBAIB_TX_CMD_CRED:
1119 case PEC_PCI_STK_PBAIB_TX_DAT_CRED:
1120 phb->pci_regs[reg] = val;
1121 break;
1122 default:
1123 qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx
1124 "=%"PRIx64"\n", addr, val);
1128 static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops = {
1129 .read = pnv_pec_stk_pci_xscom_read,
1130 .write = pnv_pec_stk_pci_xscom_write,
1131 .valid.min_access_size = 8,
1132 .valid.max_access_size = 8,
1133 .impl.min_access_size = 8,
1134 .impl.max_access_size = 8,
1135 .endianness = DEVICE_BIG_ENDIAN,
1138 static int pnv_phb4_map_irq(PCIDevice *pci_dev, int irq_num)
1140 /* Check that out properly ... */
1141 return irq_num & 3;
1144 static void pnv_phb4_set_irq(void *opaque, int irq_num, int level)
1146 PnvPHB4 *phb = PNV_PHB4(opaque);
1147 uint32_t lsi_base;
1149 /* LSI only ... */
1150 if (irq_num > 3) {
1151 phb_error(phb, "IRQ %x is not an LSI", irq_num);
1153 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
1154 lsi_base <<= 3;
1155 qemu_set_irq(phb->qirqs[lsi_base + irq_num], level);
1158 static bool pnv_phb4_resolve_pe(PnvPhb4DMASpace *ds)
1160 uint64_t rtt, addr;
1161 uint16_t rte;
1162 int bus_num;
1163 int num_PEs;
1165 /* Already resolved ? */
1166 if (ds->pe_num != PHB_INVALID_PE) {
1167 return true;
1170 /* We need to lookup the RTT */
1171 rtt = ds->phb->regs[PHB_RTT_BAR >> 3];
1172 if (!(rtt & PHB_RTT_BAR_ENABLE)) {
1173 phb_error(ds->phb, "DMA with RTT BAR disabled !");
1174 /* Set error bits ? fence ? ... */
1175 return false;
1178 /* Read RTE */
1179 bus_num = pci_bus_num(ds->bus);
1180 addr = rtt & PHB_RTT_BASE_ADDRESS_MASK;
1181 addr += 2 * PCI_BUILD_BDF(bus_num, ds->devfn);
1182 if (dma_memory_read(&address_space_memory, addr, &rte,
1183 sizeof(rte), MEMTXATTRS_UNSPECIFIED)) {
1184 phb_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr);
1185 /* Set error bits ? fence ? ... */
1186 return false;
1188 rte = be16_to_cpu(rte);
1190 /* Fail upon reading of invalid PE# */
1191 num_PEs = ds->phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1);
1192 if (rte >= num_PEs) {
1193 phb_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte);
1194 rte &= num_PEs - 1;
1196 ds->pe_num = rte;
1197 return true;
1200 static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds, hwaddr addr,
1201 bool is_write, uint64_t tve,
1202 IOMMUTLBEntry *tlb)
1204 uint64_t tta = GETFIELD(IODA3_TVT_TABLE_ADDR, tve);
1205 int32_t lev = GETFIELD(IODA3_TVT_NUM_LEVELS, tve);
1206 uint32_t tts = GETFIELD(IODA3_TVT_TCE_TABLE_SIZE, tve);
1207 uint32_t tps = GETFIELD(IODA3_TVT_IO_PSIZE, tve);
1209 /* Invalid levels */
1210 if (lev > 4) {
1211 phb_error(ds->phb, "Invalid #levels in TVE %d", lev);
1212 return;
1215 /* Invalid entry */
1216 if (tts == 0) {
1217 phb_error(ds->phb, "Access to invalid TVE");
1218 return;
1221 /* IO Page Size of 0 means untranslated, else use TCEs */
1222 if (tps == 0) {
1223 /* TODO: Handle boundaries */
1225 /* Use 4k pages like q35 ... for now */
1226 tlb->iova = addr & 0xfffffffffffff000ull;
1227 tlb->translated_addr = addr & 0x0003fffffffff000ull;
1228 tlb->addr_mask = 0xfffull;
1229 tlb->perm = IOMMU_RW;
1230 } else {
1231 uint32_t tce_shift, tbl_shift, sh;
1232 uint64_t base, taddr, tce, tce_mask;
1234 /* Address bits per bottom level TCE entry */
1235 tce_shift = tps + 11;
1237 /* Address bits per table level */
1238 tbl_shift = tts + 8;
1240 /* Top level table base address */
1241 base = tta << 12;
1243 /* Total shift to first level */
1244 sh = tbl_shift * lev + tce_shift;
1246 /* TODO: Limit to support IO page sizes */
1248 /* TODO: Multi-level untested */
1249 while ((lev--) >= 0) {
1250 /* Grab the TCE address */
1251 taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3);
1252 if (dma_memory_read(&address_space_memory, taddr, &tce,
1253 sizeof(tce), MEMTXATTRS_UNSPECIFIED)) {
1254 phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, taddr);
1255 return;
1257 tce = be64_to_cpu(tce);
1259 /* Check permission for indirect TCE */
1260 if ((lev >= 0) && !(tce & 3)) {
1261 phb_error(ds->phb, "Invalid indirect TCE at 0x%"PRIx64, taddr);
1262 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr,
1263 is_write ? 'W' : 'R', tve);
1264 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d",
1265 tta, lev, tts, tps);
1266 return;
1268 sh -= tbl_shift;
1269 base = tce & ~0xfffull;
1272 /* We exit the loop with TCE being the final TCE */
1273 tce_mask = ~((1ull << tce_shift) - 1);
1274 tlb->iova = addr & tce_mask;
1275 tlb->translated_addr = tce & tce_mask;
1276 tlb->addr_mask = ~tce_mask;
1277 tlb->perm = tce & 3;
1278 if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) {
1279 phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr);
1280 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr,
1281 is_write ? 'W' : 'R', tve);
1282 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d",
1283 tta, lev, tts, tps);
1288 static IOMMUTLBEntry pnv_phb4_translate_iommu(IOMMUMemoryRegion *iommu,
1289 hwaddr addr,
1290 IOMMUAccessFlags flag,
1291 int iommu_idx)
1293 PnvPhb4DMASpace *ds = container_of(iommu, PnvPhb4DMASpace, dma_mr);
1294 int tve_sel;
1295 uint64_t tve, cfg;
1296 IOMMUTLBEntry ret = {
1297 .target_as = &address_space_memory,
1298 .iova = addr,
1299 .translated_addr = 0,
1300 .addr_mask = ~(hwaddr)0,
1301 .perm = IOMMU_NONE,
1304 /* Resolve PE# */
1305 if (!pnv_phb4_resolve_pe(ds)) {
1306 phb_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
1307 ds->bus, pci_bus_num(ds->bus), ds->devfn);
1308 return ret;
1311 /* Check top bits */
1312 switch (addr >> 60) {
1313 case 00:
1314 /* DMA or 32-bit MSI ? */
1315 cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3];
1316 if ((cfg & PHB_PHB4C_32BIT_MSI_EN) &&
1317 ((addr & 0xffffffffffff0000ull) == 0xffff0000ull)) {
1318 phb_error(ds->phb, "xlate on 32-bit MSI region");
1319 return ret;
1321 /* Choose TVE XXX Use PHB4 Control Register */
1322 tve_sel = (addr >> 59) & 1;
1323 tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel];
1324 pnv_phb4_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret);
1325 break;
1326 case 01:
1327 phb_error(ds->phb, "xlate on 64-bit MSI region");
1328 break;
1329 default:
1330 phb_error(ds->phb, "xlate on unsupported address 0x%"PRIx64, addr);
1332 return ret;
1335 #define TYPE_PNV_PHB4_IOMMU_MEMORY_REGION "pnv-phb4-iommu-memory-region"
1336 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, PNV_PHB4_IOMMU_MEMORY_REGION,
1337 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION)
1339 static void pnv_phb4_iommu_memory_region_class_init(ObjectClass *klass,
1340 void *data)
1342 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
1344 imrc->translate = pnv_phb4_translate_iommu;
1347 static const TypeInfo pnv_phb4_iommu_memory_region_info = {
1348 .parent = TYPE_IOMMU_MEMORY_REGION,
1349 .name = TYPE_PNV_PHB4_IOMMU_MEMORY_REGION,
1350 .class_init = pnv_phb4_iommu_memory_region_class_init,
1354 * Return the index/phb-id of a PHB4 that belongs to a
1355 * pec->stacks[stack_index] stack.
1357 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index)
1359 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1360 int index = pec->index;
1361 int offset = 0;
1363 while (index--) {
1364 offset += pecc->num_stacks[index];
1367 return offset + stack_index;
1371 * MSI/MSIX memory region implementation.
1372 * The handler handles both MSI and MSIX.
1374 static void pnv_phb4_msi_write(void *opaque, hwaddr addr,
1375 uint64_t data, unsigned size)
1377 PnvPhb4DMASpace *ds = opaque;
1378 PnvPHB4 *phb = ds->phb;
1380 uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f);
1382 /* Resolve PE# */
1383 if (!pnv_phb4_resolve_pe(ds)) {
1384 phb_error(phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
1385 ds->bus, pci_bus_num(ds->bus), ds->devfn);
1386 return;
1389 /* TODO: Check it doesn't collide with LSIs */
1390 if (src >= phb->xsrc.nr_irqs) {
1391 phb_error(phb, "MSI %d out of bounds", src);
1392 return;
1395 /* TODO: check PE/MSI assignement */
1397 qemu_irq_pulse(phb->qirqs[src]);
1400 /* There is no .read as the read result is undefined by PCI spec */
1401 static uint64_t pnv_phb4_msi_read(void *opaque, hwaddr addr, unsigned size)
1403 PnvPhb4DMASpace *ds = opaque;
1405 phb_error(ds->phb, "Invalid MSI read @ 0x%" HWADDR_PRIx, addr);
1406 return -1;
1409 static const MemoryRegionOps pnv_phb4_msi_ops = {
1410 .read = pnv_phb4_msi_read,
1411 .write = pnv_phb4_msi_write,
1412 .endianness = DEVICE_LITTLE_ENDIAN
1415 static PnvPhb4DMASpace *pnv_phb4_dma_find(PnvPHB4 *phb, PCIBus *bus, int devfn)
1417 PnvPhb4DMASpace *ds;
1419 QLIST_FOREACH(ds, &phb->dma_spaces, list) {
1420 if (ds->bus == bus && ds->devfn == devfn) {
1421 break;
1424 return ds;
1427 static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn)
1429 PnvPHB4 *phb = opaque;
1430 PnvPhb4DMASpace *ds;
1431 char name[32];
1433 ds = pnv_phb4_dma_find(phb, bus, devfn);
1435 if (ds == NULL) {
1436 ds = g_malloc0(sizeof(PnvPhb4DMASpace));
1437 ds->bus = bus;
1438 ds->devfn = devfn;
1439 ds->pe_num = PHB_INVALID_PE;
1440 ds->phb = phb;
1441 snprintf(name, sizeof(name), "phb4-%d.%d-iommu", phb->chip_id,
1442 phb->phb_id);
1443 memory_region_init_iommu(&ds->dma_mr, sizeof(ds->dma_mr),
1444 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION,
1445 OBJECT(phb), name, UINT64_MAX);
1446 address_space_init(&ds->dma_as, MEMORY_REGION(&ds->dma_mr),
1447 name);
1448 memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb4_msi_ops,
1449 ds, "msi32", 0x10000);
1450 memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb4_msi_ops,
1451 ds, "msi64", 0x100000);
1452 pnv_phb4_update_msi_regions(ds);
1454 QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list);
1456 return &ds->dma_as;
1459 static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
1461 PnvPhb4PecStack *stack = phb->stack;
1462 PnvPhb4PecState *pec = stack->pec;
1463 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1464 uint32_t pec_nest_base;
1465 uint32_t pec_pci_base;
1466 char name[64];
1468 assert(pec);
1470 /* Initialize the XSCOM regions for the stack registers */
1471 snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d",
1472 pec->chip_id, pec->index, stack->stack_no);
1473 pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack),
1474 &pnv_pec_stk_nest_xscom_ops, stack, name,
1475 PHB4_PEC_NEST_STK_REGS_COUNT);
1477 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
1478 pec->chip_id, pec->index, stack->stack_no);
1479 pnv_xscom_region_init(&phb->pci_regs_mr, OBJECT(phb),
1480 &pnv_pec_stk_pci_xscom_ops, phb, name,
1481 PHB4_PEC_PCI_STK_REGS_COUNT);
1483 /* PHB pass-through */
1484 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb",
1485 pec->chip_id, pec->index, stack->stack_no);
1486 pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(phb),
1487 &pnv_phb4_xscom_ops, phb, name, 0x40);
1489 pec_nest_base = pecc->xscom_nest_base(pec);
1490 pec_pci_base = pecc->xscom_pci_base(pec);
1492 /* Populate the XSCOM address space. */
1493 pnv_xscom_add_subregion(pec->chip,
1494 pec_nest_base + 0x40 * (stack->stack_no + 1),
1495 &stack->nest_regs_mr);
1496 pnv_xscom_add_subregion(pec->chip,
1497 pec_pci_base + 0x40 * (stack->stack_no + 1),
1498 &phb->pci_regs_mr);
1499 pnv_xscom_add_subregion(pec->chip,
1500 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
1501 0x40 * stack->stack_no,
1502 &stack->phb_regs_mr);
1505 static void pnv_phb4_instance_init(Object *obj)
1507 PnvPHB4 *phb = PNV_PHB4(obj);
1509 QLIST_INIT(&phb->dma_spaces);
1511 /* XIVE interrupt source object */
1512 object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
1515 static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb,
1516 Error **errp)
1518 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1519 int chip_id = phb->chip_id;
1520 int index = phb->phb_id;
1521 int i, j;
1523 for (i = 0; i < chip->num_pecs; i++) {
1525 * For each PEC, check the amount of stacks it supports
1526 * and see if the given phb4 index matches a stack.
1528 PnvPhb4PecState *pec = &chip9->pecs[i];
1530 for (j = 0; j < pec->num_stacks; j++) {
1531 if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
1532 return &pec->stacks[j];
1537 error_setg(errp,
1538 "pnv-phb4 chip-id %d index %d didn't match any existing PEC",
1539 chip_id, index);
1541 return NULL;
1544 static void pnv_phb4_realize(DeviceState *dev, Error **errp)
1546 PnvPHB4 *phb = PNV_PHB4(dev);
1547 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
1548 XiveSource *xsrc = &phb->xsrc;
1549 Error *local_err = NULL;
1550 int nr_irqs;
1551 char name[32];
1553 /* User created PHB */
1554 if (!phb->stack) {
1555 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1556 PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
1557 PnvPhb4PecClass *pecc;
1558 BusState *s;
1560 if (!chip) {
1561 error_setg(errp, "invalid chip id: %d", phb->chip_id);
1562 return;
1565 phb->stack = pnv_phb4_get_stack(chip, phb, &local_err);
1566 if (local_err) {
1567 error_propagate(errp, local_err);
1568 return;
1571 /* All other phb properties but 'version' are already set */
1572 pecc = PNV_PHB4_PEC_GET_CLASS(phb->stack->pec);
1573 object_property_set_int(OBJECT(phb), "version", pecc->version,
1574 &error_fatal);
1577 * Assign stack->phb since pnv_phb4_update_regions() uses it
1578 * to access the phb.
1580 phb->stack->phb = phb;
1583 * Reparent user created devices to the chip to build
1584 * correctly the device tree.
1586 pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id);
1588 s = qdev_get_parent_bus(DEVICE(chip));
1589 if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) {
1590 error_propagate(errp, local_err);
1591 return;
1595 /* Set the "big_phb" flag */
1596 phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
1598 /* Controller Registers */
1599 snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
1600 phb->phb_id);
1601 memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
1602 name, 0x2000);
1605 * PHB4 doesn't support IO space. However, qemu gets very upset if
1606 * we don't have an IO region to anchor IO BARs onto so we just
1607 * initialize one which we never hook up to anything
1610 snprintf(name, sizeof(name), "phb4-%d.%d-pci-io", phb->chip_id,
1611 phb->phb_id);
1612 memory_region_init(&phb->pci_io, OBJECT(phb), name, 0x10000);
1614 snprintf(name, sizeof(name), "phb4-%d.%d-pci-mmio", phb->chip_id,
1615 phb->phb_id);
1616 memory_region_init(&phb->pci_mmio, OBJECT(phb), name,
1617 PCI_MMIO_TOTAL_SIZE);
1619 pci->bus = pci_register_root_bus(dev, dev->id,
1620 pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
1621 &phb->pci_mmio, &phb->pci_io,
1622 0, 4, TYPE_PNV_PHB4_ROOT_BUS);
1623 pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
1624 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1626 /* Add a single Root port if running with defaults */
1627 if (defaults_enabled()) {
1628 pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb),
1629 TYPE_PNV_PHB4_ROOT_PORT);
1632 /* Setup XIVE Source */
1633 if (phb->big_phb) {
1634 nr_irqs = PNV_PHB4_MAX_INTs;
1635 } else {
1636 nr_irqs = PNV_PHB4_MAX_INTs >> 1;
1638 object_property_set_int(OBJECT(xsrc), "nr-irqs", nr_irqs, &error_fatal);
1639 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(phb), &error_fatal);
1640 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) {
1641 return;
1644 pnv_phb4_update_xsrc(phb);
1646 phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
1648 pnv_phb4_xscom_realize(phb);
1651 static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
1652 PCIBus *rootbus)
1654 PnvPHB4 *phb = PNV_PHB4(host_bridge);
1656 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
1657 phb->chip_id, phb->phb_id);
1658 return phb->bus_path;
1661 static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno)
1663 PnvPHB4 *phb = PNV_PHB4(xf);
1664 uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
1665 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
1666 uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
1667 MemTxResult result;
1669 trace_pnv_phb4_xive_notify(notif_port, data);
1671 address_space_stq_be(&address_space_memory, notif_port, data,
1672 MEMTXATTRS_UNSPECIFIED, &result);
1673 if (result != MEMTX_OK) {
1674 phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", notif_port);
1675 return;
1679 static Property pnv_phb4_properties[] = {
1680 DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
1681 DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
1682 DEFINE_PROP_UINT64("version", PnvPHB4, version, 0),
1683 DEFINE_PROP_LINK("stack", PnvPHB4, stack, TYPE_PNV_PHB4_PEC_STACK,
1684 PnvPhb4PecStack *),
1685 DEFINE_PROP_END_OF_LIST(),
1688 static void pnv_phb4_class_init(ObjectClass *klass, void *data)
1690 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1691 DeviceClass *dc = DEVICE_CLASS(klass);
1692 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
1694 hc->root_bus_path = pnv_phb4_root_bus_path;
1695 dc->realize = pnv_phb4_realize;
1696 device_class_set_props(dc, pnv_phb4_properties);
1697 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1698 dc->user_creatable = true;
1700 xfc->notify = pnv_phb4_xive_notify;
1703 static const TypeInfo pnv_phb4_type_info = {
1704 .name = TYPE_PNV_PHB4,
1705 .parent = TYPE_PCIE_HOST_BRIDGE,
1706 .instance_init = pnv_phb4_instance_init,
1707 .instance_size = sizeof(PnvPHB4),
1708 .class_init = pnv_phb4_class_init,
1709 .interfaces = (InterfaceInfo[]) {
1710 { TYPE_XIVE_NOTIFIER },
1711 { },
1715 static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data)
1717 BusClass *k = BUS_CLASS(klass);
1720 * PHB4 has only a single root complex. Enforce the limit on the
1721 * parent bus
1723 k->max_dev = 1;
1726 static const TypeInfo pnv_phb4_root_bus_info = {
1727 .name = TYPE_PNV_PHB4_ROOT_BUS,
1728 .parent = TYPE_PCIE_BUS,
1729 .class_init = pnv_phb4_root_bus_class_init,
1730 .interfaces = (InterfaceInfo[]) {
1731 { INTERFACE_PCIE_DEVICE },
1736 static void pnv_phb4_root_port_reset(DeviceState *dev)
1738 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
1739 PCIDevice *d = PCI_DEVICE(dev);
1740 uint8_t *conf = d->config;
1742 rpc->parent_reset(dev);
1744 pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
1745 PCI_IO_RANGE_MASK & 0xff);
1746 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
1747 PCI_IO_RANGE_MASK & 0xff);
1748 pci_set_word(conf + PCI_MEMORY_BASE, 0);
1749 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
1750 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
1751 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
1752 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
1753 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
1756 static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
1758 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
1759 PCIDevice *pci = PCI_DEVICE(dev);
1760 PCIBus *bus = pci_get_bus(pci);
1761 PnvPHB4 *phb = NULL;
1762 Error *local_err = NULL;
1764 phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent),
1765 TYPE_PNV_PHB4);
1767 if (!phb) {
1768 error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id);
1769 return;
1772 /* Set unique chassis/slot values for the root port */
1773 qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id);
1774 qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id);
1776 rpc->parent_realize(dev, &local_err);
1777 if (local_err) {
1778 error_propagate(errp, local_err);
1779 return;
1783 static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
1785 DeviceClass *dc = DEVICE_CLASS(klass);
1786 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1787 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
1789 dc->desc = "IBM PHB4 PCIE Root Port";
1790 dc->user_creatable = true;
1792 device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
1793 &rpc->parent_realize);
1794 device_class_set_parent_reset(dc, pnv_phb4_root_port_reset,
1795 &rpc->parent_reset);
1797 k->vendor_id = PCI_VENDOR_ID_IBM;
1798 k->device_id = PNV_PHB4_DEVICE_ID;
1799 k->revision = 0;
1801 rpc->exp_offset = 0x48;
1802 rpc->aer_offset = 0x100;
1804 dc->reset = &pnv_phb4_root_port_reset;
1807 static const TypeInfo pnv_phb4_root_port_info = {
1808 .name = TYPE_PNV_PHB4_ROOT_PORT,
1809 .parent = TYPE_PCIE_ROOT_PORT,
1810 .instance_size = sizeof(PnvPHB4RootPort),
1811 .class_init = pnv_phb4_root_port_class_init,
1814 static void pnv_phb4_register_types(void)
1816 type_register_static(&pnv_phb4_root_bus_info);
1817 type_register_static(&pnv_phb4_root_port_info);
1818 type_register_static(&pnv_phb4_type_info);
1819 type_register_static(&pnv_phb4_iommu_memory_region_info);
1822 type_init(pnv_phb4_register_types);
1824 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon)
1826 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
1828 monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x\n",
1829 phb->chip_id, phb->phb_id,
1830 offset, offset + phb->xsrc.nr_irqs - 1);
1831 xive_source_pic_print_info(&phb->xsrc, 0, mon);