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x86: ich9: let firmware negotiate 'CPU hot-unplug with SMI' feature
[qemu.git] / hw / i386 / pc.c
blob9e29f3792b2a660f7046750b3f8569302cac8690
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/nvram/fw_cfg.h"
41 #include "hw/timer/hpet.h"
42 #include "hw/firmware/smbios.h"
43 #include "hw/loader.h"
44 #include "elf.h"
45 #include "migration/vmstate.h"
46 #include "multiboot.h"
47 #include "hw/rtc/mc146818rtc.h"
48 #include "hw/intc/i8259.h"
49 #include "hw/dma/i8257.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/qtest.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "exec/address-spaces.h"
70 #include "sysemu/arch_init.h"
71 #include "qemu/bitmap.h"
72 #include "qemu/config-file.h"
73 #include "qemu/error-report.h"
74 #include "qemu/option.h"
75 #include "qemu/cutils.h"
76 #include "hw/acpi/acpi.h"
77 #include "hw/acpi/cpu_hotplug.h"
78 #include "hw/boards.h"
79 #include "acpi-build.h"
80 #include "hw/mem/pc-dimm.h"
81 #include "hw/mem/nvdimm.h"
82 #include "qapi/error.h"
83 #include "qapi/qapi-visit-common.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-pmem-pci.h"
91 #include "hw/virtio/virtio-mem-pci.h"
92 #include "hw/mem/memory-device.h"
93 #include "sysemu/replay.h"
94 #include "qapi/qmp/qerror.h"
95 #include "e820_memory_layout.h"
96 #include "fw_cfg.h"
97 #include "trace.h"
98 #include CONFIG_DEVICES
99
100 GlobalProperty pc_compat_5_2[] = {
101 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
102 };
103 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
104
105 GlobalProperty pc_compat_5_1[] = {
106 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
107 };
108 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
109
110 GlobalProperty pc_compat_5_0[] = {
111 };
112 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
113
114 GlobalProperty pc_compat_4_2[] = {
115 { "mch", "smbase-smram", "off" },
116 };
117 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
118
119 GlobalProperty pc_compat_4_1[] = {};
120 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
121
122 GlobalProperty pc_compat_4_0[] = {};
123 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
124
125 GlobalProperty pc_compat_3_1[] = {
126 { "intel-iommu", "dma-drain", "off" },
127 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
128 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
129 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
130 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
131 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
132 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
133 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
134 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
135 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
136 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
137 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
138 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
139 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
140 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
141 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
142 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
143 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
144 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
145 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
146 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
147 };
148 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
149
150 GlobalProperty pc_compat_3_0[] = {
151 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
152 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
153 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
154 };
155 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
156
157 GlobalProperty pc_compat_2_12[] = {
158 { TYPE_X86_CPU, "legacy-cache", "on" },
159 { TYPE_X86_CPU, "topoext", "off" },
160 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
161 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
162 };
163 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
164
165 GlobalProperty pc_compat_2_11[] = {
166 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
167 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
168 };
169 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
170
171 GlobalProperty pc_compat_2_10[] = {
172 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
173 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
174 { "q35-pcihost", "x-pci-hole64-fix", "off" },
175 };
176 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
177
178 GlobalProperty pc_compat_2_9[] = {
179 { "mch", "extended-tseg-mbytes", "0" },
180 };
181 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
182
183 GlobalProperty pc_compat_2_8[] = {
184 { TYPE_X86_CPU, "tcg-cpuid", "off" },
185 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
186 { "ICH9-LPC", "x-smi-broadcast", "off" },
187 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
188 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
189 };
190 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
191
192 GlobalProperty pc_compat_2_7[] = {
193 { TYPE_X86_CPU, "l3-cache", "off" },
194 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
195 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
196 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
197 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
198 { "isa-pcspk", "migrate", "off" },
199 };
200 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
201
202 GlobalProperty pc_compat_2_6[] = {
203 { TYPE_X86_CPU, "cpuid-0xb", "off" },
204 { "vmxnet3", "romfile", "" },
205 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
206 { "apic-common", "legacy-instance-id", "on", }
207 };
208 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
209
210 GlobalProperty pc_compat_2_5[] = {};
211 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
212
213 GlobalProperty pc_compat_2_4[] = {
214 PC_CPU_MODEL_IDS("2.4.0")
215 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
216 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
217 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
218 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
219 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
220 { TYPE_X86_CPU, "check", "off" },
221 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
222 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
223 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
224 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
225 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
226 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
227 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
228 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
229 };
230 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
231
232 GlobalProperty pc_compat_2_3[] = {
233 PC_CPU_MODEL_IDS("2.3.0")
234 { TYPE_X86_CPU, "arat", "off" },
235 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
236 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
237 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
238 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
239 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
240 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
241 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
242 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
243 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
244 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
245 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
246 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
247 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
248 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
249 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
250 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
251 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
252 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
253 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
254 };
255 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
256
257 GlobalProperty pc_compat_2_2[] = {
258 PC_CPU_MODEL_IDS("2.2.0")
259 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
260 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
262 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
263 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
264 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
265 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
266 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
267 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
268 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
269 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
270 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
271 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
272 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
273 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
274 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
275 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
276 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
277 };
278 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
279
280 GlobalProperty pc_compat_2_1[] = {
281 PC_CPU_MODEL_IDS("2.1.0")
282 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
283 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
284 };
285 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
286
287 GlobalProperty pc_compat_2_0[] = {
288 PC_CPU_MODEL_IDS("2.0.0")
289 { "virtio-scsi-pci", "any_layout", "off" },
290 { "PIIX4_PM", "memory-hotplug-support", "off" },
291 { "apic", "version", "0x11" },
292 { "nec-usb-xhci", "superspeed-ports-first", "off" },
293 { "nec-usb-xhci", "force-pcie-endcap", "on" },
294 { "pci-serial", "prog_if", "0" },
295 { "pci-serial-2x", "prog_if", "0" },
296 { "pci-serial-4x", "prog_if", "0" },
297 { "virtio-net-pci", "guest_announce", "off" },
298 { "ICH9-LPC", "memory-hotplug-support", "off" },
299 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
300 { "ioh3420", COMPAT_PROP_PCP, "off" },
301 };
302 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
303
304 GlobalProperty pc_compat_1_7[] = {
305 PC_CPU_MODEL_IDS("1.7.0")
306 { TYPE_USB_DEVICE, "msos-desc", "no" },
307 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
308 { "hpet", HPET_INTCAP, "4" },
309 };
310 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
311
312 GlobalProperty pc_compat_1_6[] = {
313 PC_CPU_MODEL_IDS("1.6.0")
314 { "e1000", "mitigation", "off" },
315 { "qemu64-" TYPE_X86_CPU, "model", "2" },
316 { "qemu32-" TYPE_X86_CPU, "model", "3" },
317 { "i440FX-pcihost", "short_root_bus", "1" },
318 { "q35-pcihost", "short_root_bus", "1" },
319 };
320 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
321
322 GlobalProperty pc_compat_1_5[] = {
323 PC_CPU_MODEL_IDS("1.5.0")
324 { "Conroe-" TYPE_X86_CPU, "model", "2" },
325 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
326 { "Penryn-" TYPE_X86_CPU, "model", "2" },
327 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
328 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
329 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
330 { "virtio-net-pci", "any_layout", "off" },
331 { TYPE_X86_CPU, "pmu", "on" },
332 { "i440FX-pcihost", "short_root_bus", "0" },
333 { "q35-pcihost", "short_root_bus", "0" },
334 };
335 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
336
337 GlobalProperty pc_compat_1_4[] = {
338 PC_CPU_MODEL_IDS("1.4.0")
339 { "scsi-hd", "discard_granularity", "0" },
340 { "scsi-cd", "discard_granularity", "0" },
341 { "scsi-disk", "discard_granularity", "0" },
342 { "ide-hd", "discard_granularity", "0" },
343 { "ide-cd", "discard_granularity", "0" },
344 { "ide-drive", "discard_granularity", "0" },
345 { "virtio-blk-pci", "discard_granularity", "0" },
346 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
347 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
348 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
349 { "e1000", "romfile", "pxe-e1000.rom" },
350 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
351 { "pcnet", "romfile", "pxe-pcnet.rom" },
352 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
353 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
354 { "486-" TYPE_X86_CPU, "model", "0" },
355 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
356 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
357 };
358 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
359
360 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
361 {
362 GSIState *s;
363
364 s = g_new0(GSIState, 1);
365 if (kvm_ioapic_in_kernel()) {
366 kvm_pc_setup_irq_routing(pci_enabled);
367 }
368 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
369
370 return s;
371 }
372
373 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
374 unsigned size)
375 {
376 }
377
378 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
379 {
380 return 0xffffffffffffffffULL;
381 }
382
383 /* MSDOS compatibility mode FPU exception support */
384 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
385 unsigned size)
386 {
387 if (tcg_enabled()) {
388 cpu_set_ignne();
389 }
390 }
391
392 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
393 {
394 return 0xffffffffffffffffULL;
395 }
396
397 /* PC cmos mappings */
398
399 #define REG_EQUIPMENT_BYTE 0x14
400
401 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
402 int16_t cylinders, int8_t heads, int8_t sectors)
403 {
404 rtc_set_memory(s, type_ofs, 47);
405 rtc_set_memory(s, info_ofs, cylinders);
406 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
407 rtc_set_memory(s, info_ofs + 2, heads);
408 rtc_set_memory(s, info_ofs + 3, 0xff);
409 rtc_set_memory(s, info_ofs + 4, 0xff);
410 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
411 rtc_set_memory(s, info_ofs + 6, cylinders);
412 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
413 rtc_set_memory(s, info_ofs + 8, sectors);
414 }
415
416 /* convert boot_device letter to something recognizable by the bios */
417 static int boot_device2nibble(char boot_device)
418 {
419 switch(boot_device) {
420 case 'a':
421 case 'b':
422 return 0x01; /* floppy boot */
423 case 'c':
424 return 0x02; /* hard drive boot */
425 case 'd':
426 return 0x03; /* CD-ROM boot */
427 case 'n':
428 return 0x04; /* Network boot */
429 }
430 return 0;
431 }
432
433 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
434 {
435 #define PC_MAX_BOOT_DEVICES 3
436 int nbds, bds[3] = { 0, };
437 int i;
438
439 nbds = strlen(boot_device);
440 if (nbds > PC_MAX_BOOT_DEVICES) {
441 error_setg(errp, "Too many boot devices for PC");
442 return;
443 }
444 for (i = 0; i < nbds; i++) {
445 bds[i] = boot_device2nibble(boot_device[i]);
446 if (bds[i] == 0) {
447 error_setg(errp, "Invalid boot device for PC: '%c'",
448 boot_device[i]);
449 return;
450 }
451 }
452 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
453 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
454 }
455
456 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
457 {
458 set_boot_dev(opaque, boot_device, errp);
459 }
460
461 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
462 {
463 int val, nb, i;
464 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
465 FLOPPY_DRIVE_TYPE_NONE };
466
467 /* floppy type */
468 if (floppy) {
469 for (i = 0; i < 2; i++) {
470 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
471 }
472 }
473 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
474 cmos_get_fd_drive_type(fd_type[1]);
475 rtc_set_memory(rtc_state, 0x10, val);
476
477 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
478 nb = 0;
479 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
480 nb++;
481 }
482 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
483 nb++;
484 }
485 switch (nb) {
486 case 0:
487 break;
488 case 1:
489 val |= 0x01; /* 1 drive, ready for boot */
490 break;
491 case 2:
492 val |= 0x41; /* 2 drives, ready for boot */
493 break;
494 }
495 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
496 }
497
498 typedef struct pc_cmos_init_late_arg {
499 ISADevice *rtc_state;
500 BusState *idebus[2];
501 } pc_cmos_init_late_arg;
502
503 typedef struct check_fdc_state {
504 ISADevice *floppy;
505 bool multiple;
506 } CheckFdcState;
507
508 static int check_fdc(Object *obj, void *opaque)
509 {
510 CheckFdcState *state = opaque;
511 Object *fdc;
512 uint32_t iobase;
513 Error *local_err = NULL;
514
515 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
516 if (!fdc) {
517 return 0;
518 }
519
520 iobase = object_property_get_uint(obj, "iobase", &local_err);
521 if (local_err || iobase != 0x3f0) {
522 error_free(local_err);
523 return 0;
524 }
525
526 if (state->floppy) {
527 state->multiple = true;
528 } else {
529 state->floppy = ISA_DEVICE(obj);
530 }
531 return 0;
532 }
533
534 static const char * const fdc_container_path[] = {
535 "/unattached", "/peripheral", "/peripheral-anon"
536 };
537
538 /*
539 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
540 * and ACPI objects.
541 */
542 ISADevice *pc_find_fdc0(void)
543 {
544 int i;
545 Object *container;
546 CheckFdcState state = { 0 };
547
548 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
549 container = container_get(qdev_get_machine(), fdc_container_path[i]);
550 object_child_foreach(container, check_fdc, &state);
551 }
552
553 if (state.multiple) {
554 warn_report("multiple floppy disk controllers with "
555 "iobase=0x3f0 have been found");
556 error_printf("the one being picked for CMOS setup might not reflect "
557 "your intent");
558 }
559
560 return state.floppy;
561 }
562
563 static void pc_cmos_init_late(void *opaque)
564 {
565 pc_cmos_init_late_arg *arg = opaque;
566 ISADevice *s = arg->rtc_state;
567 int16_t cylinders;
568 int8_t heads, sectors;
569 int val;
570 int i, trans;
571
572 val = 0;
573 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
574 &cylinders, &heads, &sectors) >= 0) {
575 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
576 val |= 0xf0;
577 }
578 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
579 &cylinders, &heads, &sectors) >= 0) {
580 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
581 val |= 0x0f;
582 }
583 rtc_set_memory(s, 0x12, val);
584
585 val = 0;
586 for (i = 0; i < 4; i++) {
587 /* NOTE: ide_get_geometry() returns the physical
588 geometry. It is always such that: 1 <= sects <= 63, 1
589 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
590 geometry can be different if a translation is done. */
591 if (arg->idebus[i / 2] &&
592 ide_get_geometry(arg->idebus[i / 2], i % 2,
593 &cylinders, &heads, &sectors) >= 0) {
594 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
595 assert((trans & ~3) == 0);
596 val |= trans << (i * 2);
597 }
598 }
599 rtc_set_memory(s, 0x39, val);
600
601 pc_cmos_init_floppy(s, pc_find_fdc0());
602
603 qemu_unregister_reset(pc_cmos_init_late, opaque);
604 }
605
606 void pc_cmos_init(PCMachineState *pcms,
607 BusState *idebus0, BusState *idebus1,
608 ISADevice *s)
609 {
610 int val;
611 static pc_cmos_init_late_arg arg;
612 X86MachineState *x86ms = X86_MACHINE(pcms);
613
614 /* various important CMOS locations needed by PC/Bochs bios */
615
616 /* memory size */
617 /* base memory (first MiB) */
618 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
619 rtc_set_memory(s, 0x15, val);
620 rtc_set_memory(s, 0x16, val >> 8);
621 /* extended memory (next 64MiB) */
622 if (x86ms->below_4g_mem_size > 1 * MiB) {
623 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
624 } else {
625 val = 0;
626 }
627 if (val > 65535)
628 val = 65535;
629 rtc_set_memory(s, 0x17, val);
630 rtc_set_memory(s, 0x18, val >> 8);
631 rtc_set_memory(s, 0x30, val);
632 rtc_set_memory(s, 0x31, val >> 8);
633 /* memory between 16MiB and 4GiB */
634 if (x86ms->below_4g_mem_size > 16 * MiB) {
635 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
636 } else {
637 val = 0;
638 }
639 if (val > 65535)
640 val = 65535;
641 rtc_set_memory(s, 0x34, val);
642 rtc_set_memory(s, 0x35, val >> 8);
643 /* memory above 4GiB */
644 val = x86ms->above_4g_mem_size / 65536;
645 rtc_set_memory(s, 0x5b, val);
646 rtc_set_memory(s, 0x5c, val >> 8);
647 rtc_set_memory(s, 0x5d, val >> 16);
648
649 object_property_add_link(OBJECT(pcms), "rtc_state",
650 TYPE_ISA_DEVICE,
651 (Object **)&x86ms->rtc,
652 object_property_allow_set_link,
653 OBJ_PROP_LINK_STRONG);
654 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
655 &error_abort);
656
657 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
658
659 val = 0;
660 val |= 0x02; /* FPU is there */
661 val |= 0x04; /* PS/2 mouse installed */
662 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
663
664 /* hard drives and FDC */
665 arg.rtc_state = s;
666 arg.idebus[0] = idebus0;
667 arg.idebus[1] = idebus1;
668 qemu_register_reset(pc_cmos_init_late, &arg);
669 }
670
671 static void handle_a20_line_change(void *opaque, int irq, int level)
672 {
673 X86CPU *cpu = opaque;
674
675 /* XXX: send to all CPUs ? */
676 /* XXX: add logic to handle multiple A20 line sources */
677 x86_cpu_set_a20(cpu, level);
678 }
679
680 #define NE2000_NB_MAX 6
681
682 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
683 0x280, 0x380 };
684 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
685
686 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
687 {
688 static int nb_ne2k = 0;
689
690 if (nb_ne2k == NE2000_NB_MAX)
691 return;
692 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
693 ne2000_irq[nb_ne2k], nd);
694 nb_ne2k++;
695 }
696
697 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
698 {
699 X86CPU *cpu = opaque;
700
701 if (level) {
702 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
703 }
704 }
705
706 /*
707 * This function is very similar to smp_parse()
708 * in hw/core/machine.c but includes CPU die support.
709 */
710 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
711 {
712 X86MachineState *x86ms = X86_MACHINE(ms);
713
714 if (opts) {
715 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
716 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
717 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
718 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
719 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
720
721 /* compute missing values, prefer sockets over cores over threads */
722 if (cpus == 0 || sockets == 0) {
723 cores = cores > 0 ? cores : 1;
724 threads = threads > 0 ? threads : 1;
725 if (cpus == 0) {
726 sockets = sockets > 0 ? sockets : 1;
727 cpus = cores * threads * dies * sockets;
728 } else {
729 ms->smp.max_cpus =
730 qemu_opt_get_number(opts, "maxcpus", cpus);
731 sockets = ms->smp.max_cpus / (cores * threads * dies);
732 }
733 } else if (cores == 0) {
734 threads = threads > 0 ? threads : 1;
735 cores = cpus / (sockets * dies * threads);
736 cores = cores > 0 ? cores : 1;
737 } else if (threads == 0) {
738 threads = cpus / (cores * dies * sockets);
739 threads = threads > 0 ? threads : 1;
740 } else if (sockets * dies * cores * threads < cpus) {
741 error_report("cpu topology: "
742 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
743 "smp_cpus (%u)",
744 sockets, dies, cores, threads, cpus);
745 exit(1);
746 }
747
748 ms->smp.max_cpus =
749 qemu_opt_get_number(opts, "maxcpus", cpus);
750
751 if (ms->smp.max_cpus < cpus) {
752 error_report("maxcpus must be equal to or greater than smp");
753 exit(1);
754 }
755
756 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
757 error_report("Invalid CPU topology deprecated: "
758 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
759 "!= maxcpus (%u)",
760 sockets, dies, cores, threads,
761 ms->smp.max_cpus);
762 exit(1);
763 }
764
765 ms->smp.cpus = cpus;
766 ms->smp.cores = cores;
767 ms->smp.threads = threads;
768 ms->smp.sockets = sockets;
769 x86ms->smp_dies = dies;
770 }
771
772 if (ms->smp.cpus > 1) {
773 Error *blocker = NULL;
774 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
775 replay_add_blocker(blocker);
776 }
777 }
778
779 static
780 void pc_machine_done(Notifier *notifier, void *data)
781 {
782 PCMachineState *pcms = container_of(notifier,
783 PCMachineState, machine_done);
784 X86MachineState *x86ms = X86_MACHINE(pcms);
785
786 /* set the number of CPUs */
787 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
788
789 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
790
791 acpi_setup();
792 if (x86ms->fw_cfg) {
793 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
794 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
795 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
796 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
797 }
798
799 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
800 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
801
802 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
803 iommu->intr_eim != ON_OFF_AUTO_ON) {
804 error_report("current -smp configuration requires "
805 "Extended Interrupt Mode enabled. "
806 "You can add an IOMMU using: "
807 "-device intel-iommu,intremap=on,eim=on");
808 exit(EXIT_FAILURE);
809 }
810 }
811 }
812
813 void pc_guest_info_init(PCMachineState *pcms)
814 {
815 int i;
816 MachineState *ms = MACHINE(pcms);
817 X86MachineState *x86ms = X86_MACHINE(pcms);
818
819 x86ms->apic_xrupt_override = true;
820 pcms->numa_nodes = ms->numa_state->num_nodes;
821 pcms->node_mem = g_malloc0(pcms->numa_nodes *
822 sizeof *pcms->node_mem);
823 for (i = 0; i < ms->numa_state->num_nodes; i++) {
824 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
825 }
826
827 pcms->machine_done.notify = pc_machine_done;
828 qemu_add_machine_init_done_notifier(&pcms->machine_done);
829 }
830
831 /* setup pci memory address space mapping into system address space */
832 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
833 MemoryRegion *pci_address_space)
834 {
835 /* Set to lower priority than RAM */
836 memory_region_add_subregion_overlap(system_memory, 0x0,
837 pci_address_space, -1);
838 }
839
840 void xen_load_linux(PCMachineState *pcms)
841 {
842 int i;
843 FWCfgState *fw_cfg;
844 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
845 X86MachineState *x86ms = X86_MACHINE(pcms);
846
847 assert(MACHINE(pcms)->kernel_filename != NULL);
848
849 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
850 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
851 rom_set_fw(fw_cfg);
852
853 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
854 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
855 for (i = 0; i < nb_option_roms; i++) {
856 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
857 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
858 !strcmp(option_rom[i].name, "pvh.bin") ||
859 !strcmp(option_rom[i].name, "multiboot.bin"));
860 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
861 }
862 x86ms->fw_cfg = fw_cfg;
863 }
864
865 void pc_memory_init(PCMachineState *pcms,
866 MemoryRegion *system_memory,
867 MemoryRegion *rom_memory,
868 MemoryRegion **ram_memory)
869 {
870 int linux_boot, i;
871 MemoryRegion *option_rom_mr;
872 MemoryRegion *ram_below_4g, *ram_above_4g;
873 FWCfgState *fw_cfg;
874 MachineState *machine = MACHINE(pcms);
875 MachineClass *mc = MACHINE_GET_CLASS(machine);
876 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
877 X86MachineState *x86ms = X86_MACHINE(pcms);
878
879 assert(machine->ram_size == x86ms->below_4g_mem_size +
880 x86ms->above_4g_mem_size);
881
882 linux_boot = (machine->kernel_filename != NULL);
883
884 /*
885 * Split single memory region and use aliases to address portions of it,
886 * done for backwards compatibility with older qemus.
887 */
888 *ram_memory = machine->ram;
889 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
890 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
891 0, x86ms->below_4g_mem_size);
892 memory_region_add_subregion(system_memory, 0, ram_below_4g);
893 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
894 if (x86ms->above_4g_mem_size > 0) {
895 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
896 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
897 machine->ram,
898 x86ms->below_4g_mem_size,
899 x86ms->above_4g_mem_size);
900 memory_region_add_subregion(system_memory, 0x100000000ULL,
901 ram_above_4g);
902 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
903 }
904
905 if (!pcmc->has_reserved_memory &&
906 (machine->ram_slots ||
907 (machine->maxram_size > machine->ram_size))) {
908
909 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
910 mc->name);
911 exit(EXIT_FAILURE);
912 }
913
914 /* always allocate the device memory information */
915 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
916
917 /* initialize device memory address space */
918 if (pcmc->has_reserved_memory &&
919 (machine->ram_size < machine->maxram_size)) {
920 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
921
922 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
923 error_report("unsupported amount of memory slots: %"PRIu64,
924 machine->ram_slots);
925 exit(EXIT_FAILURE);
926 }
927
928 if (QEMU_ALIGN_UP(machine->maxram_size,
929 TARGET_PAGE_SIZE) != machine->maxram_size) {
930 error_report("maximum memory size must by aligned to multiple of "
931 "%d bytes", TARGET_PAGE_SIZE);
932 exit(EXIT_FAILURE);
933 }
934
935 machine->device_memory->base =
936 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
937
938 if (pcmc->enforce_aligned_dimm) {
939 /* size device region assuming 1G page max alignment per slot */
940 device_mem_size += (1 * GiB) * machine->ram_slots;
941 }
942
943 if ((machine->device_memory->base + device_mem_size) <
944 device_mem_size) {
945 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
946 machine->maxram_size);
947 exit(EXIT_FAILURE);
948 }
949
950 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
951 "device-memory", device_mem_size);
952 memory_region_add_subregion(system_memory, machine->device_memory->base,
953 &machine->device_memory->mr);
954 }
955
956 /* Initialize PC system firmware */
957 pc_system_firmware_init(pcms, rom_memory);
958
959 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
960 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
961 &error_fatal);
962 if (pcmc->pci_enabled) {
963 memory_region_set_readonly(option_rom_mr, true);
964 }
965 memory_region_add_subregion_overlap(rom_memory,
966 PC_ROM_MIN_VGA,
967 option_rom_mr,
968 1);
969
970 fw_cfg = fw_cfg_arch_create(machine,
971 x86ms->boot_cpus, x86ms->apic_id_limit);
972
973 rom_set_fw(fw_cfg);
974
975 if (pcmc->has_reserved_memory && machine->device_memory->base) {
976 uint64_t *val = g_malloc(sizeof(*val));
977 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
978 uint64_t res_mem_end = machine->device_memory->base;
979
980 if (!pcmc->broken_reserved_end) {
981 res_mem_end += memory_region_size(&machine->device_memory->mr);
982 }
983 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
984 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
985 }
986
987 if (linux_boot) {
988 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
989 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
990 }
991
992 for (i = 0; i < nb_option_roms; i++) {
993 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
994 }
995 x86ms->fw_cfg = fw_cfg;
996
997 /* Init default IOAPIC address space */
998 x86ms->ioapic_as = &address_space_memory;
999
1000 /* Init ACPI memory hotplug IO base address */
1001 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1002 }
1003
1004 /*
1005 * The 64bit pci hole starts after "above 4G RAM" and
1006 * potentially the space reserved for memory hotplug.
1007 */
1008 uint64_t pc_pci_hole64_start(void)
1009 {
1010 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1011 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1012 MachineState *ms = MACHINE(pcms);
1013 X86MachineState *x86ms = X86_MACHINE(pcms);
1014 uint64_t hole64_start = 0;
1015
1016 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1017 hole64_start = ms->device_memory->base;
1018 if (!pcmc->broken_reserved_end) {
1019 hole64_start += memory_region_size(&ms->device_memory->mr);
1020 }
1021 } else {
1022 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1023 }
1024
1025 return ROUND_UP(hole64_start, 1 * GiB);
1026 }
1027
1028 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1029 {
1030 DeviceState *dev = NULL;
1031
1032 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1033 if (pci_bus) {
1034 PCIDevice *pcidev = pci_vga_init(pci_bus);
1035 dev = pcidev ? &pcidev->qdev : NULL;
1036 } else if (isa_bus) {
1037 ISADevice *isadev = isa_vga_init(isa_bus);
1038 dev = isadev ? DEVICE(isadev) : NULL;
1039 }
1040 rom_reset_order_override();
1041 return dev;
1042 }
1043
1044 static const MemoryRegionOps ioport80_io_ops = {
1045 .write = ioport80_write,
1046 .read = ioport80_read,
1047 .endianness = DEVICE_NATIVE_ENDIAN,
1048 .impl = {
1049 .min_access_size = 1,
1050 .max_access_size = 1,
1051 },
1052 };
1053
1054 static const MemoryRegionOps ioportF0_io_ops = {
1055 .write = ioportF0_write,
1056 .read = ioportF0_read,
1057 .endianness = DEVICE_NATIVE_ENDIAN,
1058 .impl = {
1059 .min_access_size = 1,
1060 .max_access_size = 1,
1061 },
1062 };
1063
1064 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1065 {
1066 int i;
1067 DriveInfo *fd[MAX_FD];
1068 qemu_irq *a20_line;
1069 ISADevice *fdc, *i8042, *port92, *vmmouse;
1070
1071 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1072 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1073
1074 for (i = 0; i < MAX_FD; i++) {
1075 fd[i] = drive_get(IF_FLOPPY, 0, i);
1076 create_fdctrl |= !!fd[i];
1077 }
1078 if (create_fdctrl) {
1079 fdc = isa_new(TYPE_ISA_FDC);
1080 if (fdc) {
1081 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1082 isa_fdc_init_drives(fdc, fd);
1083 }
1084 }
1085
1086 i8042 = isa_create_simple(isa_bus, "i8042");
1087 if (!no_vmport) {
1088 isa_create_simple(isa_bus, TYPE_VMPORT);
1089 vmmouse = isa_try_new("vmmouse");
1090 } else {
1091 vmmouse = NULL;
1092 }
1093 if (vmmouse) {
1094 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1095 &error_abort);
1096 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1097 }
1098 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1099
1100 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1101 i8042_setup_a20_line(i8042, a20_line[0]);
1102 qdev_connect_gpio_out_named(DEVICE(port92),
1103 PORT92_A20_LINE, 0, a20_line[1]);
1104 g_free(a20_line);
1105 }
1106
1107 void pc_basic_device_init(struct PCMachineState *pcms,
1108 ISABus *isa_bus, qemu_irq *gsi,
1109 ISADevice **rtc_state,
1110 bool create_fdctrl,
1111 uint32_t hpet_irqs)
1112 {
1113 int i;
1114 DeviceState *hpet = NULL;
1115 int pit_isa_irq = 0;
1116 qemu_irq pit_alt_irq = NULL;
1117 qemu_irq rtc_irq = NULL;
1118 ISADevice *pit = NULL;
1119 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1120 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1121
1122 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1123 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1124
1125 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1126 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1127
1128 /*
1129 * Check if an HPET shall be created.
1130 *
1131 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1132 * when the HPET wants to take over. Thus we have to disable the latter.
1133 */
1134 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1135 kvm_has_pit_state2())) {
1136 hpet = qdev_try_new(TYPE_HPET);
1137 if (!hpet) {
1138 error_report("couldn't create HPET device");
1139 exit(1);
1140 }
1141 /*
1142 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1143 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1144 * IRQ2.
1145 */
1146 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1147 HPET_INTCAP, NULL);
1148 if (!compat) {
1149 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1150 }
1151 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1152 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1153
1154 for (i = 0; i < GSI_NUM_PINS; i++) {
1155 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1156 }
1157 pit_isa_irq = -1;
1158 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1159 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1160 }
1161 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1162
1163 qemu_register_boot_set(pc_boot_set, *rtc_state);
1164
1165 if (!xen_enabled() && pcms->pit_enabled) {
1166 if (kvm_pit_in_kernel()) {
1167 pit = kvm_pit_init(isa_bus, 0x40);
1168 } else {
1169 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1170 }
1171 if (hpet) {
1172 /* connect PIT to output control line of the HPET */
1173 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1174 }
1175 pcspk_init(pcms->pcspk, isa_bus, pit);
1176 }
1177
1178 i8257_dma_init(isa_bus, 0);
1179
1180 /* Super I/O */
1181 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON);
1182 }
1183
1184 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1185 {
1186 int i;
1187
1188 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1189 for (i = 0; i < nb_nics; i++) {
1190 NICInfo *nd = &nd_table[i];
1191 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1192
1193 if (g_str_equal(model, "ne2k_isa")) {
1194 pc_init_ne2k_isa(isa_bus, nd);
1195 } else {
1196 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1197 }
1198 }
1199 rom_reset_order_override();
1200 }
1201
1202 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1203 {
1204 qemu_irq *i8259;
1205
1206 if (kvm_pic_in_kernel()) {
1207 i8259 = kvm_i8259_init(isa_bus);
1208 } else if (xen_enabled()) {
1209 i8259 = xen_interrupt_controller_init();
1210 } else {
1211 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1212 }
1213
1214 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1215 i8259_irqs[i] = i8259[i];
1216 }
1217
1218 g_free(i8259);
1219 }
1220
1221 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1222 Error **errp)
1223 {
1224 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1225 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1226 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1227 const MachineState *ms = MACHINE(hotplug_dev);
1228 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1229 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1230 Error *local_err = NULL;
1231
1232 /*
1233 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1234 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1235 * addition to cover this case.
1236 */
1237 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1238 error_setg(errp,
1239 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1240 return;
1241 }
1242
1243 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1244 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1245 return;
1246 }
1247
1248 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1249 if (local_err) {
1250 error_propagate(errp, local_err);
1251 return;
1252 }
1253
1254 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1255 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1256 }
1257
1258 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1259 DeviceState *dev, Error **errp)
1260 {
1261 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1262 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1263 MachineState *ms = MACHINE(hotplug_dev);
1264 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1265
1266 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1267
1268 if (is_nvdimm) {
1269 nvdimm_plug(ms->nvdimms_state);
1270 }
1271
1272 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1273 }
1274
1275 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1276 DeviceState *dev, Error **errp)
1277 {
1278 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1279
1280 /*
1281 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1282 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1283 * addition to cover this case.
1284 */
1285 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1286 error_setg(errp,
1287 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1288 return;
1289 }
1290
1291 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1292 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1293 return;
1294 }
1295
1296 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1297 errp);
1298 }
1299
1300 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1301 DeviceState *dev, Error **errp)
1302 {
1303 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1304 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1305 Error *local_err = NULL;
1306
1307 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1308 if (local_err) {
1309 goto out;
1310 }
1311
1312 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1313 qdev_unrealize(dev);
1314 out:
1315 error_propagate(errp, local_err);
1316 }
1317
1318 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1319 DeviceState *dev, Error **errp)
1320 {
1321 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1322 Error *local_err = NULL;
1323
1324 if (!hotplug_dev2 && dev->hotplugged) {
1325 /*
1326 * Without a bus hotplug handler, we cannot control the plug/unplug
1327 * order. We should never reach this point when hotplugging on x86,
1328 * however, better add a safety net.
1329 */
1330 error_setg(errp, "hotplug of virtio based memory devices not supported"
1331 " on this bus.");
1332 return;
1333 }
1334 /*
1335 * First, see if we can plug this memory device at all. If that
1336 * succeeds, branch of to the actual hotplug handler.
1337 */
1338 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1339 &local_err);
1340 if (!local_err && hotplug_dev2) {
1341 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1342 }
1343 error_propagate(errp, local_err);
1344 }
1345
1346 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1347 DeviceState *dev, Error **errp)
1348 {
1349 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1350 Error *local_err = NULL;
1351
1352 /*
1353 * Plug the memory device first and then branch off to the actual
1354 * hotplug handler. If that one fails, we can easily undo the memory
1355 * device bits.
1356 */
1357 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1358 if (hotplug_dev2) {
1359 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1360 if (local_err) {
1361 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1362 }
1363 }
1364 error_propagate(errp, local_err);
1365 }
1366
1367 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1368 DeviceState *dev, Error **errp)
1369 {
1370 /* We don't support hot unplug of virtio based memory devices */
1371 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1372 }
1373
1374 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1375 DeviceState *dev, Error **errp)
1376 {
1377 /* We don't support hot unplug of virtio based memory devices */
1378 }
1379
1380 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1381 DeviceState *dev, Error **errp)
1382 {
1383 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1384 pc_memory_pre_plug(hotplug_dev, dev, errp);
1385 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1386 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1388 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1389 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1390 }
1391 }
1392
1393 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1394 DeviceState *dev, Error **errp)
1395 {
1396 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1397 pc_memory_plug(hotplug_dev, dev, errp);
1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1399 x86_cpu_plug(hotplug_dev, dev, errp);
1400 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1401 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1402 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1403 }
1404 }
1405
1406 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1407 DeviceState *dev, Error **errp)
1408 {
1409 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1410 pc_memory_unplug_request(hotplug_dev, dev, errp);
1411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1412 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1414 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1415 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1416 } else {
1417 error_setg(errp, "acpi: device unplug request for not supported device"
1418 " type: %s", object_get_typename(OBJECT(dev)));
1419 }
1420 }
1421
1422 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1423 DeviceState *dev, Error **errp)
1424 {
1425 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1426 pc_memory_unplug(hotplug_dev, dev, errp);
1427 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1428 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1430 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1431 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1432 } else {
1433 error_setg(errp, "acpi: device unplug for not supported device"
1434 " type: %s", object_get_typename(OBJECT(dev)));
1435 }
1436 }
1437
1438 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1439 DeviceState *dev)
1440 {
1441 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1442 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1443 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1444 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1445 return HOTPLUG_HANDLER(machine);
1446 }
1447
1448 return NULL;
1449 }
1450
1451 static void
1452 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1453 const char *name, void *opaque,
1454 Error **errp)
1455 {
1456 MachineState *ms = MACHINE(obj);
1457 int64_t value = 0;
1458
1459 if (ms->device_memory) {
1460 value = memory_region_size(&ms->device_memory->mr);
1461 }
1462
1463 visit_type_int(v, name, &value, errp);
1464 }
1465
1466 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1467 void *opaque, Error **errp)
1468 {
1469 PCMachineState *pcms = PC_MACHINE(obj);
1470 OnOffAuto vmport = pcms->vmport;
1471
1472 visit_type_OnOffAuto(v, name, &vmport, errp);
1473 }
1474
1475 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1476 void *opaque, Error **errp)
1477 {
1478 PCMachineState *pcms = PC_MACHINE(obj);
1479
1480 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1481 }
1482
1483 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1484 {
1485 PCMachineState *pcms = PC_MACHINE(obj);
1486
1487 return pcms->smbus_enabled;
1488 }
1489
1490 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1491 {
1492 PCMachineState *pcms = PC_MACHINE(obj);
1493
1494 pcms->smbus_enabled = value;
1495 }
1496
1497 static bool pc_machine_get_sata(Object *obj, Error **errp)
1498 {
1499 PCMachineState *pcms = PC_MACHINE(obj);
1500
1501 return pcms->sata_enabled;
1502 }
1503
1504 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1505 {
1506 PCMachineState *pcms = PC_MACHINE(obj);
1507
1508 pcms->sata_enabled = value;
1509 }
1510
1511 static bool pc_machine_get_pit(Object *obj, Error **errp)
1512 {
1513 PCMachineState *pcms = PC_MACHINE(obj);
1514
1515 return pcms->pit_enabled;
1516 }
1517
1518 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1519 {
1520 PCMachineState *pcms = PC_MACHINE(obj);
1521
1522 pcms->pit_enabled = value;
1523 }
1524
1525 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1526 {
1527 PCMachineState *pcms = PC_MACHINE(obj);
1528
1529 return pcms->hpet_enabled;
1530 }
1531
1532 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1533 {
1534 PCMachineState *pcms = PC_MACHINE(obj);
1535
1536 pcms->hpet_enabled = value;
1537 }
1538
1539 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1540 const char *name, void *opaque,
1541 Error **errp)
1542 {
1543 PCMachineState *pcms = PC_MACHINE(obj);
1544 uint64_t value = pcms->max_ram_below_4g;
1545
1546 visit_type_size(v, name, &value, errp);
1547 }
1548
1549 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1550 const char *name, void *opaque,
1551 Error **errp)
1552 {
1553 PCMachineState *pcms = PC_MACHINE(obj);
1554 uint64_t value;
1555
1556 if (!visit_type_size(v, name, &value, errp)) {
1557 return;
1558 }
1559 if (value > 4 * GiB) {
1560 error_setg(errp,
1561 "Machine option 'max-ram-below-4g=%"PRIu64
1562 "' expects size less than or equal to 4G", value);
1563 return;
1564 }
1565
1566 if (value < 1 * MiB) {
1567 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1568 "BIOS may not work with less than 1MiB", value);
1569 }
1570
1571 pcms->max_ram_below_4g = value;
1572 }
1573
1574 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1575 const char *name, void *opaque,
1576 Error **errp)
1577 {
1578 PCMachineState *pcms = PC_MACHINE(obj);
1579 uint64_t value = pcms->max_fw_size;
1580
1581 visit_type_size(v, name, &value, errp);
1582 }
1583
1584 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1585 const char *name, void *opaque,
1586 Error **errp)
1587 {
1588 PCMachineState *pcms = PC_MACHINE(obj);
1589 Error *error = NULL;
1590 uint64_t value;
1591
1592 visit_type_size(v, name, &value, &error);
1593 if (error) {
1594 error_propagate(errp, error);
1595 return;
1596 }
1597
1598 /*
1599 * We don't have a theoretically justifiable exact lower bound on the base
1600 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1601 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1602 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1603 * size.
1604 */
1605 if (value > 16 * MiB) {
1606 error_setg(errp,
1607 "User specified max allowed firmware size %" PRIu64 " is "
1608 "greater than 16MiB. If combined firwmare size exceeds "
1609 "16MiB the system may not boot, or experience intermittent"
1610 "stability issues.",
1611 value);
1612 return;
1613 }
1614
1615 pcms->max_fw_size = value;
1616 }
1617
1618 static void pc_machine_initfn(Object *obj)
1619 {
1620 PCMachineState *pcms = PC_MACHINE(obj);
1621
1622 #ifdef CONFIG_VMPORT
1623 pcms->vmport = ON_OFF_AUTO_AUTO;
1624 #else
1625 pcms->vmport = ON_OFF_AUTO_OFF;
1626 #endif /* CONFIG_VMPORT */
1627 pcms->max_ram_below_4g = 0; /* use default */
1628 /* acpi build is enabled by default if machine supports it */
1629 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1630 pcms->smbus_enabled = true;
1631 pcms->sata_enabled = true;
1632 pcms->pit_enabled = true;
1633 pcms->max_fw_size = 8 * MiB;
1634 #ifdef CONFIG_HPET
1635 pcms->hpet_enabled = true;
1636 #endif
1637
1638 pc_system_flash_create(pcms);
1639 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1640 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1641 OBJECT(pcms->pcspk), "audiodev");
1642 }
1643
1644 static void pc_machine_reset(MachineState *machine)
1645 {
1646 CPUState *cs;
1647 X86CPU *cpu;
1648
1649 qemu_devices_reset();
1650
1651 /* Reset APIC after devices have been reset to cancel
1652 * any changes that qemu_devices_reset() might have done.
1653 */
1654 CPU_FOREACH(cs) {
1655 cpu = X86_CPU(cs);
1656
1657 if (cpu->apic_state) {
1658 device_legacy_reset(cpu->apic_state);
1659 }
1660 }
1661 }
1662
1663 static void pc_machine_wakeup(MachineState *machine)
1664 {
1665 cpu_synchronize_all_states();
1666 pc_machine_reset(machine);
1667 cpu_synchronize_all_post_reset();
1668 }
1669
1670 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1671 {
1672 X86IOMMUState *iommu = x86_iommu_get_default();
1673 IntelIOMMUState *intel_iommu;
1674
1675 if (iommu &&
1676 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1677 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1678 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1679 if (!intel_iommu->caching_mode) {
1680 error_setg(errp, "Device assignment is not allowed without "
1681 "enabling caching-mode=on for Intel IOMMU.");
1682 return false;
1683 }
1684 }
1685
1686 return true;
1687 }
1688
1689 static void pc_machine_class_init(ObjectClass *oc, void *data)
1690 {
1691 MachineClass *mc = MACHINE_CLASS(oc);
1692 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1693 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1694
1695 pcmc->pci_enabled = true;
1696 pcmc->has_acpi_build = true;
1697 pcmc->rsdp_in_ram = true;
1698 pcmc->smbios_defaults = true;
1699 pcmc->smbios_uuid_encoded = true;
1700 pcmc->gigabyte_align = true;
1701 pcmc->has_reserved_memory = true;
1702 pcmc->kvmclock_enabled = true;
1703 pcmc->enforce_aligned_dimm = true;
1704 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1705 * to be used at the moment, 32K should be enough for a while. */
1706 pcmc->acpi_data_size = 0x20000 + 0x8000;
1707 pcmc->linuxboot_dma_enabled = true;
1708 pcmc->pvh_enabled = true;
1709 pcmc->kvmclock_create_always = true;
1710 assert(!mc->get_hotplug_handler);
1711 mc->get_hotplug_handler = pc_get_hotplug_handler;
1712 mc->hotplug_allowed = pc_hotplug_allowed;
1713 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1714 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1715 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1716 mc->auto_enable_numa_with_memhp = true;
1717 mc->auto_enable_numa_with_memdev = true;
1718 mc->has_hotpluggable_cpus = true;
1719 mc->default_boot_order = "cad";
1720 mc->smp_parse = pc_smp_parse;
1721 mc->block_default_type = IF_IDE;
1722 mc->max_cpus = 255;
1723 mc->reset = pc_machine_reset;
1724 mc->wakeup = pc_machine_wakeup;
1725 hc->pre_plug = pc_machine_device_pre_plug_cb;
1726 hc->plug = pc_machine_device_plug_cb;
1727 hc->unplug_request = pc_machine_device_unplug_request_cb;
1728 hc->unplug = pc_machine_device_unplug_cb;
1729 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1730 mc->nvdimm_supported = true;
1731 mc->default_ram_id = "pc.ram";
1732
1733 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1734 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1735 NULL, NULL);
1736 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1737 "Maximum ram below the 4G boundary (32bit boundary)");
1738
1739 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1740 pc_machine_get_device_memory_region_size, NULL,
1741 NULL, NULL);
1742
1743 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1744 pc_machine_get_vmport, pc_machine_set_vmport,
1745 NULL, NULL);
1746 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1747 "Enable vmport (pc & q35)");
1748
1749 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1750 pc_machine_get_smbus, pc_machine_set_smbus);
1751
1752 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1753 pc_machine_get_sata, pc_machine_set_sata);
1754
1755 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1756 pc_machine_get_pit, pc_machine_set_pit);
1757
1758 object_class_property_add_bool(oc, "hpet",
1759 pc_machine_get_hpet, pc_machine_set_hpet);
1760
1761 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1762 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1763 NULL, NULL);
1764 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1765 "Maximum combined firmware size");
1766 }
1767
1768 static const TypeInfo pc_machine_info = {
1769 .name = TYPE_PC_MACHINE,
1770 .parent = TYPE_X86_MACHINE,
1771 .abstract = true,
1772 .instance_size = sizeof(PCMachineState),
1773 .instance_init = pc_machine_initfn,
1774 .class_size = sizeof(PCMachineClass),
1775 .class_init = pc_machine_class_init,
1776 .interfaces = (InterfaceInfo[]) {
1777 { TYPE_HOTPLUG_HANDLER },
1778 { }
1779 },
1780 };
1781
1782 static void pc_machine_register_types(void)
1783 {
1784 type_register_static(&pc_machine_info);
1785 }
1786
1787 type_init(pc_machine_register_types)
QEmu