2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
30 # define TARGET_LONG_BITS 32
33 /* ARM processors have a weak memory model */
34 #define TCG_GUEST_DEFAULT_MO (0)
36 #define CPUArchState struct CPUARMState
38 #include "qemu-common.h"
40 #include "exec/cpu-defs.h"
42 #include "fpu/softfloat.h"
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
53 #define EXCP_HVC 11 /* HyperVisor Call */
54 #define EXCP_HYP_TRAP 12
55 #define EXCP_SMC 13 /* Secure Monitor Call */
58 #define EXCP_SEMIHOST 16 /* semihosting call */
59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
61 #define ARMV7M_EXCP_RESET 1
62 #define ARMV7M_EXCP_NMI 2
63 #define ARMV7M_EXCP_HARD 3
64 #define ARMV7M_EXCP_MEM 4
65 #define ARMV7M_EXCP_BUS 5
66 #define ARMV7M_EXCP_USAGE 6
67 #define ARMV7M_EXCP_SVC 11
68 #define ARMV7M_EXCP_DEBUG 12
69 #define ARMV7M_EXCP_PENDSV 14
70 #define ARMV7M_EXCP_SYSTICK 15
72 /* ARM-specific interrupt pending bits. */
73 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
74 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
75 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
77 /* The usual mapping for an AArch64 system register to its AArch32
78 * counterpart is for the 32 bit world to have access to the lower
79 * half only (with writes leaving the upper half untouched). It's
80 * therefore useful to be able to pass TCG the offset of the least
81 * significant half of a uint64_t struct member.
83 #ifdef HOST_WORDS_BIGENDIAN
84 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
85 #define offsetofhigh32(S, M) offsetof(S, M)
87 #define offsetoflow32(S, M) offsetof(S, M)
88 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
91 /* Meanings of the ARMCPU object's four inbound GPIO lines */
94 #define ARM_CPU_VIRQ 2
95 #define ARM_CPU_VFIQ 3
97 #define NB_MMU_MODES 7
98 /* ARM-specific extra insn start words:
99 * 1: Conditional execution bits
100 * 2: Partial exception syndrome for data aborts
102 #define TARGET_INSN_START_EXTRA_WORDS 2
104 /* The 2nd extra word holding syndrome info for data aborts does not use
105 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
106 * help the sleb128 encoder do a better job.
107 * When restoring the CPU state, we shift it back up.
109 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
110 #define ARM_INSN_START_WORD2_SHIFT 14
112 /* We currently assume float and double are IEEE single and double
113 precision respectively.
114 Doing runtime conversions is tricky because VFP registers may contain
115 integer values (eg. as the result of a FTOSI instruction).
116 s<2n> maps to the least significant half of d<n>
117 s<2n+1> maps to the most significant half of d<n>
120 /* CPU state for each instance of a generic timer (in cp15 c14) */
121 typedef struct ARMGenericTimer
{
122 uint64_t cval
; /* Timer CompareValue register */
123 uint64_t ctl
; /* Timer Control register */
126 #define GTIMER_PHYS 0
127 #define GTIMER_VIRT 1
130 #define NUM_GTIMERS 4
138 typedef struct CPUARMState
{
139 /* Regs for current mode. */
142 /* 32/64 switch only happens when taking and returning from
143 * exceptions so the overlap semantics are taken care of then
144 * instead of having a complicated union.
146 /* Regs for A64 mode. */
149 /* PSTATE isn't an architectural register for ARMv8. However, it is
150 * convenient for us to assemble the underlying state into a 32 bit format
151 * identical to the architectural format used for the SPSR. (This is also
152 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
153 * 'pstate' register are.) Of the PSTATE bits:
154 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
155 * semantics as for AArch32, as described in the comments on each field)
156 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
157 * DAIF (exception masks) are kept in env->daif
158 * all other bits are stored in their correct places in env->pstate
161 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
163 /* Frequently accessed CPSR bits are stored separately for efficiency.
164 This contains all the other bits. Use cpsr_{read,write} to access
166 uint32_t uncached_cpsr
;
169 /* Banked registers. */
170 uint64_t banked_spsr
[8];
171 uint32_t banked_r13
[8];
172 uint32_t banked_r14
[8];
174 /* These hold r8-r12. */
175 uint32_t usr_regs
[5];
176 uint32_t fiq_regs
[5];
178 /* cpsr flag cache for faster execution */
179 uint32_t CF
; /* 0 or 1 */
180 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
181 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
182 uint32_t ZF
; /* Z set if zero. */
183 uint32_t QF
; /* 0 or 1 */
184 uint32_t GE
; /* cpsr[19:16] */
185 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
186 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
187 uint64_t daif
; /* exception masks, in the bits they are in PSTATE */
189 uint64_t elr_el
[4]; /* AArch64 exception link regs */
190 uint64_t sp_el
[4]; /* AArch64 banked stack pointers */
192 /* System control coprocessor (cp15) */
195 union { /* Cache size selection */
197 uint64_t _unused_csselr0
;
199 uint64_t _unused_csselr1
;
202 uint64_t csselr_el
[4];
204 union { /* System control register. */
206 uint64_t _unused_sctlr
;
211 uint64_t sctlr_el
[4];
213 uint64_t cpacr_el1
; /* Architectural feature access control register */
214 uint64_t cptr_el
[4]; /* ARMv8 feature trap registers */
215 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
216 uint64_t sder
; /* Secure debug enable register. */
217 uint32_t nsacr
; /* Non-secure access control register. */
218 union { /* MMU translation table base 0. */
220 uint64_t _unused_ttbr0_0
;
222 uint64_t _unused_ttbr0_1
;
225 uint64_t ttbr0_el
[4];
227 union { /* MMU translation table base 1. */
229 uint64_t _unused_ttbr1_0
;
231 uint64_t _unused_ttbr1_1
;
234 uint64_t ttbr1_el
[4];
236 uint64_t vttbr_el2
; /* Virtualization Translation Table Base. */
237 /* MMU translation table base control. */
239 TCR vtcr_el2
; /* Virtualization Translation Control. */
240 uint32_t c2_data
; /* MPU data cacheable bits. */
241 uint32_t c2_insn
; /* MPU instruction cacheable bits. */
242 union { /* MMU domain access control register
243 * MPU write buffer control.
253 uint32_t pmsav5_data_ap
; /* PMSAv5 MPU data access permissions */
254 uint32_t pmsav5_insn_ap
; /* PMSAv5 MPU insn access permissions */
255 uint64_t hcr_el2
; /* Hypervisor configuration register */
256 uint64_t scr_el3
; /* Secure configuration register. */
257 union { /* Fault status registers. */
268 uint64_t _unused_dfsr
;
275 uint32_t c6_region
[8]; /* MPU base/size registers. */
276 union { /* Fault address registers. */
278 uint64_t _unused_far0
;
279 #ifdef HOST_WORDS_BIGENDIAN
290 uint64_t _unused_far3
;
296 union { /* Translation result. */
298 uint64_t _unused_par_0
;
300 uint64_t _unused_par_1
;
308 uint32_t c9_insn
; /* Cache lockdown registers. */
310 uint64_t c9_pmcr
; /* performance monitor control register */
311 uint64_t c9_pmcnten
; /* perf monitor counter enables */
312 uint32_t c9_pmovsr
; /* perf monitor overflow status */
313 uint32_t c9_pmuserenr
; /* perf monitor user enable */
314 uint64_t c9_pmselr
; /* perf monitor counter selection register */
315 uint64_t c9_pminten
; /* perf monitor interrupt enables */
316 union { /* Memory attribute redirection */
318 #ifdef HOST_WORDS_BIGENDIAN
319 uint64_t _unused_mair_0
;
322 uint64_t _unused_mair_1
;
326 uint64_t _unused_mair_0
;
329 uint64_t _unused_mair_1
;
336 union { /* vector base address register */
338 uint64_t _unused_vbar
;
345 uint32_t mvbar
; /* (monitor) vector base address register */
346 struct { /* FCSE PID. */
350 union { /* Context ID. */
352 uint64_t _unused_contextidr_0
;
353 uint64_t contextidr_ns
;
354 uint64_t _unused_contextidr_1
;
355 uint64_t contextidr_s
;
357 uint64_t contextidr_el
[4];
359 union { /* User RW Thread register. */
361 uint64_t tpidrurw_ns
;
362 uint64_t tpidrprw_ns
;
366 uint64_t tpidr_el
[4];
368 /* The secure banks of these registers don't map anywhere */
373 union { /* User RO Thread register. */
374 uint64_t tpidruro_ns
;
375 uint64_t tpidrro_el
[1];
377 uint64_t c14_cntfrq
; /* Counter Frequency register */
378 uint64_t c14_cntkctl
; /* Timer Control register */
379 uint32_t cnthctl_el2
; /* Counter/Timer Hyp Control register */
380 uint64_t cntvoff_el2
; /* Counter Virtual Offset register */
381 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
382 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
383 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
384 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
385 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
386 uint32_t c15_threadid
; /* TI debugger thread-ID. */
387 uint32_t c15_config_base_address
; /* SCU base address. */
388 uint32_t c15_diagnostic
; /* diagnostic register */
389 uint32_t c15_power_diagnostic
;
390 uint32_t c15_power_control
; /* power control */
391 uint64_t dbgbvr
[16]; /* breakpoint value registers */
392 uint64_t dbgbcr
[16]; /* breakpoint control registers */
393 uint64_t dbgwvr
[16]; /* watchpoint value registers */
394 uint64_t dbgwcr
[16]; /* watchpoint control registers */
396 uint64_t oslsr_el1
; /* OS Lock Status */
399 /* If the counter is enabled, this stores the last time the counter
400 * was reset. Otherwise it stores the counter value
403 uint64_t pmccfiltr_el0
; /* Performance Monitor Filter Register */
404 uint64_t vpidr_el2
; /* Virtualization Processor ID Register */
405 uint64_t vmpidr_el2
; /* Virtualization Multiprocessor ID Register */
413 uint32_t ccr
; /* Configuration and Control */
414 uint32_t cfsr
; /* Configurable Fault Status */
415 uint32_t hfsr
; /* HardFault Status */
416 uint32_t dfsr
; /* Debug Fault Status Register */
417 uint32_t mmfar
; /* MemManage Fault Address */
418 uint32_t bfar
; /* BusFault Address */
422 /* Information associated with an exception about to be taken:
423 * code which raises an exception must set cs->exception_index and
424 * the relevant parts of this structure; the cpu_do_interrupt function
425 * will then set the guest-visible registers as part of the exception
429 uint32_t syndrome
; /* AArch64 format syndrome register */
430 uint32_t fsr
; /* AArch32 format fault status register info */
431 uint64_t vaddress
; /* virtual addr associated with exception, if any */
432 uint32_t target_el
; /* EL the exception should be targeted for */
433 /* If we implement EL2 we will also need to store information
434 * about the intermediate physical address for stage 2 faults.
438 /* Thumb-2 EE state. */
442 /* VFP coprocessor state. */
444 /* VFP/Neon register state. Note that the mapping between S, D and Q
445 * views of the register bank differs between AArch64 and AArch32:
447 * Qn = regs[2n+1]:regs[2n]
449 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
450 * (and regs[32] to regs[63] are inaccessible)
452 * Qn = regs[2n+1]:regs[2n]
454 * Sn = regs[2n] bits 31..0
455 * This corresponds to the architecturally defined mapping between
456 * the two execution states, and means we do not need to explicitly
457 * map these registers when changing states.
462 /* We store these fpcsr fields separately for convenience. */
466 /* scratch space when Tn are not sufficient. */
469 /* fp_status is the "normal" fp status. standard_fp_status retains
470 * values corresponding to the ARM "Standard FPSCR Value", ie
471 * default-NaN, flush-to-zero, round-to-nearest and is used by
472 * any operations (generally Neon) which the architecture defines
473 * as controlled by the standard FPSCR value rather than the FPSCR.
475 * To avoid having to transfer exception bits around, we simply
476 * say that the FPSCR cumulative exception flags are the logical
477 * OR of the flags in the two fp statuses. This relies on the
478 * only thing which needs to read the exception flags being
479 * an explicit FPSCR read.
481 float_status fp_status
;
482 float_status standard_fp_status
;
484 uint64_t exclusive_addr
;
485 uint64_t exclusive_val
;
486 uint64_t exclusive_high
;
488 /* iwMMXt coprocessor state. */
496 #if defined(CONFIG_USER_ONLY)
497 /* For usermode syscall translation. */
501 struct CPUBreakpoint
*cpu_breakpoint
[16];
502 struct CPUWatchpoint
*cpu_watchpoint
[16];
504 /* Fields up to this point are cleared by a CPU reset */
505 struct {} end_reset_fields
;
509 /* Fields after CPU_COMMON are preserved across CPU reset. */
511 /* Internal CPU feature flags. */
522 const struct arm_boot_info
*boot_info
;
527 * type of a function which can be registered via arm_register_el_change_hook()
528 * to get callbacks when the CPU changes its exception level or mode.
530 typedef void ARMELChangeHook(ARMCPU
*cpu
, void *opaque
);
533 /* These values map onto the return values for
534 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
535 typedef enum ARMPSCIState
{
554 /* Coprocessor information */
556 /* For marshalling (mostly coprocessor) register state between the
557 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
558 * we use these arrays.
560 /* List of register indexes managed via these arrays; (full KVM style
561 * 64 bit indexes, not CPRegInfo 32 bit indexes)
563 uint64_t *cpreg_indexes
;
564 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
565 uint64_t *cpreg_values
;
566 /* Length of the indexes, values, reset_values arrays */
567 int32_t cpreg_array_len
;
568 /* These are used only for migration: incoming data arrives in
569 * these fields and is sanity checked in post_load before copying
570 * to the working data structures above.
572 uint64_t *cpreg_vmstate_indexes
;
573 uint64_t *cpreg_vmstate_values
;
574 int32_t cpreg_vmstate_array_len
;
576 /* Timers used by the generic (architected) timer */
577 QEMUTimer
*gt_timer
[NUM_GTIMERS
];
578 /* GPIO outputs for generic timer */
579 qemu_irq gt_timer_outputs
[NUM_GTIMERS
];
580 /* GPIO output for GICv3 maintenance interrupt signal */
581 qemu_irq gicv3_maintenance_interrupt
;
583 /* MemoryRegion to use for secure physical accesses */
584 MemoryRegion
*secure_memory
;
586 /* 'compatible' string for this CPU for Linux device trees */
587 const char *dtb_compatible
;
589 /* PSCI version for this CPU
590 * Bits[31:16] = Major Version
591 * Bits[15:0] = Minor Version
593 uint32_t psci_version
;
595 /* Should CPU start in PSCI powered-off state? */
596 bool start_powered_off
;
598 /* Current power state, access guarded by BQL */
599 ARMPSCIState power_state
;
601 /* CPU has virtualization extension */
603 /* CPU has security extension */
605 /* CPU has PMU (Performance Monitor Unit) */
608 /* CPU has memory protection unit */
610 /* PMSAv7 MPU number of supported regions */
611 uint32_t pmsav7_dregion
;
613 /* PSCI conduit used to invoke PSCI methods
614 * 0 - disabled, 1 - smc, 2 - hvc
616 uint32_t psci_conduit
;
618 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
619 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
623 /* KVM init features for this CPU */
624 uint32_t kvm_init_features
[7];
626 /* Uniprocessor system with MP extensions */
629 /* The instance init functions for implementation-specific subclasses
630 * set these fields to specify the implementation-dependent values of
631 * various constant registers and reset values of non-constant
633 * Some of these might become QOM properties eventually.
634 * Field names match the official register names as defined in the
635 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
636 * is used for reset values of non-constant registers; no reset_
637 * prefix means a constant register.
641 uint32_t reset_fpsid
;
646 uint32_t reset_sctlr
;
664 uint64_t id_aa64pfr0
;
665 uint64_t id_aa64pfr1
;
666 uint64_t id_aa64dfr0
;
667 uint64_t id_aa64dfr1
;
668 uint64_t id_aa64afr0
;
669 uint64_t id_aa64afr1
;
670 uint64_t id_aa64isar0
;
671 uint64_t id_aa64isar1
;
672 uint64_t id_aa64mmfr0
;
673 uint64_t id_aa64mmfr1
;
676 uint64_t mp_affinity
; /* MP ID without feature bits */
677 /* The elements of this array are the CCSIDR values for each cache,
678 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
682 uint32_t reset_auxcr
;
684 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
685 uint32_t dcz_blocksize
;
688 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
689 int gic_num_lrs
; /* number of list registers */
690 int gic_vpribits
; /* number of virtual priority bits */
691 int gic_vprebits
; /* number of virtual preemption bits */
693 /* Whether the cfgend input is high (i.e. this CPU should reset into
694 * big-endian mode). This setting isn't used directly: instead it modifies
695 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
696 * architecture version.
700 ARMELChangeHook
*el_change_hook
;
701 void *el_change_hook_opaque
;
704 static inline ARMCPU
*arm_env_get_cpu(CPUARMState
*env
)
706 return container_of(env
, ARMCPU
, env
);
709 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
711 #define ENV_OFFSET offsetof(ARMCPU, env)
713 #ifndef CONFIG_USER_ONLY
714 extern const struct VMStateDescription vmstate_arm_cpu
;
717 void arm_cpu_do_interrupt(CPUState
*cpu
);
718 void arm_v7m_cpu_do_interrupt(CPUState
*cpu
);
719 bool arm_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
721 void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
724 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
727 int arm_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
728 int arm_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
730 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cs
,
731 int cpuid
, void *opaque
);
732 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cs
,
733 int cpuid
, void *opaque
);
735 #ifdef TARGET_AARCH64
736 int aarch64_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
737 int aarch64_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
740 ARMCPU
*cpu_arm_init(const char *cpu_model
);
741 target_ulong
do_arm_semihosting(CPUARMState
*env
);
742 void aarch64_sync_32_to_64(CPUARMState
*env
);
743 void aarch64_sync_64_to_32(CPUARMState
*env
);
745 static inline bool is_a64(CPUARMState
*env
)
750 /* you can call this signal handler from your SIGBUS and SIGSEGV
751 signal handlers to inform the virtual CPU of exceptions. non zero
752 is returned if the signal was handled by the virtual CPU. */
753 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
760 * Synchronises the counter in the PMCCNTR. This must always be called twice,
761 * once before any action that might affect the timer and again afterwards.
762 * The function is used to swap the state of the register if required.
763 * This only happens when not in user mode (!CONFIG_USER_ONLY)
765 void pmccntr_sync(CPUARMState
*env
);
767 /* SCTLR bit meanings. Several bits have been reused in newer
768 * versions of the architecture; in that case we define constants
769 * for both old and new bit meanings. Code which tests against those
770 * bits should probably check or otherwise arrange that the CPU
771 * is the architectural version it expects.
773 #define SCTLR_M (1U << 0)
774 #define SCTLR_A (1U << 1)
775 #define SCTLR_C (1U << 2)
776 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
777 #define SCTLR_SA (1U << 3)
778 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
779 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
780 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
781 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
782 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
783 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
784 #define SCTLR_ITD (1U << 7) /* v8 onward */
785 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
786 #define SCTLR_SED (1U << 8) /* v8 onward */
787 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
788 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
789 #define SCTLR_F (1U << 10) /* up to v6 */
790 #define SCTLR_SW (1U << 10) /* v7 onward */
791 #define SCTLR_Z (1U << 11)
792 #define SCTLR_I (1U << 12)
793 #define SCTLR_V (1U << 13)
794 #define SCTLR_RR (1U << 14) /* up to v7 */
795 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
796 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
797 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
798 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
799 #define SCTLR_nTWI (1U << 16) /* v8 onward */
800 #define SCTLR_HA (1U << 17)
801 #define SCTLR_BR (1U << 17) /* PMSA only */
802 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
803 #define SCTLR_nTWE (1U << 18) /* v8 onward */
804 #define SCTLR_WXN (1U << 19)
805 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
806 #define SCTLR_UWXN (1U << 20) /* v7 onward */
807 #define SCTLR_FI (1U << 21)
808 #define SCTLR_U (1U << 22)
809 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
810 #define SCTLR_VE (1U << 24) /* up to v7 */
811 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
812 #define SCTLR_EE (1U << 25)
813 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
814 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
815 #define SCTLR_NMFI (1U << 27)
816 #define SCTLR_TRE (1U << 28)
817 #define SCTLR_AFE (1U << 29)
818 #define SCTLR_TE (1U << 30)
820 #define CPTR_TCPAC (1U << 31)
821 #define CPTR_TTA (1U << 20)
822 #define CPTR_TFP (1U << 10)
824 #define MDCR_EPMAD (1U << 21)
825 #define MDCR_EDAD (1U << 20)
826 #define MDCR_SPME (1U << 17)
827 #define MDCR_SDD (1U << 16)
828 #define MDCR_SPD (3U << 14)
829 #define MDCR_TDRA (1U << 11)
830 #define MDCR_TDOSA (1U << 10)
831 #define MDCR_TDA (1U << 9)
832 #define MDCR_TDE (1U << 8)
833 #define MDCR_HPME (1U << 7)
834 #define MDCR_TPM (1U << 6)
835 #define MDCR_TPMCR (1U << 5)
837 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
838 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
840 #define CPSR_M (0x1fU)
841 #define CPSR_T (1U << 5)
842 #define CPSR_F (1U << 6)
843 #define CPSR_I (1U << 7)
844 #define CPSR_A (1U << 8)
845 #define CPSR_E (1U << 9)
846 #define CPSR_IT_2_7 (0xfc00U)
847 #define CPSR_GE (0xfU << 16)
848 #define CPSR_IL (1U << 20)
849 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
850 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
851 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
852 * where it is live state but not accessible to the AArch32 code.
854 #define CPSR_RESERVED (0x7U << 21)
855 #define CPSR_J (1U << 24)
856 #define CPSR_IT_0_1 (3U << 25)
857 #define CPSR_Q (1U << 27)
858 #define CPSR_V (1U << 28)
859 #define CPSR_C (1U << 29)
860 #define CPSR_Z (1U << 30)
861 #define CPSR_N (1U << 31)
862 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
863 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
865 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
866 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
868 /* Bits writable in user mode. */
869 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
870 /* Execution state bits. MRS read as zero, MSR writes ignored. */
871 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
872 /* Mask of bits which may be set by exception return copying them from SPSR */
873 #define CPSR_ERET_MASK (~CPSR_RESERVED)
875 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
876 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
877 #define TTBCR_PD0 (1U << 4)
878 #define TTBCR_PD1 (1U << 5)
879 #define TTBCR_EPD0 (1U << 7)
880 #define TTBCR_IRGN0 (3U << 8)
881 #define TTBCR_ORGN0 (3U << 10)
882 #define TTBCR_SH0 (3U << 12)
883 #define TTBCR_T1SZ (3U << 16)
884 #define TTBCR_A1 (1U << 22)
885 #define TTBCR_EPD1 (1U << 23)
886 #define TTBCR_IRGN1 (3U << 24)
887 #define TTBCR_ORGN1 (3U << 26)
888 #define TTBCR_SH1 (1U << 28)
889 #define TTBCR_EAE (1U << 31)
891 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
892 * Only these are valid when in AArch64 mode; in
893 * AArch32 mode SPSRs are basically CPSR-format.
895 #define PSTATE_SP (1U)
896 #define PSTATE_M (0xFU)
897 #define PSTATE_nRW (1U << 4)
898 #define PSTATE_F (1U << 6)
899 #define PSTATE_I (1U << 7)
900 #define PSTATE_A (1U << 8)
901 #define PSTATE_D (1U << 9)
902 #define PSTATE_IL (1U << 20)
903 #define PSTATE_SS (1U << 21)
904 #define PSTATE_V (1U << 28)
905 #define PSTATE_C (1U << 29)
906 #define PSTATE_Z (1U << 30)
907 #define PSTATE_N (1U << 31)
908 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
909 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
910 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
911 /* Mode values for AArch64 */
912 #define PSTATE_MODE_EL3h 13
913 #define PSTATE_MODE_EL3t 12
914 #define PSTATE_MODE_EL2h 9
915 #define PSTATE_MODE_EL2t 8
916 #define PSTATE_MODE_EL1h 5
917 #define PSTATE_MODE_EL1t 4
918 #define PSTATE_MODE_EL0t 0
920 /* Map EL and handler into a PSTATE_MODE. */
921 static inline unsigned int aarch64_pstate_mode(unsigned int el
, bool handler
)
923 return (el
<< 2) | handler
;
926 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
927 * interprocessing, so we don't attempt to sync with the cpsr state used by
928 * the 32 bit decoder.
930 static inline uint32_t pstate_read(CPUARMState
*env
)
935 return (env
->NF
& 0x80000000) | (ZF
<< 30)
936 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
937 | env
->pstate
| env
->daif
;
940 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
942 env
->ZF
= (~val
) & PSTATE_Z
;
944 env
->CF
= (val
>> 29) & 1;
945 env
->VF
= (val
<< 3) & 0x80000000;
946 env
->daif
= val
& PSTATE_DAIF
;
947 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
950 /* Return the current CPSR value. */
951 uint32_t cpsr_read(CPUARMState
*env
);
953 typedef enum CPSRWriteType
{
954 CPSRWriteByInstr
= 0, /* from guest MSR or CPS */
955 CPSRWriteExceptionReturn
= 1, /* from guest exception return insn */
956 CPSRWriteRaw
= 2, /* trust values, do not switch reg banks */
957 CPSRWriteByGDBStub
= 3, /* from the GDB stub */
960 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
961 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
962 CPSRWriteType write_type
);
964 /* Return the current xPSR value. */
965 static inline uint32_t xpsr_read(CPUARMState
*env
)
969 return (env
->NF
& 0x80000000) | (ZF
<< 30)
970 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
971 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
972 | ((env
->condexec_bits
& 0xfc) << 8)
973 | env
->v7m
.exception
;
976 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
977 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
979 if (mask
& CPSR_NZCV
) {
980 env
->ZF
= (~val
) & CPSR_Z
;
982 env
->CF
= (val
>> 29) & 1;
983 env
->VF
= (val
<< 3) & 0x80000000;
986 env
->QF
= ((val
& CPSR_Q
) != 0);
987 if (mask
& (1 << 24))
988 env
->thumb
= ((val
& (1 << 24)) != 0);
989 if (mask
& CPSR_IT_0_1
) {
990 env
->condexec_bits
&= ~3;
991 env
->condexec_bits
|= (val
>> 25) & 3;
993 if (mask
& CPSR_IT_2_7
) {
994 env
->condexec_bits
&= 3;
995 env
->condexec_bits
|= (val
>> 8) & 0xfc;
998 env
->v7m
.exception
= val
& 0x1ff;
1002 #define HCR_VM (1ULL << 0)
1003 #define HCR_SWIO (1ULL << 1)
1004 #define HCR_PTW (1ULL << 2)
1005 #define HCR_FMO (1ULL << 3)
1006 #define HCR_IMO (1ULL << 4)
1007 #define HCR_AMO (1ULL << 5)
1008 #define HCR_VF (1ULL << 6)
1009 #define HCR_VI (1ULL << 7)
1010 #define HCR_VSE (1ULL << 8)
1011 #define HCR_FB (1ULL << 9)
1012 #define HCR_BSU_MASK (3ULL << 10)
1013 #define HCR_DC (1ULL << 12)
1014 #define HCR_TWI (1ULL << 13)
1015 #define HCR_TWE (1ULL << 14)
1016 #define HCR_TID0 (1ULL << 15)
1017 #define HCR_TID1 (1ULL << 16)
1018 #define HCR_TID2 (1ULL << 17)
1019 #define HCR_TID3 (1ULL << 18)
1020 #define HCR_TSC (1ULL << 19)
1021 #define HCR_TIDCP (1ULL << 20)
1022 #define HCR_TACR (1ULL << 21)
1023 #define HCR_TSW (1ULL << 22)
1024 #define HCR_TPC (1ULL << 23)
1025 #define HCR_TPU (1ULL << 24)
1026 #define HCR_TTLB (1ULL << 25)
1027 #define HCR_TVM (1ULL << 26)
1028 #define HCR_TGE (1ULL << 27)
1029 #define HCR_TDZ (1ULL << 28)
1030 #define HCR_HCD (1ULL << 29)
1031 #define HCR_TRVM (1ULL << 30)
1032 #define HCR_RW (1ULL << 31)
1033 #define HCR_CD (1ULL << 32)
1034 #define HCR_ID (1ULL << 33)
1035 #define HCR_MASK ((1ULL << 34) - 1)
1037 #define SCR_NS (1U << 0)
1038 #define SCR_IRQ (1U << 1)
1039 #define SCR_FIQ (1U << 2)
1040 #define SCR_EA (1U << 3)
1041 #define SCR_FW (1U << 4)
1042 #define SCR_AW (1U << 5)
1043 #define SCR_NET (1U << 6)
1044 #define SCR_SMD (1U << 7)
1045 #define SCR_HCE (1U << 8)
1046 #define SCR_SIF (1U << 9)
1047 #define SCR_RW (1U << 10)
1048 #define SCR_ST (1U << 11)
1049 #define SCR_TWI (1U << 12)
1050 #define SCR_TWE (1U << 13)
1051 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1052 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1054 /* Return the current FPSCR value. */
1055 uint32_t vfp_get_fpscr(CPUARMState
*env
);
1056 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
1058 /* For A64 the FPSCR is split into two logically distinct registers,
1059 * FPCR and FPSR. However since they still use non-overlapping bits
1060 * we store the underlying state in fpscr and just mask on read/write.
1062 #define FPSR_MASK 0xf800009f
1063 #define FPCR_MASK 0x07f79f00
1064 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
1066 return vfp_get_fpscr(env
) & FPSR_MASK
;
1069 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
1071 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
1072 vfp_set_fpscr(env
, new_fpscr
);
1075 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
1077 return vfp_get_fpscr(env
) & FPCR_MASK
;
1080 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
1082 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
1083 vfp_set_fpscr(env
, new_fpscr
);
1087 ARM_CPU_MODE_USR
= 0x10,
1088 ARM_CPU_MODE_FIQ
= 0x11,
1089 ARM_CPU_MODE_IRQ
= 0x12,
1090 ARM_CPU_MODE_SVC
= 0x13,
1091 ARM_CPU_MODE_MON
= 0x16,
1092 ARM_CPU_MODE_ABT
= 0x17,
1093 ARM_CPU_MODE_HYP
= 0x1a,
1094 ARM_CPU_MODE_UND
= 0x1b,
1095 ARM_CPU_MODE_SYS
= 0x1f
1098 /* VFP system registers. */
1099 #define ARM_VFP_FPSID 0
1100 #define ARM_VFP_FPSCR 1
1101 #define ARM_VFP_MVFR2 5
1102 #define ARM_VFP_MVFR1 6
1103 #define ARM_VFP_MVFR0 7
1104 #define ARM_VFP_FPEXC 8
1105 #define ARM_VFP_FPINST 9
1106 #define ARM_VFP_FPINST2 10
1108 /* iwMMXt coprocessor control registers. */
1109 #define ARM_IWMMXT_wCID 0
1110 #define ARM_IWMMXT_wCon 1
1111 #define ARM_IWMMXT_wCSSF 2
1112 #define ARM_IWMMXT_wCASF 3
1113 #define ARM_IWMMXT_wCGR0 8
1114 #define ARM_IWMMXT_wCGR1 9
1115 #define ARM_IWMMXT_wCGR2 10
1116 #define ARM_IWMMXT_wCGR3 11
1119 FIELD(V7M_CCR
, NONBASETHRDENA
, 0, 1)
1120 FIELD(V7M_CCR
, USERSETMPEND
, 1, 1)
1121 FIELD(V7M_CCR
, UNALIGN_TRP
, 3, 1)
1122 FIELD(V7M_CCR
, DIV_0_TRP
, 4, 1)
1123 FIELD(V7M_CCR
, BFHFNMIGN
, 8, 1)
1124 FIELD(V7M_CCR
, STKALIGN
, 9, 1)
1125 FIELD(V7M_CCR
, DC
, 16, 1)
1126 FIELD(V7M_CCR
, IC
, 17, 1)
1128 /* V7M CFSR bits for MMFSR */
1129 FIELD(V7M_CFSR
, IACCVIOL
, 0, 1)
1130 FIELD(V7M_CFSR
, DACCVIOL
, 1, 1)
1131 FIELD(V7M_CFSR
, MUNSTKERR
, 3, 1)
1132 FIELD(V7M_CFSR
, MSTKERR
, 4, 1)
1133 FIELD(V7M_CFSR
, MLSPERR
, 5, 1)
1134 FIELD(V7M_CFSR
, MMARVALID
, 7, 1)
1136 /* V7M CFSR bits for BFSR */
1137 FIELD(V7M_CFSR
, IBUSERR
, 8 + 0, 1)
1138 FIELD(V7M_CFSR
, PRECISERR
, 8 + 1, 1)
1139 FIELD(V7M_CFSR
, IMPRECISERR
, 8 + 2, 1)
1140 FIELD(V7M_CFSR
, UNSTKERR
, 8 + 3, 1)
1141 FIELD(V7M_CFSR
, STKERR
, 8 + 4, 1)
1142 FIELD(V7M_CFSR
, LSPERR
, 8 + 5, 1)
1143 FIELD(V7M_CFSR
, BFARVALID
, 8 + 7, 1)
1145 /* V7M CFSR bits for UFSR */
1146 FIELD(V7M_CFSR
, UNDEFINSTR
, 16 + 0, 1)
1147 FIELD(V7M_CFSR
, INVSTATE
, 16 + 1, 1)
1148 FIELD(V7M_CFSR
, INVPC
, 16 + 2, 1)
1149 FIELD(V7M_CFSR
, NOCP
, 16 + 3, 1)
1150 FIELD(V7M_CFSR
, UNALIGNED
, 16 + 8, 1)
1151 FIELD(V7M_CFSR
, DIVBYZERO
, 16 + 9, 1)
1154 FIELD(V7M_HFSR
, VECTTBL
, 1, 1)
1155 FIELD(V7M_HFSR
, FORCED
, 30, 1)
1156 FIELD(V7M_HFSR
, DEBUGEVT
, 31, 1)
1159 FIELD(V7M_DFSR
, HALTED
, 0, 1)
1160 FIELD(V7M_DFSR
, BKPT
, 1, 1)
1161 FIELD(V7M_DFSR
, DWTTRAP
, 2, 1)
1162 FIELD(V7M_DFSR
, VCATCH
, 3, 1)
1163 FIELD(V7M_DFSR
, EXTERNAL
, 4, 1)
1165 /* If adding a feature bit which corresponds to a Linux ELF
1166 * HWCAP bit, remember to update the feature-bit-to-hwcap
1167 * mapping in linux-user/elfload.c:get_elf_hwcap().
1171 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
1172 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
1173 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
1178 ARM_FEATURE_MPU
, /* Only has Memory Protection Unit, not full MMU. */
1180 ARM_FEATURE_VFP_FP16
,
1182 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
1183 ARM_FEATURE_M
, /* Microcontroller profile. */
1184 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
1185 ARM_FEATURE_THUMB2EE
,
1186 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
1189 ARM_FEATURE_STRONGARM
,
1190 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
1191 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
1192 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
1193 ARM_FEATURE_GENERIC_TIMER
,
1194 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
1195 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
1196 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
1197 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
1198 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
1199 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
1200 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
1201 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
1203 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
1204 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
1205 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
1206 ARM_FEATURE_CRC
, /* ARMv8 CRC instructions */
1207 ARM_FEATURE_CBAR_RO
, /* has cp15 CBAR and it is read-only */
1208 ARM_FEATURE_EL2
, /* has EL2 Virtualization support */
1209 ARM_FEATURE_EL3
, /* has EL3 Secure monitor support */
1210 ARM_FEATURE_V8_SHA1
, /* implements SHA1 part of v8 Crypto Extensions */
1211 ARM_FEATURE_V8_SHA256
, /* implements SHA256 part of v8 Crypto Extensions */
1212 ARM_FEATURE_V8_PMULL
, /* implements PMULL part of v8 Crypto Extensions */
1213 ARM_FEATURE_THUMB_DSP
, /* DSP insns supported in the Thumb encodings */
1214 ARM_FEATURE_PMU
, /* has PMU support */
1215 ARM_FEATURE_VBAR
, /* has cp15 VBAR */
1218 static inline int arm_feature(CPUARMState
*env
, int feature
)
1220 return (env
->features
& (1ULL << feature
)) != 0;
1223 #if !defined(CONFIG_USER_ONLY)
1224 /* Return true if exception levels below EL3 are in secure state,
1225 * or would be following an exception return to that level.
1226 * Unlike arm_is_secure() (which is always a question about the
1227 * _current_ state of the CPU) this doesn't care about the current
1230 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
1232 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1233 return !(env
->cp15
.scr_el3
& SCR_NS
);
1235 /* If EL3 is not supported then the secure state is implementation
1236 * defined, in which case QEMU defaults to non-secure.
1242 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
1243 static inline bool arm_is_el3_or_mon(CPUARMState
*env
)
1245 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1246 if (is_a64(env
) && extract32(env
->pstate
, 2, 2) == 3) {
1247 /* CPU currently in AArch64 state and EL3 */
1249 } else if (!is_a64(env
) &&
1250 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
1251 /* CPU currently in AArch32 state and monitor mode */
1258 /* Return true if the processor is in secure state */
1259 static inline bool arm_is_secure(CPUARMState
*env
)
1261 if (arm_is_el3_or_mon(env
)) {
1264 return arm_is_secure_below_el3(env
);
1268 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
1273 static inline bool arm_is_secure(CPUARMState
*env
)
1279 /* Return true if the specified exception level is running in AArch64 state. */
1280 static inline bool arm_el_is_aa64(CPUARMState
*env
, int el
)
1282 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
1283 * and if we're not in EL0 then the state of EL0 isn't well defined.)
1285 assert(el
>= 1 && el
<= 3);
1286 bool aa64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
1288 /* The highest exception level is always at the maximum supported
1289 * register width, and then lower levels have a register width controlled
1290 * by bits in the SCR or HCR registers.
1296 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1297 aa64
= aa64
&& (env
->cp15
.scr_el3
& SCR_RW
);
1304 if (arm_feature(env
, ARM_FEATURE_EL2
) && !arm_is_secure_below_el3(env
)) {
1305 aa64
= aa64
&& (env
->cp15
.hcr_el2
& HCR_RW
);
1311 /* Function for determing whether guest cp register reads and writes should
1312 * access the secure or non-secure bank of a cp register. When EL3 is
1313 * operating in AArch32 state, the NS-bit determines whether the secure
1314 * instance of a cp register should be used. When EL3 is AArch64 (or if
1315 * it doesn't exist at all) then there is no register banking, and all
1316 * accesses are to the non-secure version.
1318 static inline bool access_secure_reg(CPUARMState
*env
)
1320 bool ret
= (arm_feature(env
, ARM_FEATURE_EL3
) &&
1321 !arm_el_is_aa64(env
, 3) &&
1322 !(env
->cp15
.scr_el3
& SCR_NS
));
1327 /* Macros for accessing a specified CP register bank */
1328 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
1329 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1331 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1334 (_env)->cp15._regname##_s = (_val); \
1336 (_env)->cp15._regname##_ns = (_val); \
1340 /* Macros for automatically accessing a specific CP register bank depending on
1341 * the current secure state of the system. These macros are not intended for
1342 * supporting instruction translation reads/writes as these are dependent
1343 * solely on the SCR.NS bit and not the mode.
1345 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1346 A32_BANKED_REG_GET((_env), _regname, \
1347 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1349 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1350 A32_BANKED_REG_SET((_env), _regname, \
1351 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1354 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
1355 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
1356 uint32_t cur_el
, bool secure
);
1358 /* Interface between CPU and Interrupt controller. */
1359 #ifndef CONFIG_USER_ONLY
1360 bool armv7m_nvic_can_take_pending_exception(void *opaque
);
1362 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque
)
1367 void armv7m_nvic_set_pending(void *opaque
, int irq
);
1368 int armv7m_nvic_acknowledge_irq(void *opaque
);
1369 void armv7m_nvic_complete_irq(void *opaque
, int irq
);
1371 /* Interface for defining coprocessor registers.
1372 * Registers are defined in tables of arm_cp_reginfo structs
1373 * which are passed to define_arm_cp_regs().
1376 /* When looking up a coprocessor register we look for it
1377 * via an integer which encodes all of:
1378 * coprocessor number
1379 * Crn, Crm, opc1, opc2 fields
1380 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1381 * or via MRRC/MCRR?)
1382 * non-secure/secure bank (AArch32 only)
1383 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1384 * (In this case crn and opc2 should be zero.)
1385 * For AArch64, there is no 32/64 bit size distinction;
1386 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1387 * and 4 bit CRn and CRm. The encoding patterns are chosen
1388 * to be easy to convert to and from the KVM encodings, and also
1389 * so that the hashtable can contain both AArch32 and AArch64
1390 * registers (to allow for interprocessing where we might run
1391 * 32 bit code on a 64 bit core).
1393 /* This bit is private to our hashtable cpreg; in KVM register
1394 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1395 * in the upper bits of the 64 bit ID.
1397 #define CP_REG_AA64_SHIFT 28
1398 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1400 /* To enable banking of coprocessor registers depending on ns-bit we
1401 * add a bit to distinguish between secure and non-secure cpregs in the
1404 #define CP_REG_NS_SHIFT 29
1405 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1407 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1408 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1409 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1411 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1412 (CP_REG_AA64_MASK | \
1413 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1414 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1415 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1416 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1417 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1418 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1420 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1421 * version used as a key for the coprocessor register hashtable
1423 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
1425 uint32_t cpregid
= kvmid
;
1426 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
1427 cpregid
|= CP_REG_AA64_MASK
;
1429 if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
1430 cpregid
|= (1 << 15);
1433 /* KVM is always non-secure so add the NS flag on AArch32 register
1436 cpregid
|= 1 << CP_REG_NS_SHIFT
;
1441 /* Convert a truncated 32 bit hashtable key into the full
1442 * 64 bit KVM register ID.
1444 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
1448 if (cpregid
& CP_REG_AA64_MASK
) {
1449 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
1450 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
1452 kvmid
= cpregid
& ~(1 << 15);
1453 if (cpregid
& (1 << 15)) {
1454 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
1456 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
1462 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1463 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1464 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1465 * TCG can assume the value to be constant (ie load at translate time)
1466 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1467 * indicates that the TB should not be ended after a write to this register
1468 * (the default is that the TB ends after cp writes). OVERRIDE permits
1469 * a register definition to override a previous definition for the
1470 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1471 * old must have the OVERRIDE bit set.
1472 * ALIAS indicates that this register is an alias view of some underlying
1473 * state which is also visible via another register, and that the other
1474 * register is handling migration and reset; registers marked ALIAS will not be
1475 * migrated but may have their state set by syncing of register state from KVM.
1476 * NO_RAW indicates that this register has no underlying state and does not
1477 * support raw access for state saving/loading; it will not be used for either
1478 * migration or KVM state synchronization. (Typically this is for "registers"
1479 * which are actually used as instructions for cache maintenance and so on.)
1480 * IO indicates that this register does I/O and therefore its accesses
1481 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1482 * registers which implement clocks or timers require this.
1484 #define ARM_CP_SPECIAL 1
1485 #define ARM_CP_CONST 2
1486 #define ARM_CP_64BIT 4
1487 #define ARM_CP_SUPPRESS_TB_END 8
1488 #define ARM_CP_OVERRIDE 16
1489 #define ARM_CP_ALIAS 32
1490 #define ARM_CP_IO 64
1491 #define ARM_CP_NO_RAW 128
1492 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1493 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1494 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1495 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1496 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1497 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1498 /* Used only as a terminator for ARMCPRegInfo lists */
1499 #define ARM_CP_SENTINEL 0xffff
1500 /* Mask of only the flag bits in a type field */
1501 #define ARM_CP_FLAG_MASK 0xff
1503 /* Valid values for ARMCPRegInfo state field, indicating which of
1504 * the AArch32 and AArch64 execution states this register is visible in.
1505 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1506 * If the reginfo is declared to be visible in both states then a second
1507 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1508 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1509 * Note that we rely on the values of these enums as we iterate through
1510 * the various states in some places.
1513 ARM_CP_STATE_AA32
= 0,
1514 ARM_CP_STATE_AA64
= 1,
1515 ARM_CP_STATE_BOTH
= 2,
1518 /* ARM CP register secure state flags. These flags identify security state
1519 * attributes for a given CP register entry.
1520 * The existence of both or neither secure and non-secure flags indicates that
1521 * the register has both a secure and non-secure hash entry. A single one of
1522 * these flags causes the register to only be hashed for the specified
1524 * Although definitions may have any combination of the S/NS bits, each
1525 * registered entry will only have one to identify whether the entry is secure
1529 ARM_CP_SECSTATE_S
= (1 << 0), /* bit[0]: Secure state register */
1530 ARM_CP_SECSTATE_NS
= (1 << 1), /* bit[1]: Non-secure state register */
1533 /* Return true if cptype is a valid type field. This is used to try to
1534 * catch errors where the sentinel has been accidentally left off the end
1535 * of a list of registers.
1537 static inline bool cptype_valid(int cptype
)
1539 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
1540 || ((cptype
& ARM_CP_SPECIAL
) &&
1541 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
1545 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1546 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1547 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1548 * (ie any of the privileged modes in Secure state, or Monitor mode).
1549 * If a register is accessible in one privilege level it's always accessible
1550 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1551 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1552 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1553 * terminology a little and call this PL3.
1554 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1555 * with the ELx exception levels.
1557 * If access permissions for a register are more complex than can be
1558 * described with these bits, then use a laxer set of restrictions, and
1559 * do the more restrictive/complex check inside a helper function.
1563 #define PL2_R (0x20 | PL3_R)
1564 #define PL2_W (0x10 | PL3_W)
1565 #define PL1_R (0x08 | PL2_R)
1566 #define PL1_W (0x04 | PL2_W)
1567 #define PL0_R (0x02 | PL1_R)
1568 #define PL0_W (0x01 | PL1_W)
1570 #define PL3_RW (PL3_R | PL3_W)
1571 #define PL2_RW (PL2_R | PL2_W)
1572 #define PL1_RW (PL1_R | PL1_W)
1573 #define PL0_RW (PL0_R | PL0_W)
1575 /* Return the highest implemented Exception Level */
1576 static inline int arm_highest_el(CPUARMState
*env
)
1578 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1581 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1587 /* Return the current Exception Level (as per ARMv8; note that this differs
1588 * from the ARMv7 Privilege Level).
1590 static inline int arm_current_el(CPUARMState
*env
)
1592 if (arm_feature(env
, ARM_FEATURE_M
)) {
1593 return !((env
->v7m
.exception
== 0) && (env
->v7m
.control
& 1));
1597 return extract32(env
->pstate
, 2, 2);
1600 switch (env
->uncached_cpsr
& 0x1f) {
1601 case ARM_CPU_MODE_USR
:
1603 case ARM_CPU_MODE_HYP
:
1605 case ARM_CPU_MODE_MON
:
1608 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
1609 /* If EL3 is 32-bit then all secure privileged modes run in
1619 typedef struct ARMCPRegInfo ARMCPRegInfo
;
1621 typedef enum CPAccessResult
{
1622 /* Access is permitted */
1624 /* Access fails due to a configurable trap or enable which would
1625 * result in a categorized exception syndrome giving information about
1626 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1627 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1628 * PL1 if in EL0, otherwise to the current EL).
1631 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1632 * Note that this is not a catch-all case -- the set of cases which may
1633 * result in this failure is specifically defined by the architecture.
1635 CP_ACCESS_TRAP_UNCATEGORIZED
= 2,
1636 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1637 CP_ACCESS_TRAP_EL2
= 3,
1638 CP_ACCESS_TRAP_EL3
= 4,
1639 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
1640 CP_ACCESS_TRAP_UNCATEGORIZED_EL2
= 5,
1641 CP_ACCESS_TRAP_UNCATEGORIZED_EL3
= 6,
1642 /* Access fails and results in an exception syndrome for an FP access,
1643 * trapped directly to EL2 or EL3
1645 CP_ACCESS_TRAP_FP_EL2
= 7,
1646 CP_ACCESS_TRAP_FP_EL3
= 8,
1649 /* Access functions for coprocessor registers. These cannot fail and
1650 * may not raise exceptions.
1652 typedef uint64_t CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1653 typedef void CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
1655 /* Access permission check functions for coprocessor registers. */
1656 typedef CPAccessResult
CPAccessFn(CPUARMState
*env
,
1657 const ARMCPRegInfo
*opaque
,
1659 /* Hook function for register reset */
1660 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1664 /* Definition of an ARM coprocessor register */
1665 struct ARMCPRegInfo
{
1666 /* Name of register (useful mainly for debugging, need not be unique) */
1668 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1669 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1670 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1671 * will be decoded to this register. The register read and write
1672 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1673 * used by the program, so it is possible to register a wildcard and
1674 * then behave differently on read/write if necessary.
1675 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1676 * must both be zero.
1677 * For AArch64-visible registers, opc0 is also used.
1678 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1679 * way to distinguish (for KVM's benefit) guest-visible system registers
1680 * from demuxed ones provided to preserve the "no side effects on
1681 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1682 * visible (to match KVM's encoding); cp==0 will be converted to
1683 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1691 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1693 /* Register type: ARM_CP_* bits/values */
1695 /* Access rights: PL*_[RW] */
1697 /* Security state: ARM_CP_SECSTATE_* bits/values */
1699 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1700 * this register was defined: can be used to hand data through to the
1701 * register read/write functions, since they are passed the ARMCPRegInfo*.
1704 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1705 * fieldoffset is non-zero, the reset value of the register.
1707 uint64_t resetvalue
;
1708 /* Offset of the field in CPUARMState for this register.
1710 * This is not needed if either:
1711 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1712 * 2. both readfn and writefn are specified
1714 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
1716 /* Offsets of the secure and non-secure fields in CPUARMState for the
1717 * register if it is banked. These fields are only used during the static
1718 * registration of a register. During hashing the bank associated
1719 * with a given security state is copied to fieldoffset which is used from
1722 * It is expected that register definitions use either fieldoffset or
1723 * bank_fieldoffsets in the definition but not both. It is also expected
1724 * that both bank offsets are set when defining a banked register. This
1725 * use indicates that a register is banked.
1727 ptrdiff_t bank_fieldoffsets
[2];
1729 /* Function for making any access checks for this register in addition to
1730 * those specified by the 'access' permissions bits. If NULL, no extra
1731 * checks required. The access check is performed at runtime, not at
1734 CPAccessFn
*accessfn
;
1735 /* Function for handling reads of this register. If NULL, then reads
1736 * will be done by loading from the offset into CPUARMState specified
1740 /* Function for handling writes of this register. If NULL, then writes
1741 * will be done by writing to the offset into CPUARMState specified
1745 /* Function for doing a "raw" read; used when we need to copy
1746 * coprocessor state to the kernel for KVM or out for
1747 * migration. This only needs to be provided if there is also a
1748 * readfn and it has side effects (for instance clear-on-read bits).
1750 CPReadFn
*raw_readfn
;
1751 /* Function for doing a "raw" write; used when we need to copy KVM
1752 * kernel coprocessor state into userspace, or for inbound
1753 * migration. This only needs to be provided if there is also a
1754 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1755 * or similar behaviour.
1757 CPWriteFn
*raw_writefn
;
1758 /* Function for resetting the register. If NULL, then reset will be done
1759 * by writing resetvalue to the field specified in fieldoffset. If
1760 * fieldoffset is 0 then no reset will be done.
1765 /* Macros which are lvalues for the field in CPUARMState for the
1768 #define CPREG_FIELD32(env, ri) \
1769 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1770 #define CPREG_FIELD64(env, ri) \
1771 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1773 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1775 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1776 const ARMCPRegInfo
*regs
, void *opaque
);
1777 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1778 const ARMCPRegInfo
*regs
, void *opaque
);
1779 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1781 define_arm_cp_regs_with_opaque(cpu
, regs
, 0);
1783 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1785 define_one_arm_cp_reg_with_opaque(cpu
, regs
, 0);
1787 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
1789 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1790 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1792 /* CPReadFn that can be used for read-as-zero behaviour */
1793 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1795 /* CPResetFn that does nothing, for use if no reset is required even
1796 * if fieldoffset is non zero.
1798 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1800 /* Return true if this reginfo struct's field in the cpu state struct
1803 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo
*ri
)
1805 return (ri
->state
== ARM_CP_STATE_AA64
) || (ri
->type
& ARM_CP_64BIT
);
1808 static inline bool cp_access_ok(int current_el
,
1809 const ARMCPRegInfo
*ri
, int isread
)
1811 return (ri
->access
>> ((current_el
* 2) + isread
)) & 1;
1814 /* Raw read of a coprocessor register (as needed for migration, etc) */
1815 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1818 * write_list_to_cpustate
1821 * For each register listed in the ARMCPU cpreg_indexes list, write
1822 * its value from the cpreg_values list into the ARMCPUState structure.
1823 * This updates TCG's working data structures from KVM data or
1824 * from incoming migration state.
1826 * Returns: true if all register values were updated correctly,
1827 * false if some register was unknown or could not be written.
1828 * Note that we do not stop early on failure -- we will attempt
1829 * writing all registers in the list.
1831 bool write_list_to_cpustate(ARMCPU
*cpu
);
1834 * write_cpustate_to_list:
1837 * For each register listed in the ARMCPU cpreg_indexes list, write
1838 * its value from the ARMCPUState structure into the cpreg_values list.
1839 * This is used to copy info from TCG's working data structures into
1840 * KVM or for outbound migration.
1842 * Returns: true if all register values were read correctly,
1843 * false if some register was unknown or could not be read.
1844 * Note that we do not stop early on failure -- we will attempt
1845 * reading all registers in the list.
1847 bool write_cpustate_to_list(ARMCPU
*cpu
);
1849 #define ARM_CPUID_TI915T 0x54029152
1850 #define ARM_CPUID_TI925T 0x54029252
1852 #if defined(CONFIG_USER_ONLY)
1853 #define TARGET_PAGE_BITS 12
1855 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
1856 * have to support 1K tiny pages.
1858 #define TARGET_PAGE_BITS_VARY
1859 #define TARGET_PAGE_BITS_MIN 10
1862 #if defined(TARGET_AARCH64)
1863 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1864 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1866 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1867 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1870 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
1871 unsigned int target_el
)
1873 CPUARMState
*env
= cs
->env_ptr
;
1874 unsigned int cur_el
= arm_current_el(env
);
1875 bool secure
= arm_is_secure(env
);
1876 bool pstate_unmasked
;
1877 int8_t unmasked
= 0;
1879 /* Don't take exceptions if they target a lower EL.
1880 * This check should catch any exceptions that would not be taken but left
1883 if (cur_el
> target_el
) {
1889 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
1893 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
1897 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_FMO
)) {
1898 /* VFIQs are only taken when hypervized and non-secure. */
1901 return !(env
->daif
& PSTATE_F
);
1903 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_IMO
)) {
1904 /* VIRQs are only taken when hypervized and non-secure. */
1907 return !(env
->daif
& PSTATE_I
);
1909 g_assert_not_reached();
1912 /* Use the target EL, current execution state and SCR/HCR settings to
1913 * determine whether the corresponding CPSR bit is used to mask the
1916 if ((target_el
> cur_el
) && (target_el
!= 1)) {
1917 /* Exceptions targeting a higher EL may not be maskable */
1918 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
1919 /* 64-bit masking rules are simple: exceptions to EL3
1920 * can't be masked, and exceptions to EL2 can only be
1921 * masked from Secure state. The HCR and SCR settings
1922 * don't affect the masking logic, only the interrupt routing.
1924 if (target_el
== 3 || !secure
) {
1928 /* The old 32-bit-only environment has a more complicated
1929 * masking setup. HCR and SCR bits not only affect interrupt
1930 * routing but also change the behaviour of masking.
1936 /* If FIQs are routed to EL3 or EL2 then there are cases where
1937 * we override the CPSR.F in determining if the exception is
1938 * masked or not. If neither of these are set then we fall back
1939 * to the CPSR.F setting otherwise we further assess the state
1942 hcr
= (env
->cp15
.hcr_el2
& HCR_FMO
);
1943 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
1945 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
1946 * CPSR.F bit masks FIQ interrupts when taken in non-secure
1947 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
1948 * when non-secure but only when FIQs are only routed to EL3.
1950 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
1953 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
1954 * we may override the CPSR.I masking when in non-secure state.
1955 * The SCR.IRQ setting has already been taken into consideration
1956 * when setting the target EL, so it does not have a further
1959 hcr
= (env
->cp15
.hcr_el2
& HCR_IMO
);
1963 g_assert_not_reached();
1966 if ((scr
|| hcr
) && !secure
) {
1972 /* The PSTATE bits only mask the interrupt if we have not overriden the
1975 return unmasked
|| pstate_unmasked
;
1978 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1980 #define cpu_signal_handler cpu_arm_signal_handler
1981 #define cpu_list arm_cpu_list
1983 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
1986 * + NonSecure EL1 & 0 stage 1
1987 * + NonSecure EL1 & 0 stage 2
1989 * + Secure EL1 & EL0
1992 * + NonSecure PL1 & 0 stage 1
1993 * + NonSecure PL1 & 0 stage 2
1995 * + Secure PL0 & PL1
1996 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
1998 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
1999 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
2000 * may differ in access permissions even if the VA->PA map is the same
2001 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2002 * translation, which means that we have one mmu_idx that deals with two
2003 * concatenated translation regimes [this sort of combined s1+2 TLB is
2004 * architecturally permitted]
2005 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2006 * handling via the TLB. The only way to do a stage 1 translation without
2007 * the immediate stage 2 translation is via the ATS or AT system insns,
2008 * which can be slow-pathed and always do a page table walk.
2009 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2010 * translation regimes, because they map reasonably well to each other
2011 * and they can't both be active at the same time.
2012 * This gives us the following list of mmu_idx values:
2014 * NS EL0 (aka NS PL0) stage 1+2
2015 * NS EL1 (aka NS PL1) stage 1+2
2016 * NS EL2 (aka NS PL2)
2019 * S EL1 (not used if EL3 is 32 bit)
2022 * (The last of these is an mmu_idx because we want to be able to use the TLB
2023 * for the accesses done as part of a stage 1 page table walk, rather than
2024 * having to walk the stage 2 page table over and over.)
2026 * Our enumeration includes at the end some entries which are not "true"
2027 * mmu_idx values in that they don't have corresponding TLBs and are only
2028 * valid for doing slow path page table walks.
2030 * The constant names here are patterned after the general style of the names
2031 * of the AT/ATS operations.
2032 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2034 typedef enum ARMMMUIdx
{
2035 ARMMMUIdx_S12NSE0
= 0,
2036 ARMMMUIdx_S12NSE1
= 1,
2039 ARMMMUIdx_S1SE0
= 4,
2040 ARMMMUIdx_S1SE1
= 5,
2042 /* Indexes below here don't have TLBs and are used only for AT system
2043 * instructions or for the first stage of an S12 page table walk.
2045 ARMMMUIdx_S1NSE0
= 7,
2046 ARMMMUIdx_S1NSE1
= 8,
2049 #define MMU_USER_IDX 0
2051 /* Return the exception level we're running at if this is our mmu_idx */
2052 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
2054 assert(mmu_idx
< ARMMMUIdx_S2NS
);
2058 /* Determine the current mmu_idx to use for normal loads/stores */
2059 static inline int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
2061 int el
= arm_current_el(env
);
2063 if (el
< 2 && arm_is_secure_below_el3(env
)) {
2064 return ARMMMUIdx_S1SE0
+ el
;
2069 /* Indexes used when registering address spaces with cpu_address_space_init */
2070 typedef enum ARMASIdx
{
2075 /* Return the Exception Level targeted by debug exceptions. */
2076 static inline int arm_debug_target_el(CPUARMState
*env
)
2078 bool secure
= arm_is_secure(env
);
2079 bool route_to_el2
= false;
2081 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
) {
2082 route_to_el2
= env
->cp15
.hcr_el2
& HCR_TGE
||
2083 env
->cp15
.mdcr_el2
& (1 << 8);
2088 } else if (arm_feature(env
, ARM_FEATURE_EL3
) &&
2089 !arm_el_is_aa64(env
, 3) && secure
) {
2096 static inline bool aa64_generate_debug_exceptions(CPUARMState
*env
)
2098 if (arm_is_secure(env
)) {
2099 /* MDCR_EL3.SDD disables debug events from Secure state */
2100 if (extract32(env
->cp15
.mdcr_el3
, 16, 1) != 0
2101 || arm_current_el(env
) == 3) {
2106 if (arm_current_el(env
) == arm_debug_target_el(env
)) {
2107 if ((extract32(env
->cp15
.mdscr_el1
, 13, 1) == 0)
2108 || (env
->daif
& PSTATE_D
)) {
2115 static inline bool aa32_generate_debug_exceptions(CPUARMState
*env
)
2117 int el
= arm_current_el(env
);
2119 if (el
== 0 && arm_el_is_aa64(env
, 1)) {
2120 return aa64_generate_debug_exceptions(env
);
2123 if (arm_is_secure(env
)) {
2126 if (el
== 0 && (env
->cp15
.sder
& 1)) {
2127 /* SDER.SUIDEN means debug exceptions from Secure EL0
2128 * are always enabled. Otherwise they are controlled by
2129 * SDCR.SPD like those from other Secure ELs.
2134 spd
= extract32(env
->cp15
.mdcr_el3
, 14, 2);
2137 /* SPD == 0b01 is reserved, but behaves as 0b00. */
2139 /* For 0b00 we return true if external secure invasive debug
2140 * is enabled. On real hardware this is controlled by external
2141 * signals to the core. QEMU always permits debug, and behaves
2142 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
2155 /* Return true if debugging exceptions are currently enabled.
2156 * This corresponds to what in ARM ARM pseudocode would be
2157 * if UsingAArch32() then
2158 * return AArch32.GenerateDebugExceptions()
2160 * return AArch64.GenerateDebugExceptions()
2161 * We choose to push the if() down into this function for clarity,
2162 * since the pseudocode has it at all callsites except for the one in
2163 * CheckSoftwareStep(), where it is elided because both branches would
2164 * always return the same value.
2166 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
2167 * don't yet implement those exception levels or their associated trap bits.
2169 static inline bool arm_generate_debug_exceptions(CPUARMState
*env
)
2172 return aa64_generate_debug_exceptions(env
);
2174 return aa32_generate_debug_exceptions(env
);
2178 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
2179 * implicitly means this always returns false in pre-v8 CPUs.)
2181 static inline bool arm_singlestep_active(CPUARMState
*env
)
2183 return extract32(env
->cp15
.mdscr_el1
, 0, 1)
2184 && arm_el_is_aa64(env
, arm_debug_target_el(env
))
2185 && arm_generate_debug_exceptions(env
);
2188 static inline bool arm_sctlr_b(CPUARMState
*env
)
2191 /* We need not implement SCTLR.ITD in user-mode emulation, so
2192 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2193 * This lets people run BE32 binaries with "-cpu any".
2195 #ifndef CONFIG_USER_ONLY
2196 !arm_feature(env
, ARM_FEATURE_V7
) &&
2198 (env
->cp15
.sctlr_el
[1] & SCTLR_B
) != 0;
2201 /* Return true if the processor is in big-endian mode. */
2202 static inline bool arm_cpu_data_is_big_endian(CPUARMState
*env
)
2206 /* In 32bit endianness is determined by looking at CPSR's E bit */
2209 #ifdef CONFIG_USER_ONLY
2210 /* In system mode, BE32 is modelled in line with the
2211 * architecture (as word-invariant big-endianness), where loads
2212 * and stores are done little endian but from addresses which
2213 * are adjusted by XORing with the appropriate constant. So the
2214 * endianness to use for the raw data access is not affected by
2216 * In user mode, however, we model BE32 as byte-invariant
2217 * big-endianness (because user-only code cannot tell the
2218 * difference), and so we need to use a data access endianness
2219 * that depends on SCTLR.B.
2223 ((env
->uncached_cpsr
& CPSR_E
) ? 1 : 0);
2226 cur_el
= arm_current_el(env
);
2229 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
2232 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
2235 #include "exec/cpu-all.h"
2237 /* Bit usage in the TB flags field: bit 31 indicates whether we are
2238 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
2239 * We put flags which are shared between 32 and 64 bit mode at the top
2240 * of the word, and flags which apply to only one mode at the bottom.
2242 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2243 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2244 #define ARM_TBFLAG_MMUIDX_SHIFT 28
2245 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2246 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2247 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2248 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2249 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2250 /* Target EL if we take a floating-point-disabled exception */
2251 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2252 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2254 /* Bit usage when in AArch32 state: */
2255 #define ARM_TBFLAG_THUMB_SHIFT 0
2256 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2257 #define ARM_TBFLAG_VECLEN_SHIFT 1
2258 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2259 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2260 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2261 #define ARM_TBFLAG_VFPEN_SHIFT 7
2262 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2263 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
2264 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2265 #define ARM_TBFLAG_SCTLR_B_SHIFT 16
2266 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2267 /* We store the bottom two bits of the CPAR as TB flags and handle
2268 * checks on the other bits at runtime
2270 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2271 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2272 /* Indicates whether cp register reads and writes by guest code should access
2273 * the secure or nonsecure bank of banked registers; note that this is not
2274 * the same thing as the current security state of the processor!
2276 #define ARM_TBFLAG_NS_SHIFT 19
2277 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2278 #define ARM_TBFLAG_BE_DATA_SHIFT 20
2279 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2281 /* Bit usage when in AArch64 state */
2282 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
2283 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
2284 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */
2285 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
2287 /* some convenience accessor macros */
2288 #define ARM_TBFLAG_AARCH64_STATE(F) \
2289 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2290 #define ARM_TBFLAG_MMUIDX(F) \
2291 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2292 #define ARM_TBFLAG_SS_ACTIVE(F) \
2293 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2294 #define ARM_TBFLAG_PSTATE_SS(F) \
2295 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2296 #define ARM_TBFLAG_FPEXC_EL(F) \
2297 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2298 #define ARM_TBFLAG_THUMB(F) \
2299 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2300 #define ARM_TBFLAG_VECLEN(F) \
2301 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2302 #define ARM_TBFLAG_VECSTRIDE(F) \
2303 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2304 #define ARM_TBFLAG_VFPEN(F) \
2305 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2306 #define ARM_TBFLAG_CONDEXEC(F) \
2307 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2308 #define ARM_TBFLAG_SCTLR_B(F) \
2309 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2310 #define ARM_TBFLAG_XSCALE_CPAR(F) \
2311 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2312 #define ARM_TBFLAG_NS(F) \
2313 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2314 #define ARM_TBFLAG_BE_DATA(F) \
2315 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2316 #define ARM_TBFLAG_TBI0(F) \
2317 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
2318 #define ARM_TBFLAG_TBI1(F) \
2319 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT)
2321 static inline bool bswap_code(bool sctlr_b
)
2323 #ifdef CONFIG_USER_ONLY
2324 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
2325 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
2326 * would also end up as a mixed-endian mode with BE code, LE data.
2329 #ifdef TARGET_WORDS_BIGENDIAN
2334 /* All code access in ARM is little endian, and there are no loaders
2335 * doing swaps that need to be reversed
2341 /* Return the exception level to which FP-disabled exceptions should
2342 * be taken, or 0 if FP is enabled.
2344 static inline int fp_exception_el(CPUARMState
*env
)
2347 int cur_el
= arm_current_el(env
);
2349 /* CPACR and the CPTR registers don't exist before v6, so FP is
2352 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
2356 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
2357 * 0, 2 : trap EL0 and EL1/PL1 accesses
2358 * 1 : trap only EL0 accesses
2359 * 3 : trap no accesses
2361 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
2365 if (cur_el
== 0 || cur_el
== 1) {
2366 /* Trap to PL1, which might be EL1 or EL3 */
2367 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
2372 if (cur_el
== 3 && !is_a64(env
)) {
2373 /* Secure PL1 running at EL3 */
2386 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
2387 * check because zero bits in the registers mean "don't trap".
2390 /* CPTR_EL2 : present in v7VE or v8 */
2391 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
2392 && !arm_is_secure_below_el3(env
)) {
2393 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
2397 /* CPTR_EL3 : present in v8 */
2398 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
2399 /* Trap all FP ops to EL3 */
2406 #ifdef CONFIG_USER_ONLY
2407 static inline bool arm_cpu_bswap_data(CPUARMState
*env
)
2410 #ifdef TARGET_WORDS_BIGENDIAN
2413 arm_cpu_data_is_big_endian(env
);
2417 #ifndef CONFIG_USER_ONLY
2421 * @mmu_idx: MMU index indicating required translation regime
2423 * Extracts the TBI0 value from the appropriate TCR for the current EL
2425 * Returns: the TBI0 value.
2427 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
2432 * @mmu_idx: MMU index indicating required translation regime
2434 * Extracts the TBI1 value from the appropriate TCR for the current EL
2436 * Returns: the TBI1 value.
2438 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
2440 /* We can't handle tagged addresses properly in user-only mode */
2441 static inline uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
2446 static inline uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
2452 static inline void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
2453 target_ulong
*cs_base
, uint32_t *flags
)
2455 ARMMMUIdx mmu_idx
= cpu_mmu_index(env
, false);
2458 *flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
2459 /* Get control bits for tagged addresses */
2460 *flags
|= (arm_regime_tbi0(env
, mmu_idx
) << ARM_TBFLAG_TBI0_SHIFT
);
2461 *flags
|= (arm_regime_tbi1(env
, mmu_idx
) << ARM_TBFLAG_TBI1_SHIFT
);
2463 *pc
= env
->regs
[15];
2464 *flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
2465 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
2466 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
2467 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
2468 | (arm_sctlr_b(env
) << ARM_TBFLAG_SCTLR_B_SHIFT
);
2469 if (!(access_secure_reg(env
))) {
2470 *flags
|= ARM_TBFLAG_NS_MASK
;
2472 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
2473 || arm_el_is_aa64(env
, 1)) {
2474 *flags
|= ARM_TBFLAG_VFPEN_MASK
;
2476 *flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
2477 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
2480 *flags
|= (mmu_idx
<< ARM_TBFLAG_MMUIDX_SHIFT
);
2482 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
2483 * states defined in the ARM ARM for software singlestep:
2484 * SS_ACTIVE PSTATE.SS State
2485 * 0 x Inactive (the TB flag for SS is always 0)
2486 * 1 0 Active-pending
2487 * 1 1 Active-not-pending
2489 if (arm_singlestep_active(env
)) {
2490 *flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
2492 if (env
->pstate
& PSTATE_SS
) {
2493 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
2496 if (env
->uncached_cpsr
& PSTATE_SS
) {
2497 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
2501 if (arm_cpu_data_is_big_endian(env
)) {
2502 *flags
|= ARM_TBFLAG_BE_DATA_MASK
;
2504 *flags
|= fp_exception_el(env
) << ARM_TBFLAG_FPEXC_EL_SHIFT
;
2510 QEMU_PSCI_CONDUIT_DISABLED
= 0,
2511 QEMU_PSCI_CONDUIT_SMC
= 1,
2512 QEMU_PSCI_CONDUIT_HVC
= 2,
2515 #ifndef CONFIG_USER_ONLY
2516 /* Return the address space index to use for a memory access */
2517 static inline int arm_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
2519 return attrs
.secure
? ARMASIdx_S
: ARMASIdx_NS
;
2522 /* Return the AddressSpace to use for a memory access
2523 * (which depends on whether the access is S or NS, and whether
2524 * the board gave us a separate AddressSpace for S accesses).
2526 static inline AddressSpace
*arm_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
2528 return cpu_get_address_space(cs
, arm_asidx_from_attrs(cs
, attrs
));
2533 * arm_register_el_change_hook:
2534 * Register a hook function which will be called back whenever this
2535 * CPU changes exception level or mode. The hook function will be
2536 * passed a pointer to the ARMCPU and the opaque data pointer passed
2537 * to this function when the hook was registered.
2539 * Note that we currently only support registering a single hook function,
2540 * and will assert if this function is called twice.
2541 * This facility is intended for the use of the GICv3 emulation.
2543 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
2547 * arm_get_el_change_hook_opaque:
2548 * Return the opaque data that will be used by the el_change_hook
2551 static inline void *arm_get_el_change_hook_opaque(ARMCPU
*cpu
)
2553 return cpu
->el_change_hook_opaque
;