include/hw/ssi/aspeed_smc.h

   1 /*
   2  * ASPEED AST2400 SMC Controller (SPI Flash Only)
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef ASPEED_SMC_H
  26 #define ASPEED_SMC_H
  27
  28 #include "hw/ssi/ssi.h"
  29 #include "hw/sysbus.h"
  30 #include "qom/object.h"
  31
  32 struct AspeedSMCState;
  33
  34 #define TYPE_ASPEED_SMC_FLASH "aspeed.smc.flash"
  35 OBJECT_DECLARE_SIMPLE_TYPE(AspeedSMCFlash, ASPEED_SMC_FLASH)
  36 struct AspeedSMCFlash {
  37     SysBusDevice parent_obj;
  38
  39     struct AspeedSMCState *controller;
  40     uint8_t cs;
  41
  42     MemoryRegion mmio;
  43 };
  44
  45 #define TYPE_ASPEED_SMC "aspeed.smc"
  46 OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC)
  47
  48 #define ASPEED_SMC_R_MAX        (0x100 / 4)
  49 #define ASPEED_SMC_CS_MAX       5
  50
  51 struct AspeedSMCState {
  52     SysBusDevice parent_obj;
  53
  54     MemoryRegion mmio;
  55     MemoryRegion mmio_flash_container;
  56     MemoryRegion mmio_flash;
  57
  58     qemu_irq irq;
  59
  60     uint32_t num_cs;
  61     qemu_irq *cs_lines;
  62     bool inject_failure;
  63
  64     SSIBus *spi;
  65
  66     uint32_t regs[ASPEED_SMC_R_MAX];
  67
  68     /* depends on the controller type */
  69     uint8_t r_conf;
  70     uint8_t r_ce_ctrl;
  71     uint8_t r_ctrl0;
  72     uint8_t r_timings;
  73     uint8_t conf_enable_w0;
  74
  75     AddressSpace flash_as;
  76     MemoryRegion *dram_mr;
  77     AddressSpace dram_as;
  78
  79     AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX];
  80
  81     uint8_t snoop_index;
  82     uint8_t snoop_dummies;
  83 };
  84
  85 typedef struct AspeedSegments {
  86     hwaddr addr;
  87     uint32_t size;
  88 } AspeedSegments;
  89
  90 struct AspeedSMCClass {
  91     SysBusDeviceClass parent_obj;
  92
  93     uint8_t r_conf;
  94     uint8_t r_ce_ctrl;
  95     uint8_t r_ctrl0;
  96     uint8_t r_timings;
  97     uint8_t nregs_timings;
  98     uint8_t conf_enable_w0;
  99     uint8_t max_peripherals;
 100     const uint32_t *resets;
 101     const AspeedSegments *segments;
 102     uint32_t segment_addr_mask;
 103     hwaddr flash_window_base;
 104     uint32_t flash_window_size;
 105     uint32_t features;
 106     hwaddr dma_flash_mask;
 107     hwaddr dma_dram_mask;
 108     uint32_t nregs;
 109     uint32_t (*segment_to_reg)(const AspeedSMCState *s,
 110                                const AspeedSegments *seg);
 111     void (*reg_to_segment)(const AspeedSMCState *s, uint32_t reg,
 112                            AspeedSegments *seg);
 113     void (*dma_ctrl)(AspeedSMCState *s, uint32_t value);
 114     int (*addr_width)(const AspeedSMCState *s);
 115 };
 116
 117 #endif /* ASPEED_SMC_H */