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mips/mips_jazz: add max ram size check
[qemu.git] / hw / usb / hcd-uhci.c
blob37f7beb3fa2207eb5dae4ff1d76a0c493cf9d01f
1 /*
2 * USB UHCI controller emulation
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28
29 #include "qemu/osdep.h"
30 #include "hw/usb.h"
31 #include "hw/usb/uhci-regs.h"
32 #include "migration/vmstate.h"
33 #include "hw/pci/pci.h"
34 #include "hw/qdev-properties.h"
35 #include "qapi/error.h"
36 #include "qemu/timer.h"
37 #include "qemu/iov.h"
38 #include "sysemu/dma.h"
39 #include "trace.h"
40 #include "qemu/main-loop.h"
41 #include "qemu/module.h"
42
43 #define FRAME_TIMER_FREQ 1000
44
45 #define FRAME_MAX_LOOPS 256
46
47 /* Must be large enough to handle 10 frame delay for initial isoc requests */
48 #define QH_VALID 32
49
50 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
51
52 #define NB_PORTS 2
53
54 enum {
55 TD_RESULT_STOP_FRAME = 10,
56 TD_RESULT_COMPLETE,
57 TD_RESULT_NEXT_QH,
58 TD_RESULT_ASYNC_START,
59 TD_RESULT_ASYNC_CONT,
60 };
61
62 typedef struct UHCIState UHCIState;
63 typedef struct UHCIAsync UHCIAsync;
64 typedef struct UHCIQueue UHCIQueue;
65 typedef struct UHCIInfo UHCIInfo;
66 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
67
68 struct UHCIInfo {
69 const char *name;
70 uint16_t vendor_id;
71 uint16_t device_id;
72 uint8_t revision;
73 uint8_t irq_pin;
74 void (*realize)(PCIDevice *dev, Error **errp);
75 bool unplug;
76 };
77
78 struct UHCIPCIDeviceClass {
79 PCIDeviceClass parent_class;
80 UHCIInfo info;
81 };
82
83 /*
84 * Pending async transaction.
85 * 'packet' must be the first field because completion
86 * handler does "(UHCIAsync *) pkt" cast.
87 */
88
89 struct UHCIAsync {
90 USBPacket packet;
91 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */
92 uint8_t *buf;
93 UHCIQueue *queue;
94 QTAILQ_ENTRY(UHCIAsync) next;
95 uint32_t td_addr;
96 uint8_t done;
97 };
98
99 struct UHCIQueue {
100 uint32_t qh_addr;
101 uint32_t token;
102 UHCIState *uhci;
103 USBEndpoint *ep;
104 QTAILQ_ENTRY(UHCIQueue) next;
105 QTAILQ_HEAD(, UHCIAsync) asyncs;
106 int8_t valid;
107 };
108
109 typedef struct UHCIPort {
110 USBPort port;
111 uint16_t ctrl;
112 } UHCIPort;
113
114 struct UHCIState {
115 PCIDevice dev;
116 MemoryRegion io_bar;
117 USBBus bus; /* Note unused when we're a companion controller */
118 uint16_t cmd; /* cmd register */
119 uint16_t status;
120 uint16_t intr; /* interrupt enable register */
121 uint16_t frnum; /* frame number */
122 uint32_t fl_base_addr; /* frame list base address */
123 uint8_t sof_timing;
124 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
125 int64_t expire_time;
126 QEMUTimer *frame_timer;
127 QEMUBH *bh;
128 uint32_t frame_bytes;
129 uint32_t frame_bandwidth;
130 bool completions_only;
131 UHCIPort ports[NB_PORTS];
132
133 /* Interrupts that should be raised at the end of the current frame. */
134 uint32_t pending_int_mask;
135
136 /* Active packets */
137 QTAILQ_HEAD(, UHCIQueue) queues;
138 uint8_t num_ports_vmstate;
139
140 /* Properties */
141 char *masterbus;
142 uint32_t firstport;
143 uint32_t maxframes;
144 };
145
146 typedef struct UHCI_TD {
147 uint32_t link;
148 uint32_t ctrl; /* see TD_CTRL_xxx */
149 uint32_t token;
150 uint32_t buffer;
151 } UHCI_TD;
152
153 typedef struct UHCI_QH {
154 uint32_t link;
155 uint32_t el_link;
156 } UHCI_QH;
157
158 static void uhci_async_cancel(UHCIAsync *async);
159 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
160 static void uhci_resume(void *opaque);
161
162 #define TYPE_UHCI "pci-uhci-usb"
163 #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI)
164
165 static inline int32_t uhci_queue_token(UHCI_TD *td)
166 {
167 if ((td->token & (0xf << 15)) == 0) {
168 /* ctrl ep, cover ep and dev, not pid! */
169 return td->token & 0x7ff00;
170 } else {
171 /* covers ep, dev, pid -> identifies the endpoint */
172 return td->token & 0x7ffff;
173 }
174 }
175
176 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
177 USBEndpoint *ep)
178 {
179 UHCIQueue *queue;
180
181 queue = g_new0(UHCIQueue, 1);
182 queue->uhci = s;
183 queue->qh_addr = qh_addr;
184 queue->token = uhci_queue_token(td);
185 queue->ep = ep;
186 QTAILQ_INIT(&queue->asyncs);
187 QTAILQ_INSERT_HEAD(&s->queues, queue, next);
188 queue->valid = QH_VALID;
189 trace_usb_uhci_queue_add(queue->token);
190 return queue;
191 }
192
193 static void uhci_queue_free(UHCIQueue *queue, const char *reason)
194 {
195 UHCIState *s = queue->uhci;
196 UHCIAsync *async;
197
198 while (!QTAILQ_EMPTY(&queue->asyncs)) {
199 async = QTAILQ_FIRST(&queue->asyncs);
200 uhci_async_cancel(async);
201 }
202 usb_device_ep_stopped(queue->ep->dev, queue->ep);
203
204 trace_usb_uhci_queue_del(queue->token, reason);
205 QTAILQ_REMOVE(&s->queues, queue, next);
206 g_free(queue);
207 }
208
209 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
210 {
211 uint32_t token = uhci_queue_token(td);
212 UHCIQueue *queue;
213
214 QTAILQ_FOREACH(queue, &s->queues, next) {
215 if (queue->token == token) {
216 return queue;
217 }
218 }
219 return NULL;
220 }
221
222 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
223 uint32_t td_addr, bool queuing)
224 {
225 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
226 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f;
227
228 return queue->qh_addr == qh_addr &&
229 queue->token == uhci_queue_token(td) &&
230 queue_token_addr == queue->ep->dev->addr &&
231 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
232 first->td_addr == td_addr);
233 }
234
235 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
236 {
237 UHCIAsync *async = g_new0(UHCIAsync, 1);
238
239 async->queue = queue;
240 async->td_addr = td_addr;
241 usb_packet_init(&async->packet);
242 trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
243
244 return async;
245 }
246
247 static void uhci_async_free(UHCIAsync *async)
248 {
249 trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
250 usb_packet_cleanup(&async->packet);
251 if (async->buf != async->static_buf) {
252 g_free(async->buf);
253 }
254 g_free(async);
255 }
256
257 static void uhci_async_link(UHCIAsync *async)
258 {
259 UHCIQueue *queue = async->queue;
260 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
261 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
262 }
263
264 static void uhci_async_unlink(UHCIAsync *async)
265 {
266 UHCIQueue *queue = async->queue;
267 QTAILQ_REMOVE(&queue->asyncs, async, next);
268 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
269 }
270
271 static void uhci_async_cancel(UHCIAsync *async)
272 {
273 uhci_async_unlink(async);
274 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
275 async->done);
276 if (!async->done)
277 usb_cancel_packet(&async->packet);
278 uhci_async_free(async);
279 }
280
281 /*
282 * Mark all outstanding async packets as invalid.
283 * This is used for canceling them when TDs are removed by the HCD.
284 */
285 static void uhci_async_validate_begin(UHCIState *s)
286 {
287 UHCIQueue *queue;
288
289 QTAILQ_FOREACH(queue, &s->queues, next) {
290 queue->valid--;
291 }
292 }
293
294 /*
295 * Cancel async packets that are no longer valid
296 */
297 static void uhci_async_validate_end(UHCIState *s)
298 {
299 UHCIQueue *queue, *n;
300
301 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
302 if (!queue->valid) {
303 uhci_queue_free(queue, "validate-end");
304 }
305 }
306 }
307
308 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
309 {
310 UHCIQueue *queue, *n;
311
312 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
313 if (queue->ep->dev == dev) {
314 uhci_queue_free(queue, "cancel-device");
315 }
316 }
317 }
318
319 static void uhci_async_cancel_all(UHCIState *s)
320 {
321 UHCIQueue *queue, *nq;
322
323 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
324 uhci_queue_free(queue, "cancel-all");
325 }
326 }
327
328 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
329 {
330 UHCIQueue *queue;
331 UHCIAsync *async;
332
333 QTAILQ_FOREACH(queue, &s->queues, next) {
334 QTAILQ_FOREACH(async, &queue->asyncs, next) {
335 if (async->td_addr == td_addr) {
336 return async;
337 }
338 }
339 }
340 return NULL;
341 }
342
343 static void uhci_update_irq(UHCIState *s)
344 {
345 int level;
346 if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
347 ((s->status2 & 2) && (s->intr & (1 << 3))) ||
348 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
349 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
350 (s->status & UHCI_STS_HSERR) ||
351 (s->status & UHCI_STS_HCPERR)) {
352 level = 1;
353 } else {
354 level = 0;
355 }
356 pci_set_irq(&s->dev, level);
357 }
358
359 static void uhci_reset(DeviceState *dev)
360 {
361 PCIDevice *d = PCI_DEVICE(dev);
362 UHCIState *s = UHCI(d);
363 uint8_t *pci_conf;
364 int i;
365 UHCIPort *port;
366
367 trace_usb_uhci_reset();
368
369 pci_conf = s->dev.config;
370
371 pci_conf[0x6a] = 0x01; /* usb clock */
372 pci_conf[0x6b] = 0x00;
373 s->cmd = 0;
374 s->status = UHCI_STS_HCHALTED;
375 s->status2 = 0;
376 s->intr = 0;
377 s->fl_base_addr = 0;
378 s->sof_timing = 64;
379
380 for(i = 0; i < NB_PORTS; i++) {
381 port = &s->ports[i];
382 port->ctrl = 0x0080;
383 if (port->port.dev && port->port.dev->attached) {
384 usb_port_reset(&port->port);
385 }
386 }
387
388 uhci_async_cancel_all(s);
389 qemu_bh_cancel(s->bh);
390 uhci_update_irq(s);
391 }
392
393 static const VMStateDescription vmstate_uhci_port = {
394 .name = "uhci port",
395 .version_id = 1,
396 .minimum_version_id = 1,
397 .fields = (VMStateField[]) {
398 VMSTATE_UINT16(ctrl, UHCIPort),
399 VMSTATE_END_OF_LIST()
400 }
401 };
402
403 static int uhci_post_load(void *opaque, int version_id)
404 {
405 UHCIState *s = opaque;
406
407 if (version_id < 2) {
408 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
409 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
410 }
411 return 0;
412 }
413
414 static const VMStateDescription vmstate_uhci = {
415 .name = "uhci",
416 .version_id = 3,
417 .minimum_version_id = 1,
418 .post_load = uhci_post_load,
419 .fields = (VMStateField[]) {
420 VMSTATE_PCI_DEVICE(dev, UHCIState),
421 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL),
422 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
423 vmstate_uhci_port, UHCIPort),
424 VMSTATE_UINT16(cmd, UHCIState),
425 VMSTATE_UINT16(status, UHCIState),
426 VMSTATE_UINT16(intr, UHCIState),
427 VMSTATE_UINT16(frnum, UHCIState),
428 VMSTATE_UINT32(fl_base_addr, UHCIState),
429 VMSTATE_UINT8(sof_timing, UHCIState),
430 VMSTATE_UINT8(status2, UHCIState),
431 VMSTATE_TIMER_PTR(frame_timer, UHCIState),
432 VMSTATE_INT64_V(expire_time, UHCIState, 2),
433 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3),
434 VMSTATE_END_OF_LIST()
435 }
436 };
437
438 static void uhci_port_write(void *opaque, hwaddr addr,
439 uint64_t val, unsigned size)
440 {
441 UHCIState *s = opaque;
442
443 trace_usb_uhci_mmio_writew(addr, val);
444
445 switch(addr) {
446 case 0x00:
447 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
448 /* start frame processing */
449 trace_usb_uhci_schedule_start();
450 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
451 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
452 timer_mod(s->frame_timer, s->expire_time);
453 s->status &= ~UHCI_STS_HCHALTED;
454 } else if (!(val & UHCI_CMD_RS)) {
455 s->status |= UHCI_STS_HCHALTED;
456 }
457 if (val & UHCI_CMD_GRESET) {
458 UHCIPort *port;
459 int i;
460
461 /* send reset on the USB bus */
462 for(i = 0; i < NB_PORTS; i++) {
463 port = &s->ports[i];
464 usb_device_reset(port->port.dev);
465 }
466 uhci_reset(DEVICE(s));
467 return;
468 }
469 if (val & UHCI_CMD_HCRESET) {
470 uhci_reset(DEVICE(s));
471 return;
472 }
473 s->cmd = val;
474 if (val & UHCI_CMD_EGSM) {
475 if ((s->ports[0].ctrl & UHCI_PORT_RD) ||
476 (s->ports[1].ctrl & UHCI_PORT_RD)) {
477 uhci_resume(s);
478 }
479 }
480 break;
481 case 0x02:
482 s->status &= ~val;
483 /* XXX: the chip spec is not coherent, so we add a hidden
484 register to distinguish between IOC and SPD */
485 if (val & UHCI_STS_USBINT)
486 s->status2 = 0;
487 uhci_update_irq(s);
488 break;
489 case 0x04:
490 s->intr = val;
491 uhci_update_irq(s);
492 break;
493 case 0x06:
494 if (s->status & UHCI_STS_HCHALTED)
495 s->frnum = val & 0x7ff;
496 break;
497 case 0x08:
498 s->fl_base_addr &= 0xffff0000;
499 s->fl_base_addr |= val & ~0xfff;
500 break;
501 case 0x0a:
502 s->fl_base_addr &= 0x0000ffff;
503 s->fl_base_addr |= (val << 16);
504 break;
505 case 0x0c:
506 s->sof_timing = val & 0xff;
507 break;
508 case 0x10 ... 0x1f:
509 {
510 UHCIPort *port;
511 USBDevice *dev;
512 int n;
513
514 n = (addr >> 1) & 7;
515 if (n >= NB_PORTS)
516 return;
517 port = &s->ports[n];
518 dev = port->port.dev;
519 if (dev && dev->attached) {
520 /* port reset */
521 if ( (val & UHCI_PORT_RESET) &&
522 !(port->ctrl & UHCI_PORT_RESET) ) {
523 usb_device_reset(dev);
524 }
525 }
526 port->ctrl &= UHCI_PORT_READ_ONLY;
527 /* enabled may only be set if a device is connected */
528 if (!(port->ctrl & UHCI_PORT_CCS)) {
529 val &= ~UHCI_PORT_EN;
530 }
531 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
532 /* some bits are reset when a '1' is written to them */
533 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
534 }
535 break;
536 }
537 }
538
539 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
540 {
541 UHCIState *s = opaque;
542 uint32_t val;
543
544 switch(addr) {
545 case 0x00:
546 val = s->cmd;
547 break;
548 case 0x02:
549 val = s->status;
550 break;
551 case 0x04:
552 val = s->intr;
553 break;
554 case 0x06:
555 val = s->frnum;
556 break;
557 case 0x08:
558 val = s->fl_base_addr & 0xffff;
559 break;
560 case 0x0a:
561 val = (s->fl_base_addr >> 16) & 0xffff;
562 break;
563 case 0x0c:
564 val = s->sof_timing;
565 break;
566 case 0x10 ... 0x1f:
567 {
568 UHCIPort *port;
569 int n;
570 n = (addr >> 1) & 7;
571 if (n >= NB_PORTS)
572 goto read_default;
573 port = &s->ports[n];
574 val = port->ctrl;
575 }
576 break;
577 default:
578 read_default:
579 val = 0xff7f; /* disabled port */
580 break;
581 }
582
583 trace_usb_uhci_mmio_readw(addr, val);
584
585 return val;
586 }
587
588 /* signal resume if controller suspended */
589 static void uhci_resume (void *opaque)
590 {
591 UHCIState *s = (UHCIState *)opaque;
592
593 if (!s)
594 return;
595
596 if (s->cmd & UHCI_CMD_EGSM) {
597 s->cmd |= UHCI_CMD_FGR;
598 s->status |= UHCI_STS_RD;
599 uhci_update_irq(s);
600 }
601 }
602
603 static void uhci_attach(USBPort *port1)
604 {
605 UHCIState *s = port1->opaque;
606 UHCIPort *port = &s->ports[port1->index];
607
608 /* set connect status */
609 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
610
611 /* update speed */
612 if (port->port.dev->speed == USB_SPEED_LOW) {
613 port->ctrl |= UHCI_PORT_LSDA;
614 } else {
615 port->ctrl &= ~UHCI_PORT_LSDA;
616 }
617
618 uhci_resume(s);
619 }
620
621 static void uhci_detach(USBPort *port1)
622 {
623 UHCIState *s = port1->opaque;
624 UHCIPort *port = &s->ports[port1->index];
625
626 uhci_async_cancel_device(s, port1->dev);
627
628 /* set connect status */
629 if (port->ctrl & UHCI_PORT_CCS) {
630 port->ctrl &= ~UHCI_PORT_CCS;
631 port->ctrl |= UHCI_PORT_CSC;
632 }
633 /* disable port */
634 if (port->ctrl & UHCI_PORT_EN) {
635 port->ctrl &= ~UHCI_PORT_EN;
636 port->ctrl |= UHCI_PORT_ENC;
637 }
638
639 uhci_resume(s);
640 }
641
642 static void uhci_child_detach(USBPort *port1, USBDevice *child)
643 {
644 UHCIState *s = port1->opaque;
645
646 uhci_async_cancel_device(s, child);
647 }
648
649 static void uhci_wakeup(USBPort *port1)
650 {
651 UHCIState *s = port1->opaque;
652 UHCIPort *port = &s->ports[port1->index];
653
654 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
655 port->ctrl |= UHCI_PORT_RD;
656 uhci_resume(s);
657 }
658 }
659
660 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
661 {
662 USBDevice *dev;
663 int i;
664
665 for (i = 0; i < NB_PORTS; i++) {
666 UHCIPort *port = &s->ports[i];
667 if (!(port->ctrl & UHCI_PORT_EN)) {
668 continue;
669 }
670 dev = usb_find_device(&port->port, addr);
671 if (dev != NULL) {
672 return dev;
673 }
674 }
675 return NULL;
676 }
677
678 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
679 {
680 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
681 le32_to_cpus(&td->link);
682 le32_to_cpus(&td->ctrl);
683 le32_to_cpus(&td->token);
684 le32_to_cpus(&td->buffer);
685 }
686
687 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
688 int status, uint32_t *int_mask)
689 {
690 uint32_t queue_token = uhci_queue_token(td);
691 int ret;
692
693 switch (status) {
694 case USB_RET_NAK:
695 td->ctrl |= TD_CTRL_NAK;
696 return TD_RESULT_NEXT_QH;
697
698 case USB_RET_STALL:
699 td->ctrl |= TD_CTRL_STALL;
700 trace_usb_uhci_packet_complete_stall(queue_token, td_addr);
701 ret = TD_RESULT_NEXT_QH;
702 break;
703
704 case USB_RET_BABBLE:
705 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
706 /* frame interrupted */
707 trace_usb_uhci_packet_complete_babble(queue_token, td_addr);
708 ret = TD_RESULT_STOP_FRAME;
709 break;
710
711 case USB_RET_IOERROR:
712 case USB_RET_NODEV:
713 default:
714 td->ctrl |= TD_CTRL_TIMEOUT;
715 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
716 trace_usb_uhci_packet_complete_error(queue_token, td_addr);
717 ret = TD_RESULT_NEXT_QH;
718 break;
719 }
720
721 td->ctrl &= ~TD_CTRL_ACTIVE;
722 s->status |= UHCI_STS_USBERR;
723 if (td->ctrl & TD_CTRL_IOC) {
724 *int_mask |= 0x01;
725 }
726 uhci_update_irq(s);
727 return ret;
728 }
729
730 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
731 {
732 int len = 0, max_len;
733 uint8_t pid;
734
735 max_len = ((td->token >> 21) + 1) & 0x7ff;
736 pid = td->token & 0xff;
737
738 if (td->ctrl & TD_CTRL_IOS)
739 td->ctrl &= ~TD_CTRL_ACTIVE;
740
741 if (async->packet.status != USB_RET_SUCCESS) {
742 return uhci_handle_td_error(s, td, async->td_addr,
743 async->packet.status, int_mask);
744 }
745
746 len = async->packet.actual_length;
747 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
748
749 /* The NAK bit may have been set by a previous frame, so clear it
750 here. The docs are somewhat unclear, but win2k relies on this
751 behavior. */
752 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
753 if (td->ctrl & TD_CTRL_IOC)
754 *int_mask |= 0x01;
755
756 if (pid == USB_TOKEN_IN) {
757 pci_dma_write(&s->dev, td->buffer, async->buf, len);
758 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
759 *int_mask |= 0x02;
760 /* short packet: do not update QH */
761 trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
762 async->td_addr);
763 return TD_RESULT_NEXT_QH;
764 }
765 }
766
767 /* success */
768 trace_usb_uhci_packet_complete_success(async->queue->token,
769 async->td_addr);
770 return TD_RESULT_COMPLETE;
771 }
772
773 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
774 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
775 {
776 int ret, max_len;
777 bool spd;
778 bool queuing = (q != NULL);
779 uint8_t pid = td->token & 0xff;
780 UHCIAsync *async;
781
782 async = uhci_async_find_td(s, td_addr);
783 if (async) {
784 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
785 assert(q == NULL || q == async->queue);
786 q = async->queue;
787 } else {
788 uhci_queue_free(async->queue, "guest re-used pending td");
789 async = NULL;
790 }
791 }
792
793 if (q == NULL) {
794 q = uhci_queue_find(s, td);
795 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
796 uhci_queue_free(q, "guest re-used qh");
797 q = NULL;
798 }
799 }
800
801 if (q) {
802 q->valid = QH_VALID;
803 }
804
805 /* Is active ? */
806 if (!(td->ctrl & TD_CTRL_ACTIVE)) {
807 if (async) {
808 /* Guest marked a pending td non-active, cancel the queue */
809 uhci_queue_free(async->queue, "pending td non-active");
810 }
811 /*
812 * ehci11d spec page 22: "Even if the Active bit in the TD is already
813 * cleared when the TD is fetched ... an IOC interrupt is generated"
814 */
815 if (td->ctrl & TD_CTRL_IOC) {
816 *int_mask |= 0x01;
817 }
818 return TD_RESULT_NEXT_QH;
819 }
820
821 switch (pid) {
822 case USB_TOKEN_OUT:
823 case USB_TOKEN_SETUP:
824 case USB_TOKEN_IN:
825 break;
826 default:
827 /* invalid pid : frame interrupted */
828 s->status |= UHCI_STS_HCPERR;
829 s->cmd &= ~UHCI_CMD_RS;
830 uhci_update_irq(s);
831 return TD_RESULT_STOP_FRAME;
832 }
833
834 if (async) {
835 if (queuing) {
836 /* we are busy filling the queue, we are not prepared
837 to consume completed packages then, just leave them
838 in async state */
839 return TD_RESULT_ASYNC_CONT;
840 }
841 if (!async->done) {
842 UHCI_TD last_td;
843 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs);
844 /*
845 * While we are waiting for the current td to complete, the guest
846 * may have added more tds to the queue. Note we re-read the td
847 * rather then caching it, as we want to see guest made changes!
848 */
849 uhci_read_td(s, &last_td, last->td_addr);
850 uhci_queue_fill(async->queue, &last_td);
851
852 return TD_RESULT_ASYNC_CONT;
853 }
854 uhci_async_unlink(async);
855 goto done;
856 }
857
858 if (s->completions_only) {
859 return TD_RESULT_ASYNC_CONT;
860 }
861
862 /* Allocate new packet */
863 if (q == NULL) {
864 USBDevice *dev;
865 USBEndpoint *ep;
866
867 dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
868 if (dev == NULL) {
869 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV,
870 int_mask);
871 }
872 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
873 q = uhci_queue_new(s, qh_addr, td, ep);
874 }
875 async = uhci_async_alloc(q, td_addr);
876
877 max_len = ((td->token >> 21) + 1) & 0x7ff;
878 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
879 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd,
880 (td->ctrl & TD_CTRL_IOC) != 0);
881 if (max_len <= sizeof(async->static_buf)) {
882 async->buf = async->static_buf;
883 } else {
884 async->buf = g_malloc(max_len);
885 }
886 usb_packet_addbuf(&async->packet, async->buf, max_len);
887
888 switch(pid) {
889 case USB_TOKEN_OUT:
890 case USB_TOKEN_SETUP:
891 pci_dma_read(&s->dev, td->buffer, async->buf, max_len);
892 usb_handle_packet(q->ep->dev, &async->packet);
893 if (async->packet.status == USB_RET_SUCCESS) {
894 async->packet.actual_length = max_len;
895 }
896 break;
897
898 case USB_TOKEN_IN:
899 usb_handle_packet(q->ep->dev, &async->packet);
900 break;
901
902 default:
903 abort(); /* Never to execute */
904 }
905
906 if (async->packet.status == USB_RET_ASYNC) {
907 uhci_async_link(async);
908 if (!queuing) {
909 uhci_queue_fill(q, td);
910 }
911 return TD_RESULT_ASYNC_START;
912 }
913
914 done:
915 ret = uhci_complete_td(s, td, async, int_mask);
916 uhci_async_free(async);
917 return ret;
918 }
919
920 static void uhci_async_complete(USBPort *port, USBPacket *packet)
921 {
922 UHCIAsync *async = container_of(packet, UHCIAsync, packet);
923 UHCIState *s = async->queue->uhci;
924
925 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
926 uhci_async_cancel(async);
927 return;
928 }
929
930 async->done = 1;
931 /* Force processing of this packet *now*, needed for migration */
932 s->completions_only = true;
933 qemu_bh_schedule(s->bh);
934 }
935
936 static int is_valid(uint32_t link)
937 {
938 return (link & 1) == 0;
939 }
940
941 static int is_qh(uint32_t link)
942 {
943 return (link & 2) != 0;
944 }
945
946 static int depth_first(uint32_t link)
947 {
948 return (link & 4) != 0;
949 }
950
951 /* QH DB used for detecting QH loops */
952 #define UHCI_MAX_QUEUES 128
953 typedef struct {
954 uint32_t addr[UHCI_MAX_QUEUES];
955 int count;
956 } QhDb;
957
958 static void qhdb_reset(QhDb *db)
959 {
960 db->count = 0;
961 }
962
963 /* Add QH to DB. Returns 1 if already present or DB is full. */
964 static int qhdb_insert(QhDb *db, uint32_t addr)
965 {
966 int i;
967 for (i = 0; i < db->count; i++)
968 if (db->addr[i] == addr)
969 return 1;
970
971 if (db->count >= UHCI_MAX_QUEUES)
972 return 1;
973
974 db->addr[db->count++] = addr;
975 return 0;
976 }
977
978 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
979 {
980 uint32_t int_mask = 0;
981 uint32_t plink = td->link;
982 UHCI_TD ptd;
983 int ret;
984
985 while (is_valid(plink)) {
986 uhci_read_td(q->uhci, &ptd, plink);
987 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
988 break;
989 }
990 if (uhci_queue_token(&ptd) != q->token) {
991 break;
992 }
993 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
994 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
995 if (ret == TD_RESULT_ASYNC_CONT) {
996 break;
997 }
998 assert(ret == TD_RESULT_ASYNC_START);
999 assert(int_mask == 0);
1000 plink = ptd.link;
1001 }
1002 usb_device_flush_ep_queue(q->ep->dev, q->ep);
1003 }
1004
1005 static void uhci_process_frame(UHCIState *s)
1006 {
1007 uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
1008 uint32_t curr_qh, td_count = 0;
1009 int cnt, ret;
1010 UHCI_TD td;
1011 UHCI_QH qh;
1012 QhDb qhdb;
1013
1014 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
1015
1016 pci_dma_read(&s->dev, frame_addr, &link, 4);
1017 le32_to_cpus(&link);
1018
1019 int_mask = 0;
1020 curr_qh = 0;
1021
1022 qhdb_reset(&qhdb);
1023
1024 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1025 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) {
1026 /* We've reached the usb 1.1 bandwidth, which is
1027 1280 bytes/frame, stop processing */
1028 trace_usb_uhci_frame_stop_bandwidth();
1029 break;
1030 }
1031 if (is_qh(link)) {
1032 /* QH */
1033 trace_usb_uhci_qh_load(link & ~0xf);
1034
1035 if (qhdb_insert(&qhdb, link)) {
1036 /*
1037 * We're going in circles. Which is not a bug because
1038 * HCD is allowed to do that as part of the BW management.
1039 *
1040 * Stop processing here if no transaction has been done
1041 * since we've been here last time.
1042 */
1043 if (td_count == 0) {
1044 trace_usb_uhci_frame_loop_stop_idle();
1045 break;
1046 } else {
1047 trace_usb_uhci_frame_loop_continue();
1048 td_count = 0;
1049 qhdb_reset(&qhdb);
1050 qhdb_insert(&qhdb, link);
1051 }
1052 }
1053
1054 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1055 le32_to_cpus(&qh.link);
1056 le32_to_cpus(&qh.el_link);
1057
1058 if (!is_valid(qh.el_link)) {
1059 /* QH w/o elements */
1060 curr_qh = 0;
1061 link = qh.link;
1062 } else {
1063 /* QH with elements */
1064 curr_qh = link;
1065 link = qh.el_link;
1066 }
1067 continue;
1068 }
1069
1070 /* TD */
1071 uhci_read_td(s, &td, link);
1072 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1073
1074 old_td_ctrl = td.ctrl;
1075 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
1076 if (old_td_ctrl != td.ctrl) {
1077 /* update the status bits of the TD */
1078 val = cpu_to_le32(td.ctrl);
1079 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1080 }
1081
1082 switch (ret) {
1083 case TD_RESULT_STOP_FRAME: /* interrupted frame */
1084 goto out;
1085
1086 case TD_RESULT_NEXT_QH:
1087 case TD_RESULT_ASYNC_CONT:
1088 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1089 link = curr_qh ? qh.link : td.link;
1090 continue;
1091
1092 case TD_RESULT_ASYNC_START:
1093 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1094 link = curr_qh ? qh.link : td.link;
1095 continue;
1096
1097 case TD_RESULT_COMPLETE:
1098 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1099 link = td.link;
1100 td_count++;
1101 s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1102
1103 if (curr_qh) {
1104 /* update QH element link */
1105 qh.el_link = link;
1106 val = cpu_to_le32(qh.el_link);
1107 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1108
1109 if (!depth_first(link)) {
1110 /* done with this QH */
1111 curr_qh = 0;
1112 link = qh.link;
1113 }
1114 }
1115 break;
1116
1117 default:
1118 assert(!"unknown return code");
1119 }
1120
1121 /* go to the next entry */
1122 }
1123
1124 out:
1125 s->pending_int_mask |= int_mask;
1126 }
1127
1128 static void uhci_bh(void *opaque)
1129 {
1130 UHCIState *s = opaque;
1131 uhci_process_frame(s);
1132 }
1133
1134 static void uhci_frame_timer(void *opaque)
1135 {
1136 UHCIState *s = opaque;
1137 uint64_t t_now, t_last_run;
1138 int i, frames;
1139 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ;
1140
1141 s->completions_only = false;
1142 qemu_bh_cancel(s->bh);
1143
1144 if (!(s->cmd & UHCI_CMD_RS)) {
1145 /* Full stop */
1146 trace_usb_uhci_schedule_stop();
1147 timer_del(s->frame_timer);
1148 uhci_async_cancel_all(s);
1149 /* set hchalted bit in status - UHCI11D 2.1.2 */
1150 s->status |= UHCI_STS_HCHALTED;
1151 return;
1152 }
1153
1154 /* We still store expire_time in our state, for migration */
1155 t_last_run = s->expire_time - frame_t;
1156 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1157
1158 /* Process up to MAX_FRAMES_PER_TICK frames */
1159 frames = (t_now - t_last_run) / frame_t;
1160 if (frames > s->maxframes) {
1161 int skipped = frames - s->maxframes;
1162 s->expire_time += skipped * frame_t;
1163 s->frnum = (s->frnum + skipped) & 0x7ff;
1164 frames -= skipped;
1165 }
1166 if (frames > MAX_FRAMES_PER_TICK) {
1167 frames = MAX_FRAMES_PER_TICK;
1168 }
1169
1170 for (i = 0; i < frames; i++) {
1171 s->frame_bytes = 0;
1172 trace_usb_uhci_frame_start(s->frnum);
1173 uhci_async_validate_begin(s);
1174 uhci_process_frame(s);
1175 uhci_async_validate_end(s);
1176 /* The spec says frnum is the frame currently being processed, and
1177 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1178 s->frnum = (s->frnum + 1) & 0x7ff;
1179 s->expire_time += frame_t;
1180 }
1181
1182 /* Complete the previous frame(s) */
1183 if (s->pending_int_mask) {
1184 s->status2 |= s->pending_int_mask;
1185 s->status |= UHCI_STS_USBINT;
1186 uhci_update_irq(s);
1187 }
1188 s->pending_int_mask = 0;
1189
1190 timer_mod(s->frame_timer, t_now + frame_t);
1191 }
1192
1193 static const MemoryRegionOps uhci_ioport_ops = {
1194 .read = uhci_port_read,
1195 .write = uhci_port_write,
1196 .valid.min_access_size = 1,
1197 .valid.max_access_size = 4,
1198 .impl.min_access_size = 2,
1199 .impl.max_access_size = 2,
1200 .endianness = DEVICE_LITTLE_ENDIAN,
1201 };
1202
1203 static USBPortOps uhci_port_ops = {
1204 .attach = uhci_attach,
1205 .detach = uhci_detach,
1206 .child_detach = uhci_child_detach,
1207 .wakeup = uhci_wakeup,
1208 .complete = uhci_async_complete,
1209 };
1210
1211 static USBBusOps uhci_bus_ops = {
1212 };
1213
1214 static void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
1215 {
1216 Error *err = NULL;
1217 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1218 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
1219 UHCIState *s = UHCI(dev);
1220 uint8_t *pci_conf = s->dev.config;
1221 int i;
1222
1223 pci_conf[PCI_CLASS_PROG] = 0x00;
1224 /* TODO: reset value should be 0. */
1225 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1226
1227 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
1228
1229 if (s->masterbus) {
1230 USBPort *ports[NB_PORTS];
1231 for(i = 0; i < NB_PORTS; i++) {
1232 ports[i] = &s->ports[i].port;
1233 }
1234 usb_register_companion(s->masterbus, ports, NB_PORTS,
1235 s->firstport, s, &uhci_port_ops,
1236 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1237 &err);
1238 if (err) {
1239 error_propagate(errp, err);
1240 return;
1241 }
1242 } else {
1243 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev));
1244 for (i = 0; i < NB_PORTS; i++) {
1245 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1246 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1247 }
1248 }
1249 s->bh = qemu_bh_new(uhci_bh, s);
1250 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s);
1251 s->num_ports_vmstate = NB_PORTS;
1252 QTAILQ_INIT(&s->queues);
1253
1254 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,
1255 "uhci", 0x20);
1256
1257 /* Use region 4 for consistency with real hardware. BSD guests seem
1258 to rely on this. */
1259 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1260 }
1261
1262 static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
1263 {
1264 UHCIState *s = UHCI(dev);
1265 uint8_t *pci_conf = s->dev.config;
1266
1267 /* USB misc control 1/2 */
1268 pci_set_long(pci_conf + 0x40,0x00001000);
1269 /* PM capability */
1270 pci_set_long(pci_conf + 0x80,0x00020001);
1271 /* USB legacy support */
1272 pci_set_long(pci_conf + 0xc0,0x00002000);
1273
1274 usb_uhci_common_realize(dev, errp);
1275 }
1276
1277 static void usb_uhci_exit(PCIDevice *dev)
1278 {
1279 UHCIState *s = UHCI(dev);
1280
1281 trace_usb_uhci_exit();
1282
1283 if (s->frame_timer) {
1284 timer_del(s->frame_timer);
1285 timer_free(s->frame_timer);
1286 s->frame_timer = NULL;
1287 }
1288
1289 if (s->bh) {
1290 qemu_bh_delete(s->bh);
1291 }
1292
1293 uhci_async_cancel_all(s);
1294
1295 if (!s->masterbus) {
1296 usb_bus_release(&s->bus);
1297 }
1298 }
1299
1300 static Property uhci_properties_companion[] = {
1301 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1302 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1303 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1304 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1305 DEFINE_PROP_END_OF_LIST(),
1306 };
1307 static Property uhci_properties_standalone[] = {
1308 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1309 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1310 DEFINE_PROP_END_OF_LIST(),
1311 };
1312
1313 static void uhci_class_init(ObjectClass *klass, void *data)
1314 {
1315 DeviceClass *dc = DEVICE_CLASS(klass);
1316 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1317
1318 k->class_id = PCI_CLASS_SERIAL_USB;
1319 dc->vmsd = &vmstate_uhci;
1320 dc->reset = uhci_reset;
1321 set_bit(DEVICE_CATEGORY_USB, dc->categories);
1322 }
1323
1324 static const TypeInfo uhci_pci_type_info = {
1325 .name = TYPE_UHCI,
1326 .parent = TYPE_PCI_DEVICE,
1327 .instance_size = sizeof(UHCIState),
1328 .class_size = sizeof(UHCIPCIDeviceClass),
1329 .abstract = true,
1330 .class_init = uhci_class_init,
1331 .interfaces = (InterfaceInfo[]) {
1332 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1333 { },
1334 },
1335 };
1336
1337 static void uhci_data_class_init(ObjectClass *klass, void *data)
1338 {
1339 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1340 DeviceClass *dc = DEVICE_CLASS(klass);
1341 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
1342 UHCIInfo *info = data;
1343
1344 k->realize = info->realize ? info->realize : usb_uhci_common_realize;
1345 k->exit = info->unplug ? usb_uhci_exit : NULL;
1346 k->vendor_id = info->vendor_id;
1347 k->device_id = info->device_id;
1348 k->revision = info->revision;
1349 if (!info->unplug) {
1350 /* uhci controllers in companion setups can't be hotplugged */
1351 dc->hotpluggable = false;
1352 device_class_set_props(dc, uhci_properties_companion);
1353 } else {
1354 device_class_set_props(dc, uhci_properties_standalone);
1355 }
1356 u->info = *info;
1357 }
1358
1359 static UHCIInfo uhci_info[] = {
1360 {
1361 .name = "piix3-usb-uhci",
1362 .vendor_id = PCI_VENDOR_ID_INTEL,
1363 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
1364 .revision = 0x01,
1365 .irq_pin = 3,
1366 .unplug = true,
1367 },{
1368 .name = "piix4-usb-uhci",
1369 .vendor_id = PCI_VENDOR_ID_INTEL,
1370 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
1371 .revision = 0x01,
1372 .irq_pin = 3,
1373 .unplug = true,
1374 },{
1375 .name = "vt82c686b-usb-uhci",
1376 .vendor_id = PCI_VENDOR_ID_VIA,
1377 .device_id = PCI_DEVICE_ID_VIA_UHCI,
1378 .revision = 0x01,
1379 .irq_pin = 3,
1380 .realize = usb_uhci_vt82c686b_realize,
1381 .unplug = true,
1382 },{
1383 .name = "ich9-usb-uhci1", /* 00:1d.0 */
1384 .vendor_id = PCI_VENDOR_ID_INTEL,
1385 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
1386 .revision = 0x03,
1387 .irq_pin = 0,
1388 .unplug = false,
1389 },{
1390 .name = "ich9-usb-uhci2", /* 00:1d.1 */
1391 .vendor_id = PCI_VENDOR_ID_INTEL,
1392 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
1393 .revision = 0x03,
1394 .irq_pin = 1,
1395 .unplug = false,
1396 },{
1397 .name = "ich9-usb-uhci3", /* 00:1d.2 */
1398 .vendor_id = PCI_VENDOR_ID_INTEL,
1399 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
1400 .revision = 0x03,
1401 .irq_pin = 2,
1402 .unplug = false,
1403 },{
1404 .name = "ich9-usb-uhci4", /* 00:1a.0 */
1405 .vendor_id = PCI_VENDOR_ID_INTEL,
1406 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
1407 .revision = 0x03,
1408 .irq_pin = 0,
1409 .unplug = false,
1410 },{
1411 .name = "ich9-usb-uhci5", /* 00:1a.1 */
1412 .vendor_id = PCI_VENDOR_ID_INTEL,
1413 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
1414 .revision = 0x03,
1415 .irq_pin = 1,
1416 .unplug = false,
1417 },{
1418 .name = "ich9-usb-uhci6", /* 00:1a.2 */
1419 .vendor_id = PCI_VENDOR_ID_INTEL,
1420 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
1421 .revision = 0x03,
1422 .irq_pin = 2,
1423 .unplug = false,
1424 }
1425 };
1426
1427 static void uhci_register_types(void)
1428 {
1429 TypeInfo uhci_type_info = {
1430 .parent = TYPE_UHCI,
1431 .class_init = uhci_data_class_init,
1432 };
1433 int i;
1434
1435 type_register_static(&uhci_pci_type_info);
1436
1437 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
1438 uhci_type_info.name = uhci_info[i].name;
1439 uhci_type_info.class_data = uhci_info + i;
1440 type_register(&uhci_type_info);
1441 }
1442 }
1443
1444 type_init(uhci_register_types)
QEmu