4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
29 #include "translate.h"
30 #include "internals.h"
31 #include "qemu/host-utils.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X
[32];
41 static TCGv_i64 cpu_pc
;
43 /* Load/store exclusive handling */
44 static TCGv_i64 cpu_exclusive_high
;
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
109 switch (s
->mmu_idx
) {
110 case ARMMMUIdx_S12NSE1
:
111 return ARMMMUIdx_S12NSE0
;
112 case ARMMMUIdx_S1SE1
:
113 return ARMMMUIdx_S1SE0
;
115 g_assert_not_reached();
121 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
122 fprintf_function cpu_fprintf
, int flags
)
124 ARMCPU
*cpu
= ARM_CPU(cs
);
125 CPUARMState
*env
= &cpu
->env
;
126 uint32_t psr
= pstate_read(env
);
129 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
130 env
->pc
, env
->xregs
[31]);
131 for (i
= 0; i
< 31; i
++) {
132 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
134 cpu_fprintf(f
, "\n");
139 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
141 psr
& PSTATE_N
? 'N' : '-',
142 psr
& PSTATE_Z
? 'Z' : '-',
143 psr
& PSTATE_C
? 'C' : '-',
144 psr
& PSTATE_V
? 'V' : '-');
145 cpu_fprintf(f
, "\n");
147 if (flags
& CPU_DUMP_FPU
) {
149 for (i
= 0; i
< numvfpregs
; i
+= 2) {
150 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
151 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
152 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
154 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
155 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
156 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
159 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
160 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
164 void gen_a64_set_pc_im(uint64_t val
)
166 tcg_gen_movi_i64(cpu_pc
, val
);
169 static void gen_exception_internal(int excp
)
171 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
173 assert(excp_is_internal(excp
));
174 gen_helper_exception_internal(cpu_env
, tcg_excp
);
175 tcg_temp_free_i32(tcg_excp
);
178 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
180 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
181 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
182 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
184 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
186 tcg_temp_free_i32(tcg_el
);
187 tcg_temp_free_i32(tcg_syn
);
188 tcg_temp_free_i32(tcg_excp
);
191 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
193 gen_a64_set_pc_im(s
->pc
- offset
);
194 gen_exception_internal(excp
);
195 s
->is_jmp
= DISAS_EXC
;
198 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
199 uint32_t syndrome
, uint32_t target_el
)
201 gen_a64_set_pc_im(s
->pc
- offset
);
202 gen_exception(excp
, syndrome
, target_el
);
203 s
->is_jmp
= DISAS_EXC
;
206 static void gen_ss_advance(DisasContext
*s
)
208 /* If the singlestep state is Active-not-pending, advance to
213 gen_helper_clear_pstate_ss(cpu_env
);
217 static void gen_step_complete_exception(DisasContext
*s
)
219 /* We just completed step of an insn. Move from Active-not-pending
220 * to Active-pending, and then also take the swstep exception.
221 * This corresponds to making the (IMPDEF) choice to prioritize
222 * swstep exceptions over asynchronous exceptions taken to an exception
223 * level where debug is disabled. This choice has the advantage that
224 * we do not need to maintain internal state corresponding to the
225 * ISV/EX syndrome bits between completion of the step and generation
226 * of the exception, and our syndrome information is always correct.
229 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
230 default_exception_el(s
));
231 s
->is_jmp
= DISAS_EXC
;
234 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
236 /* No direct tb linking with singlestep (either QEMU's or the ARM
237 * debug architecture kind) or deterministic io
239 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
243 /* Only link tbs from inside the same guest page */
244 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
251 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
253 TranslationBlock
*tb
;
256 if (use_goto_tb(s
, n
, dest
)) {
258 gen_a64_set_pc_im(dest
);
259 tcg_gen_exit_tb((intptr_t)tb
+ n
);
260 s
->is_jmp
= DISAS_TB_JUMP
;
262 gen_a64_set_pc_im(dest
);
264 gen_step_complete_exception(s
);
265 } else if (s
->singlestep_enabled
) {
266 gen_exception_internal(EXCP_DEBUG
);
269 s
->is_jmp
= DISAS_TB_JUMP
;
274 static void unallocated_encoding(DisasContext
*s
)
276 /* Unallocated and reserved encodings are uncategorized */
277 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
278 default_exception_el(s
));
281 #define unsupported_encoding(s, insn) \
283 qemu_log_mask(LOG_UNIMP, \
284 "%s:%d: unsupported instruction encoding 0x%08x " \
285 "at pc=%016" PRIx64 "\n", \
286 __FILE__, __LINE__, insn, s->pc - 4); \
287 unallocated_encoding(s); \
290 static void init_tmp_a64_array(DisasContext
*s
)
292 #ifdef CONFIG_DEBUG_TCG
294 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
295 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
298 s
->tmp_a64_count
= 0;
301 static void free_tmp_a64(DisasContext
*s
)
304 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
305 tcg_temp_free_i64(s
->tmp_a64
[i
]);
307 init_tmp_a64_array(s
);
310 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
312 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
313 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
316 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
318 TCGv_i64 t
= new_tmp_a64(s
);
319 tcg_gen_movi_i64(t
, 0);
324 * Register access functions
326 * These functions are used for directly accessing a register in where
327 * changes to the final register value are likely to be made. If you
328 * need to use a register for temporary calculation (e.g. index type
329 * operations) use the read_* form.
331 * B1.2.1 Register mappings
333 * In instruction register encoding 31 can refer to ZR (zero register) or
334 * the SP (stack pointer) depending on context. In QEMU's case we map SP
335 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
336 * This is the point of the _sp forms.
338 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
341 return new_tmp_a64_zero(s
);
347 /* register access for when 31 == SP */
348 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
353 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
354 * representing the register contents. This TCGv is an auto-freed
355 * temporary so it need not be explicitly freed, and may be modified.
357 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
359 TCGv_i64 v
= new_tmp_a64(s
);
362 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
364 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
367 tcg_gen_movi_i64(v
, 0);
372 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
374 TCGv_i64 v
= new_tmp_a64(s
);
376 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
378 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
383 /* We should have at some point before trying to access an FP register
384 * done the necessary access check, so assert that
385 * (a) we did the check and
386 * (b) we didn't then just plough ahead anyway if it failed.
387 * Print the instruction pattern in the abort message so we can figure
388 * out what we need to fix if a user encounters this problem in the wild.
390 static inline void assert_fp_access_checked(DisasContext
*s
)
392 #ifdef CONFIG_DEBUG_TCG
393 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
394 fprintf(stderr
, "target-arm: FP access check missing for "
395 "instruction 0x%08x\n", s
->insn
);
401 /* Return the offset into CPUARMState of an element of specified
402 * size, 'element' places in from the least significant end of
403 * the FP/vector register Qn.
405 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
406 int element
, TCGMemOp size
)
408 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
409 #ifdef HOST_WORDS_BIGENDIAN
410 /* This is complicated slightly because vfp.regs[2n] is
411 * still the low half and vfp.regs[2n+1] the high half
412 * of the 128 bit vector, even on big endian systems.
413 * Calculate the offset assuming a fully bigendian 128 bits,
414 * then XOR to account for the order of the two 64 bit halves.
416 offs
+= (16 - ((element
+ 1) * (1 << size
)));
419 offs
+= element
* (1 << size
);
421 assert_fp_access_checked(s
);
425 /* Return the offset into CPUARMState of a slice (from
426 * the least significant end) of FP register Qn (ie
428 * (Note that this is not the same mapping as for A32; see cpu.h)
430 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
432 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
433 #ifdef HOST_WORDS_BIGENDIAN
434 offs
+= (8 - (1 << size
));
436 assert_fp_access_checked(s
);
440 /* Offset of the high half of the 128 bit vector Qn */
441 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
443 assert_fp_access_checked(s
);
444 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
447 /* Convenience accessors for reading and writing single and double
448 * FP registers. Writing clears the upper parts of the associated
449 * 128 bit vector register, as required by the architecture.
450 * Note that unlike the GP register accessors, the values returned
451 * by the read functions must be manually freed.
453 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
455 TCGv_i64 v
= tcg_temp_new_i64();
457 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
461 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
463 TCGv_i32 v
= tcg_temp_new_i32();
465 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
469 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
471 TCGv_i64 tcg_zero
= tcg_const_i64(0);
473 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
474 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
475 tcg_temp_free_i64(tcg_zero
);
478 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
480 TCGv_i64 tmp
= tcg_temp_new_i64();
482 tcg_gen_extu_i32_i64(tmp
, v
);
483 write_fp_dreg(s
, reg
, tmp
);
484 tcg_temp_free_i64(tmp
);
487 static TCGv_ptr
get_fpstatus_ptr(void)
489 TCGv_ptr statusptr
= tcg_temp_new_ptr();
492 /* In A64 all instructions (both FP and Neon) use the FPCR;
493 * there is no equivalent of the A32 Neon "standard FPSCR value"
494 * and all operations use vfp.fp_status.
496 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
497 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
501 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
502 * than the 32 bit equivalent.
504 static inline void gen_set_NZ64(TCGv_i64 result
)
506 TCGv_i64 flag
= tcg_temp_new_i64();
508 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
509 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
510 tcg_gen_shri_i64(flag
, result
, 32);
511 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
512 tcg_temp_free_i64(flag
);
515 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
516 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
519 gen_set_NZ64(result
);
521 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
522 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
524 tcg_gen_movi_i32(cpu_CF
, 0);
525 tcg_gen_movi_i32(cpu_VF
, 0);
528 /* dest = T0 + T1; compute C, N, V and Z flags */
529 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
532 TCGv_i64 result
, flag
, tmp
;
533 result
= tcg_temp_new_i64();
534 flag
= tcg_temp_new_i64();
535 tmp
= tcg_temp_new_i64();
537 tcg_gen_movi_i64(tmp
, 0);
538 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
540 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
542 gen_set_NZ64(result
);
544 tcg_gen_xor_i64(flag
, result
, t0
);
545 tcg_gen_xor_i64(tmp
, t0
, t1
);
546 tcg_gen_andc_i64(flag
, flag
, tmp
);
547 tcg_temp_free_i64(tmp
);
548 tcg_gen_shri_i64(flag
, flag
, 32);
549 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
551 tcg_gen_mov_i64(dest
, result
);
552 tcg_temp_free_i64(result
);
553 tcg_temp_free_i64(flag
);
555 /* 32 bit arithmetic */
556 TCGv_i32 t0_32
= tcg_temp_new_i32();
557 TCGv_i32 t1_32
= tcg_temp_new_i32();
558 TCGv_i32 tmp
= tcg_temp_new_i32();
560 tcg_gen_movi_i32(tmp
, 0);
561 tcg_gen_trunc_i64_i32(t0_32
, t0
);
562 tcg_gen_trunc_i64_i32(t1_32
, t1
);
563 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
564 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
565 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
566 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
567 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
568 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
570 tcg_temp_free_i32(tmp
);
571 tcg_temp_free_i32(t0_32
);
572 tcg_temp_free_i32(t1_32
);
576 /* dest = T0 - T1; compute C, N, V and Z flags */
577 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
580 /* 64 bit arithmetic */
581 TCGv_i64 result
, flag
, tmp
;
583 result
= tcg_temp_new_i64();
584 flag
= tcg_temp_new_i64();
585 tcg_gen_sub_i64(result
, t0
, t1
);
587 gen_set_NZ64(result
);
589 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
590 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
592 tcg_gen_xor_i64(flag
, result
, t0
);
593 tmp
= tcg_temp_new_i64();
594 tcg_gen_xor_i64(tmp
, t0
, t1
);
595 tcg_gen_and_i64(flag
, flag
, tmp
);
596 tcg_temp_free_i64(tmp
);
597 tcg_gen_shri_i64(flag
, flag
, 32);
598 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
599 tcg_gen_mov_i64(dest
, result
);
600 tcg_temp_free_i64(flag
);
601 tcg_temp_free_i64(result
);
603 /* 32 bit arithmetic */
604 TCGv_i32 t0_32
= tcg_temp_new_i32();
605 TCGv_i32 t1_32
= tcg_temp_new_i32();
608 tcg_gen_trunc_i64_i32(t0_32
, t0
);
609 tcg_gen_trunc_i64_i32(t1_32
, t1
);
610 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
611 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
612 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
613 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
614 tmp
= tcg_temp_new_i32();
615 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
616 tcg_temp_free_i32(t0_32
);
617 tcg_temp_free_i32(t1_32
);
618 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
619 tcg_temp_free_i32(tmp
);
620 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
624 /* dest = T0 + T1 + CF; do not compute flags. */
625 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
627 TCGv_i64 flag
= tcg_temp_new_i64();
628 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
629 tcg_gen_add_i64(dest
, t0
, t1
);
630 tcg_gen_add_i64(dest
, dest
, flag
);
631 tcg_temp_free_i64(flag
);
634 tcg_gen_ext32u_i64(dest
, dest
);
638 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
639 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
642 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
643 result
= tcg_temp_new_i64();
644 cf_64
= tcg_temp_new_i64();
645 vf_64
= tcg_temp_new_i64();
646 tmp
= tcg_const_i64(0);
648 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
649 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
650 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
651 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
652 gen_set_NZ64(result
);
654 tcg_gen_xor_i64(vf_64
, result
, t0
);
655 tcg_gen_xor_i64(tmp
, t0
, t1
);
656 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
657 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
658 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
660 tcg_gen_mov_i64(dest
, result
);
662 tcg_temp_free_i64(tmp
);
663 tcg_temp_free_i64(vf_64
);
664 tcg_temp_free_i64(cf_64
);
665 tcg_temp_free_i64(result
);
667 TCGv_i32 t0_32
, t1_32
, tmp
;
668 t0_32
= tcg_temp_new_i32();
669 t1_32
= tcg_temp_new_i32();
670 tmp
= tcg_const_i32(0);
672 tcg_gen_trunc_i64_i32(t0_32
, t0
);
673 tcg_gen_trunc_i64_i32(t1_32
, t1
);
674 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
675 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
677 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
678 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
679 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
680 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
681 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
683 tcg_temp_free_i32(tmp
);
684 tcg_temp_free_i32(t1_32
);
685 tcg_temp_free_i32(t0_32
);
690 * Load/Store generators
694 * Store from GPR register to memory.
696 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
697 TCGv_i64 tcg_addr
, int size
, int memidx
)
700 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
703 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
704 TCGv_i64 tcg_addr
, int size
)
706 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
710 * Load from memory to GPR register
712 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
713 int size
, bool is_signed
, bool extend
, int memidx
)
715 TCGMemOp memop
= MO_TE
+ size
;
723 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
725 if (extend
&& is_signed
) {
727 tcg_gen_ext32u_i64(dest
, dest
);
731 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
732 int size
, bool is_signed
, bool extend
)
734 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
739 * Store from FP register to memory
741 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
743 /* This writes the bottom N bits of a 128 bit wide vector to memory */
744 TCGv_i64 tmp
= tcg_temp_new_i64();
745 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
747 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
749 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
750 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
751 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
752 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
753 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
754 tcg_temp_free_i64(tcg_hiaddr
);
757 tcg_temp_free_i64(tmp
);
761 * Load from memory to FP register
763 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
765 /* This always zero-extends and writes to a full 128 bit wide vector */
766 TCGv_i64 tmplo
= tcg_temp_new_i64();
770 TCGMemOp memop
= MO_TE
+ size
;
771 tmphi
= tcg_const_i64(0);
772 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
775 tmphi
= tcg_temp_new_i64();
776 tcg_hiaddr
= tcg_temp_new_i64();
778 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
779 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
780 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
781 tcg_temp_free_i64(tcg_hiaddr
);
784 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
785 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
787 tcg_temp_free_i64(tmplo
);
788 tcg_temp_free_i64(tmphi
);
792 * Vector load/store helpers.
794 * The principal difference between this and a FP load is that we don't
795 * zero extend as we are filling a partial chunk of the vector register.
796 * These functions don't support 128 bit loads/stores, which would be
797 * normal load/store operations.
799 * The _i32 versions are useful when operating on 32 bit quantities
800 * (eg for floating point single or using Neon helper functions).
803 /* Get value of an element within a vector register */
804 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
805 int element
, TCGMemOp memop
)
807 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
810 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
813 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
816 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
819 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
822 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
825 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
829 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
832 g_assert_not_reached();
836 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
837 int element
, TCGMemOp memop
)
839 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
842 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
845 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
848 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
851 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
855 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
858 g_assert_not_reached();
862 /* Set value of an element within a vector register */
863 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
864 int element
, TCGMemOp memop
)
866 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
869 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
872 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
875 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
878 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
881 g_assert_not_reached();
885 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
886 int destidx
, int element
, TCGMemOp memop
)
888 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
891 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
894 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
897 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
900 g_assert_not_reached();
904 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
905 * vector ops all need to do this).
907 static void clear_vec_high(DisasContext
*s
, int rd
)
909 TCGv_i64 tcg_zero
= tcg_const_i64(0);
911 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
912 tcg_temp_free_i64(tcg_zero
);
915 /* Store from vector register to memory */
916 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
917 TCGv_i64 tcg_addr
, int size
)
919 TCGMemOp memop
= MO_TE
+ size
;
920 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
922 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
923 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
925 tcg_temp_free_i64(tcg_tmp
);
928 /* Load from memory to vector register */
929 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
930 TCGv_i64 tcg_addr
, int size
)
932 TCGMemOp memop
= MO_TE
+ size
;
933 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
935 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
936 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
938 tcg_temp_free_i64(tcg_tmp
);
941 /* Check that FP/Neon access is enabled. If it is, return
942 * true. If not, emit code to generate an appropriate exception,
943 * and return false; the caller should not emit any code for
944 * the instruction. Note that this check must happen after all
945 * unallocated-encoding checks (otherwise the syndrome information
946 * for the resulting exception will be incorrect).
948 static inline bool fp_access_check(DisasContext
*s
)
950 assert(!s
->fp_access_checked
);
951 s
->fp_access_checked
= true;
953 if (!s
->fp_excp_el
) {
957 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
963 * This utility function is for doing register extension with an
964 * optional shift. You will likely want to pass a temporary for the
965 * destination register. See DecodeRegExtend() in the ARM ARM.
967 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
968 int option
, unsigned int shift
)
970 int extsize
= extract32(option
, 0, 2);
971 bool is_signed
= extract32(option
, 2, 1);
976 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
979 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
982 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
985 tcg_gen_mov_i64(tcg_out
, tcg_in
);
991 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
994 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
997 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1000 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1006 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1010 static inline void gen_check_sp_alignment(DisasContext
*s
)
1012 /* The AArch64 architecture mandates that (if enabled via PSTATE
1013 * or SCTLR bits) there is a check that SP is 16-aligned on every
1014 * SP-relative load or store (with an exception generated if it is not).
1015 * In line with general QEMU practice regarding misaligned accesses,
1016 * we omit these checks for the sake of guest program performance.
1017 * This function is provided as a hook so we can more easily add these
1018 * checks in future (possibly as a "favour catching guest program bugs
1019 * over speed" user selectable option).
1024 * This provides a simple table based table lookup decoder. It is
1025 * intended to be used when the relevant bits for decode are too
1026 * awkwardly placed and switch/if based logic would be confusing and
1027 * deeply nested. Since it's a linear search through the table, tables
1028 * should be kept small.
1030 * It returns the first handler where insn & mask == pattern, or
1031 * NULL if there is no match.
1032 * The table is terminated by an empty mask (i.e. 0)
1034 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1037 const AArch64DecodeTable
*tptr
= table
;
1039 while (tptr
->mask
) {
1040 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1041 return tptr
->disas_fn
;
1049 * the instruction disassembly implemented here matches
1050 * the instruction encoding classifications in chapter 3 (C3)
1051 * of the ARM Architecture Reference Manual (DDI0487A_a)
1054 /* C3.2.7 Unconditional branch (immediate)
1056 * +----+-----------+-------------------------------------+
1057 * | op | 0 0 1 0 1 | imm26 |
1058 * +----+-----------+-------------------------------------+
1060 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1062 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1064 if (insn
& (1U << 31)) {
1065 /* C5.6.26 BL Branch with link */
1066 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1069 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1070 gen_goto_tb(s
, 0, addr
);
1073 /* C3.2.1 Compare & branch (immediate)
1074 * 31 30 25 24 23 5 4 0
1075 * +----+-------------+----+---------------------+--------+
1076 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1077 * +----+-------------+----+---------------------+--------+
1079 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1081 unsigned int sf
, op
, rt
;
1083 TCGLabel
*label_match
;
1086 sf
= extract32(insn
, 31, 1);
1087 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1088 rt
= extract32(insn
, 0, 5);
1089 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1091 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1092 label_match
= gen_new_label();
1094 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1095 tcg_cmp
, 0, label_match
);
1097 gen_goto_tb(s
, 0, s
->pc
);
1098 gen_set_label(label_match
);
1099 gen_goto_tb(s
, 1, addr
);
1102 /* C3.2.5 Test & branch (immediate)
1103 * 31 30 25 24 23 19 18 5 4 0
1104 * +----+-------------+----+-------+-------------+------+
1105 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1106 * +----+-------------+----+-------+-------------+------+
1108 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1110 unsigned int bit_pos
, op
, rt
;
1112 TCGLabel
*label_match
;
1115 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1116 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1117 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1118 rt
= extract32(insn
, 0, 5);
1120 tcg_cmp
= tcg_temp_new_i64();
1121 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1122 label_match
= gen_new_label();
1123 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1124 tcg_cmp
, 0, label_match
);
1125 tcg_temp_free_i64(tcg_cmp
);
1126 gen_goto_tb(s
, 0, s
->pc
);
1127 gen_set_label(label_match
);
1128 gen_goto_tb(s
, 1, addr
);
1131 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1132 * 31 25 24 23 5 4 3 0
1133 * +---------------+----+---------------------+----+------+
1134 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1135 * +---------------+----+---------------------+----+------+
1137 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1142 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1143 unallocated_encoding(s
);
1146 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1147 cond
= extract32(insn
, 0, 4);
1150 /* genuinely conditional branches */
1151 TCGLabel
*label_match
= gen_new_label();
1152 arm_gen_test_cc(cond
, label_match
);
1153 gen_goto_tb(s
, 0, s
->pc
);
1154 gen_set_label(label_match
);
1155 gen_goto_tb(s
, 1, addr
);
1157 /* 0xe and 0xf are both "always" conditions */
1158 gen_goto_tb(s
, 0, addr
);
1163 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1164 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1166 unsigned int selector
= crm
<< 3 | op2
;
1169 unallocated_encoding(s
);
1177 s
->is_jmp
= DISAS_WFI
;
1180 s
->is_jmp
= DISAS_YIELD
;
1183 s
->is_jmp
= DISAS_WFE
;
1187 /* we treat all as NOP at least for now */
1190 /* default specified as NOP equivalent */
1195 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1197 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1200 /* CLREX, DSB, DMB, ISB */
1201 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1202 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1205 unallocated_encoding(s
);
1216 /* We don't emulate caches so barriers are no-ops */
1219 unallocated_encoding(s
);
1224 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1225 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1226 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1228 int op
= op1
<< 3 | op2
;
1230 case 0x05: /* SPSel */
1231 if (s
->current_el
== 0) {
1232 unallocated_encoding(s
);
1236 case 0x1e: /* DAIFSet */
1237 case 0x1f: /* DAIFClear */
1239 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1240 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1241 gen_a64_set_pc_im(s
->pc
- 4);
1242 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1243 tcg_temp_free_i32(tcg_imm
);
1244 tcg_temp_free_i32(tcg_op
);
1245 s
->is_jmp
= DISAS_UPDATE
;
1249 unallocated_encoding(s
);
1254 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1256 TCGv_i32 tmp
= tcg_temp_new_i32();
1257 TCGv_i32 nzcv
= tcg_temp_new_i32();
1259 /* build bit 31, N */
1260 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1261 /* build bit 30, Z */
1262 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1263 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1264 /* build bit 29, C */
1265 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1266 /* build bit 28, V */
1267 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1268 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1269 /* generate result */
1270 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1272 tcg_temp_free_i32(nzcv
);
1273 tcg_temp_free_i32(tmp
);
1276 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1279 TCGv_i32 nzcv
= tcg_temp_new_i32();
1281 /* take NZCV from R[t] */
1282 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1285 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1287 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1288 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1290 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1291 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1293 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1294 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1295 tcg_temp_free_i32(nzcv
);
1298 /* C5.6.129 MRS - move from system register
1299 * C5.6.131 MSR (register) - move to system register
1302 * These are all essentially the same insn in 'read' and 'write'
1303 * versions, with varying op0 fields.
1305 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1306 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1307 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1309 const ARMCPRegInfo
*ri
;
1312 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1313 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1314 crn
, crm
, op0
, op1
, op2
));
1317 /* Unknown register; this might be a guest error or a QEMU
1318 * unimplemented feature.
1320 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1321 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1322 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1323 unallocated_encoding(s
);
1327 /* Check access permissions */
1328 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1329 unallocated_encoding(s
);
1334 /* Emit code to perform further access permissions checks at
1335 * runtime; this may result in an exception.
1341 gen_a64_set_pc_im(s
->pc
- 4);
1342 tmpptr
= tcg_const_ptr(ri
);
1343 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1344 tcg_syn
= tcg_const_i32(syndrome
);
1345 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
);
1346 tcg_temp_free_ptr(tmpptr
);
1347 tcg_temp_free_i32(tcg_syn
);
1350 /* Handle special cases first */
1351 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1355 tcg_rt
= cpu_reg(s
, rt
);
1357 gen_get_nzcv(tcg_rt
);
1359 gen_set_nzcv(tcg_rt
);
1362 case ARM_CP_CURRENTEL
:
1363 /* Reads as current EL value from pstate, which is
1364 * guaranteed to be constant by the tb flags.
1366 tcg_rt
= cpu_reg(s
, rt
);
1367 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1370 /* Writes clear the aligned block of memory which rt points into. */
1371 tcg_rt
= cpu_reg(s
, rt
);
1372 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1378 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1382 tcg_rt
= cpu_reg(s
, rt
);
1385 if (ri
->type
& ARM_CP_CONST
) {
1386 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1387 } else if (ri
->readfn
) {
1389 tmpptr
= tcg_const_ptr(ri
);
1390 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1391 tcg_temp_free_ptr(tmpptr
);
1393 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1396 if (ri
->type
& ARM_CP_CONST
) {
1397 /* If not forbidden by access permissions, treat as WI */
1399 } else if (ri
->writefn
) {
1401 tmpptr
= tcg_const_ptr(ri
);
1402 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1403 tcg_temp_free_ptr(tmpptr
);
1405 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1409 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1410 /* I/O operations must end the TB here (whether read or write) */
1412 s
->is_jmp
= DISAS_UPDATE
;
1413 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1414 /* We default to ending the TB on a coprocessor register write,
1415 * but allow this to be suppressed by the register definition
1416 * (usually only necessary to work around guest bugs).
1418 s
->is_jmp
= DISAS_UPDATE
;
1423 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1424 * +---------------------+---+-----+-----+-------+-------+-----+------+
1425 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1426 * +---------------------+---+-----+-----+-------+-------+-----+------+
1428 static void disas_system(DisasContext
*s
, uint32_t insn
)
1430 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1431 l
= extract32(insn
, 21, 1);
1432 op0
= extract32(insn
, 19, 2);
1433 op1
= extract32(insn
, 16, 3);
1434 crn
= extract32(insn
, 12, 4);
1435 crm
= extract32(insn
, 8, 4);
1436 op2
= extract32(insn
, 5, 3);
1437 rt
= extract32(insn
, 0, 5);
1440 if (l
|| rt
!= 31) {
1441 unallocated_encoding(s
);
1445 case 2: /* C5.6.68 HINT */
1446 handle_hint(s
, insn
, op1
, op2
, crm
);
1448 case 3: /* CLREX, DSB, DMB, ISB */
1449 handle_sync(s
, insn
, op1
, op2
, crm
);
1451 case 4: /* C5.6.130 MSR (immediate) */
1452 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1455 unallocated_encoding(s
);
1460 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1463 /* C3.2.3 Exception generation
1465 * 31 24 23 21 20 5 4 2 1 0
1466 * +-----------------+-----+------------------------+-----+----+
1467 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1468 * +-----------------------+------------------------+----------+
1470 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1472 int opc
= extract32(insn
, 21, 3);
1473 int op2_ll
= extract32(insn
, 0, 5);
1474 int imm16
= extract32(insn
, 5, 16);
1479 /* For SVC, HVC and SMC we advance the single-step state
1480 * machine before taking the exception. This is architecturally
1481 * mandated, to ensure that single-stepping a system call
1482 * instruction works properly.
1487 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1488 default_exception_el(s
));
1491 if (s
->current_el
== 0) {
1492 unallocated_encoding(s
);
1495 /* The pre HVC helper handles cases when HVC gets trapped
1496 * as an undefined insn by runtime configuration.
1498 gen_a64_set_pc_im(s
->pc
- 4);
1499 gen_helper_pre_hvc(cpu_env
);
1501 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1504 if (s
->current_el
== 0) {
1505 unallocated_encoding(s
);
1508 gen_a64_set_pc_im(s
->pc
- 4);
1509 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1510 gen_helper_pre_smc(cpu_env
, tmp
);
1511 tcg_temp_free_i32(tmp
);
1513 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1516 unallocated_encoding(s
);
1522 unallocated_encoding(s
);
1526 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1527 default_exception_el(s
));
1531 unallocated_encoding(s
);
1535 unsupported_encoding(s
, insn
);
1538 if (op2_ll
< 1 || op2_ll
> 3) {
1539 unallocated_encoding(s
);
1542 /* DCPS1, DCPS2, DCPS3 */
1543 unsupported_encoding(s
, insn
);
1546 unallocated_encoding(s
);
1551 /* C3.2.7 Unconditional branch (register)
1552 * 31 25 24 21 20 16 15 10 9 5 4 0
1553 * +---------------+-------+-------+-------+------+-------+
1554 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1555 * +---------------+-------+-------+-------+------+-------+
1557 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1559 unsigned int opc
, op2
, op3
, rn
, op4
;
1561 opc
= extract32(insn
, 21, 4);
1562 op2
= extract32(insn
, 16, 5);
1563 op3
= extract32(insn
, 10, 6);
1564 rn
= extract32(insn
, 5, 5);
1565 op4
= extract32(insn
, 0, 5);
1567 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1568 unallocated_encoding(s
);
1575 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1578 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1579 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1582 if (s
->current_el
== 0) {
1583 unallocated_encoding(s
);
1586 gen_helper_exception_return(cpu_env
);
1587 s
->is_jmp
= DISAS_JUMP
;
1591 unallocated_encoding(s
);
1593 unsupported_encoding(s
, insn
);
1597 unallocated_encoding(s
);
1601 s
->is_jmp
= DISAS_JUMP
;
1604 /* C3.2 Branches, exception generating and system instructions */
1605 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1607 switch (extract32(insn
, 25, 7)) {
1608 case 0x0a: case 0x0b:
1609 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1610 disas_uncond_b_imm(s
, insn
);
1612 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1613 disas_comp_b_imm(s
, insn
);
1615 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1616 disas_test_b_imm(s
, insn
);
1618 case 0x2a: /* Conditional branch (immediate) */
1619 disas_cond_b_imm(s
, insn
);
1621 case 0x6a: /* Exception generation / System */
1622 if (insn
& (1 << 24)) {
1623 disas_system(s
, insn
);
1628 case 0x6b: /* Unconditional branch (register) */
1629 disas_uncond_b_reg(s
, insn
);
1632 unallocated_encoding(s
);
1638 * Load/Store exclusive instructions are implemented by remembering
1639 * the value/address loaded, and seeing if these are the same
1640 * when the store is performed. This is not actually the architecturally
1641 * mandated semantics, but it works for typical guest code sequences
1642 * and avoids having to monitor regular stores.
1644 * In system emulation mode only one CPU will be running at once, so
1645 * this sequence is effectively atomic. In user emulation mode we
1646 * throw an exception and handle the atomic operation elsewhere.
1648 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1649 TCGv_i64 addr
, int size
, bool is_pair
)
1651 TCGv_i64 tmp
= tcg_temp_new_i64();
1652 TCGMemOp memop
= MO_TE
+ size
;
1654 g_assert(size
<= 3);
1655 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1658 TCGv_i64 addr2
= tcg_temp_new_i64();
1659 TCGv_i64 hitmp
= tcg_temp_new_i64();
1661 g_assert(size
>= 2);
1662 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1663 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1664 tcg_temp_free_i64(addr2
);
1665 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1666 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1667 tcg_temp_free_i64(hitmp
);
1670 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1671 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1673 tcg_temp_free_i64(tmp
);
1674 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1677 #ifdef CONFIG_USER_ONLY
1678 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1679 TCGv_i64 addr
, int size
, int is_pair
)
1681 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1682 tcg_gen_movi_i32(cpu_exclusive_info
,
1683 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1684 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1687 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1688 TCGv_i64 inaddr
, int size
, int is_pair
)
1690 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1691 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1694 * [addr + datasize] = {Rt2};
1700 * env->exclusive_addr = -1;
1702 TCGLabel
*fail_label
= gen_new_label();
1703 TCGLabel
*done_label
= gen_new_label();
1704 TCGv_i64 addr
= tcg_temp_local_new_i64();
1707 /* Copy input into a local temp so it is not trashed when the
1708 * basic block ends at the branch insn.
1710 tcg_gen_mov_i64(addr
, inaddr
);
1711 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1713 tmp
= tcg_temp_new_i64();
1714 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1715 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1716 tcg_temp_free_i64(tmp
);
1719 TCGv_i64 addrhi
= tcg_temp_new_i64();
1720 TCGv_i64 tmphi
= tcg_temp_new_i64();
1722 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1723 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1724 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1726 tcg_temp_free_i64(tmphi
);
1727 tcg_temp_free_i64(addrhi
);
1730 /* We seem to still have the exclusive monitor, so do the store */
1731 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1733 TCGv_i64 addrhi
= tcg_temp_new_i64();
1735 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1736 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1737 get_mem_index(s
), MO_TE
+ size
);
1738 tcg_temp_free_i64(addrhi
);
1741 tcg_temp_free_i64(addr
);
1743 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1744 tcg_gen_br(done_label
);
1745 gen_set_label(fail_label
);
1746 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1747 gen_set_label(done_label
);
1748 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1753 /* C3.3.6 Load/store exclusive
1755 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1756 * +-----+-------------+----+---+----+------+----+-------+------+------+
1757 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1758 * +-----+-------------+----+---+----+------+----+-------+------+------+
1760 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1761 * L: 0 -> store, 1 -> load
1762 * o2: 0 -> exclusive, 1 -> not
1763 * o1: 0 -> single register, 1 -> register pair
1764 * o0: 1 -> load-acquire/store-release, 0 -> not
1766 * o0 == 0 AND o2 == 1 is un-allocated
1767 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1769 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1771 int rt
= extract32(insn
, 0, 5);
1772 int rn
= extract32(insn
, 5, 5);
1773 int rt2
= extract32(insn
, 10, 5);
1774 int is_lasr
= extract32(insn
, 15, 1);
1775 int rs
= extract32(insn
, 16, 5);
1776 int is_pair
= extract32(insn
, 21, 1);
1777 int is_store
= !extract32(insn
, 22, 1);
1778 int is_excl
= !extract32(insn
, 23, 1);
1779 int size
= extract32(insn
, 30, 2);
1782 if ((!is_excl
&& !is_lasr
) ||
1783 (is_pair
&& size
< 2)) {
1784 unallocated_encoding(s
);
1789 gen_check_sp_alignment(s
);
1791 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1793 /* Note that since TCG is single threaded load-acquire/store-release
1794 * semantics require no extra if (is_lasr) { ... } handling.
1800 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1802 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1805 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1807 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1809 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1812 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1813 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1815 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1817 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1824 * C3.3.5 Load register (literal)
1826 * 31 30 29 27 26 25 24 23 5 4 0
1827 * +-----+-------+---+-----+-------------------+-------+
1828 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1829 * +-----+-------+---+-----+-------------------+-------+
1831 * V: 1 -> vector (simd/fp)
1832 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1833 * 10-> 32 bit signed, 11 -> prefetch
1834 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1836 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1838 int rt
= extract32(insn
, 0, 5);
1839 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1840 bool is_vector
= extract32(insn
, 26, 1);
1841 int opc
= extract32(insn
, 30, 2);
1842 bool is_signed
= false;
1844 TCGv_i64 tcg_rt
, tcg_addr
;
1848 unallocated_encoding(s
);
1852 if (!fp_access_check(s
)) {
1857 /* PRFM (literal) : prefetch */
1860 size
= 2 + extract32(opc
, 0, 1);
1861 is_signed
= extract32(opc
, 1, 1);
1864 tcg_rt
= cpu_reg(s
, rt
);
1866 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1868 do_fp_ld(s
, rt
, tcg_addr
, size
);
1870 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1872 tcg_temp_free_i64(tcg_addr
);
1876 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1877 * C5.6.81 LDP (Load Pair - non vector)
1878 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1879 * C5.6.176 STNP (Store Pair - non-temporal hint)
1880 * C5.6.177 STP (Store Pair - non vector)
1881 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1882 * C6.3.165 LDP (Load Pair of SIMD&FP)
1883 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1884 * C6.3.284 STP (Store Pair of SIMD&FP)
1886 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1887 * +-----+-------+---+---+-------+---+-----------------------------+
1888 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1889 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1891 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1893 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1894 * V: 0 -> GPR, 1 -> Vector
1895 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1896 * 10 -> signed offset, 11 -> pre-index
1897 * L: 0 -> Store 1 -> Load
1899 * Rt, Rt2 = GPR or SIMD registers to be stored
1900 * Rn = general purpose register containing address
1901 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1903 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1905 int rt
= extract32(insn
, 0, 5);
1906 int rn
= extract32(insn
, 5, 5);
1907 int rt2
= extract32(insn
, 10, 5);
1908 uint64_t offset
= sextract64(insn
, 15, 7);
1909 int index
= extract32(insn
, 23, 2);
1910 bool is_vector
= extract32(insn
, 26, 1);
1911 bool is_load
= extract32(insn
, 22, 1);
1912 int opc
= extract32(insn
, 30, 2);
1914 bool is_signed
= false;
1915 bool postindex
= false;
1918 TCGv_i64 tcg_addr
; /* calculated address */
1922 unallocated_encoding(s
);
1929 size
= 2 + extract32(opc
, 1, 1);
1930 is_signed
= extract32(opc
, 0, 1);
1931 if (!is_load
&& is_signed
) {
1932 unallocated_encoding(s
);
1938 case 1: /* post-index */
1943 /* signed offset with "non-temporal" hint. Since we don't emulate
1944 * caches we don't care about hints to the cache system about
1945 * data access patterns, and handle this identically to plain
1949 /* There is no non-temporal-hint version of LDPSW */
1950 unallocated_encoding(s
);
1955 case 2: /* signed offset, rn not updated */
1958 case 3: /* pre-index */
1964 if (is_vector
&& !fp_access_check(s
)) {
1971 gen_check_sp_alignment(s
);
1974 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1977 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1982 do_fp_ld(s
, rt
, tcg_addr
, size
);
1984 do_fp_st(s
, rt
, tcg_addr
, size
);
1987 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1989 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1991 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1994 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1997 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1999 do_fp_st(s
, rt2
, tcg_addr
, size
);
2002 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2004 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
2006 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
2012 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2014 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2016 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2021 * C3.3.8 Load/store (immediate post-indexed)
2022 * C3.3.9 Load/store (immediate pre-indexed)
2023 * C3.3.12 Load/store (unscaled immediate)
2025 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2026 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2027 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2028 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2030 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2032 * V = 0 -> non-vector
2033 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2034 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2036 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
2038 int rt
= extract32(insn
, 0, 5);
2039 int rn
= extract32(insn
, 5, 5);
2040 int imm9
= sextract32(insn
, 12, 9);
2041 int opc
= extract32(insn
, 22, 2);
2042 int size
= extract32(insn
, 30, 2);
2043 int idx
= extract32(insn
, 10, 2);
2044 bool is_signed
= false;
2045 bool is_store
= false;
2046 bool is_extended
= false;
2047 bool is_unpriv
= (idx
== 2);
2048 bool is_vector
= extract32(insn
, 26, 1);
2055 size
|= (opc
& 2) << 1;
2056 if (size
> 4 || is_unpriv
) {
2057 unallocated_encoding(s
);
2060 is_store
= ((opc
& 1) == 0);
2061 if (!fp_access_check(s
)) {
2065 if (size
== 3 && opc
== 2) {
2066 /* PRFM - prefetch */
2068 unallocated_encoding(s
);
2073 if (opc
== 3 && size
> 1) {
2074 unallocated_encoding(s
);
2077 is_store
= (opc
== 0);
2078 is_signed
= opc
& (1<<1);
2079 is_extended
= (size
< 3) && (opc
& 1);
2099 gen_check_sp_alignment(s
);
2101 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2104 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2109 do_fp_st(s
, rt
, tcg_addr
, size
);
2111 do_fp_ld(s
, rt
, tcg_addr
, size
);
2114 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2115 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2118 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2120 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2121 is_signed
, is_extended
, memidx
);
2126 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2128 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2130 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2135 * C3.3.10 Load/store (register offset)
2137 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2138 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2139 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2140 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2143 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2144 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2146 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2147 * opc<0>: 0 -> store, 1 -> load
2148 * V: 1 -> vector/simd
2149 * opt: extend encoding (see DecodeRegExtend)
2150 * S: if S=1 then scale (essentially index by sizeof(size))
2151 * Rt: register to transfer into/out of
2152 * Rn: address register or SP for base
2153 * Rm: offset register or ZR for offset
2155 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2157 int rt
= extract32(insn
, 0, 5);
2158 int rn
= extract32(insn
, 5, 5);
2159 int shift
= extract32(insn
, 12, 1);
2160 int rm
= extract32(insn
, 16, 5);
2161 int opc
= extract32(insn
, 22, 2);
2162 int opt
= extract32(insn
, 13, 3);
2163 int size
= extract32(insn
, 30, 2);
2164 bool is_signed
= false;
2165 bool is_store
= false;
2166 bool is_extended
= false;
2167 bool is_vector
= extract32(insn
, 26, 1);
2172 if (extract32(opt
, 1, 1) == 0) {
2173 unallocated_encoding(s
);
2178 size
|= (opc
& 2) << 1;
2180 unallocated_encoding(s
);
2183 is_store
= !extract32(opc
, 0, 1);
2184 if (!fp_access_check(s
)) {
2188 if (size
== 3 && opc
== 2) {
2189 /* PRFM - prefetch */
2192 if (opc
== 3 && size
> 1) {
2193 unallocated_encoding(s
);
2196 is_store
= (opc
== 0);
2197 is_signed
= extract32(opc
, 1, 1);
2198 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2202 gen_check_sp_alignment(s
);
2204 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2206 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2207 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2209 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2213 do_fp_st(s
, rt
, tcg_addr
, size
);
2215 do_fp_ld(s
, rt
, tcg_addr
, size
);
2218 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2220 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2222 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2228 * C3.3.13 Load/store (unsigned immediate)
2230 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2231 * +----+-------+---+-----+-----+------------+-------+------+
2232 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2233 * +----+-------+---+-----+-----+------------+-------+------+
2236 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2237 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2239 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2240 * opc<0>: 0 -> store, 1 -> load
2241 * Rn: base address register (inc SP)
2242 * Rt: target register
2244 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2246 int rt
= extract32(insn
, 0, 5);
2247 int rn
= extract32(insn
, 5, 5);
2248 unsigned int imm12
= extract32(insn
, 10, 12);
2249 bool is_vector
= extract32(insn
, 26, 1);
2250 int size
= extract32(insn
, 30, 2);
2251 int opc
= extract32(insn
, 22, 2);
2252 unsigned int offset
;
2257 bool is_signed
= false;
2258 bool is_extended
= false;
2261 size
|= (opc
& 2) << 1;
2263 unallocated_encoding(s
);
2266 is_store
= !extract32(opc
, 0, 1);
2267 if (!fp_access_check(s
)) {
2271 if (size
== 3 && opc
== 2) {
2272 /* PRFM - prefetch */
2275 if (opc
== 3 && size
> 1) {
2276 unallocated_encoding(s
);
2279 is_store
= (opc
== 0);
2280 is_signed
= extract32(opc
, 1, 1);
2281 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2285 gen_check_sp_alignment(s
);
2287 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2288 offset
= imm12
<< size
;
2289 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2293 do_fp_st(s
, rt
, tcg_addr
, size
);
2295 do_fp_ld(s
, rt
, tcg_addr
, size
);
2298 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2300 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2302 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2307 /* Load/store register (all forms) */
2308 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2310 switch (extract32(insn
, 24, 2)) {
2312 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2313 disas_ldst_reg_roffset(s
, insn
);
2315 /* Load/store register (unscaled immediate)
2316 * Load/store immediate pre/post-indexed
2317 * Load/store register unprivileged
2319 disas_ldst_reg_imm9(s
, insn
);
2323 disas_ldst_reg_unsigned_imm(s
, insn
);
2326 unallocated_encoding(s
);
2331 /* C3.3.1 AdvSIMD load/store multiple structures
2333 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2334 * +---+---+---------------+---+-------------+--------+------+------+------+
2335 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2336 * +---+---+---------------+---+-------------+--------+------+------+------+
2338 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2340 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2341 * +---+---+---------------+---+---+---------+--------+------+------+------+
2342 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2343 * +---+---+---------------+---+---+---------+--------+------+------+------+
2345 * Rt: first (or only) SIMD&FP register to be transferred
2346 * Rn: base address or SP
2347 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2349 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2351 int rt
= extract32(insn
, 0, 5);
2352 int rn
= extract32(insn
, 5, 5);
2353 int size
= extract32(insn
, 10, 2);
2354 int opcode
= extract32(insn
, 12, 4);
2355 bool is_store
= !extract32(insn
, 22, 1);
2356 bool is_postidx
= extract32(insn
, 23, 1);
2357 bool is_q
= extract32(insn
, 30, 1);
2358 TCGv_i64 tcg_addr
, tcg_rn
;
2360 int ebytes
= 1 << size
;
2361 int elements
= (is_q
? 128 : 64) / (8 << size
);
2362 int rpt
; /* num iterations */
2363 int selem
; /* structure elements */
2366 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2367 unallocated_encoding(s
);
2371 /* From the shared decode logic */
2402 unallocated_encoding(s
);
2406 if (size
== 3 && !is_q
&& selem
!= 1) {
2408 unallocated_encoding(s
);
2412 if (!fp_access_check(s
)) {
2417 gen_check_sp_alignment(s
);
2420 tcg_rn
= cpu_reg_sp(s
, rn
);
2421 tcg_addr
= tcg_temp_new_i64();
2422 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2424 for (r
= 0; r
< rpt
; r
++) {
2426 for (e
= 0; e
< elements
; e
++) {
2427 int tt
= (rt
+ r
) % 32;
2429 for (xs
= 0; xs
< selem
; xs
++) {
2431 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2433 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2435 /* For non-quad operations, setting a slice of the low
2436 * 64 bits of the register clears the high 64 bits (in
2437 * the ARM ARM pseudocode this is implicit in the fact
2438 * that 'rval' is a 64 bit wide variable). We optimize
2439 * by noticing that we only need to do this the first
2440 * time we touch a register.
2442 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2443 clear_vec_high(s
, tt
);
2446 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2453 int rm
= extract32(insn
, 16, 5);
2455 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2457 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2460 tcg_temp_free_i64(tcg_addr
);
2463 /* C3.3.3 AdvSIMD load/store single structure
2465 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2466 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2467 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2468 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2470 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2472 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2473 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2474 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2475 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2477 * Rt: first (or only) SIMD&FP register to be transferred
2478 * Rn: base address or SP
2479 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2480 * index = encoded in Q:S:size dependent on size
2482 * lane_size = encoded in R, opc
2483 * transfer width = encoded in opc, S, size
2485 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2487 int rt
= extract32(insn
, 0, 5);
2488 int rn
= extract32(insn
, 5, 5);
2489 int size
= extract32(insn
, 10, 2);
2490 int S
= extract32(insn
, 12, 1);
2491 int opc
= extract32(insn
, 13, 3);
2492 int R
= extract32(insn
, 21, 1);
2493 int is_load
= extract32(insn
, 22, 1);
2494 int is_postidx
= extract32(insn
, 23, 1);
2495 int is_q
= extract32(insn
, 30, 1);
2497 int scale
= extract32(opc
, 1, 2);
2498 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2499 bool replicate
= false;
2500 int index
= is_q
<< 3 | S
<< 2 | size
;
2502 TCGv_i64 tcg_addr
, tcg_rn
;
2506 if (!is_load
|| S
) {
2507 unallocated_encoding(s
);
2516 if (extract32(size
, 0, 1)) {
2517 unallocated_encoding(s
);
2523 if (extract32(size
, 1, 1)) {
2524 unallocated_encoding(s
);
2527 if (!extract32(size
, 0, 1)) {
2531 unallocated_encoding(s
);
2539 g_assert_not_reached();
2542 if (!fp_access_check(s
)) {
2546 ebytes
= 1 << scale
;
2549 gen_check_sp_alignment(s
);
2552 tcg_rn
= cpu_reg_sp(s
, rn
);
2553 tcg_addr
= tcg_temp_new_i64();
2554 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2556 for (xs
= 0; xs
< selem
; xs
++) {
2558 /* Load and replicate to all elements */
2560 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2562 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2563 get_mem_index(s
), MO_TE
+ scale
);
2566 mulconst
= 0x0101010101010101ULL
;
2569 mulconst
= 0x0001000100010001ULL
;
2572 mulconst
= 0x0000000100000001ULL
;
2578 g_assert_not_reached();
2581 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2583 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2585 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2587 clear_vec_high(s
, rt
);
2589 tcg_temp_free_i64(tcg_tmp
);
2591 /* Load/store one element per register */
2593 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2595 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2598 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2603 int rm
= extract32(insn
, 16, 5);
2605 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2607 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2610 tcg_temp_free_i64(tcg_addr
);
2613 /* C3.3 Loads and stores */
2614 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2616 switch (extract32(insn
, 24, 6)) {
2617 case 0x08: /* Load/store exclusive */
2618 disas_ldst_excl(s
, insn
);
2620 case 0x18: case 0x1c: /* Load register (literal) */
2621 disas_ld_lit(s
, insn
);
2623 case 0x28: case 0x29:
2624 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2625 disas_ldst_pair(s
, insn
);
2627 case 0x38: case 0x39:
2628 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2629 disas_ldst_reg(s
, insn
);
2631 case 0x0c: /* AdvSIMD load/store multiple structures */
2632 disas_ldst_multiple_struct(s
, insn
);
2634 case 0x0d: /* AdvSIMD load/store single structure */
2635 disas_ldst_single_struct(s
, insn
);
2638 unallocated_encoding(s
);
2643 /* C3.4.6 PC-rel. addressing
2644 * 31 30 29 28 24 23 5 4 0
2645 * +----+-------+-----------+-------------------+------+
2646 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2647 * +----+-------+-----------+-------------------+------+
2649 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2651 unsigned int page
, rd
;
2655 page
= extract32(insn
, 31, 1);
2656 /* SignExtend(immhi:immlo) -> offset */
2657 offset
= sextract64(insn
, 5, 19);
2658 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2659 rd
= extract32(insn
, 0, 5);
2663 /* ADRP (page based) */
2668 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2672 * C3.4.1 Add/subtract (immediate)
2674 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2675 * +--+--+--+-----------+-----+-------------+-----+-----+
2676 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2677 * +--+--+--+-----------+-----+-------------+-----+-----+
2679 * sf: 0 -> 32bit, 1 -> 64bit
2680 * op: 0 -> add , 1 -> sub
2682 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2684 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2686 int rd
= extract32(insn
, 0, 5);
2687 int rn
= extract32(insn
, 5, 5);
2688 uint64_t imm
= extract32(insn
, 10, 12);
2689 int shift
= extract32(insn
, 22, 2);
2690 bool setflags
= extract32(insn
, 29, 1);
2691 bool sub_op
= extract32(insn
, 30, 1);
2692 bool is_64bit
= extract32(insn
, 31, 1);
2694 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2695 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2696 TCGv_i64 tcg_result
;
2705 unallocated_encoding(s
);
2709 tcg_result
= tcg_temp_new_i64();
2712 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2714 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2717 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2719 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2721 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2723 tcg_temp_free_i64(tcg_imm
);
2727 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2729 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2732 tcg_temp_free_i64(tcg_result
);
2735 /* The input should be a value in the bottom e bits (with higher
2736 * bits zero); returns that value replicated into every element
2737 * of size e in a 64 bit integer.
2739 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2749 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2750 static inline uint64_t bitmask64(unsigned int length
)
2752 assert(length
> 0 && length
<= 64);
2753 return ~0ULL >> (64 - length
);
2756 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2757 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2758 * value (ie should cause a guest UNDEF exception), and true if they are
2759 * valid, in which case the decoded bit pattern is written to result.
2761 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2762 unsigned int imms
, unsigned int immr
)
2765 unsigned e
, levels
, s
, r
;
2768 assert(immn
< 2 && imms
< 64 && immr
< 64);
2770 /* The bit patterns we create here are 64 bit patterns which
2771 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2772 * 64 bits each. Each element contains the same value: a run
2773 * of between 1 and e-1 non-zero bits, rotated within the
2774 * element by between 0 and e-1 bits.
2776 * The element size and run length are encoded into immn (1 bit)
2777 * and imms (6 bits) as follows:
2778 * 64 bit elements: immn = 1, imms = <length of run - 1>
2779 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2780 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2781 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2782 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2783 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2784 * Notice that immn = 0, imms = 11111x is the only combination
2785 * not covered by one of the above options; this is reserved.
2786 * Further, <length of run - 1> all-ones is a reserved pattern.
2788 * In all cases the rotation is by immr % e (and immr is 6 bits).
2791 /* First determine the element size */
2792 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2794 /* This is the immn == 0, imms == 0x11111x case */
2804 /* <length of run - 1> mustn't be all-ones. */
2808 /* Create the value of one element: s+1 set bits rotated
2809 * by r within the element (which is e bits wide)...
2811 mask
= bitmask64(s
+ 1);
2813 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2814 mask
&= bitmask64(e
);
2816 /* ...then replicate the element over the whole 64 bit value */
2817 mask
= bitfield_replicate(mask
, e
);
2822 /* C3.4.4 Logical (immediate)
2823 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2824 * +----+-----+-------------+---+------+------+------+------+
2825 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2826 * +----+-----+-------------+---+------+------+------+------+
2828 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2830 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2831 TCGv_i64 tcg_rd
, tcg_rn
;
2833 bool is_and
= false;
2835 sf
= extract32(insn
, 31, 1);
2836 opc
= extract32(insn
, 29, 2);
2837 is_n
= extract32(insn
, 22, 1);
2838 immr
= extract32(insn
, 16, 6);
2839 imms
= extract32(insn
, 10, 6);
2840 rn
= extract32(insn
, 5, 5);
2841 rd
= extract32(insn
, 0, 5);
2844 unallocated_encoding(s
);
2848 if (opc
== 0x3) { /* ANDS */
2849 tcg_rd
= cpu_reg(s
, rd
);
2851 tcg_rd
= cpu_reg_sp(s
, rd
);
2853 tcg_rn
= cpu_reg(s
, rn
);
2855 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2856 /* some immediate field values are reserved */
2857 unallocated_encoding(s
);
2862 wmask
&= 0xffffffff;
2866 case 0x3: /* ANDS */
2868 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2872 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2875 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2878 assert(FALSE
); /* must handle all above */
2882 if (!sf
&& !is_and
) {
2883 /* zero extend final result; we know we can skip this for AND
2884 * since the immediate had the high 32 bits clear.
2886 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2889 if (opc
== 3) { /* ANDS */
2890 gen_logic_CC(sf
, tcg_rd
);
2895 * C3.4.5 Move wide (immediate)
2897 * 31 30 29 28 23 22 21 20 5 4 0
2898 * +--+-----+-------------+-----+----------------+------+
2899 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2900 * +--+-----+-------------+-----+----------------+------+
2902 * sf: 0 -> 32 bit, 1 -> 64 bit
2903 * opc: 00 -> N, 10 -> Z, 11 -> K
2904 * hw: shift/16 (0,16, and sf only 32, 48)
2906 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2908 int rd
= extract32(insn
, 0, 5);
2909 uint64_t imm
= extract32(insn
, 5, 16);
2910 int sf
= extract32(insn
, 31, 1);
2911 int opc
= extract32(insn
, 29, 2);
2912 int pos
= extract32(insn
, 21, 2) << 4;
2913 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2916 if (!sf
&& (pos
>= 32)) {
2917 unallocated_encoding(s
);
2931 tcg_gen_movi_i64(tcg_rd
, imm
);
2934 tcg_imm
= tcg_const_i64(imm
);
2935 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2936 tcg_temp_free_i64(tcg_imm
);
2938 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2942 unallocated_encoding(s
);
2948 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2949 * +----+-----+-------------+---+------+------+------+------+
2950 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2951 * +----+-----+-------------+---+------+------+------+------+
2953 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2955 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2956 TCGv_i64 tcg_rd
, tcg_tmp
;
2958 sf
= extract32(insn
, 31, 1);
2959 opc
= extract32(insn
, 29, 2);
2960 n
= extract32(insn
, 22, 1);
2961 ri
= extract32(insn
, 16, 6);
2962 si
= extract32(insn
, 10, 6);
2963 rn
= extract32(insn
, 5, 5);
2964 rd
= extract32(insn
, 0, 5);
2965 bitsize
= sf
? 64 : 32;
2967 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2968 unallocated_encoding(s
);
2972 tcg_rd
= cpu_reg(s
, rd
);
2973 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2975 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2977 if (opc
!= 1) { /* SBFM or UBFM */
2978 tcg_gen_movi_i64(tcg_rd
, 0);
2981 /* do the bit move operation */
2983 /* Wd<s-r:0> = Wn<s:r> */
2984 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2986 len
= (si
- ri
) + 1;
2988 /* Wd<32+s-r,32-r> = Wn<s:0> */
2993 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2995 if (opc
== 0) { /* SBFM - sign extend the destination field */
2996 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2997 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3000 if (!sf
) { /* zero extend final result */
3001 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3006 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3007 * +----+------+-------------+---+----+------+--------+------+------+
3008 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3009 * +----+------+-------------+---+----+------+--------+------+------+
3011 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3013 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3015 sf
= extract32(insn
, 31, 1);
3016 n
= extract32(insn
, 22, 1);
3017 rm
= extract32(insn
, 16, 5);
3018 imm
= extract32(insn
, 10, 6);
3019 rn
= extract32(insn
, 5, 5);
3020 rd
= extract32(insn
, 0, 5);
3021 op21
= extract32(insn
, 29, 2);
3022 op0
= extract32(insn
, 21, 1);
3023 bitsize
= sf
? 64 : 32;
3025 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3026 unallocated_encoding(s
);
3028 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3030 tcg_rd
= cpu_reg(s
, rd
);
3033 /* OPTME: we can special case rm==rn as a rotate */
3034 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3035 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3036 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3037 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3038 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3040 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3043 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3044 * so an extract from bit 0 is a special case.
3047 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3049 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3056 /* C3.4 Data processing - immediate */
3057 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3059 switch (extract32(insn
, 23, 6)) {
3060 case 0x20: case 0x21: /* PC-rel. addressing */
3061 disas_pc_rel_adr(s
, insn
);
3063 case 0x22: case 0x23: /* Add/subtract (immediate) */
3064 disas_add_sub_imm(s
, insn
);
3066 case 0x24: /* Logical (immediate) */
3067 disas_logic_imm(s
, insn
);
3069 case 0x25: /* Move wide (immediate) */
3070 disas_movw_imm(s
, insn
);
3072 case 0x26: /* Bitfield */
3073 disas_bitfield(s
, insn
);
3075 case 0x27: /* Extract */
3076 disas_extract(s
, insn
);
3079 unallocated_encoding(s
);
3084 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3085 * Note that it is the caller's responsibility to ensure that the
3086 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3087 * mandated semantics for out of range shifts.
3089 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3090 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3092 switch (shift_type
) {
3093 case A64_SHIFT_TYPE_LSL
:
3094 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3096 case A64_SHIFT_TYPE_LSR
:
3097 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3099 case A64_SHIFT_TYPE_ASR
:
3101 tcg_gen_ext32s_i64(dst
, src
);
3103 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3105 case A64_SHIFT_TYPE_ROR
:
3107 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3110 t0
= tcg_temp_new_i32();
3111 t1
= tcg_temp_new_i32();
3112 tcg_gen_trunc_i64_i32(t0
, src
);
3113 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
3114 tcg_gen_rotr_i32(t0
, t0
, t1
);
3115 tcg_gen_extu_i32_i64(dst
, t0
);
3116 tcg_temp_free_i32(t0
);
3117 tcg_temp_free_i32(t1
);
3121 assert(FALSE
); /* all shift types should be handled */
3125 if (!sf
) { /* zero extend final result */
3126 tcg_gen_ext32u_i64(dst
, dst
);
3130 /* Shift a TCGv src by immediate, put result in dst.
3131 * The shift amount must be in range (this should always be true as the
3132 * relevant instructions will UNDEF on bad shift immediates).
3134 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3135 enum a64_shift_type shift_type
, unsigned int shift_i
)
3137 assert(shift_i
< (sf
? 64 : 32));
3140 tcg_gen_mov_i64(dst
, src
);
3142 TCGv_i64 shift_const
;
3144 shift_const
= tcg_const_i64(shift_i
);
3145 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3146 tcg_temp_free_i64(shift_const
);
3150 /* C3.5.10 Logical (shifted register)
3151 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3152 * +----+-----+-----------+-------+---+------+--------+------+------+
3153 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3154 * +----+-----+-----------+-------+---+------+--------+------+------+
3156 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3158 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3159 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3161 sf
= extract32(insn
, 31, 1);
3162 opc
= extract32(insn
, 29, 2);
3163 shift_type
= extract32(insn
, 22, 2);
3164 invert
= extract32(insn
, 21, 1);
3165 rm
= extract32(insn
, 16, 5);
3166 shift_amount
= extract32(insn
, 10, 6);
3167 rn
= extract32(insn
, 5, 5);
3168 rd
= extract32(insn
, 0, 5);
3170 if (!sf
&& (shift_amount
& (1 << 5))) {
3171 unallocated_encoding(s
);
3175 tcg_rd
= cpu_reg(s
, rd
);
3177 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3178 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3179 * register-register MOV and MVN, so it is worth special casing.
3181 tcg_rm
= cpu_reg(s
, rm
);
3183 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3185 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3189 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3191 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3197 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3200 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3203 tcg_rn
= cpu_reg(s
, rn
);
3205 switch (opc
| (invert
<< 2)) {
3208 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3211 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3214 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3218 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3221 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3224 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3232 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3236 gen_logic_CC(sf
, tcg_rd
);
3241 * C3.5.1 Add/subtract (extended register)
3243 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3244 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3245 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3246 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3248 * sf: 0 -> 32bit, 1 -> 64bit
3249 * op: 0 -> add , 1 -> sub
3252 * option: extension type (see DecodeRegExtend)
3253 * imm3: optional shift to Rm
3255 * Rd = Rn + LSL(extend(Rm), amount)
3257 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3259 int rd
= extract32(insn
, 0, 5);
3260 int rn
= extract32(insn
, 5, 5);
3261 int imm3
= extract32(insn
, 10, 3);
3262 int option
= extract32(insn
, 13, 3);
3263 int rm
= extract32(insn
, 16, 5);
3264 bool setflags
= extract32(insn
, 29, 1);
3265 bool sub_op
= extract32(insn
, 30, 1);
3266 bool sf
= extract32(insn
, 31, 1);
3268 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3270 TCGv_i64 tcg_result
;
3273 unallocated_encoding(s
);
3277 /* non-flag setting ops may use SP */
3279 tcg_rd
= cpu_reg_sp(s
, rd
);
3281 tcg_rd
= cpu_reg(s
, rd
);
3283 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3285 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3286 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3288 tcg_result
= tcg_temp_new_i64();
3292 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3294 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3298 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3300 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3305 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3307 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3310 tcg_temp_free_i64(tcg_result
);
3314 * C3.5.2 Add/subtract (shifted register)
3316 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3317 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3318 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3319 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3321 * sf: 0 -> 32bit, 1 -> 64bit
3322 * op: 0 -> add , 1 -> sub
3324 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3325 * imm6: Shift amount to apply to Rm before the add/sub
3327 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3329 int rd
= extract32(insn
, 0, 5);
3330 int rn
= extract32(insn
, 5, 5);
3331 int imm6
= extract32(insn
, 10, 6);
3332 int rm
= extract32(insn
, 16, 5);
3333 int shift_type
= extract32(insn
, 22, 2);
3334 bool setflags
= extract32(insn
, 29, 1);
3335 bool sub_op
= extract32(insn
, 30, 1);
3336 bool sf
= extract32(insn
, 31, 1);
3338 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3339 TCGv_i64 tcg_rn
, tcg_rm
;
3340 TCGv_i64 tcg_result
;
3342 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3343 unallocated_encoding(s
);
3347 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3348 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3350 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3352 tcg_result
= tcg_temp_new_i64();
3356 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3358 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3362 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3364 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3369 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3371 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3374 tcg_temp_free_i64(tcg_result
);
3377 /* C3.5.9 Data-processing (3 source)
3379 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3380 +--+------+-----------+------+------+----+------+------+------+
3381 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3382 +--+------+-----------+------+------+----+------+------+------+
3385 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3387 int rd
= extract32(insn
, 0, 5);
3388 int rn
= extract32(insn
, 5, 5);
3389 int ra
= extract32(insn
, 10, 5);
3390 int rm
= extract32(insn
, 16, 5);
3391 int op_id
= (extract32(insn
, 29, 3) << 4) |
3392 (extract32(insn
, 21, 3) << 1) |
3393 extract32(insn
, 15, 1);
3394 bool sf
= extract32(insn
, 31, 1);
3395 bool is_sub
= extract32(op_id
, 0, 1);
3396 bool is_high
= extract32(op_id
, 2, 1);
3397 bool is_signed
= false;
3402 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3404 case 0x42: /* SMADDL */
3405 case 0x43: /* SMSUBL */
3406 case 0x44: /* SMULH */
3409 case 0x0: /* MADD (32bit) */
3410 case 0x1: /* MSUB (32bit) */
3411 case 0x40: /* MADD (64bit) */
3412 case 0x41: /* MSUB (64bit) */
3413 case 0x4a: /* UMADDL */
3414 case 0x4b: /* UMSUBL */
3415 case 0x4c: /* UMULH */
3418 unallocated_encoding(s
);
3423 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3424 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3425 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3426 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3429 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3431 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3434 tcg_temp_free_i64(low_bits
);
3438 tcg_op1
= tcg_temp_new_i64();
3439 tcg_op2
= tcg_temp_new_i64();
3440 tcg_tmp
= tcg_temp_new_i64();
3443 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3444 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3447 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3448 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3450 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3451 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3455 if (ra
== 31 && !is_sub
) {
3456 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3457 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3459 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3461 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3463 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3468 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3471 tcg_temp_free_i64(tcg_op1
);
3472 tcg_temp_free_i64(tcg_op2
);
3473 tcg_temp_free_i64(tcg_tmp
);
3476 /* C3.5.3 - Add/subtract (with carry)
3477 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3478 * +--+--+--+------------------------+------+---------+------+-----+
3479 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3480 * +--+--+--+------------------------+------+---------+------+-----+
3484 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3486 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3487 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3489 if (extract32(insn
, 10, 6) != 0) {
3490 unallocated_encoding(s
);
3494 sf
= extract32(insn
, 31, 1);
3495 op
= extract32(insn
, 30, 1);
3496 setflags
= extract32(insn
, 29, 1);
3497 rm
= extract32(insn
, 16, 5);
3498 rn
= extract32(insn
, 5, 5);
3499 rd
= extract32(insn
, 0, 5);
3501 tcg_rd
= cpu_reg(s
, rd
);
3502 tcg_rn
= cpu_reg(s
, rn
);
3505 tcg_y
= new_tmp_a64(s
);
3506 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3508 tcg_y
= cpu_reg(s
, rm
);
3512 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3514 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3518 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3519 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3520 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3521 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3522 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3525 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3527 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3528 TCGLabel
*label_continue
= NULL
;
3529 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3531 if (!extract32(insn
, 29, 1)) {
3532 unallocated_encoding(s
);
3535 if (insn
& (1 << 10 | 1 << 4)) {
3536 unallocated_encoding(s
);
3539 sf
= extract32(insn
, 31, 1);
3540 op
= extract32(insn
, 30, 1);
3541 is_imm
= extract32(insn
, 11, 1);
3542 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3543 cond
= extract32(insn
, 12, 4);
3544 rn
= extract32(insn
, 5, 5);
3545 nzcv
= extract32(insn
, 0, 4);
3547 if (cond
< 0x0e) { /* not always */
3548 TCGLabel
*label_match
= gen_new_label();
3549 label_continue
= gen_new_label();
3550 arm_gen_test_cc(cond
, label_match
);
3552 tcg_tmp
= tcg_temp_new_i64();
3553 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3554 gen_set_nzcv(tcg_tmp
);
3555 tcg_temp_free_i64(tcg_tmp
);
3556 tcg_gen_br(label_continue
);
3557 gen_set_label(label_match
);
3559 /* match, or condition is always */
3561 tcg_y
= new_tmp_a64(s
);
3562 tcg_gen_movi_i64(tcg_y
, y
);
3564 tcg_y
= cpu_reg(s
, y
);
3566 tcg_rn
= cpu_reg(s
, rn
);
3568 tcg_tmp
= tcg_temp_new_i64();
3570 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3572 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3574 tcg_temp_free_i64(tcg_tmp
);
3576 if (cond
< 0x0e) { /* continue */
3577 gen_set_label(label_continue
);
3581 /* C3.5.6 Conditional select
3582 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3583 * +----+----+---+-----------------+------+------+-----+------+------+
3584 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3585 * +----+----+---+-----------------+------+------+-----+------+------+
3587 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3589 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3590 TCGv_i64 tcg_rd
, tcg_src
;
3592 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3593 /* S == 1 or op2<1> == 1 */
3594 unallocated_encoding(s
);
3597 sf
= extract32(insn
, 31, 1);
3598 else_inv
= extract32(insn
, 30, 1);
3599 rm
= extract32(insn
, 16, 5);
3600 cond
= extract32(insn
, 12, 4);
3601 else_inc
= extract32(insn
, 10, 1);
3602 rn
= extract32(insn
, 5, 5);
3603 rd
= extract32(insn
, 0, 5);
3606 /* silly no-op write; until we use movcond we must special-case
3607 * this to avoid a dead temporary across basic blocks.
3612 tcg_rd
= cpu_reg(s
, rd
);
3614 if (cond
>= 0x0e) { /* condition "always" */
3615 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3616 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3618 /* OPTME: we could use movcond here, at the cost of duplicating
3619 * a lot of the arm_gen_test_cc() logic.
3621 TCGLabel
*label_match
= gen_new_label();
3622 TCGLabel
*label_continue
= gen_new_label();
3624 arm_gen_test_cc(cond
, label_match
);
3626 tcg_src
= cpu_reg(s
, rm
);
3628 if (else_inv
&& else_inc
) {
3629 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3630 } else if (else_inv
) {
3631 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3632 } else if (else_inc
) {
3633 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3635 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3638 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3640 tcg_gen_br(label_continue
);
3642 gen_set_label(label_match
);
3643 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3644 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3646 gen_set_label(label_continue
);
3650 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3651 unsigned int rn
, unsigned int rd
)
3653 TCGv_i64 tcg_rd
, tcg_rn
;
3654 tcg_rd
= cpu_reg(s
, rd
);
3655 tcg_rn
= cpu_reg(s
, rn
);
3658 gen_helper_clz64(tcg_rd
, tcg_rn
);
3660 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3661 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3662 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3663 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3664 tcg_temp_free_i32(tcg_tmp32
);
3668 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3669 unsigned int rn
, unsigned int rd
)
3671 TCGv_i64 tcg_rd
, tcg_rn
;
3672 tcg_rd
= cpu_reg(s
, rd
);
3673 tcg_rn
= cpu_reg(s
, rn
);
3676 gen_helper_cls64(tcg_rd
, tcg_rn
);
3678 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3679 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3680 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3681 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3682 tcg_temp_free_i32(tcg_tmp32
);
3686 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3687 unsigned int rn
, unsigned int rd
)
3689 TCGv_i64 tcg_rd
, tcg_rn
;
3690 tcg_rd
= cpu_reg(s
, rd
);
3691 tcg_rn
= cpu_reg(s
, rn
);
3694 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3696 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3697 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3698 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3699 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3700 tcg_temp_free_i32(tcg_tmp32
);
3704 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3705 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3706 unsigned int rn
, unsigned int rd
)
3709 unallocated_encoding(s
);
3712 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3715 /* C5.6.149 REV with sf==0, opcode==2
3716 * C5.6.151 REV32 (sf==1, opcode==2)
3718 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3719 unsigned int rn
, unsigned int rd
)
3721 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3724 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3725 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3727 /* bswap32_i64 requires zero high word */
3728 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3729 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3730 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3731 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3732 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3734 tcg_temp_free_i64(tcg_tmp
);
3736 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3737 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3741 /* C5.6.150 REV16 (opcode==1) */
3742 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3743 unsigned int rn
, unsigned int rd
)
3745 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3746 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3747 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3749 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3750 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3752 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3753 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3754 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3755 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3758 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3759 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3760 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3761 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3763 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3764 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3765 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3768 tcg_temp_free_i64(tcg_tmp
);
3771 /* C3.5.7 Data-processing (1 source)
3772 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3773 * +----+---+---+-----------------+---------+--------+------+------+
3774 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3775 * +----+---+---+-----------------+---------+--------+------+------+
3777 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3779 unsigned int sf
, opcode
, rn
, rd
;
3781 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3782 unallocated_encoding(s
);
3786 sf
= extract32(insn
, 31, 1);
3787 opcode
= extract32(insn
, 10, 6);
3788 rn
= extract32(insn
, 5, 5);
3789 rd
= extract32(insn
, 0, 5);
3793 handle_rbit(s
, sf
, rn
, rd
);
3796 handle_rev16(s
, sf
, rn
, rd
);
3799 handle_rev32(s
, sf
, rn
, rd
);
3802 handle_rev64(s
, sf
, rn
, rd
);
3805 handle_clz(s
, sf
, rn
, rd
);
3808 handle_cls(s
, sf
, rn
, rd
);
3813 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3814 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3816 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3817 tcg_rd
= cpu_reg(s
, rd
);
3819 if (!sf
&& is_signed
) {
3820 tcg_n
= new_tmp_a64(s
);
3821 tcg_m
= new_tmp_a64(s
);
3822 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3823 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3825 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3826 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3830 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3832 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3835 if (!sf
) { /* zero extend final result */
3836 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3840 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3841 static void handle_shift_reg(DisasContext
*s
,
3842 enum a64_shift_type shift_type
, unsigned int sf
,
3843 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3845 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3846 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3847 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3849 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3850 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3851 tcg_temp_free_i64(tcg_shift
);
3854 /* CRC32[BHWX], CRC32C[BHWX] */
3855 static void handle_crc32(DisasContext
*s
,
3856 unsigned int sf
, unsigned int sz
, bool crc32c
,
3857 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3859 TCGv_i64 tcg_acc
, tcg_val
;
3862 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
3863 || (sf
== 1 && sz
!= 3)
3864 || (sf
== 0 && sz
== 3)) {
3865 unallocated_encoding(s
);
3870 tcg_val
= cpu_reg(s
, rm
);
3884 g_assert_not_reached();
3886 tcg_val
= new_tmp_a64(s
);
3887 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
3890 tcg_acc
= cpu_reg(s
, rn
);
3891 tcg_bytes
= tcg_const_i32(1 << sz
);
3894 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3896 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3899 tcg_temp_free_i32(tcg_bytes
);
3902 /* C3.5.8 Data-processing (2 source)
3903 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3904 * +----+---+---+-----------------+------+--------+------+------+
3905 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3906 * +----+---+---+-----------------+------+--------+------+------+
3908 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3910 unsigned int sf
, rm
, opcode
, rn
, rd
;
3911 sf
= extract32(insn
, 31, 1);
3912 rm
= extract32(insn
, 16, 5);
3913 opcode
= extract32(insn
, 10, 6);
3914 rn
= extract32(insn
, 5, 5);
3915 rd
= extract32(insn
, 0, 5);
3917 if (extract32(insn
, 29, 1)) {
3918 unallocated_encoding(s
);
3924 handle_div(s
, false, sf
, rm
, rn
, rd
);
3927 handle_div(s
, true, sf
, rm
, rn
, rd
);
3930 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3933 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3936 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3939 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3948 case 23: /* CRC32 */
3950 int sz
= extract32(opcode
, 0, 2);
3951 bool crc32c
= extract32(opcode
, 2, 1);
3952 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
3956 unallocated_encoding(s
);
3961 /* C3.5 Data processing - register */
3962 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3964 switch (extract32(insn
, 24, 5)) {
3965 case 0x0a: /* Logical (shifted register) */
3966 disas_logic_reg(s
, insn
);
3968 case 0x0b: /* Add/subtract */
3969 if (insn
& (1 << 21)) { /* (extended register) */
3970 disas_add_sub_ext_reg(s
, insn
);
3972 disas_add_sub_reg(s
, insn
);
3975 case 0x1b: /* Data-processing (3 source) */
3976 disas_data_proc_3src(s
, insn
);
3979 switch (extract32(insn
, 21, 3)) {
3980 case 0x0: /* Add/subtract (with carry) */
3981 disas_adc_sbc(s
, insn
);
3983 case 0x2: /* Conditional compare */
3984 disas_cc(s
, insn
); /* both imm and reg forms */
3986 case 0x4: /* Conditional select */
3987 disas_cond_select(s
, insn
);
3989 case 0x6: /* Data-processing */
3990 if (insn
& (1 << 30)) { /* (1 source) */
3991 disas_data_proc_1src(s
, insn
);
3992 } else { /* (2 source) */
3993 disas_data_proc_2src(s
, insn
);
3997 unallocated_encoding(s
);
4002 unallocated_encoding(s
);
4007 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4008 unsigned int rn
, unsigned int rm
,
4009 bool cmp_with_zero
, bool signal_all_nans
)
4011 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4012 TCGv_ptr fpst
= get_fpstatus_ptr();
4015 TCGv_i64 tcg_vn
, tcg_vm
;
4017 tcg_vn
= read_fp_dreg(s
, rn
);
4018 if (cmp_with_zero
) {
4019 tcg_vm
= tcg_const_i64(0);
4021 tcg_vm
= read_fp_dreg(s
, rm
);
4023 if (signal_all_nans
) {
4024 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4026 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4028 tcg_temp_free_i64(tcg_vn
);
4029 tcg_temp_free_i64(tcg_vm
);
4031 TCGv_i32 tcg_vn
, tcg_vm
;
4033 tcg_vn
= read_fp_sreg(s
, rn
);
4034 if (cmp_with_zero
) {
4035 tcg_vm
= tcg_const_i32(0);
4037 tcg_vm
= read_fp_sreg(s
, rm
);
4039 if (signal_all_nans
) {
4040 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4042 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4044 tcg_temp_free_i32(tcg_vn
);
4045 tcg_temp_free_i32(tcg_vm
);
4048 tcg_temp_free_ptr(fpst
);
4050 gen_set_nzcv(tcg_flags
);
4052 tcg_temp_free_i64(tcg_flags
);
4055 /* C3.6.22 Floating point compare
4056 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4057 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4058 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4059 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4061 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4063 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4065 mos
= extract32(insn
, 29, 3);
4066 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4067 rm
= extract32(insn
, 16, 5);
4068 op
= extract32(insn
, 14, 2);
4069 rn
= extract32(insn
, 5, 5);
4070 opc
= extract32(insn
, 3, 2);
4071 op2r
= extract32(insn
, 0, 3);
4073 if (mos
|| op
|| op2r
|| type
> 1) {
4074 unallocated_encoding(s
);
4078 if (!fp_access_check(s
)) {
4082 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4085 /* C3.6.23 Floating point conditional compare
4086 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4087 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4088 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4089 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4091 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4093 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4095 TCGLabel
*label_continue
= NULL
;
4097 mos
= extract32(insn
, 29, 3);
4098 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4099 rm
= extract32(insn
, 16, 5);
4100 cond
= extract32(insn
, 12, 4);
4101 rn
= extract32(insn
, 5, 5);
4102 op
= extract32(insn
, 4, 1);
4103 nzcv
= extract32(insn
, 0, 4);
4105 if (mos
|| type
> 1) {
4106 unallocated_encoding(s
);
4110 if (!fp_access_check(s
)) {
4114 if (cond
< 0x0e) { /* not always */
4115 TCGLabel
*label_match
= gen_new_label();
4116 label_continue
= gen_new_label();
4117 arm_gen_test_cc(cond
, label_match
);
4119 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4120 gen_set_nzcv(tcg_flags
);
4121 tcg_temp_free_i64(tcg_flags
);
4122 tcg_gen_br(label_continue
);
4123 gen_set_label(label_match
);
4126 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4129 gen_set_label(label_continue
);
4133 /* copy src FP register to dst FP register; type specifies single or double */
4134 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
4137 TCGv_i64 v
= read_fp_dreg(s
, src
);
4138 write_fp_dreg(s
, dst
, v
);
4139 tcg_temp_free_i64(v
);
4141 TCGv_i32 v
= read_fp_sreg(s
, src
);
4142 write_fp_sreg(s
, dst
, v
);
4143 tcg_temp_free_i32(v
);
4147 /* C3.6.24 Floating point conditional select
4148 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4149 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4150 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4151 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4153 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4155 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4156 TCGLabel
*label_continue
= NULL
;
4158 mos
= extract32(insn
, 29, 3);
4159 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4160 rm
= extract32(insn
, 16, 5);
4161 cond
= extract32(insn
, 12, 4);
4162 rn
= extract32(insn
, 5, 5);
4163 rd
= extract32(insn
, 0, 5);
4165 if (mos
|| type
> 1) {
4166 unallocated_encoding(s
);
4170 if (!fp_access_check(s
)) {
4174 if (cond
< 0x0e) { /* not always */
4175 TCGLabel
*label_match
= gen_new_label();
4176 label_continue
= gen_new_label();
4177 arm_gen_test_cc(cond
, label_match
);
4179 gen_mov_fp2fp(s
, type
, rd
, rm
);
4180 tcg_gen_br(label_continue
);
4181 gen_set_label(label_match
);
4184 gen_mov_fp2fp(s
, type
, rd
, rn
);
4186 if (cond
< 0x0e) { /* continue */
4187 gen_set_label(label_continue
);
4191 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4192 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4198 fpst
= get_fpstatus_ptr();
4199 tcg_op
= read_fp_sreg(s
, rn
);
4200 tcg_res
= tcg_temp_new_i32();
4203 case 0x0: /* FMOV */
4204 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4206 case 0x1: /* FABS */
4207 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4209 case 0x2: /* FNEG */
4210 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4212 case 0x3: /* FSQRT */
4213 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4215 case 0x8: /* FRINTN */
4216 case 0x9: /* FRINTP */
4217 case 0xa: /* FRINTM */
4218 case 0xb: /* FRINTZ */
4219 case 0xc: /* FRINTA */
4221 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4223 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4224 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4226 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4227 tcg_temp_free_i32(tcg_rmode
);
4230 case 0xe: /* FRINTX */
4231 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4233 case 0xf: /* FRINTI */
4234 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4240 write_fp_sreg(s
, rd
, tcg_res
);
4242 tcg_temp_free_ptr(fpst
);
4243 tcg_temp_free_i32(tcg_op
);
4244 tcg_temp_free_i32(tcg_res
);
4247 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4248 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4254 fpst
= get_fpstatus_ptr();
4255 tcg_op
= read_fp_dreg(s
, rn
);
4256 tcg_res
= tcg_temp_new_i64();
4259 case 0x0: /* FMOV */
4260 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4262 case 0x1: /* FABS */
4263 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4265 case 0x2: /* FNEG */
4266 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4268 case 0x3: /* FSQRT */
4269 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4271 case 0x8: /* FRINTN */
4272 case 0x9: /* FRINTP */
4273 case 0xa: /* FRINTM */
4274 case 0xb: /* FRINTZ */
4275 case 0xc: /* FRINTA */
4277 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4279 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4280 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4282 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4283 tcg_temp_free_i32(tcg_rmode
);
4286 case 0xe: /* FRINTX */
4287 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4289 case 0xf: /* FRINTI */
4290 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4296 write_fp_dreg(s
, rd
, tcg_res
);
4298 tcg_temp_free_ptr(fpst
);
4299 tcg_temp_free_i64(tcg_op
);
4300 tcg_temp_free_i64(tcg_res
);
4303 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4304 int rd
, int rn
, int dtype
, int ntype
)
4309 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4311 /* Single to double */
4312 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4313 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4314 write_fp_dreg(s
, rd
, tcg_rd
);
4315 tcg_temp_free_i64(tcg_rd
);
4317 /* Single to half */
4318 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4319 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4320 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4321 write_fp_sreg(s
, rd
, tcg_rd
);
4322 tcg_temp_free_i32(tcg_rd
);
4324 tcg_temp_free_i32(tcg_rn
);
4329 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4330 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4332 /* Double to single */
4333 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4335 /* Double to half */
4336 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4337 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4339 write_fp_sreg(s
, rd
, tcg_rd
);
4340 tcg_temp_free_i32(tcg_rd
);
4341 tcg_temp_free_i64(tcg_rn
);
4346 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4347 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4349 /* Half to single */
4350 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4351 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4352 write_fp_sreg(s
, rd
, tcg_rd
);
4353 tcg_temp_free_i32(tcg_rd
);
4355 /* Half to double */
4356 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4357 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4358 write_fp_dreg(s
, rd
, tcg_rd
);
4359 tcg_temp_free_i64(tcg_rd
);
4361 tcg_temp_free_i32(tcg_rn
);
4369 /* C3.6.25 Floating point data-processing (1 source)
4370 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4371 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4372 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4373 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4375 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4377 int type
= extract32(insn
, 22, 2);
4378 int opcode
= extract32(insn
, 15, 6);
4379 int rn
= extract32(insn
, 5, 5);
4380 int rd
= extract32(insn
, 0, 5);
4383 case 0x4: case 0x5: case 0x7:
4385 /* FCVT between half, single and double precision */
4386 int dtype
= extract32(opcode
, 0, 2);
4387 if (type
== 2 || dtype
== type
) {
4388 unallocated_encoding(s
);
4391 if (!fp_access_check(s
)) {
4395 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4401 /* 32-to-32 and 64-to-64 ops */
4404 if (!fp_access_check(s
)) {
4408 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4411 if (!fp_access_check(s
)) {
4415 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4418 unallocated_encoding(s
);
4422 unallocated_encoding(s
);
4427 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4428 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4429 int rd
, int rn
, int rm
)
4436 tcg_res
= tcg_temp_new_i32();
4437 fpst
= get_fpstatus_ptr();
4438 tcg_op1
= read_fp_sreg(s
, rn
);
4439 tcg_op2
= read_fp_sreg(s
, rm
);
4442 case 0x0: /* FMUL */
4443 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4445 case 0x1: /* FDIV */
4446 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4448 case 0x2: /* FADD */
4449 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4451 case 0x3: /* FSUB */
4452 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4454 case 0x4: /* FMAX */
4455 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4457 case 0x5: /* FMIN */
4458 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4460 case 0x6: /* FMAXNM */
4461 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4463 case 0x7: /* FMINNM */
4464 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4466 case 0x8: /* FNMUL */
4467 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4468 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4472 write_fp_sreg(s
, rd
, tcg_res
);
4474 tcg_temp_free_ptr(fpst
);
4475 tcg_temp_free_i32(tcg_op1
);
4476 tcg_temp_free_i32(tcg_op2
);
4477 tcg_temp_free_i32(tcg_res
);
4480 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4481 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4482 int rd
, int rn
, int rm
)
4489 tcg_res
= tcg_temp_new_i64();
4490 fpst
= get_fpstatus_ptr();
4491 tcg_op1
= read_fp_dreg(s
, rn
);
4492 tcg_op2
= read_fp_dreg(s
, rm
);
4495 case 0x0: /* FMUL */
4496 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4498 case 0x1: /* FDIV */
4499 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4501 case 0x2: /* FADD */
4502 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4504 case 0x3: /* FSUB */
4505 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4507 case 0x4: /* FMAX */
4508 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4510 case 0x5: /* FMIN */
4511 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4513 case 0x6: /* FMAXNM */
4514 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4516 case 0x7: /* FMINNM */
4517 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4519 case 0x8: /* FNMUL */
4520 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4521 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4525 write_fp_dreg(s
, rd
, tcg_res
);
4527 tcg_temp_free_ptr(fpst
);
4528 tcg_temp_free_i64(tcg_op1
);
4529 tcg_temp_free_i64(tcg_op2
);
4530 tcg_temp_free_i64(tcg_res
);
4533 /* C3.6.26 Floating point data-processing (2 source)
4534 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4535 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4536 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4537 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4539 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4541 int type
= extract32(insn
, 22, 2);
4542 int rd
= extract32(insn
, 0, 5);
4543 int rn
= extract32(insn
, 5, 5);
4544 int rm
= extract32(insn
, 16, 5);
4545 int opcode
= extract32(insn
, 12, 4);
4548 unallocated_encoding(s
);
4554 if (!fp_access_check(s
)) {
4557 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4560 if (!fp_access_check(s
)) {
4563 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4566 unallocated_encoding(s
);
4570 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4571 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4572 int rd
, int rn
, int rm
, int ra
)
4574 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4575 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4576 TCGv_ptr fpst
= get_fpstatus_ptr();
4578 tcg_op1
= read_fp_sreg(s
, rn
);
4579 tcg_op2
= read_fp_sreg(s
, rm
);
4580 tcg_op3
= read_fp_sreg(s
, ra
);
4582 /* These are fused multiply-add, and must be done as one
4583 * floating point operation with no rounding between the
4584 * multiplication and addition steps.
4585 * NB that doing the negations here as separate steps is
4586 * correct : an input NaN should come out with its sign bit
4587 * flipped if it is a negated-input.
4590 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4594 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4597 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4599 write_fp_sreg(s
, rd
, tcg_res
);
4601 tcg_temp_free_ptr(fpst
);
4602 tcg_temp_free_i32(tcg_op1
);
4603 tcg_temp_free_i32(tcg_op2
);
4604 tcg_temp_free_i32(tcg_op3
);
4605 tcg_temp_free_i32(tcg_res
);
4608 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4609 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4610 int rd
, int rn
, int rm
, int ra
)
4612 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4613 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4614 TCGv_ptr fpst
= get_fpstatus_ptr();
4616 tcg_op1
= read_fp_dreg(s
, rn
);
4617 tcg_op2
= read_fp_dreg(s
, rm
);
4618 tcg_op3
= read_fp_dreg(s
, ra
);
4620 /* These are fused multiply-add, and must be done as one
4621 * floating point operation with no rounding between the
4622 * multiplication and addition steps.
4623 * NB that doing the negations here as separate steps is
4624 * correct : an input NaN should come out with its sign bit
4625 * flipped if it is a negated-input.
4628 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4632 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4635 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4637 write_fp_dreg(s
, rd
, tcg_res
);
4639 tcg_temp_free_ptr(fpst
);
4640 tcg_temp_free_i64(tcg_op1
);
4641 tcg_temp_free_i64(tcg_op2
);
4642 tcg_temp_free_i64(tcg_op3
);
4643 tcg_temp_free_i64(tcg_res
);
4646 /* C3.6.27 Floating point data-processing (3 source)
4647 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4648 * +---+---+---+-----------+------+----+------+----+------+------+------+
4649 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4650 * +---+---+---+-----------+------+----+------+----+------+------+------+
4652 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4654 int type
= extract32(insn
, 22, 2);
4655 int rd
= extract32(insn
, 0, 5);
4656 int rn
= extract32(insn
, 5, 5);
4657 int ra
= extract32(insn
, 10, 5);
4658 int rm
= extract32(insn
, 16, 5);
4659 bool o0
= extract32(insn
, 15, 1);
4660 bool o1
= extract32(insn
, 21, 1);
4664 if (!fp_access_check(s
)) {
4667 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4670 if (!fp_access_check(s
)) {
4673 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4676 unallocated_encoding(s
);
4680 /* C3.6.28 Floating point immediate
4681 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4682 * +---+---+---+-----------+------+---+------------+-------+------+------+
4683 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4684 * +---+---+---+-----------+------+---+------------+-------+------+------+
4686 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4688 int rd
= extract32(insn
, 0, 5);
4689 int imm8
= extract32(insn
, 13, 8);
4690 int is_double
= extract32(insn
, 22, 2);
4694 if (is_double
> 1) {
4695 unallocated_encoding(s
);
4699 if (!fp_access_check(s
)) {
4703 /* The imm8 encodes the sign bit, enough bits to represent
4704 * an exponent in the range 01....1xx to 10....0xx,
4705 * and the most significant 4 bits of the mantissa; see
4706 * VFPExpandImm() in the v8 ARM ARM.
4709 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4710 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4711 extract32(imm8
, 0, 6);
4714 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4715 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4716 (extract32(imm8
, 0, 6) << 3);
4720 tcg_res
= tcg_const_i64(imm
);
4721 write_fp_dreg(s
, rd
, tcg_res
);
4722 tcg_temp_free_i64(tcg_res
);
4725 /* Handle floating point <=> fixed point conversions. Note that we can
4726 * also deal with fp <=> integer conversions as a special case (scale == 64)
4727 * OPTME: consider handling that special case specially or at least skipping
4728 * the call to scalbn in the helpers for zero shifts.
4730 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4731 bool itof
, int rmode
, int scale
, int sf
, int type
)
4733 bool is_signed
= !(opcode
& 1);
4734 bool is_double
= type
;
4735 TCGv_ptr tcg_fpstatus
;
4738 tcg_fpstatus
= get_fpstatus_ptr();
4740 tcg_shift
= tcg_const_i32(64 - scale
);
4743 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4745 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4748 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4750 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4753 tcg_int
= tcg_extend
;
4757 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4759 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4760 tcg_shift
, tcg_fpstatus
);
4762 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4763 tcg_shift
, tcg_fpstatus
);
4765 write_fp_dreg(s
, rd
, tcg_double
);
4766 tcg_temp_free_i64(tcg_double
);
4768 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4770 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4771 tcg_shift
, tcg_fpstatus
);
4773 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4774 tcg_shift
, tcg_fpstatus
);
4776 write_fp_sreg(s
, rd
, tcg_single
);
4777 tcg_temp_free_i32(tcg_single
);
4780 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4783 if (extract32(opcode
, 2, 1)) {
4784 /* There are too many rounding modes to all fit into rmode,
4785 * so FCVTA[US] is a special case.
4787 rmode
= FPROUNDING_TIEAWAY
;
4790 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4792 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4795 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4798 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4799 tcg_shift
, tcg_fpstatus
);
4801 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4802 tcg_shift
, tcg_fpstatus
);
4806 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4807 tcg_shift
, tcg_fpstatus
);
4809 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4810 tcg_shift
, tcg_fpstatus
);
4813 tcg_temp_free_i64(tcg_double
);
4815 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4818 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4819 tcg_shift
, tcg_fpstatus
);
4821 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4822 tcg_shift
, tcg_fpstatus
);
4825 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4827 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4828 tcg_shift
, tcg_fpstatus
);
4830 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4831 tcg_shift
, tcg_fpstatus
);
4833 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4834 tcg_temp_free_i32(tcg_dest
);
4836 tcg_temp_free_i32(tcg_single
);
4839 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4840 tcg_temp_free_i32(tcg_rmode
);
4843 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4847 tcg_temp_free_ptr(tcg_fpstatus
);
4848 tcg_temp_free_i32(tcg_shift
);
4851 /* C3.6.29 Floating point <-> fixed point conversions
4852 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4853 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4854 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4855 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4857 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4859 int rd
= extract32(insn
, 0, 5);
4860 int rn
= extract32(insn
, 5, 5);
4861 int scale
= extract32(insn
, 10, 6);
4862 int opcode
= extract32(insn
, 16, 3);
4863 int rmode
= extract32(insn
, 19, 2);
4864 int type
= extract32(insn
, 22, 2);
4865 bool sbit
= extract32(insn
, 29, 1);
4866 bool sf
= extract32(insn
, 31, 1);
4869 if (sbit
|| (type
> 1)
4870 || (!sf
&& scale
< 32)) {
4871 unallocated_encoding(s
);
4875 switch ((rmode
<< 3) | opcode
) {
4876 case 0x2: /* SCVTF */
4877 case 0x3: /* UCVTF */
4880 case 0x18: /* FCVTZS */
4881 case 0x19: /* FCVTZU */
4885 unallocated_encoding(s
);
4889 if (!fp_access_check(s
)) {
4893 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4896 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4898 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4899 * without conversion.
4903 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4909 TCGv_i64 tmp
= tcg_temp_new_i64();
4910 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4911 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4912 tcg_gen_movi_i64(tmp
, 0);
4913 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4914 tcg_temp_free_i64(tmp
);
4920 TCGv_i64 tmp
= tcg_const_i64(0);
4921 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4922 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4923 tcg_temp_free_i64(tmp
);
4927 /* 64 bit to top half. */
4928 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4932 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4937 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
4941 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
4944 /* 64 bits from top half */
4945 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
4951 /* C3.6.30 Floating point <-> integer conversions
4952 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4953 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4954 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4955 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4957 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4959 int rd
= extract32(insn
, 0, 5);
4960 int rn
= extract32(insn
, 5, 5);
4961 int opcode
= extract32(insn
, 16, 3);
4962 int rmode
= extract32(insn
, 19, 2);
4963 int type
= extract32(insn
, 22, 2);
4964 bool sbit
= extract32(insn
, 29, 1);
4965 bool sf
= extract32(insn
, 31, 1);
4968 unallocated_encoding(s
);
4974 bool itof
= opcode
& 1;
4977 unallocated_encoding(s
);
4981 switch (sf
<< 3 | type
<< 1 | rmode
) {
4982 case 0x0: /* 32 bit */
4983 case 0xa: /* 64 bit */
4984 case 0xd: /* 64 bit to top half of quad */
4987 /* all other sf/type/rmode combinations are invalid */
4988 unallocated_encoding(s
);
4992 if (!fp_access_check(s
)) {
4995 handle_fmov(s
, rd
, rn
, type
, itof
);
4997 /* actual FP conversions */
4998 bool itof
= extract32(opcode
, 1, 1);
5000 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5001 unallocated_encoding(s
);
5005 if (!fp_access_check(s
)) {
5008 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5012 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5013 * 31 30 29 28 25 24 0
5014 * +---+---+---+---------+-----------------------------+
5015 * | | 0 | | 1 1 1 1 | |
5016 * +---+---+---+---------+-----------------------------+
5018 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5020 if (extract32(insn
, 24, 1)) {
5021 /* Floating point data-processing (3 source) */
5022 disas_fp_3src(s
, insn
);
5023 } else if (extract32(insn
, 21, 1) == 0) {
5024 /* Floating point to fixed point conversions */
5025 disas_fp_fixed_conv(s
, insn
);
5027 switch (extract32(insn
, 10, 2)) {
5029 /* Floating point conditional compare */
5030 disas_fp_ccomp(s
, insn
);
5033 /* Floating point data-processing (2 source) */
5034 disas_fp_2src(s
, insn
);
5037 /* Floating point conditional select */
5038 disas_fp_csel(s
, insn
);
5041 switch (ctz32(extract32(insn
, 12, 4))) {
5042 case 0: /* [15:12] == xxx1 */
5043 /* Floating point immediate */
5044 disas_fp_imm(s
, insn
);
5046 case 1: /* [15:12] == xx10 */
5047 /* Floating point compare */
5048 disas_fp_compare(s
, insn
);
5050 case 2: /* [15:12] == x100 */
5051 /* Floating point data-processing (1 source) */
5052 disas_fp_1src(s
, insn
);
5054 case 3: /* [15:12] == 1000 */
5055 unallocated_encoding(s
);
5057 default: /* [15:12] == 0000 */
5058 /* Floating point <-> integer conversions */
5059 disas_fp_int_conv(s
, insn
);
5067 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5070 /* Extract 64 bits from the middle of two concatenated 64 bit
5071 * vector register slices left:right. The extracted bits start
5072 * at 'pos' bits into the right (least significant) side.
5073 * We return the result in tcg_right, and guarantee not to
5076 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5077 assert(pos
> 0 && pos
< 64);
5079 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5080 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5081 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5083 tcg_temp_free_i64(tcg_tmp
);
5087 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5088 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5089 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5090 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5092 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5094 int is_q
= extract32(insn
, 30, 1);
5095 int op2
= extract32(insn
, 22, 2);
5096 int imm4
= extract32(insn
, 11, 4);
5097 int rm
= extract32(insn
, 16, 5);
5098 int rn
= extract32(insn
, 5, 5);
5099 int rd
= extract32(insn
, 0, 5);
5100 int pos
= imm4
<< 3;
5101 TCGv_i64 tcg_resl
, tcg_resh
;
5103 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5104 unallocated_encoding(s
);
5108 if (!fp_access_check(s
)) {
5112 tcg_resh
= tcg_temp_new_i64();
5113 tcg_resl
= tcg_temp_new_i64();
5115 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5116 * either extracting 128 bits from a 128:128 concatenation, or
5117 * extracting 64 bits from a 64:64 concatenation.
5120 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5122 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5123 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5125 tcg_gen_movi_i64(tcg_resh
, 0);
5132 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5133 EltPosns
*elt
= eltposns
;
5140 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5142 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5145 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5146 tcg_hh
= tcg_temp_new_i64();
5147 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5148 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5149 tcg_temp_free_i64(tcg_hh
);
5153 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5154 tcg_temp_free_i64(tcg_resl
);
5155 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5156 tcg_temp_free_i64(tcg_resh
);
5160 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5161 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5162 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5163 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5165 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5167 int op2
= extract32(insn
, 22, 2);
5168 int is_q
= extract32(insn
, 30, 1);
5169 int rm
= extract32(insn
, 16, 5);
5170 int rn
= extract32(insn
, 5, 5);
5171 int rd
= extract32(insn
, 0, 5);
5172 int is_tblx
= extract32(insn
, 12, 1);
5173 int len
= extract32(insn
, 13, 2);
5174 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5175 TCGv_i32 tcg_regno
, tcg_numregs
;
5178 unallocated_encoding(s
);
5182 if (!fp_access_check(s
)) {
5186 /* This does a table lookup: for every byte element in the input
5187 * we index into a table formed from up to four vector registers,
5188 * and then the output is the result of the lookups. Our helper
5189 * function does the lookup operation for a single 64 bit part of
5192 tcg_resl
= tcg_temp_new_i64();
5193 tcg_resh
= tcg_temp_new_i64();
5196 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5198 tcg_gen_movi_i64(tcg_resl
, 0);
5200 if (is_tblx
&& is_q
) {
5201 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5203 tcg_gen_movi_i64(tcg_resh
, 0);
5206 tcg_idx
= tcg_temp_new_i64();
5207 tcg_regno
= tcg_const_i32(rn
);
5208 tcg_numregs
= tcg_const_i32(len
+ 1);
5209 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5210 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5211 tcg_regno
, tcg_numregs
);
5213 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5214 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5215 tcg_regno
, tcg_numregs
);
5217 tcg_temp_free_i64(tcg_idx
);
5218 tcg_temp_free_i32(tcg_regno
);
5219 tcg_temp_free_i32(tcg_numregs
);
5221 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5222 tcg_temp_free_i64(tcg_resl
);
5223 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5224 tcg_temp_free_i64(tcg_resh
);
5227 /* C3.6.3 ZIP/UZP/TRN
5228 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5229 * +---+---+-------------+------+---+------+---+------------------+------+
5230 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5231 * +---+---+-------------+------+---+------+---+------------------+------+
5233 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5235 int rd
= extract32(insn
, 0, 5);
5236 int rn
= extract32(insn
, 5, 5);
5237 int rm
= extract32(insn
, 16, 5);
5238 int size
= extract32(insn
, 22, 2);
5239 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5240 * bit 2 indicates 1 vs 2 variant of the insn.
5242 int opcode
= extract32(insn
, 12, 2);
5243 bool part
= extract32(insn
, 14, 1);
5244 bool is_q
= extract32(insn
, 30, 1);
5245 int esize
= 8 << size
;
5247 int datasize
= is_q
? 128 : 64;
5248 int elements
= datasize
/ esize
;
5249 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5251 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5252 unallocated_encoding(s
);
5256 if (!fp_access_check(s
)) {
5260 tcg_resl
= tcg_const_i64(0);
5261 tcg_resh
= tcg_const_i64(0);
5262 tcg_res
= tcg_temp_new_i64();
5264 for (i
= 0; i
< elements
; i
++) {
5266 case 1: /* UZP1/2 */
5268 int midpoint
= elements
/ 2;
5270 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5272 read_vec_element(s
, tcg_res
, rm
,
5273 2 * (i
- midpoint
) + part
, size
);
5277 case 2: /* TRN1/2 */
5279 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5281 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5284 case 3: /* ZIP1/2 */
5286 int base
= part
* elements
/ 2;
5288 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5290 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5295 g_assert_not_reached();
5300 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5301 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5303 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5304 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5308 tcg_temp_free_i64(tcg_res
);
5310 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5311 tcg_temp_free_i64(tcg_resl
);
5312 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5313 tcg_temp_free_i64(tcg_resh
);
5316 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5317 int opc
, bool is_min
, TCGv_ptr fpst
)
5319 /* Helper function for disas_simd_across_lanes: do a single precision
5320 * min/max operation on the specified two inputs,
5321 * and return the result in tcg_elt1.
5325 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5327 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5332 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5334 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5339 /* C3.6.4 AdvSIMD across lanes
5340 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5341 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5342 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5343 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5345 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5347 int rd
= extract32(insn
, 0, 5);
5348 int rn
= extract32(insn
, 5, 5);
5349 int size
= extract32(insn
, 22, 2);
5350 int opcode
= extract32(insn
, 12, 5);
5351 bool is_q
= extract32(insn
, 30, 1);
5352 bool is_u
= extract32(insn
, 29, 1);
5354 bool is_min
= false;
5358 TCGv_i64 tcg_res
, tcg_elt
;
5361 case 0x1b: /* ADDV */
5363 unallocated_encoding(s
);
5367 case 0x3: /* SADDLV, UADDLV */
5368 case 0xa: /* SMAXV, UMAXV */
5369 case 0x1a: /* SMINV, UMINV */
5370 if (size
== 3 || (size
== 2 && !is_q
)) {
5371 unallocated_encoding(s
);
5375 case 0xc: /* FMAXNMV, FMINNMV */
5376 case 0xf: /* FMAXV, FMINV */
5377 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5378 unallocated_encoding(s
);
5381 /* Bit 1 of size field encodes min vs max, and actual size is always
5382 * 32 bits: adjust the size variable so following code can rely on it
5384 is_min
= extract32(size
, 1, 1);
5389 unallocated_encoding(s
);
5393 if (!fp_access_check(s
)) {
5398 elements
= (is_q
? 128 : 64) / esize
;
5400 tcg_res
= tcg_temp_new_i64();
5401 tcg_elt
= tcg_temp_new_i64();
5403 /* These instructions operate across all lanes of a vector
5404 * to produce a single result. We can guarantee that a 64
5405 * bit intermediate is sufficient:
5406 * + for [US]ADDLV the maximum element size is 32 bits, and
5407 * the result type is 64 bits
5408 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5409 * same as the element size, which is 32 bits at most
5410 * For the integer operations we can choose to work at 64
5411 * or 32 bits and truncate at the end; for simplicity
5412 * we use 64 bits always. The floating point
5413 * ops do require 32 bit intermediates, though.
5416 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5418 for (i
= 1; i
< elements
; i
++) {
5419 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5422 case 0x03: /* SADDLV / UADDLV */
5423 case 0x1b: /* ADDV */
5424 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5426 case 0x0a: /* SMAXV / UMAXV */
5427 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5429 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5431 case 0x1a: /* SMINV / UMINV */
5432 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5434 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5438 g_assert_not_reached();
5443 /* Floating point ops which work on 32 bit (single) intermediates.
5444 * Note that correct NaN propagation requires that we do these
5445 * operations in exactly the order specified by the pseudocode.
5447 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5448 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5449 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5450 TCGv_ptr fpst
= get_fpstatus_ptr();
5452 assert(esize
== 32);
5453 assert(elements
== 4);
5455 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5456 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5457 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5458 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5460 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5462 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5463 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5464 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5465 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5467 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5469 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5471 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5472 tcg_temp_free_i32(tcg_elt1
);
5473 tcg_temp_free_i32(tcg_elt2
);
5474 tcg_temp_free_i32(tcg_elt3
);
5475 tcg_temp_free_ptr(fpst
);
5478 tcg_temp_free_i64(tcg_elt
);
5480 /* Now truncate the result to the width required for the final output */
5481 if (opcode
== 0x03) {
5482 /* SADDLV, UADDLV: result is 2*esize */
5488 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5491 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5494 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5499 g_assert_not_reached();
5502 write_fp_dreg(s
, rd
, tcg_res
);
5503 tcg_temp_free_i64(tcg_res
);
5506 /* C6.3.31 DUP (Element, Vector)
5508 * 31 30 29 21 20 16 15 10 9 5 4 0
5509 * +---+---+-------------------+--------+-------------+------+------+
5510 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5511 * +---+---+-------------------+--------+-------------+------+------+
5513 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5515 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5518 int size
= ctz32(imm5
);
5519 int esize
= 8 << size
;
5520 int elements
= (is_q
? 128 : 64) / esize
;
5524 if (size
> 3 || (size
== 3 && !is_q
)) {
5525 unallocated_encoding(s
);
5529 if (!fp_access_check(s
)) {
5533 index
= imm5
>> (size
+ 1);
5535 tmp
= tcg_temp_new_i64();
5536 read_vec_element(s
, tmp
, rn
, index
, size
);
5538 for (i
= 0; i
< elements
; i
++) {
5539 write_vec_element(s
, tmp
, rd
, i
, size
);
5543 clear_vec_high(s
, rd
);
5546 tcg_temp_free_i64(tmp
);
5549 /* C6.3.31 DUP (element, scalar)
5550 * 31 21 20 16 15 10 9 5 4 0
5551 * +-----------------------+--------+-------------+------+------+
5552 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5553 * +-----------------------+--------+-------------+------+------+
5555 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5558 int size
= ctz32(imm5
);
5563 unallocated_encoding(s
);
5567 if (!fp_access_check(s
)) {
5571 index
= imm5
>> (size
+ 1);
5573 /* This instruction just extracts the specified element and
5574 * zero-extends it into the bottom of the destination register.
5576 tmp
= tcg_temp_new_i64();
5577 read_vec_element(s
, tmp
, rn
, index
, size
);
5578 write_fp_dreg(s
, rd
, tmp
);
5579 tcg_temp_free_i64(tmp
);
5582 /* C6.3.32 DUP (General)
5584 * 31 30 29 21 20 16 15 10 9 5 4 0
5585 * +---+---+-------------------+--------+-------------+------+------+
5586 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5587 * +---+---+-------------------+--------+-------------+------+------+
5589 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5591 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5594 int size
= ctz32(imm5
);
5595 int esize
= 8 << size
;
5596 int elements
= (is_q
? 128 : 64)/esize
;
5599 if (size
> 3 || ((size
== 3) && !is_q
)) {
5600 unallocated_encoding(s
);
5604 if (!fp_access_check(s
)) {
5608 for (i
= 0; i
< elements
; i
++) {
5609 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5612 clear_vec_high(s
, rd
);
5616 /* C6.3.150 INS (Element)
5618 * 31 21 20 16 15 14 11 10 9 5 4 0
5619 * +-----------------------+--------+------------+---+------+------+
5620 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5621 * +-----------------------+--------+------------+---+------+------+
5623 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5624 * index: encoded in imm5<4:size+1>
5626 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5629 int size
= ctz32(imm5
);
5630 int src_index
, dst_index
;
5634 unallocated_encoding(s
);
5638 if (!fp_access_check(s
)) {
5642 dst_index
= extract32(imm5
, 1+size
, 5);
5643 src_index
= extract32(imm4
, size
, 4);
5645 tmp
= tcg_temp_new_i64();
5647 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5648 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5650 tcg_temp_free_i64(tmp
);
5654 /* C6.3.151 INS (General)
5656 * 31 21 20 16 15 10 9 5 4 0
5657 * +-----------------------+--------+-------------+------+------+
5658 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5659 * +-----------------------+--------+-------------+------+------+
5661 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5662 * index: encoded in imm5<4:size+1>
5664 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5666 int size
= ctz32(imm5
);
5670 unallocated_encoding(s
);
5674 if (!fp_access_check(s
)) {
5678 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5679 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5683 * C6.3.321 UMOV (General)
5684 * C6.3.237 SMOV (General)
5686 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5687 * +---+---+-------------------+--------+-------------+------+------+
5688 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5689 * +---+---+-------------------+--------+-------------+------+------+
5691 * U: unsigned when set
5692 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5694 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5695 int rn
, int rd
, int imm5
)
5697 int size
= ctz32(imm5
);
5701 /* Check for UnallocatedEncodings */
5703 if (size
> 2 || (size
== 2 && !is_q
)) {
5704 unallocated_encoding(s
);
5709 || (size
< 3 && is_q
)
5710 || (size
== 3 && !is_q
)) {
5711 unallocated_encoding(s
);
5716 if (!fp_access_check(s
)) {
5720 element
= extract32(imm5
, 1+size
, 4);
5722 tcg_rd
= cpu_reg(s
, rd
);
5723 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5724 if (is_signed
&& !is_q
) {
5725 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5729 /* C3.6.5 AdvSIMD copy
5730 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5731 * +---+---+----+-----------------+------+---+------+---+------+------+
5732 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5733 * +---+---+----+-----------------+------+---+------+---+------+------+
5735 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5737 int rd
= extract32(insn
, 0, 5);
5738 int rn
= extract32(insn
, 5, 5);
5739 int imm4
= extract32(insn
, 11, 4);
5740 int op
= extract32(insn
, 29, 1);
5741 int is_q
= extract32(insn
, 30, 1);
5742 int imm5
= extract32(insn
, 16, 5);
5747 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5749 unallocated_encoding(s
);
5754 /* DUP (element - vector) */
5755 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5759 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5764 handle_simd_insg(s
, rd
, rn
, imm5
);
5766 unallocated_encoding(s
);
5771 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5772 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5775 unallocated_encoding(s
);
5781 /* C3.6.6 AdvSIMD modified immediate
5782 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5783 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5784 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5785 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5787 * There are a number of operations that can be carried out here:
5788 * MOVI - move (shifted) imm into register
5789 * MVNI - move inverted (shifted) imm into register
5790 * ORR - bitwise OR of (shifted) imm with register
5791 * BIC - bitwise clear of (shifted) imm with register
5793 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5795 int rd
= extract32(insn
, 0, 5);
5796 int cmode
= extract32(insn
, 12, 4);
5797 int cmode_3_1
= extract32(cmode
, 1, 3);
5798 int cmode_0
= extract32(cmode
, 0, 1);
5799 int o2
= extract32(insn
, 11, 1);
5800 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5801 bool is_neg
= extract32(insn
, 29, 1);
5802 bool is_q
= extract32(insn
, 30, 1);
5804 TCGv_i64 tcg_rd
, tcg_imm
;
5807 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5808 unallocated_encoding(s
);
5812 if (!fp_access_check(s
)) {
5816 /* See AdvSIMDExpandImm() in ARM ARM */
5817 switch (cmode_3_1
) {
5818 case 0: /* Replicate(Zeros(24):imm8, 2) */
5819 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5820 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5821 case 3: /* Replicate(imm8:Zeros(24), 2) */
5823 int shift
= cmode_3_1
* 8;
5824 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5827 case 4: /* Replicate(Zeros(8):imm8, 4) */
5828 case 5: /* Replicate(imm8:Zeros(8), 4) */
5830 int shift
= (cmode_3_1
& 0x1) * 8;
5831 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5836 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5837 imm
= (abcdefgh
<< 16) | 0xffff;
5839 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5840 imm
= (abcdefgh
<< 8) | 0xff;
5842 imm
= bitfield_replicate(imm
, 32);
5845 if (!cmode_0
&& !is_neg
) {
5846 imm
= bitfield_replicate(abcdefgh
, 8);
5847 } else if (!cmode_0
&& is_neg
) {
5850 for (i
= 0; i
< 8; i
++) {
5851 if ((abcdefgh
) & (1 << i
)) {
5852 imm
|= 0xffULL
<< (i
* 8);
5855 } else if (cmode_0
) {
5857 imm
= (abcdefgh
& 0x3f) << 48;
5858 if (abcdefgh
& 0x80) {
5859 imm
|= 0x8000000000000000ULL
;
5861 if (abcdefgh
& 0x40) {
5862 imm
|= 0x3fc0000000000000ULL
;
5864 imm
|= 0x4000000000000000ULL
;
5867 imm
= (abcdefgh
& 0x3f) << 19;
5868 if (abcdefgh
& 0x80) {
5871 if (abcdefgh
& 0x40) {
5882 if (cmode_3_1
!= 7 && is_neg
) {
5886 tcg_imm
= tcg_const_i64(imm
);
5887 tcg_rd
= new_tmp_a64(s
);
5889 for (i
= 0; i
< 2; i
++) {
5890 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
5892 if (i
== 1 && !is_q
) {
5893 /* non-quad ops clear high half of vector */
5894 tcg_gen_movi_i64(tcg_rd
, 0);
5895 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5896 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5899 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5902 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5906 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5908 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5911 tcg_temp_free_i64(tcg_imm
);
5914 /* C3.6.7 AdvSIMD scalar copy
5915 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5916 * +-----+----+-----------------+------+---+------+---+------+------+
5917 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5918 * +-----+----+-----------------+------+---+------+---+------+------+
5920 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5922 int rd
= extract32(insn
, 0, 5);
5923 int rn
= extract32(insn
, 5, 5);
5924 int imm4
= extract32(insn
, 11, 4);
5925 int imm5
= extract32(insn
, 16, 5);
5926 int op
= extract32(insn
, 29, 1);
5928 if (op
!= 0 || imm4
!= 0) {
5929 unallocated_encoding(s
);
5933 /* DUP (element, scalar) */
5934 handle_simd_dupes(s
, rd
, rn
, imm5
);
5937 /* C3.6.8 AdvSIMD scalar pairwise
5938 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5939 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5940 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5941 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5943 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5945 int u
= extract32(insn
, 29, 1);
5946 int size
= extract32(insn
, 22, 2);
5947 int opcode
= extract32(insn
, 12, 5);
5948 int rn
= extract32(insn
, 5, 5);
5949 int rd
= extract32(insn
, 0, 5);
5952 /* For some ops (the FP ones), size[1] is part of the encoding.
5953 * For ADDP strictly it is not but size[1] is always 1 for valid
5956 opcode
|= (extract32(size
, 1, 1) << 5);
5959 case 0x3b: /* ADDP */
5960 if (u
|| size
!= 3) {
5961 unallocated_encoding(s
);
5964 if (!fp_access_check(s
)) {
5968 TCGV_UNUSED_PTR(fpst
);
5970 case 0xc: /* FMAXNMP */
5971 case 0xd: /* FADDP */
5972 case 0xf: /* FMAXP */
5973 case 0x2c: /* FMINNMP */
5974 case 0x2f: /* FMINP */
5975 /* FP op, size[0] is 32 or 64 bit */
5977 unallocated_encoding(s
);
5980 if (!fp_access_check(s
)) {
5984 size
= extract32(size
, 0, 1) ? 3 : 2;
5985 fpst
= get_fpstatus_ptr();
5988 unallocated_encoding(s
);
5993 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5994 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5995 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5997 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5998 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6001 case 0x3b: /* ADDP */
6002 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6004 case 0xc: /* FMAXNMP */
6005 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6007 case 0xd: /* FADDP */
6008 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6010 case 0xf: /* FMAXP */
6011 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6013 case 0x2c: /* FMINNMP */
6014 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6016 case 0x2f: /* FMINP */
6017 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6020 g_assert_not_reached();
6023 write_fp_dreg(s
, rd
, tcg_res
);
6025 tcg_temp_free_i64(tcg_op1
);
6026 tcg_temp_free_i64(tcg_op2
);
6027 tcg_temp_free_i64(tcg_res
);
6029 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6030 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6031 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6033 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6034 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6037 case 0xc: /* FMAXNMP */
6038 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6040 case 0xd: /* FADDP */
6041 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6043 case 0xf: /* FMAXP */
6044 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6046 case 0x2c: /* FMINNMP */
6047 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6049 case 0x2f: /* FMINP */
6050 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6053 g_assert_not_reached();
6056 write_fp_sreg(s
, rd
, tcg_res
);
6058 tcg_temp_free_i32(tcg_op1
);
6059 tcg_temp_free_i32(tcg_op2
);
6060 tcg_temp_free_i32(tcg_res
);
6063 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6064 tcg_temp_free_ptr(fpst
);
6069 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6071 * This code is handles the common shifting code and is used by both
6072 * the vector and scalar code.
6074 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6075 TCGv_i64 tcg_rnd
, bool accumulate
,
6076 bool is_u
, int size
, int shift
)
6078 bool extended_result
= false;
6079 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6081 TCGv_i64 tcg_src_hi
;
6083 if (round
&& size
== 3) {
6084 extended_result
= true;
6085 ext_lshift
= 64 - shift
;
6086 tcg_src_hi
= tcg_temp_new_i64();
6087 } else if (shift
== 64) {
6088 if (!accumulate
&& is_u
) {
6089 /* result is zero */
6090 tcg_gen_movi_i64(tcg_res
, 0);
6095 /* Deal with the rounding step */
6097 if (extended_result
) {
6098 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6100 /* take care of sign extending tcg_res */
6101 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6102 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6103 tcg_src
, tcg_src_hi
,
6106 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6110 tcg_temp_free_i64(tcg_zero
);
6112 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6116 /* Now do the shift right */
6117 if (round
&& extended_result
) {
6118 /* extended case, >64 bit precision required */
6119 if (ext_lshift
== 0) {
6120 /* special case, only high bits matter */
6121 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6123 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6124 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6125 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6130 /* essentially shifting in 64 zeros */
6131 tcg_gen_movi_i64(tcg_src
, 0);
6133 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6137 /* effectively extending the sign-bit */
6138 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6140 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6146 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6148 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6151 if (extended_result
) {
6152 tcg_temp_free_i64(tcg_src_hi
);
6156 /* Common SHL/SLI - Shift left with an optional insert */
6157 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6158 bool insert
, int shift
)
6160 if (insert
) { /* SLI */
6161 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6163 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6167 /* SRI: shift right with insert */
6168 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6169 int size
, int shift
)
6171 int esize
= 8 << size
;
6173 /* shift count same as element size is valid but does nothing;
6174 * special case to avoid potential shift by 64.
6176 if (shift
!= esize
) {
6177 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6178 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6182 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6183 static void handle_scalar_simd_shri(DisasContext
*s
,
6184 bool is_u
, int immh
, int immb
,
6185 int opcode
, int rn
, int rd
)
6188 int immhb
= immh
<< 3 | immb
;
6189 int shift
= 2 * (8 << size
) - immhb
;
6190 bool accumulate
= false;
6192 bool insert
= false;
6197 if (!extract32(immh
, 3, 1)) {
6198 unallocated_encoding(s
);
6202 if (!fp_access_check(s
)) {
6207 case 0x02: /* SSRA / USRA (accumulate) */
6210 case 0x04: /* SRSHR / URSHR (rounding) */
6213 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6214 accumulate
= round
= true;
6216 case 0x08: /* SRI */
6222 uint64_t round_const
= 1ULL << (shift
- 1);
6223 tcg_round
= tcg_const_i64(round_const
);
6225 TCGV_UNUSED_I64(tcg_round
);
6228 tcg_rn
= read_fp_dreg(s
, rn
);
6229 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6232 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6234 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6235 accumulate
, is_u
, size
, shift
);
6238 write_fp_dreg(s
, rd
, tcg_rd
);
6240 tcg_temp_free_i64(tcg_rn
);
6241 tcg_temp_free_i64(tcg_rd
);
6243 tcg_temp_free_i64(tcg_round
);
6247 /* SHL/SLI - Scalar shift left */
6248 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6249 int immh
, int immb
, int opcode
,
6252 int size
= 32 - clz32(immh
) - 1;
6253 int immhb
= immh
<< 3 | immb
;
6254 int shift
= immhb
- (8 << size
);
6255 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6256 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6258 if (!extract32(immh
, 3, 1)) {
6259 unallocated_encoding(s
);
6263 if (!fp_access_check(s
)) {
6267 tcg_rn
= read_fp_dreg(s
, rn
);
6268 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6270 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6272 write_fp_dreg(s
, rd
, tcg_rd
);
6274 tcg_temp_free_i64(tcg_rn
);
6275 tcg_temp_free_i64(tcg_rd
);
6278 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6279 * (signed/unsigned) narrowing */
6280 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6281 bool is_u_shift
, bool is_u_narrow
,
6282 int immh
, int immb
, int opcode
,
6285 int immhb
= immh
<< 3 | immb
;
6286 int size
= 32 - clz32(immh
) - 1;
6287 int esize
= 8 << size
;
6288 int shift
= (2 * esize
) - immhb
;
6289 int elements
= is_scalar
? 1 : (64 / esize
);
6290 bool round
= extract32(opcode
, 0, 1);
6291 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6292 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6293 TCGv_i32 tcg_rd_narrowed
;
6296 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6297 { gen_helper_neon_narrow_sat_s8
,
6298 gen_helper_neon_unarrow_sat8
},
6299 { gen_helper_neon_narrow_sat_s16
,
6300 gen_helper_neon_unarrow_sat16
},
6301 { gen_helper_neon_narrow_sat_s32
,
6302 gen_helper_neon_unarrow_sat32
},
6305 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6306 gen_helper_neon_narrow_sat_u8
,
6307 gen_helper_neon_narrow_sat_u16
,
6308 gen_helper_neon_narrow_sat_u32
,
6311 NeonGenNarrowEnvFn
*narrowfn
;
6317 if (extract32(immh
, 3, 1)) {
6318 unallocated_encoding(s
);
6322 if (!fp_access_check(s
)) {
6327 narrowfn
= unsigned_narrow_fns
[size
];
6329 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6332 tcg_rn
= tcg_temp_new_i64();
6333 tcg_rd
= tcg_temp_new_i64();
6334 tcg_rd_narrowed
= tcg_temp_new_i32();
6335 tcg_final
= tcg_const_i64(0);
6338 uint64_t round_const
= 1ULL << (shift
- 1);
6339 tcg_round
= tcg_const_i64(round_const
);
6341 TCGV_UNUSED_I64(tcg_round
);
6344 for (i
= 0; i
< elements
; i
++) {
6345 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6346 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6347 false, is_u_shift
, size
+1, shift
);
6348 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6349 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6350 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6354 clear_vec_high(s
, rd
);
6355 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6357 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6361 tcg_temp_free_i64(tcg_round
);
6363 tcg_temp_free_i64(tcg_rn
);
6364 tcg_temp_free_i64(tcg_rd
);
6365 tcg_temp_free_i32(tcg_rd_narrowed
);
6366 tcg_temp_free_i64(tcg_final
);
6370 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6371 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6372 bool src_unsigned
, bool dst_unsigned
,
6373 int immh
, int immb
, int rn
, int rd
)
6375 int immhb
= immh
<< 3 | immb
;
6376 int size
= 32 - clz32(immh
) - 1;
6377 int shift
= immhb
- (8 << size
);
6381 assert(!(scalar
&& is_q
));
6384 if (!is_q
&& extract32(immh
, 3, 1)) {
6385 unallocated_encoding(s
);
6389 /* Since we use the variable-shift helpers we must
6390 * replicate the shift count into each element of
6391 * the tcg_shift value.
6395 shift
|= shift
<< 8;
6398 shift
|= shift
<< 16;
6404 g_assert_not_reached();
6408 if (!fp_access_check(s
)) {
6413 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6414 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6415 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6416 { NULL
, gen_helper_neon_qshl_u64
},
6418 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6419 int maxpass
= is_q
? 2 : 1;
6421 for (pass
= 0; pass
< maxpass
; pass
++) {
6422 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6424 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6425 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6426 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6428 tcg_temp_free_i64(tcg_op
);
6430 tcg_temp_free_i64(tcg_shift
);
6433 clear_vec_high(s
, rd
);
6436 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6437 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6439 { gen_helper_neon_qshl_s8
,
6440 gen_helper_neon_qshl_s16
,
6441 gen_helper_neon_qshl_s32
},
6442 { gen_helper_neon_qshlu_s8
,
6443 gen_helper_neon_qshlu_s16
,
6444 gen_helper_neon_qshlu_s32
}
6446 { NULL
, NULL
, NULL
},
6447 { gen_helper_neon_qshl_u8
,
6448 gen_helper_neon_qshl_u16
,
6449 gen_helper_neon_qshl_u32
}
6452 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6453 TCGMemOp memop
= scalar
? size
: MO_32
;
6454 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6456 for (pass
= 0; pass
< maxpass
; pass
++) {
6457 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6459 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6460 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6464 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6467 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6472 g_assert_not_reached();
6474 write_fp_sreg(s
, rd
, tcg_op
);
6476 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6479 tcg_temp_free_i32(tcg_op
);
6481 tcg_temp_free_i32(tcg_shift
);
6483 if (!is_q
&& !scalar
) {
6484 clear_vec_high(s
, rd
);
6489 /* Common vector code for handling integer to FP conversion */
6490 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6491 int elements
, int is_signed
,
6492 int fracbits
, int size
)
6494 bool is_double
= size
== 3 ? true : false;
6495 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6496 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6497 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6498 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6501 for (pass
= 0; pass
< elements
; pass
++) {
6502 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6505 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6507 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6508 tcg_shift
, tcg_fpst
);
6510 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6511 tcg_shift
, tcg_fpst
);
6513 if (elements
== 1) {
6514 write_fp_dreg(s
, rd
, tcg_double
);
6516 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6518 tcg_temp_free_i64(tcg_double
);
6520 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6522 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6523 tcg_shift
, tcg_fpst
);
6525 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6526 tcg_shift
, tcg_fpst
);
6528 if (elements
== 1) {
6529 write_fp_sreg(s
, rd
, tcg_single
);
6531 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6533 tcg_temp_free_i32(tcg_single
);
6537 if (!is_double
&& elements
== 2) {
6538 clear_vec_high(s
, rd
);
6541 tcg_temp_free_i64(tcg_int
);
6542 tcg_temp_free_ptr(tcg_fpst
);
6543 tcg_temp_free_i32(tcg_shift
);
6546 /* UCVTF/SCVTF - Integer to FP conversion */
6547 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6548 bool is_q
, bool is_u
,
6549 int immh
, int immb
, int opcode
,
6552 bool is_double
= extract32(immh
, 3, 1);
6553 int size
= is_double
? MO_64
: MO_32
;
6555 int immhb
= immh
<< 3 | immb
;
6556 int fracbits
= (is_double
? 128 : 64) - immhb
;
6558 if (!extract32(immh
, 2, 2)) {
6559 unallocated_encoding(s
);
6566 elements
= is_double
? 2 : is_q
? 4 : 2;
6567 if (is_double
&& !is_q
) {
6568 unallocated_encoding(s
);
6573 if (!fp_access_check(s
)) {
6577 /* immh == 0 would be a failure of the decode logic */
6580 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6583 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6584 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6585 bool is_q
, bool is_u
,
6586 int immh
, int immb
, int rn
, int rd
)
6588 bool is_double
= extract32(immh
, 3, 1);
6589 int immhb
= immh
<< 3 | immb
;
6590 int fracbits
= (is_double
? 128 : 64) - immhb
;
6592 TCGv_ptr tcg_fpstatus
;
6593 TCGv_i32 tcg_rmode
, tcg_shift
;
6595 if (!extract32(immh
, 2, 2)) {
6596 unallocated_encoding(s
);
6600 if (!is_scalar
&& !is_q
&& is_double
) {
6601 unallocated_encoding(s
);
6605 if (!fp_access_check(s
)) {
6609 assert(!(is_scalar
&& is_q
));
6611 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6612 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6613 tcg_fpstatus
= get_fpstatus_ptr();
6614 tcg_shift
= tcg_const_i32(fracbits
);
6617 int maxpass
= is_scalar
? 1 : 2;
6619 for (pass
= 0; pass
< maxpass
; pass
++) {
6620 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6622 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6624 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6626 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6628 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6629 tcg_temp_free_i64(tcg_op
);
6632 clear_vec_high(s
, rd
);
6635 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6636 for (pass
= 0; pass
< maxpass
; pass
++) {
6637 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6639 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6641 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6643 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6646 write_fp_sreg(s
, rd
, tcg_op
);
6648 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6650 tcg_temp_free_i32(tcg_op
);
6652 if (!is_q
&& !is_scalar
) {
6653 clear_vec_high(s
, rd
);
6657 tcg_temp_free_ptr(tcg_fpstatus
);
6658 tcg_temp_free_i32(tcg_shift
);
6659 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6660 tcg_temp_free_i32(tcg_rmode
);
6663 /* C3.6.9 AdvSIMD scalar shift by immediate
6664 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6665 * +-----+---+-------------+------+------+--------+---+------+------+
6666 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6667 * +-----+---+-------------+------+------+--------+---+------+------+
6669 * This is the scalar version so it works on a fixed sized registers
6671 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6673 int rd
= extract32(insn
, 0, 5);
6674 int rn
= extract32(insn
, 5, 5);
6675 int opcode
= extract32(insn
, 11, 5);
6676 int immb
= extract32(insn
, 16, 3);
6677 int immh
= extract32(insn
, 19, 4);
6678 bool is_u
= extract32(insn
, 29, 1);
6681 unallocated_encoding(s
);
6686 case 0x08: /* SRI */
6688 unallocated_encoding(s
);
6692 case 0x00: /* SSHR / USHR */
6693 case 0x02: /* SSRA / USRA */
6694 case 0x04: /* SRSHR / URSHR */
6695 case 0x06: /* SRSRA / URSRA */
6696 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6698 case 0x0a: /* SHL / SLI */
6699 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6701 case 0x1c: /* SCVTF, UCVTF */
6702 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6705 case 0x10: /* SQSHRUN, SQSHRUN2 */
6706 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6708 unallocated_encoding(s
);
6711 handle_vec_simd_sqshrn(s
, true, false, false, true,
6712 immh
, immb
, opcode
, rn
, rd
);
6714 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6715 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6716 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6717 immh
, immb
, opcode
, rn
, rd
);
6719 case 0xc: /* SQSHLU */
6721 unallocated_encoding(s
);
6724 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6726 case 0xe: /* SQSHL, UQSHL */
6727 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6729 case 0x1f: /* FCVTZS, FCVTZU */
6730 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6733 unallocated_encoding(s
);
6738 /* C3.6.10 AdvSIMD scalar three different
6739 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6740 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6741 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6742 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6744 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6746 bool is_u
= extract32(insn
, 29, 1);
6747 int size
= extract32(insn
, 22, 2);
6748 int opcode
= extract32(insn
, 12, 4);
6749 int rm
= extract32(insn
, 16, 5);
6750 int rn
= extract32(insn
, 5, 5);
6751 int rd
= extract32(insn
, 0, 5);
6754 unallocated_encoding(s
);
6759 case 0x9: /* SQDMLAL, SQDMLAL2 */
6760 case 0xb: /* SQDMLSL, SQDMLSL2 */
6761 case 0xd: /* SQDMULL, SQDMULL2 */
6762 if (size
== 0 || size
== 3) {
6763 unallocated_encoding(s
);
6768 unallocated_encoding(s
);
6772 if (!fp_access_check(s
)) {
6777 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6778 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6779 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6781 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6782 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6784 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6785 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6788 case 0xd: /* SQDMULL, SQDMULL2 */
6790 case 0xb: /* SQDMLSL, SQDMLSL2 */
6791 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6793 case 0x9: /* SQDMLAL, SQDMLAL2 */
6794 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6795 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6799 g_assert_not_reached();
6802 write_fp_dreg(s
, rd
, tcg_res
);
6804 tcg_temp_free_i64(tcg_op1
);
6805 tcg_temp_free_i64(tcg_op2
);
6806 tcg_temp_free_i64(tcg_res
);
6808 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6809 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6810 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6812 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6813 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6815 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6816 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6819 case 0xd: /* SQDMULL, SQDMULL2 */
6821 case 0xb: /* SQDMLSL, SQDMLSL2 */
6822 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6824 case 0x9: /* SQDMLAL, SQDMLAL2 */
6826 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6827 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6828 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6830 tcg_temp_free_i64(tcg_op3
);
6834 g_assert_not_reached();
6837 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6838 write_fp_dreg(s
, rd
, tcg_res
);
6840 tcg_temp_free_i32(tcg_op1
);
6841 tcg_temp_free_i32(tcg_op2
);
6842 tcg_temp_free_i64(tcg_res
);
6846 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6847 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6849 /* Handle 64x64->64 opcodes which are shared between the scalar
6850 * and vector 3-same groups. We cover every opcode where size == 3
6851 * is valid in either the three-reg-same (integer, not pairwise)
6852 * or scalar-three-reg-same groups. (Some opcodes are not yet
6858 case 0x1: /* SQADD */
6860 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6862 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6865 case 0x5: /* SQSUB */
6867 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6869 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6872 case 0x6: /* CMGT, CMHI */
6873 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6874 * We implement this using setcond (test) and then negating.
6876 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6878 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6879 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6881 case 0x7: /* CMGE, CMHS */
6882 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6884 case 0x11: /* CMTST, CMEQ */
6889 /* CMTST : test is "if (X & Y != 0)". */
6890 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6891 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6892 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6894 case 0x8: /* SSHL, USHL */
6896 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6898 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6901 case 0x9: /* SQSHL, UQSHL */
6903 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6905 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6908 case 0xa: /* SRSHL, URSHL */
6910 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6912 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6915 case 0xb: /* SQRSHL, UQRSHL */
6917 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6919 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6922 case 0x10: /* ADD, SUB */
6924 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6926 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6930 g_assert_not_reached();
6934 /* Handle the 3-same-operands float operations; shared by the scalar
6935 * and vector encodings. The caller must filter out any encodings
6936 * not allocated for the encoding it is dealing with.
6938 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6939 int fpopcode
, int rd
, int rn
, int rm
)
6942 TCGv_ptr fpst
= get_fpstatus_ptr();
6944 for (pass
= 0; pass
< elements
; pass
++) {
6947 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6948 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6949 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6951 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6952 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6955 case 0x39: /* FMLS */
6956 /* As usual for ARM, separate negation for fused multiply-add */
6957 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6959 case 0x19: /* FMLA */
6960 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6961 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6964 case 0x18: /* FMAXNM */
6965 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6967 case 0x1a: /* FADD */
6968 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6970 case 0x1b: /* FMULX */
6971 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6973 case 0x1c: /* FCMEQ */
6974 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6976 case 0x1e: /* FMAX */
6977 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6979 case 0x1f: /* FRECPS */
6980 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6982 case 0x38: /* FMINNM */
6983 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6985 case 0x3a: /* FSUB */
6986 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6988 case 0x3e: /* FMIN */
6989 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6991 case 0x3f: /* FRSQRTS */
6992 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6994 case 0x5b: /* FMUL */
6995 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6997 case 0x5c: /* FCMGE */
6998 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7000 case 0x5d: /* FACGE */
7001 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7003 case 0x5f: /* FDIV */
7004 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7006 case 0x7a: /* FABD */
7007 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7008 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7010 case 0x7c: /* FCMGT */
7011 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7013 case 0x7d: /* FACGT */
7014 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7017 g_assert_not_reached();
7020 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7022 tcg_temp_free_i64(tcg_res
);
7023 tcg_temp_free_i64(tcg_op1
);
7024 tcg_temp_free_i64(tcg_op2
);
7027 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7028 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7029 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7031 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7032 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7035 case 0x39: /* FMLS */
7036 /* As usual for ARM, separate negation for fused multiply-add */
7037 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7039 case 0x19: /* FMLA */
7040 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7041 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7044 case 0x1a: /* FADD */
7045 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7047 case 0x1b: /* FMULX */
7048 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7050 case 0x1c: /* FCMEQ */
7051 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7053 case 0x1e: /* FMAX */
7054 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7056 case 0x1f: /* FRECPS */
7057 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7059 case 0x18: /* FMAXNM */
7060 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7062 case 0x38: /* FMINNM */
7063 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7065 case 0x3a: /* FSUB */
7066 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7068 case 0x3e: /* FMIN */
7069 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7071 case 0x3f: /* FRSQRTS */
7072 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7074 case 0x5b: /* FMUL */
7075 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7077 case 0x5c: /* FCMGE */
7078 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7080 case 0x5d: /* FACGE */
7081 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7083 case 0x5f: /* FDIV */
7084 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7086 case 0x7a: /* FABD */
7087 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7088 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7090 case 0x7c: /* FCMGT */
7091 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7093 case 0x7d: /* FACGT */
7094 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7097 g_assert_not_reached();
7100 if (elements
== 1) {
7101 /* scalar single so clear high part */
7102 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7104 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7105 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7106 tcg_temp_free_i64(tcg_tmp
);
7108 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7111 tcg_temp_free_i32(tcg_res
);
7112 tcg_temp_free_i32(tcg_op1
);
7113 tcg_temp_free_i32(tcg_op2
);
7117 tcg_temp_free_ptr(fpst
);
7119 if ((elements
<< size
) < 4) {
7120 /* scalar, or non-quad vector op */
7121 clear_vec_high(s
, rd
);
7125 /* C3.6.11 AdvSIMD scalar three same
7126 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7127 * +-----+---+-----------+------+---+------+--------+---+------+------+
7128 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7129 * +-----+---+-----------+------+---+------+--------+---+------+------+
7131 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7133 int rd
= extract32(insn
, 0, 5);
7134 int rn
= extract32(insn
, 5, 5);
7135 int opcode
= extract32(insn
, 11, 5);
7136 int rm
= extract32(insn
, 16, 5);
7137 int size
= extract32(insn
, 22, 2);
7138 bool u
= extract32(insn
, 29, 1);
7141 if (opcode
>= 0x18) {
7142 /* Floating point: U, size[1] and opcode indicate operation */
7143 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7145 case 0x1b: /* FMULX */
7146 case 0x1f: /* FRECPS */
7147 case 0x3f: /* FRSQRTS */
7148 case 0x5d: /* FACGE */
7149 case 0x7d: /* FACGT */
7150 case 0x1c: /* FCMEQ */
7151 case 0x5c: /* FCMGE */
7152 case 0x7c: /* FCMGT */
7153 case 0x7a: /* FABD */
7156 unallocated_encoding(s
);
7160 if (!fp_access_check(s
)) {
7164 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7169 case 0x1: /* SQADD, UQADD */
7170 case 0x5: /* SQSUB, UQSUB */
7171 case 0x9: /* SQSHL, UQSHL */
7172 case 0xb: /* SQRSHL, UQRSHL */
7174 case 0x8: /* SSHL, USHL */
7175 case 0xa: /* SRSHL, URSHL */
7176 case 0x6: /* CMGT, CMHI */
7177 case 0x7: /* CMGE, CMHS */
7178 case 0x11: /* CMTST, CMEQ */
7179 case 0x10: /* ADD, SUB (vector) */
7181 unallocated_encoding(s
);
7185 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7186 if (size
!= 1 && size
!= 2) {
7187 unallocated_encoding(s
);
7192 unallocated_encoding(s
);
7196 if (!fp_access_check(s
)) {
7200 tcg_rd
= tcg_temp_new_i64();
7203 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7204 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7206 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7207 tcg_temp_free_i64(tcg_rn
);
7208 tcg_temp_free_i64(tcg_rm
);
7210 /* Do a single operation on the lowest element in the vector.
7211 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7212 * no side effects for all these operations.
7213 * OPTME: special-purpose helpers would avoid doing some
7214 * unnecessary work in the helper for the 8 and 16 bit cases.
7216 NeonGenTwoOpEnvFn
*genenvfn
;
7217 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7218 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7219 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7221 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7222 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7225 case 0x1: /* SQADD, UQADD */
7227 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7228 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7229 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7230 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7232 genenvfn
= fns
[size
][u
];
7235 case 0x5: /* SQSUB, UQSUB */
7237 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7238 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7239 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7240 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7242 genenvfn
= fns
[size
][u
];
7245 case 0x9: /* SQSHL, UQSHL */
7247 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7248 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7249 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7250 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7252 genenvfn
= fns
[size
][u
];
7255 case 0xb: /* SQRSHL, UQRSHL */
7257 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7258 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7259 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7260 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7262 genenvfn
= fns
[size
][u
];
7265 case 0x16: /* SQDMULH, SQRDMULH */
7267 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7268 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7269 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7271 assert(size
== 1 || size
== 2);
7272 genenvfn
= fns
[size
- 1][u
];
7276 g_assert_not_reached();
7279 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7280 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7281 tcg_temp_free_i32(tcg_rd32
);
7282 tcg_temp_free_i32(tcg_rn
);
7283 tcg_temp_free_i32(tcg_rm
);
7286 write_fp_dreg(s
, rd
, tcg_rd
);
7288 tcg_temp_free_i64(tcg_rd
);
7291 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7292 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7293 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7295 /* Handle 64->64 opcodes which are shared between the scalar and
7296 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7297 * is valid in either group and also the double-precision fp ops.
7298 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7304 case 0x4: /* CLS, CLZ */
7306 gen_helper_clz64(tcg_rd
, tcg_rn
);
7308 gen_helper_cls64(tcg_rd
, tcg_rn
);
7312 /* This opcode is shared with CNT and RBIT but we have earlier
7313 * enforced that size == 3 if and only if this is the NOT insn.
7315 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7317 case 0x7: /* SQABS, SQNEG */
7319 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7321 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7324 case 0xa: /* CMLT */
7325 /* 64 bit integer comparison against zero, result is
7326 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7331 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7332 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7334 case 0x8: /* CMGT, CMGE */
7335 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7337 case 0x9: /* CMEQ, CMLE */
7338 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7340 case 0xb: /* ABS, NEG */
7342 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7344 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7345 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7346 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7348 tcg_temp_free_i64(tcg_zero
);
7351 case 0x2f: /* FABS */
7352 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7354 case 0x6f: /* FNEG */
7355 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7357 case 0x7f: /* FSQRT */
7358 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7360 case 0x1a: /* FCVTNS */
7361 case 0x1b: /* FCVTMS */
7362 case 0x1c: /* FCVTAS */
7363 case 0x3a: /* FCVTPS */
7364 case 0x3b: /* FCVTZS */
7366 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7367 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7368 tcg_temp_free_i32(tcg_shift
);
7371 case 0x5a: /* FCVTNU */
7372 case 0x5b: /* FCVTMU */
7373 case 0x5c: /* FCVTAU */
7374 case 0x7a: /* FCVTPU */
7375 case 0x7b: /* FCVTZU */
7377 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7378 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7379 tcg_temp_free_i32(tcg_shift
);
7382 case 0x18: /* FRINTN */
7383 case 0x19: /* FRINTM */
7384 case 0x38: /* FRINTP */
7385 case 0x39: /* FRINTZ */
7386 case 0x58: /* FRINTA */
7387 case 0x79: /* FRINTI */
7388 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7390 case 0x59: /* FRINTX */
7391 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7394 g_assert_not_reached();
7398 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7399 bool is_scalar
, bool is_u
, bool is_q
,
7400 int size
, int rn
, int rd
)
7402 bool is_double
= (size
== 3);
7405 if (!fp_access_check(s
)) {
7409 fpst
= get_fpstatus_ptr();
7412 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7413 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7414 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7415 NeonGenTwoDoubleOPFn
*genfn
;
7420 case 0x2e: /* FCMLT (zero) */
7423 case 0x2c: /* FCMGT (zero) */
7424 genfn
= gen_helper_neon_cgt_f64
;
7426 case 0x2d: /* FCMEQ (zero) */
7427 genfn
= gen_helper_neon_ceq_f64
;
7429 case 0x6d: /* FCMLE (zero) */
7432 case 0x6c: /* FCMGE (zero) */
7433 genfn
= gen_helper_neon_cge_f64
;
7436 g_assert_not_reached();
7439 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7440 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7442 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7444 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7446 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7449 clear_vec_high(s
, rd
);
7452 tcg_temp_free_i64(tcg_res
);
7453 tcg_temp_free_i64(tcg_zero
);
7454 tcg_temp_free_i64(tcg_op
);
7456 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7457 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7458 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7459 NeonGenTwoSingleOPFn
*genfn
;
7461 int pass
, maxpasses
;
7464 case 0x2e: /* FCMLT (zero) */
7467 case 0x2c: /* FCMGT (zero) */
7468 genfn
= gen_helper_neon_cgt_f32
;
7470 case 0x2d: /* FCMEQ (zero) */
7471 genfn
= gen_helper_neon_ceq_f32
;
7473 case 0x6d: /* FCMLE (zero) */
7476 case 0x6c: /* FCMGE (zero) */
7477 genfn
= gen_helper_neon_cge_f32
;
7480 g_assert_not_reached();
7486 maxpasses
= is_q
? 4 : 2;
7489 for (pass
= 0; pass
< maxpasses
; pass
++) {
7490 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7492 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7494 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7497 write_fp_sreg(s
, rd
, tcg_res
);
7499 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7502 tcg_temp_free_i32(tcg_res
);
7503 tcg_temp_free_i32(tcg_zero
);
7504 tcg_temp_free_i32(tcg_op
);
7505 if (!is_q
&& !is_scalar
) {
7506 clear_vec_high(s
, rd
);
7510 tcg_temp_free_ptr(fpst
);
7513 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7514 bool is_scalar
, bool is_u
, bool is_q
,
7515 int size
, int rn
, int rd
)
7517 bool is_double
= (size
== 3);
7518 TCGv_ptr fpst
= get_fpstatus_ptr();
7521 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7522 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7525 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7526 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7528 case 0x3d: /* FRECPE */
7529 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7531 case 0x3f: /* FRECPX */
7532 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7534 case 0x7d: /* FRSQRTE */
7535 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7538 g_assert_not_reached();
7540 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7543 clear_vec_high(s
, rd
);
7546 tcg_temp_free_i64(tcg_res
);
7547 tcg_temp_free_i64(tcg_op
);
7549 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7550 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7551 int pass
, maxpasses
;
7556 maxpasses
= is_q
? 4 : 2;
7559 for (pass
= 0; pass
< maxpasses
; pass
++) {
7560 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7563 case 0x3c: /* URECPE */
7564 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7566 case 0x3d: /* FRECPE */
7567 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7569 case 0x3f: /* FRECPX */
7570 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7572 case 0x7d: /* FRSQRTE */
7573 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7576 g_assert_not_reached();
7580 write_fp_sreg(s
, rd
, tcg_res
);
7582 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7585 tcg_temp_free_i32(tcg_res
);
7586 tcg_temp_free_i32(tcg_op
);
7587 if (!is_q
&& !is_scalar
) {
7588 clear_vec_high(s
, rd
);
7591 tcg_temp_free_ptr(fpst
);
7594 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7595 int opcode
, bool u
, bool is_q
,
7596 int size
, int rn
, int rd
)
7598 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7599 * in the source becomes a size element in the destination).
7602 TCGv_i32 tcg_res
[2];
7603 int destelt
= is_q
? 2 : 0;
7604 int passes
= scalar
? 1 : 2;
7607 tcg_res
[1] = tcg_const_i32(0);
7610 for (pass
= 0; pass
< passes
; pass
++) {
7611 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7612 NeonGenNarrowFn
*genfn
= NULL
;
7613 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7616 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7618 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7620 tcg_res
[pass
] = tcg_temp_new_i32();
7623 case 0x12: /* XTN, SQXTUN */
7625 static NeonGenNarrowFn
* const xtnfns
[3] = {
7626 gen_helper_neon_narrow_u8
,
7627 gen_helper_neon_narrow_u16
,
7628 tcg_gen_trunc_i64_i32
,
7630 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7631 gen_helper_neon_unarrow_sat8
,
7632 gen_helper_neon_unarrow_sat16
,
7633 gen_helper_neon_unarrow_sat32
,
7636 genenvfn
= sqxtunfns
[size
];
7638 genfn
= xtnfns
[size
];
7642 case 0x14: /* SQXTN, UQXTN */
7644 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7645 { gen_helper_neon_narrow_sat_s8
,
7646 gen_helper_neon_narrow_sat_u8
},
7647 { gen_helper_neon_narrow_sat_s16
,
7648 gen_helper_neon_narrow_sat_u16
},
7649 { gen_helper_neon_narrow_sat_s32
,
7650 gen_helper_neon_narrow_sat_u32
},
7652 genenvfn
= fns
[size
][u
];
7655 case 0x16: /* FCVTN, FCVTN2 */
7656 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7658 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7660 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7661 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7662 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
7663 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7664 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
7665 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
7666 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7667 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7668 tcg_temp_free_i32(tcg_lo
);
7669 tcg_temp_free_i32(tcg_hi
);
7672 case 0x56: /* FCVTXN, FCVTXN2 */
7673 /* 64 bit to 32 bit float conversion
7674 * with von Neumann rounding (round to odd)
7677 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7680 g_assert_not_reached();
7684 genfn(tcg_res
[pass
], tcg_op
);
7685 } else if (genenvfn
) {
7686 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7689 tcg_temp_free_i64(tcg_op
);
7692 for (pass
= 0; pass
< 2; pass
++) {
7693 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7694 tcg_temp_free_i32(tcg_res
[pass
]);
7697 clear_vec_high(s
, rd
);
7701 /* Remaining saturating accumulating ops */
7702 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7703 bool is_q
, int size
, int rn
, int rd
)
7705 bool is_double
= (size
== 3);
7708 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7709 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7712 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7713 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7714 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7716 if (is_u
) { /* USQADD */
7717 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7718 } else { /* SUQADD */
7719 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7721 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7724 clear_vec_high(s
, rd
);
7727 tcg_temp_free_i64(tcg_rd
);
7728 tcg_temp_free_i64(tcg_rn
);
7730 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7731 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7732 int pass
, maxpasses
;
7737 maxpasses
= is_q
? 4 : 2;
7740 for (pass
= 0; pass
< maxpasses
; pass
++) {
7742 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7743 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7745 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7746 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7749 if (is_u
) { /* USQADD */
7752 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7755 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7758 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7761 g_assert_not_reached();
7763 } else { /* SUQADD */
7766 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7769 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7772 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7775 g_assert_not_reached();
7780 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7781 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7782 tcg_temp_free_i64(tcg_zero
);
7784 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7788 clear_vec_high(s
, rd
);
7791 tcg_temp_free_i32(tcg_rd
);
7792 tcg_temp_free_i32(tcg_rn
);
7796 /* C3.6.12 AdvSIMD scalar two reg misc
7797 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7798 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7799 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7800 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7802 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7804 int rd
= extract32(insn
, 0, 5);
7805 int rn
= extract32(insn
, 5, 5);
7806 int opcode
= extract32(insn
, 12, 5);
7807 int size
= extract32(insn
, 22, 2);
7808 bool u
= extract32(insn
, 29, 1);
7809 bool is_fcvt
= false;
7812 TCGv_ptr tcg_fpstatus
;
7815 case 0x3: /* USQADD / SUQADD*/
7816 if (!fp_access_check(s
)) {
7819 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7821 case 0x7: /* SQABS / SQNEG */
7823 case 0xa: /* CMLT */
7825 unallocated_encoding(s
);
7829 case 0x8: /* CMGT, CMGE */
7830 case 0x9: /* CMEQ, CMLE */
7831 case 0xb: /* ABS, NEG */
7833 unallocated_encoding(s
);
7837 case 0x12: /* SQXTUN */
7839 unallocated_encoding(s
);
7843 case 0x14: /* SQXTN, UQXTN */
7845 unallocated_encoding(s
);
7848 if (!fp_access_check(s
)) {
7851 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7856 /* Floating point: U, size[1] and opcode indicate operation;
7857 * size[0] indicates single or double precision.
7859 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7860 size
= extract32(size
, 0, 1) ? 3 : 2;
7862 case 0x2c: /* FCMGT (zero) */
7863 case 0x2d: /* FCMEQ (zero) */
7864 case 0x2e: /* FCMLT (zero) */
7865 case 0x6c: /* FCMGE (zero) */
7866 case 0x6d: /* FCMLE (zero) */
7867 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7869 case 0x1d: /* SCVTF */
7870 case 0x5d: /* UCVTF */
7872 bool is_signed
= (opcode
== 0x1d);
7873 if (!fp_access_check(s
)) {
7876 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7879 case 0x3d: /* FRECPE */
7880 case 0x3f: /* FRECPX */
7881 case 0x7d: /* FRSQRTE */
7882 if (!fp_access_check(s
)) {
7885 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7887 case 0x1a: /* FCVTNS */
7888 case 0x1b: /* FCVTMS */
7889 case 0x3a: /* FCVTPS */
7890 case 0x3b: /* FCVTZS */
7891 case 0x5a: /* FCVTNU */
7892 case 0x5b: /* FCVTMU */
7893 case 0x7a: /* FCVTPU */
7894 case 0x7b: /* FCVTZU */
7896 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7898 case 0x1c: /* FCVTAS */
7899 case 0x5c: /* FCVTAU */
7900 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7902 rmode
= FPROUNDING_TIEAWAY
;
7904 case 0x56: /* FCVTXN, FCVTXN2 */
7906 unallocated_encoding(s
);
7909 if (!fp_access_check(s
)) {
7912 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
7915 unallocated_encoding(s
);
7920 unallocated_encoding(s
);
7924 if (!fp_access_check(s
)) {
7929 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7930 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7931 tcg_fpstatus
= get_fpstatus_ptr();
7933 TCGV_UNUSED_I32(tcg_rmode
);
7934 TCGV_UNUSED_PTR(tcg_fpstatus
);
7938 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7939 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7941 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7942 write_fp_dreg(s
, rd
, tcg_rd
);
7943 tcg_temp_free_i64(tcg_rd
);
7944 tcg_temp_free_i64(tcg_rn
);
7946 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7947 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7949 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7952 case 0x7: /* SQABS, SQNEG */
7954 NeonGenOneOpEnvFn
*genfn
;
7955 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
7956 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
7957 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
7958 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
7960 genfn
= fns
[size
][u
];
7961 genfn(tcg_rd
, cpu_env
, tcg_rn
);
7964 case 0x1a: /* FCVTNS */
7965 case 0x1b: /* FCVTMS */
7966 case 0x1c: /* FCVTAS */
7967 case 0x3a: /* FCVTPS */
7968 case 0x3b: /* FCVTZS */
7970 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7971 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7972 tcg_temp_free_i32(tcg_shift
);
7975 case 0x5a: /* FCVTNU */
7976 case 0x5b: /* FCVTMU */
7977 case 0x5c: /* FCVTAU */
7978 case 0x7a: /* FCVTPU */
7979 case 0x7b: /* FCVTZU */
7981 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7982 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7983 tcg_temp_free_i32(tcg_shift
);
7987 g_assert_not_reached();
7990 write_fp_sreg(s
, rd
, tcg_rd
);
7991 tcg_temp_free_i32(tcg_rd
);
7992 tcg_temp_free_i32(tcg_rn
);
7996 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7997 tcg_temp_free_i32(tcg_rmode
);
7998 tcg_temp_free_ptr(tcg_fpstatus
);
8002 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8003 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8004 int immh
, int immb
, int opcode
, int rn
, int rd
)
8006 int size
= 32 - clz32(immh
) - 1;
8007 int immhb
= immh
<< 3 | immb
;
8008 int shift
= 2 * (8 << size
) - immhb
;
8009 bool accumulate
= false;
8011 bool insert
= false;
8012 int dsize
= is_q
? 128 : 64;
8013 int esize
= 8 << size
;
8014 int elements
= dsize
/esize
;
8015 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8016 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8017 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8021 if (extract32(immh
, 3, 1) && !is_q
) {
8022 unallocated_encoding(s
);
8026 if (size
> 3 && !is_q
) {
8027 unallocated_encoding(s
);
8031 if (!fp_access_check(s
)) {
8036 case 0x02: /* SSRA / USRA (accumulate) */
8039 case 0x04: /* SRSHR / URSHR (rounding) */
8042 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8043 accumulate
= round
= true;
8045 case 0x08: /* SRI */
8051 uint64_t round_const
= 1ULL << (shift
- 1);
8052 tcg_round
= tcg_const_i64(round_const
);
8054 TCGV_UNUSED_I64(tcg_round
);
8057 for (i
= 0; i
< elements
; i
++) {
8058 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8059 if (accumulate
|| insert
) {
8060 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8064 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8066 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8067 accumulate
, is_u
, size
, shift
);
8070 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8074 clear_vec_high(s
, rd
);
8078 tcg_temp_free_i64(tcg_round
);
8082 /* SHL/SLI - Vector shift left */
8083 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8084 int immh
, int immb
, int opcode
, int rn
, int rd
)
8086 int size
= 32 - clz32(immh
) - 1;
8087 int immhb
= immh
<< 3 | immb
;
8088 int shift
= immhb
- (8 << size
);
8089 int dsize
= is_q
? 128 : 64;
8090 int esize
= 8 << size
;
8091 int elements
= dsize
/esize
;
8092 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8093 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8096 if (extract32(immh
, 3, 1) && !is_q
) {
8097 unallocated_encoding(s
);
8101 if (size
> 3 && !is_q
) {
8102 unallocated_encoding(s
);
8106 if (!fp_access_check(s
)) {
8110 for (i
= 0; i
< elements
; i
++) {
8111 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8113 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8116 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8118 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8122 clear_vec_high(s
, rd
);
8126 /* USHLL/SHLL - Vector shift left with widening */
8127 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8128 int immh
, int immb
, int opcode
, int rn
, int rd
)
8130 int size
= 32 - clz32(immh
) - 1;
8131 int immhb
= immh
<< 3 | immb
;
8132 int shift
= immhb
- (8 << size
);
8134 int esize
= 8 << size
;
8135 int elements
= dsize
/esize
;
8136 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8137 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8141 unallocated_encoding(s
);
8145 if (!fp_access_check(s
)) {
8149 /* For the LL variants the store is larger than the load,
8150 * so if rd == rn we would overwrite parts of our input.
8151 * So load everything right now and use shifts in the main loop.
8153 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8155 for (i
= 0; i
< elements
; i
++) {
8156 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8157 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8158 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8159 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8163 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8164 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8165 int immh
, int immb
, int opcode
, int rn
, int rd
)
8167 int immhb
= immh
<< 3 | immb
;
8168 int size
= 32 - clz32(immh
) - 1;
8170 int esize
= 8 << size
;
8171 int elements
= dsize
/esize
;
8172 int shift
= (2 * esize
) - immhb
;
8173 bool round
= extract32(opcode
, 0, 1);
8174 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8178 if (extract32(immh
, 3, 1)) {
8179 unallocated_encoding(s
);
8183 if (!fp_access_check(s
)) {
8187 tcg_rn
= tcg_temp_new_i64();
8188 tcg_rd
= tcg_temp_new_i64();
8189 tcg_final
= tcg_temp_new_i64();
8190 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8193 uint64_t round_const
= 1ULL << (shift
- 1);
8194 tcg_round
= tcg_const_i64(round_const
);
8196 TCGV_UNUSED_I64(tcg_round
);
8199 for (i
= 0; i
< elements
; i
++) {
8200 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8201 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8202 false, true, size
+1, shift
);
8204 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8208 clear_vec_high(s
, rd
);
8209 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8211 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8215 tcg_temp_free_i64(tcg_round
);
8217 tcg_temp_free_i64(tcg_rn
);
8218 tcg_temp_free_i64(tcg_rd
);
8219 tcg_temp_free_i64(tcg_final
);
8224 /* C3.6.14 AdvSIMD shift by immediate
8225 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8226 * +---+---+---+-------------+------+------+--------+---+------+------+
8227 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8228 * +---+---+---+-------------+------+------+--------+---+------+------+
8230 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8232 int rd
= extract32(insn
, 0, 5);
8233 int rn
= extract32(insn
, 5, 5);
8234 int opcode
= extract32(insn
, 11, 5);
8235 int immb
= extract32(insn
, 16, 3);
8236 int immh
= extract32(insn
, 19, 4);
8237 bool is_u
= extract32(insn
, 29, 1);
8238 bool is_q
= extract32(insn
, 30, 1);
8241 case 0x08: /* SRI */
8243 unallocated_encoding(s
);
8247 case 0x00: /* SSHR / USHR */
8248 case 0x02: /* SSRA / USRA (accumulate) */
8249 case 0x04: /* SRSHR / URSHR (rounding) */
8250 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8251 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8253 case 0x0a: /* SHL / SLI */
8254 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8256 case 0x10: /* SHRN */
8257 case 0x11: /* RSHRN / SQRSHRUN */
8259 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8262 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8265 case 0x12: /* SQSHRN / UQSHRN */
8266 case 0x13: /* SQRSHRN / UQRSHRN */
8267 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8270 case 0x14: /* SSHLL / USHLL */
8271 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8273 case 0x1c: /* SCVTF / UCVTF */
8274 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8277 case 0xc: /* SQSHLU */
8279 unallocated_encoding(s
);
8282 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8284 case 0xe: /* SQSHL, UQSHL */
8285 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8287 case 0x1f: /* FCVTZS/ FCVTZU */
8288 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8291 unallocated_encoding(s
);
8296 /* Generate code to do a "long" addition or subtraction, ie one done in
8297 * TCGv_i64 on vector lanes twice the width specified by size.
8299 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8300 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8302 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8303 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8304 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8305 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8307 NeonGenTwo64OpFn
*genfn
;
8310 genfn
= fns
[size
][is_sub
];
8311 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8314 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8315 int opcode
, int rd
, int rn
, int rm
)
8317 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8318 TCGv_i64 tcg_res
[2];
8321 tcg_res
[0] = tcg_temp_new_i64();
8322 tcg_res
[1] = tcg_temp_new_i64();
8324 /* Does this op do an adding accumulate, a subtracting accumulate,
8325 * or no accumulate at all?
8343 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8344 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8347 /* size == 2 means two 32x32->64 operations; this is worth special
8348 * casing because we can generally handle it inline.
8351 for (pass
= 0; pass
< 2; pass
++) {
8352 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8353 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8354 TCGv_i64 tcg_passres
;
8355 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8357 int elt
= pass
+ is_q
* 2;
8359 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8360 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8363 tcg_passres
= tcg_res
[pass
];
8365 tcg_passres
= tcg_temp_new_i64();
8369 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8370 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8372 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8373 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8375 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8376 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8378 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8379 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8381 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8382 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8383 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8385 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8386 tcg_temp_free_i64(tcg_tmp1
);
8387 tcg_temp_free_i64(tcg_tmp2
);
8390 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8391 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8392 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8393 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8395 case 9: /* SQDMLAL, SQDMLAL2 */
8396 case 11: /* SQDMLSL, SQDMLSL2 */
8397 case 13: /* SQDMULL, SQDMULL2 */
8398 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8399 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8400 tcg_passres
, tcg_passres
);
8403 g_assert_not_reached();
8406 if (opcode
== 9 || opcode
== 11) {
8407 /* saturating accumulate ops */
8409 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8411 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8412 tcg_res
[pass
], tcg_passres
);
8413 } else if (accop
> 0) {
8414 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8415 } else if (accop
< 0) {
8416 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8420 tcg_temp_free_i64(tcg_passres
);
8423 tcg_temp_free_i64(tcg_op1
);
8424 tcg_temp_free_i64(tcg_op2
);
8427 /* size 0 or 1, generally helper functions */
8428 for (pass
= 0; pass
< 2; pass
++) {
8429 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8430 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8431 TCGv_i64 tcg_passres
;
8432 int elt
= pass
+ is_q
* 2;
8434 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8435 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8438 tcg_passres
= tcg_res
[pass
];
8440 tcg_passres
= tcg_temp_new_i64();
8444 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8445 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8447 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8448 static NeonGenWidenFn
* const widenfns
[2][2] = {
8449 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8450 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8452 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8454 widenfn(tcg_op2_64
, tcg_op2
);
8455 widenfn(tcg_passres
, tcg_op1
);
8456 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8457 tcg_passres
, tcg_op2_64
);
8458 tcg_temp_free_i64(tcg_op2_64
);
8461 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8462 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8465 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8467 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8471 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8473 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8477 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8478 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8479 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8482 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8484 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8488 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8490 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8494 case 9: /* SQDMLAL, SQDMLAL2 */
8495 case 11: /* SQDMLSL, SQDMLSL2 */
8496 case 13: /* SQDMULL, SQDMULL2 */
8498 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8499 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8500 tcg_passres
, tcg_passres
);
8502 case 14: /* PMULL */
8504 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8507 g_assert_not_reached();
8509 tcg_temp_free_i32(tcg_op1
);
8510 tcg_temp_free_i32(tcg_op2
);
8513 if (opcode
== 9 || opcode
== 11) {
8514 /* saturating accumulate ops */
8516 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8518 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8522 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8523 tcg_res
[pass
], tcg_passres
);
8525 tcg_temp_free_i64(tcg_passres
);
8530 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8531 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8532 tcg_temp_free_i64(tcg_res
[0]);
8533 tcg_temp_free_i64(tcg_res
[1]);
8536 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8537 int opcode
, int rd
, int rn
, int rm
)
8539 TCGv_i64 tcg_res
[2];
8540 int part
= is_q
? 2 : 0;
8543 for (pass
= 0; pass
< 2; pass
++) {
8544 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8545 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8546 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8547 static NeonGenWidenFn
* const widenfns
[3][2] = {
8548 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8549 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8550 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8552 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8554 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8555 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8556 widenfn(tcg_op2_wide
, tcg_op2
);
8557 tcg_temp_free_i32(tcg_op2
);
8558 tcg_res
[pass
] = tcg_temp_new_i64();
8559 gen_neon_addl(size
, (opcode
== 3),
8560 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8561 tcg_temp_free_i64(tcg_op1
);
8562 tcg_temp_free_i64(tcg_op2_wide
);
8565 for (pass
= 0; pass
< 2; pass
++) {
8566 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8567 tcg_temp_free_i64(tcg_res
[pass
]);
8571 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8573 tcg_gen_shri_i64(in
, in
, 32);
8574 tcg_gen_trunc_i64_i32(res
, in
);
8577 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8579 tcg_gen_addi_i64(in
, in
, 1U << 31);
8580 do_narrow_high_u32(res
, in
);
8583 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8584 int opcode
, int rd
, int rn
, int rm
)
8586 TCGv_i32 tcg_res
[2];
8587 int part
= is_q
? 2 : 0;
8590 for (pass
= 0; pass
< 2; pass
++) {
8591 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8592 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8593 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8594 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8595 { gen_helper_neon_narrow_high_u8
,
8596 gen_helper_neon_narrow_round_high_u8
},
8597 { gen_helper_neon_narrow_high_u16
,
8598 gen_helper_neon_narrow_round_high_u16
},
8599 { do_narrow_high_u32
, do_narrow_round_high_u32
},
8601 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8603 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8604 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8606 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8608 tcg_temp_free_i64(tcg_op1
);
8609 tcg_temp_free_i64(tcg_op2
);
8611 tcg_res
[pass
] = tcg_temp_new_i32();
8612 gennarrow(tcg_res
[pass
], tcg_wideres
);
8613 tcg_temp_free_i64(tcg_wideres
);
8616 for (pass
= 0; pass
< 2; pass
++) {
8617 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8618 tcg_temp_free_i32(tcg_res
[pass
]);
8621 clear_vec_high(s
, rd
);
8625 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8627 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8628 * is the only three-reg-diff instruction which produces a
8629 * 128-bit wide result from a single operation. However since
8630 * it's possible to calculate the two halves more or less
8631 * separately we just use two helper calls.
8633 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8634 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8635 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8637 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8638 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8639 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8640 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8641 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8642 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8644 tcg_temp_free_i64(tcg_op1
);
8645 tcg_temp_free_i64(tcg_op2
);
8646 tcg_temp_free_i64(tcg_res
);
8649 /* C3.6.15 AdvSIMD three different
8650 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8651 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8652 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8653 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8655 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8657 /* Instructions in this group fall into three basic classes
8658 * (in each case with the operation working on each element in
8659 * the input vectors):
8660 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8662 * (2) wide 64 x 128 -> 128
8663 * (3) narrowing 128 x 128 -> 64
8664 * Here we do initial decode, catch unallocated cases and
8665 * dispatch to separate functions for each class.
8667 int is_q
= extract32(insn
, 30, 1);
8668 int is_u
= extract32(insn
, 29, 1);
8669 int size
= extract32(insn
, 22, 2);
8670 int opcode
= extract32(insn
, 12, 4);
8671 int rm
= extract32(insn
, 16, 5);
8672 int rn
= extract32(insn
, 5, 5);
8673 int rd
= extract32(insn
, 0, 5);
8676 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8677 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8678 /* 64 x 128 -> 128 */
8680 unallocated_encoding(s
);
8683 if (!fp_access_check(s
)) {
8686 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8688 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8689 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8690 /* 128 x 128 -> 64 */
8692 unallocated_encoding(s
);
8695 if (!fp_access_check(s
)) {
8698 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8700 case 14: /* PMULL, PMULL2 */
8701 if (is_u
|| size
== 1 || size
== 2) {
8702 unallocated_encoding(s
);
8706 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8707 unallocated_encoding(s
);
8710 if (!fp_access_check(s
)) {
8713 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8717 case 9: /* SQDMLAL, SQDMLAL2 */
8718 case 11: /* SQDMLSL, SQDMLSL2 */
8719 case 13: /* SQDMULL, SQDMULL2 */
8720 if (is_u
|| size
== 0) {
8721 unallocated_encoding(s
);
8725 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8726 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8727 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8728 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8729 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8730 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8731 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8732 /* 64 x 64 -> 128 */
8734 unallocated_encoding(s
);
8738 if (!fp_access_check(s
)) {
8742 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8745 /* opcode 15 not allocated */
8746 unallocated_encoding(s
);
8751 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8752 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8754 int rd
= extract32(insn
, 0, 5);
8755 int rn
= extract32(insn
, 5, 5);
8756 int rm
= extract32(insn
, 16, 5);
8757 int size
= extract32(insn
, 22, 2);
8758 bool is_u
= extract32(insn
, 29, 1);
8759 bool is_q
= extract32(insn
, 30, 1);
8760 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8763 if (!fp_access_check(s
)) {
8767 tcg_op1
= tcg_temp_new_i64();
8768 tcg_op2
= tcg_temp_new_i64();
8769 tcg_res
[0] = tcg_temp_new_i64();
8770 tcg_res
[1] = tcg_temp_new_i64();
8772 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8773 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8774 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8779 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8782 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8785 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8788 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8793 /* B* ops need res loaded to operate on */
8794 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8799 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8801 case 1: /* BSL bitwise select */
8802 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8803 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8804 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8806 case 2: /* BIT, bitwise insert if true */
8807 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8808 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8809 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8811 case 3: /* BIF, bitwise insert if false */
8812 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8813 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8814 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8820 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8822 tcg_gen_movi_i64(tcg_res
[1], 0);
8824 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8826 tcg_temp_free_i64(tcg_op1
);
8827 tcg_temp_free_i64(tcg_op2
);
8828 tcg_temp_free_i64(tcg_res
[0]);
8829 tcg_temp_free_i64(tcg_res
[1]);
8832 /* Helper functions for 32 bit comparisons */
8833 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8835 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8838 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8840 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8843 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8845 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8848 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8850 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8853 /* Pairwise op subgroup of C3.6.16.
8855 * This is called directly or via the handle_3same_float for float pairwise
8856 * operations where the opcode and size are calculated differently.
8858 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8859 int size
, int rn
, int rm
, int rd
)
8864 /* Floating point operations need fpst */
8865 if (opcode
>= 0x58) {
8866 fpst
= get_fpstatus_ptr();
8868 TCGV_UNUSED_PTR(fpst
);
8871 if (!fp_access_check(s
)) {
8875 /* These operations work on the concatenated rm:rn, with each pair of
8876 * adjacent elements being operated on to produce an element in the result.
8879 TCGv_i64 tcg_res
[2];
8881 for (pass
= 0; pass
< 2; pass
++) {
8882 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8883 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8884 int passreg
= (pass
== 0) ? rn
: rm
;
8886 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8887 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8888 tcg_res
[pass
] = tcg_temp_new_i64();
8891 case 0x17: /* ADDP */
8892 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8894 case 0x58: /* FMAXNMP */
8895 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8897 case 0x5a: /* FADDP */
8898 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8900 case 0x5e: /* FMAXP */
8901 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8903 case 0x78: /* FMINNMP */
8904 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8906 case 0x7e: /* FMINP */
8907 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8910 g_assert_not_reached();
8913 tcg_temp_free_i64(tcg_op1
);
8914 tcg_temp_free_i64(tcg_op2
);
8917 for (pass
= 0; pass
< 2; pass
++) {
8918 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8919 tcg_temp_free_i64(tcg_res
[pass
]);
8922 int maxpass
= is_q
? 4 : 2;
8923 TCGv_i32 tcg_res
[4];
8925 for (pass
= 0; pass
< maxpass
; pass
++) {
8926 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8927 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8928 NeonGenTwoOpFn
*genfn
= NULL
;
8929 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8930 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8932 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8933 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8934 tcg_res
[pass
] = tcg_temp_new_i32();
8937 case 0x17: /* ADDP */
8939 static NeonGenTwoOpFn
* const fns
[3] = {
8940 gen_helper_neon_padd_u8
,
8941 gen_helper_neon_padd_u16
,
8947 case 0x14: /* SMAXP, UMAXP */
8949 static NeonGenTwoOpFn
* const fns
[3][2] = {
8950 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8951 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8952 { gen_max_s32
, gen_max_u32
},
8954 genfn
= fns
[size
][u
];
8957 case 0x15: /* SMINP, UMINP */
8959 static NeonGenTwoOpFn
* const fns
[3][2] = {
8960 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8961 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8962 { gen_min_s32
, gen_min_u32
},
8964 genfn
= fns
[size
][u
];
8967 /* The FP operations are all on single floats (32 bit) */
8968 case 0x58: /* FMAXNMP */
8969 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8971 case 0x5a: /* FADDP */
8972 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8974 case 0x5e: /* FMAXP */
8975 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8977 case 0x78: /* FMINNMP */
8978 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8980 case 0x7e: /* FMINP */
8981 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8984 g_assert_not_reached();
8987 /* FP ops called directly, otherwise call now */
8989 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8992 tcg_temp_free_i32(tcg_op1
);
8993 tcg_temp_free_i32(tcg_op2
);
8996 for (pass
= 0; pass
< maxpass
; pass
++) {
8997 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8998 tcg_temp_free_i32(tcg_res
[pass
]);
9001 clear_vec_high(s
, rd
);
9005 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9006 tcg_temp_free_ptr(fpst
);
9010 /* Floating point op subgroup of C3.6.16. */
9011 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9013 /* For floating point ops, the U, size[1] and opcode bits
9014 * together indicate the operation. size[0] indicates single
9017 int fpopcode
= extract32(insn
, 11, 5)
9018 | (extract32(insn
, 23, 1) << 5)
9019 | (extract32(insn
, 29, 1) << 6);
9020 int is_q
= extract32(insn
, 30, 1);
9021 int size
= extract32(insn
, 22, 1);
9022 int rm
= extract32(insn
, 16, 5);
9023 int rn
= extract32(insn
, 5, 5);
9024 int rd
= extract32(insn
, 0, 5);
9026 int datasize
= is_q
? 128 : 64;
9027 int esize
= 32 << size
;
9028 int elements
= datasize
/ esize
;
9030 if (size
== 1 && !is_q
) {
9031 unallocated_encoding(s
);
9036 case 0x58: /* FMAXNMP */
9037 case 0x5a: /* FADDP */
9038 case 0x5e: /* FMAXP */
9039 case 0x78: /* FMINNMP */
9040 case 0x7e: /* FMINP */
9041 if (size
&& !is_q
) {
9042 unallocated_encoding(s
);
9045 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9048 case 0x1b: /* FMULX */
9049 case 0x1f: /* FRECPS */
9050 case 0x3f: /* FRSQRTS */
9051 case 0x5d: /* FACGE */
9052 case 0x7d: /* FACGT */
9053 case 0x19: /* FMLA */
9054 case 0x39: /* FMLS */
9055 case 0x18: /* FMAXNM */
9056 case 0x1a: /* FADD */
9057 case 0x1c: /* FCMEQ */
9058 case 0x1e: /* FMAX */
9059 case 0x38: /* FMINNM */
9060 case 0x3a: /* FSUB */
9061 case 0x3e: /* FMIN */
9062 case 0x5b: /* FMUL */
9063 case 0x5c: /* FCMGE */
9064 case 0x5f: /* FDIV */
9065 case 0x7a: /* FABD */
9066 case 0x7c: /* FCMGT */
9067 if (!fp_access_check(s
)) {
9071 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9074 unallocated_encoding(s
);
9079 /* Integer op subgroup of C3.6.16. */
9080 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9082 int is_q
= extract32(insn
, 30, 1);
9083 int u
= extract32(insn
, 29, 1);
9084 int size
= extract32(insn
, 22, 2);
9085 int opcode
= extract32(insn
, 11, 5);
9086 int rm
= extract32(insn
, 16, 5);
9087 int rn
= extract32(insn
, 5, 5);
9088 int rd
= extract32(insn
, 0, 5);
9092 case 0x13: /* MUL, PMUL */
9093 if (u
&& size
!= 0) {
9094 unallocated_encoding(s
);
9098 case 0x0: /* SHADD, UHADD */
9099 case 0x2: /* SRHADD, URHADD */
9100 case 0x4: /* SHSUB, UHSUB */
9101 case 0xc: /* SMAX, UMAX */
9102 case 0xd: /* SMIN, UMIN */
9103 case 0xe: /* SABD, UABD */
9104 case 0xf: /* SABA, UABA */
9105 case 0x12: /* MLA, MLS */
9107 unallocated_encoding(s
);
9111 case 0x16: /* SQDMULH, SQRDMULH */
9112 if (size
== 0 || size
== 3) {
9113 unallocated_encoding(s
);
9118 if (size
== 3 && !is_q
) {
9119 unallocated_encoding(s
);
9125 if (!fp_access_check(s
)) {
9131 for (pass
= 0; pass
< 2; pass
++) {
9132 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9133 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9134 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9136 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9137 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9139 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9141 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9143 tcg_temp_free_i64(tcg_res
);
9144 tcg_temp_free_i64(tcg_op1
);
9145 tcg_temp_free_i64(tcg_op2
);
9148 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9149 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9150 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9151 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9152 NeonGenTwoOpFn
*genfn
= NULL
;
9153 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9155 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9156 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9159 case 0x0: /* SHADD, UHADD */
9161 static NeonGenTwoOpFn
* const fns
[3][2] = {
9162 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9163 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9164 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9166 genfn
= fns
[size
][u
];
9169 case 0x1: /* SQADD, UQADD */
9171 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9172 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9173 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9174 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9176 genenvfn
= fns
[size
][u
];
9179 case 0x2: /* SRHADD, URHADD */
9181 static NeonGenTwoOpFn
* const fns
[3][2] = {
9182 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9183 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9184 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9186 genfn
= fns
[size
][u
];
9189 case 0x4: /* SHSUB, UHSUB */
9191 static NeonGenTwoOpFn
* const fns
[3][2] = {
9192 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9193 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9194 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9196 genfn
= fns
[size
][u
];
9199 case 0x5: /* SQSUB, UQSUB */
9201 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9202 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9203 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9204 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9206 genenvfn
= fns
[size
][u
];
9209 case 0x6: /* CMGT, CMHI */
9211 static NeonGenTwoOpFn
* const fns
[3][2] = {
9212 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9213 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9214 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9216 genfn
= fns
[size
][u
];
9219 case 0x7: /* CMGE, CMHS */
9221 static NeonGenTwoOpFn
* const fns
[3][2] = {
9222 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9223 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9224 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9226 genfn
= fns
[size
][u
];
9229 case 0x8: /* SSHL, USHL */
9231 static NeonGenTwoOpFn
* const fns
[3][2] = {
9232 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9233 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9234 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9236 genfn
= fns
[size
][u
];
9239 case 0x9: /* SQSHL, UQSHL */
9241 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9242 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9243 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9244 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9246 genenvfn
= fns
[size
][u
];
9249 case 0xa: /* SRSHL, URSHL */
9251 static NeonGenTwoOpFn
* const fns
[3][2] = {
9252 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9253 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9254 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9256 genfn
= fns
[size
][u
];
9259 case 0xb: /* SQRSHL, UQRSHL */
9261 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9262 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9263 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9264 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9266 genenvfn
= fns
[size
][u
];
9269 case 0xc: /* SMAX, UMAX */
9271 static NeonGenTwoOpFn
* const fns
[3][2] = {
9272 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9273 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9274 { gen_max_s32
, gen_max_u32
},
9276 genfn
= fns
[size
][u
];
9280 case 0xd: /* SMIN, UMIN */
9282 static NeonGenTwoOpFn
* const fns
[3][2] = {
9283 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9284 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9285 { gen_min_s32
, gen_min_u32
},
9287 genfn
= fns
[size
][u
];
9290 case 0xe: /* SABD, UABD */
9291 case 0xf: /* SABA, UABA */
9293 static NeonGenTwoOpFn
* const fns
[3][2] = {
9294 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9295 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9296 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9298 genfn
= fns
[size
][u
];
9301 case 0x10: /* ADD, SUB */
9303 static NeonGenTwoOpFn
* const fns
[3][2] = {
9304 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9305 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9306 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9308 genfn
= fns
[size
][u
];
9311 case 0x11: /* CMTST, CMEQ */
9313 static NeonGenTwoOpFn
* const fns
[3][2] = {
9314 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9315 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9316 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9318 genfn
= fns
[size
][u
];
9321 case 0x13: /* MUL, PMUL */
9325 genfn
= gen_helper_neon_mul_p8
;
9328 /* fall through : MUL */
9329 case 0x12: /* MLA, MLS */
9331 static NeonGenTwoOpFn
* const fns
[3] = {
9332 gen_helper_neon_mul_u8
,
9333 gen_helper_neon_mul_u16
,
9339 case 0x16: /* SQDMULH, SQRDMULH */
9341 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9342 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9343 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9345 assert(size
== 1 || size
== 2);
9346 genenvfn
= fns
[size
- 1][u
];
9350 g_assert_not_reached();
9354 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9356 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9359 if (opcode
== 0xf || opcode
== 0x12) {
9360 /* SABA, UABA, MLA, MLS: accumulating ops */
9361 static NeonGenTwoOpFn
* const fns
[3][2] = {
9362 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9363 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9364 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9366 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9368 genfn
= fns
[size
][is_sub
];
9369 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9370 genfn(tcg_res
, tcg_op1
, tcg_res
);
9373 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9375 tcg_temp_free_i32(tcg_res
);
9376 tcg_temp_free_i32(tcg_op1
);
9377 tcg_temp_free_i32(tcg_op2
);
9382 clear_vec_high(s
, rd
);
9386 /* C3.6.16 AdvSIMD three same
9387 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9388 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9389 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9390 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9392 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9394 int opcode
= extract32(insn
, 11, 5);
9397 case 0x3: /* logic ops */
9398 disas_simd_3same_logic(s
, insn
);
9400 case 0x17: /* ADDP */
9401 case 0x14: /* SMAXP, UMAXP */
9402 case 0x15: /* SMINP, UMINP */
9404 /* Pairwise operations */
9405 int is_q
= extract32(insn
, 30, 1);
9406 int u
= extract32(insn
, 29, 1);
9407 int size
= extract32(insn
, 22, 2);
9408 int rm
= extract32(insn
, 16, 5);
9409 int rn
= extract32(insn
, 5, 5);
9410 int rd
= extract32(insn
, 0, 5);
9411 if (opcode
== 0x17) {
9412 if (u
|| (size
== 3 && !is_q
)) {
9413 unallocated_encoding(s
);
9418 unallocated_encoding(s
);
9422 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9426 /* floating point ops, sz[1] and U are part of opcode */
9427 disas_simd_3same_float(s
, insn
);
9430 disas_simd_3same_int(s
, insn
);
9435 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9436 int size
, int rn
, int rd
)
9438 /* Handle 2-reg-misc ops which are widening (so each size element
9439 * in the source becomes a 2*size element in the destination.
9440 * The only instruction like this is FCVTL.
9445 /* 32 -> 64 bit fp conversion */
9446 TCGv_i64 tcg_res
[2];
9447 int srcelt
= is_q
? 2 : 0;
9449 for (pass
= 0; pass
< 2; pass
++) {
9450 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9451 tcg_res
[pass
] = tcg_temp_new_i64();
9453 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9454 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9455 tcg_temp_free_i32(tcg_op
);
9457 for (pass
= 0; pass
< 2; pass
++) {
9458 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9459 tcg_temp_free_i64(tcg_res
[pass
]);
9462 /* 16 -> 32 bit fp conversion */
9463 int srcelt
= is_q
? 4 : 0;
9464 TCGv_i32 tcg_res
[4];
9466 for (pass
= 0; pass
< 4; pass
++) {
9467 tcg_res
[pass
] = tcg_temp_new_i32();
9469 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9470 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9473 for (pass
= 0; pass
< 4; pass
++) {
9474 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9475 tcg_temp_free_i32(tcg_res
[pass
]);
9480 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9481 bool is_q
, int size
, int rn
, int rd
)
9483 int op
= (opcode
<< 1) | u
;
9484 int opsz
= op
+ size
;
9485 int grp_size
= 3 - opsz
;
9486 int dsize
= is_q
? 128 : 64;
9490 unallocated_encoding(s
);
9494 if (!fp_access_check(s
)) {
9499 /* Special case bytes, use bswap op on each group of elements */
9500 int groups
= dsize
/ (8 << grp_size
);
9502 for (i
= 0; i
< groups
; i
++) {
9503 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9505 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9508 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9511 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9514 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9517 g_assert_not_reached();
9519 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9520 tcg_temp_free_i64(tcg_tmp
);
9523 clear_vec_high(s
, rd
);
9526 int revmask
= (1 << grp_size
) - 1;
9527 int esize
= 8 << size
;
9528 int elements
= dsize
/ esize
;
9529 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9530 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9531 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9533 for (i
= 0; i
< elements
; i
++) {
9534 int e_rev
= (i
& 0xf) ^ revmask
;
9535 int off
= e_rev
* esize
;
9536 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9538 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9539 tcg_rn
, off
- 64, esize
);
9541 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9544 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9545 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9547 tcg_temp_free_i64(tcg_rd_hi
);
9548 tcg_temp_free_i64(tcg_rd
);
9549 tcg_temp_free_i64(tcg_rn
);
9553 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9554 bool is_q
, int size
, int rn
, int rd
)
9556 /* Implement the pairwise operations from 2-misc:
9557 * SADDLP, UADDLP, SADALP, UADALP.
9558 * These all add pairs of elements in the input to produce a
9559 * double-width result element in the output (possibly accumulating).
9561 bool accum
= (opcode
== 0x6);
9562 int maxpass
= is_q
? 2 : 1;
9564 TCGv_i64 tcg_res
[2];
9567 /* 32 + 32 -> 64 op */
9568 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9570 for (pass
= 0; pass
< maxpass
; pass
++) {
9571 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9572 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9574 tcg_res
[pass
] = tcg_temp_new_i64();
9576 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9577 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9578 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9580 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9581 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9584 tcg_temp_free_i64(tcg_op1
);
9585 tcg_temp_free_i64(tcg_op2
);
9588 for (pass
= 0; pass
< maxpass
; pass
++) {
9589 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9590 NeonGenOneOpFn
*genfn
;
9591 static NeonGenOneOpFn
* const fns
[2][2] = {
9592 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9593 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9596 genfn
= fns
[size
][u
];
9598 tcg_res
[pass
] = tcg_temp_new_i64();
9600 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9601 genfn(tcg_res
[pass
], tcg_op
);
9604 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9606 gen_helper_neon_addl_u16(tcg_res
[pass
],
9607 tcg_res
[pass
], tcg_op
);
9609 gen_helper_neon_addl_u32(tcg_res
[pass
],
9610 tcg_res
[pass
], tcg_op
);
9613 tcg_temp_free_i64(tcg_op
);
9617 tcg_res
[1] = tcg_const_i64(0);
9619 for (pass
= 0; pass
< 2; pass
++) {
9620 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9621 tcg_temp_free_i64(tcg_res
[pass
]);
9625 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9627 /* Implement SHLL and SHLL2 */
9629 int part
= is_q
? 2 : 0;
9630 TCGv_i64 tcg_res
[2];
9632 for (pass
= 0; pass
< 2; pass
++) {
9633 static NeonGenWidenFn
* const widenfns
[3] = {
9634 gen_helper_neon_widen_u8
,
9635 gen_helper_neon_widen_u16
,
9636 tcg_gen_extu_i32_i64
,
9638 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9639 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9641 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9642 tcg_res
[pass
] = tcg_temp_new_i64();
9643 widenfn(tcg_res
[pass
], tcg_op
);
9644 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9646 tcg_temp_free_i32(tcg_op
);
9649 for (pass
= 0; pass
< 2; pass
++) {
9650 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9651 tcg_temp_free_i64(tcg_res
[pass
]);
9655 /* C3.6.17 AdvSIMD two reg misc
9656 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9657 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9658 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9659 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9661 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9663 int size
= extract32(insn
, 22, 2);
9664 int opcode
= extract32(insn
, 12, 5);
9665 bool u
= extract32(insn
, 29, 1);
9666 bool is_q
= extract32(insn
, 30, 1);
9667 int rn
= extract32(insn
, 5, 5);
9668 int rd
= extract32(insn
, 0, 5);
9669 bool need_fpstatus
= false;
9670 bool need_rmode
= false;
9673 TCGv_ptr tcg_fpstatus
;
9676 case 0x0: /* REV64, REV32 */
9677 case 0x1: /* REV16 */
9678 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9680 case 0x5: /* CNT, NOT, RBIT */
9681 if (u
&& size
== 0) {
9682 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9685 } else if (u
&& size
== 1) {
9688 } else if (!u
&& size
== 0) {
9692 unallocated_encoding(s
);
9694 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9695 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9697 unallocated_encoding(s
);
9700 if (!fp_access_check(s
)) {
9704 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9706 case 0x4: /* CLS, CLZ */
9708 unallocated_encoding(s
);
9712 case 0x2: /* SADDLP, UADDLP */
9713 case 0x6: /* SADALP, UADALP */
9715 unallocated_encoding(s
);
9718 if (!fp_access_check(s
)) {
9721 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9723 case 0x13: /* SHLL, SHLL2 */
9724 if (u
== 0 || size
== 3) {
9725 unallocated_encoding(s
);
9728 if (!fp_access_check(s
)) {
9731 handle_shll(s
, is_q
, size
, rn
, rd
);
9733 case 0xa: /* CMLT */
9735 unallocated_encoding(s
);
9739 case 0x8: /* CMGT, CMGE */
9740 case 0x9: /* CMEQ, CMLE */
9741 case 0xb: /* ABS, NEG */
9742 if (size
== 3 && !is_q
) {
9743 unallocated_encoding(s
);
9747 case 0x3: /* SUQADD, USQADD */
9748 if (size
== 3 && !is_q
) {
9749 unallocated_encoding(s
);
9752 if (!fp_access_check(s
)) {
9755 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9757 case 0x7: /* SQABS, SQNEG */
9758 if (size
== 3 && !is_q
) {
9759 unallocated_encoding(s
);
9767 /* Floating point: U, size[1] and opcode indicate operation;
9768 * size[0] indicates single or double precision.
9770 int is_double
= extract32(size
, 0, 1);
9771 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9772 size
= is_double
? 3 : 2;
9774 case 0x2f: /* FABS */
9775 case 0x6f: /* FNEG */
9776 if (size
== 3 && !is_q
) {
9777 unallocated_encoding(s
);
9781 case 0x1d: /* SCVTF */
9782 case 0x5d: /* UCVTF */
9784 bool is_signed
= (opcode
== 0x1d) ? true : false;
9785 int elements
= is_double
? 2 : is_q
? 4 : 2;
9786 if (is_double
&& !is_q
) {
9787 unallocated_encoding(s
);
9790 if (!fp_access_check(s
)) {
9793 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9796 case 0x2c: /* FCMGT (zero) */
9797 case 0x2d: /* FCMEQ (zero) */
9798 case 0x2e: /* FCMLT (zero) */
9799 case 0x6c: /* FCMGE (zero) */
9800 case 0x6d: /* FCMLE (zero) */
9801 if (size
== 3 && !is_q
) {
9802 unallocated_encoding(s
);
9805 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9807 case 0x7f: /* FSQRT */
9808 if (size
== 3 && !is_q
) {
9809 unallocated_encoding(s
);
9813 case 0x1a: /* FCVTNS */
9814 case 0x1b: /* FCVTMS */
9815 case 0x3a: /* FCVTPS */
9816 case 0x3b: /* FCVTZS */
9817 case 0x5a: /* FCVTNU */
9818 case 0x5b: /* FCVTMU */
9819 case 0x7a: /* FCVTPU */
9820 case 0x7b: /* FCVTZU */
9821 need_fpstatus
= true;
9823 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9824 if (size
== 3 && !is_q
) {
9825 unallocated_encoding(s
);
9829 case 0x5c: /* FCVTAU */
9830 case 0x1c: /* FCVTAS */
9831 need_fpstatus
= true;
9833 rmode
= FPROUNDING_TIEAWAY
;
9834 if (size
== 3 && !is_q
) {
9835 unallocated_encoding(s
);
9839 case 0x3c: /* URECPE */
9841 unallocated_encoding(s
);
9845 case 0x3d: /* FRECPE */
9846 case 0x7d: /* FRSQRTE */
9847 if (size
== 3 && !is_q
) {
9848 unallocated_encoding(s
);
9851 if (!fp_access_check(s
)) {
9854 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9856 case 0x56: /* FCVTXN, FCVTXN2 */
9858 unallocated_encoding(s
);
9862 case 0x16: /* FCVTN, FCVTN2 */
9863 /* handle_2misc_narrow does a 2*size -> size operation, but these
9864 * instructions encode the source size rather than dest size.
9866 if (!fp_access_check(s
)) {
9869 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9871 case 0x17: /* FCVTL, FCVTL2 */
9872 if (!fp_access_check(s
)) {
9875 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9877 case 0x18: /* FRINTN */
9878 case 0x19: /* FRINTM */
9879 case 0x38: /* FRINTP */
9880 case 0x39: /* FRINTZ */
9882 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9884 case 0x59: /* FRINTX */
9885 case 0x79: /* FRINTI */
9886 need_fpstatus
= true;
9887 if (size
== 3 && !is_q
) {
9888 unallocated_encoding(s
);
9892 case 0x58: /* FRINTA */
9894 rmode
= FPROUNDING_TIEAWAY
;
9895 need_fpstatus
= true;
9896 if (size
== 3 && !is_q
) {
9897 unallocated_encoding(s
);
9901 case 0x7c: /* URSQRTE */
9903 unallocated_encoding(s
);
9906 need_fpstatus
= true;
9909 unallocated_encoding(s
);
9915 unallocated_encoding(s
);
9919 if (!fp_access_check(s
)) {
9923 if (need_fpstatus
) {
9924 tcg_fpstatus
= get_fpstatus_ptr();
9926 TCGV_UNUSED_PTR(tcg_fpstatus
);
9929 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9930 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9932 TCGV_UNUSED_I32(tcg_rmode
);
9936 /* All 64-bit element operations can be shared with scalar 2misc */
9939 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9940 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9941 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9943 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9945 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9946 tcg_rmode
, tcg_fpstatus
);
9948 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9950 tcg_temp_free_i64(tcg_res
);
9951 tcg_temp_free_i64(tcg_op
);
9956 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9957 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9958 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9961 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9964 /* Special cases for 32 bit elements */
9966 case 0xa: /* CMLT */
9967 /* 32 bit integer comparison against zero, result is
9968 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9973 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9974 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9976 case 0x8: /* CMGT, CMGE */
9977 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9979 case 0x9: /* CMEQ, CMLE */
9980 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9984 gen_helper_clz32(tcg_res
, tcg_op
);
9986 gen_helper_cls32(tcg_res
, tcg_op
);
9989 case 0x7: /* SQABS, SQNEG */
9991 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
9993 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
9996 case 0xb: /* ABS, NEG */
9998 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10000 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10001 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10002 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10003 tcg_zero
, tcg_op
, tcg_res
);
10004 tcg_temp_free_i32(tcg_zero
);
10007 case 0x2f: /* FABS */
10008 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10010 case 0x6f: /* FNEG */
10011 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10013 case 0x7f: /* FSQRT */
10014 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10016 case 0x1a: /* FCVTNS */
10017 case 0x1b: /* FCVTMS */
10018 case 0x1c: /* FCVTAS */
10019 case 0x3a: /* FCVTPS */
10020 case 0x3b: /* FCVTZS */
10022 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10023 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10024 tcg_shift
, tcg_fpstatus
);
10025 tcg_temp_free_i32(tcg_shift
);
10028 case 0x5a: /* FCVTNU */
10029 case 0x5b: /* FCVTMU */
10030 case 0x5c: /* FCVTAU */
10031 case 0x7a: /* FCVTPU */
10032 case 0x7b: /* FCVTZU */
10034 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10035 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10036 tcg_shift
, tcg_fpstatus
);
10037 tcg_temp_free_i32(tcg_shift
);
10040 case 0x18: /* FRINTN */
10041 case 0x19: /* FRINTM */
10042 case 0x38: /* FRINTP */
10043 case 0x39: /* FRINTZ */
10044 case 0x58: /* FRINTA */
10045 case 0x79: /* FRINTI */
10046 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10048 case 0x59: /* FRINTX */
10049 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10051 case 0x7c: /* URSQRTE */
10052 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10055 g_assert_not_reached();
10058 /* Use helpers for 8 and 16 bit elements */
10060 case 0x5: /* CNT, RBIT */
10061 /* For these two insns size is part of the opcode specifier
10062 * (handled earlier); they always operate on byte elements.
10065 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10067 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10070 case 0x7: /* SQABS, SQNEG */
10072 NeonGenOneOpEnvFn
*genfn
;
10073 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10074 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10075 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10077 genfn
= fns
[size
][u
];
10078 genfn(tcg_res
, cpu_env
, tcg_op
);
10081 case 0x8: /* CMGT, CMGE */
10082 case 0x9: /* CMEQ, CMLE */
10083 case 0xa: /* CMLT */
10085 static NeonGenTwoOpFn
* const fns
[3][2] = {
10086 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10087 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10088 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10090 NeonGenTwoOpFn
*genfn
;
10093 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10095 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10096 comp
= (opcode
- 0x8) * 2 + u
;
10097 /* ...but LE, LT are implemented as reverse GE, GT */
10098 reverse
= (comp
> 2);
10102 genfn
= fns
[comp
][size
];
10104 genfn(tcg_res
, tcg_zero
, tcg_op
);
10106 genfn(tcg_res
, tcg_op
, tcg_zero
);
10108 tcg_temp_free_i32(tcg_zero
);
10111 case 0xb: /* ABS, NEG */
10113 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10115 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10117 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10119 tcg_temp_free_i32(tcg_zero
);
10122 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10124 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10128 case 0x4: /* CLS, CLZ */
10131 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10133 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10137 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10139 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10144 g_assert_not_reached();
10148 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10150 tcg_temp_free_i32(tcg_res
);
10151 tcg_temp_free_i32(tcg_op
);
10155 clear_vec_high(s
, rd
);
10159 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10160 tcg_temp_free_i32(tcg_rmode
);
10162 if (need_fpstatus
) {
10163 tcg_temp_free_ptr(tcg_fpstatus
);
10167 /* C3.6.13 AdvSIMD scalar x indexed element
10168 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10169 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10170 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10171 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10172 * C3.6.18 AdvSIMD vector x indexed element
10173 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10174 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10175 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10176 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10178 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10180 /* This encoding has two kinds of instruction:
10181 * normal, where we perform elt x idxelt => elt for each
10182 * element in the vector
10183 * long, where we perform elt x idxelt and generate a result of
10184 * double the width of the input element
10185 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10187 bool is_scalar
= extract32(insn
, 28, 1);
10188 bool is_q
= extract32(insn
, 30, 1);
10189 bool u
= extract32(insn
, 29, 1);
10190 int size
= extract32(insn
, 22, 2);
10191 int l
= extract32(insn
, 21, 1);
10192 int m
= extract32(insn
, 20, 1);
10193 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10194 int rm
= extract32(insn
, 16, 4);
10195 int opcode
= extract32(insn
, 12, 4);
10196 int h
= extract32(insn
, 11, 1);
10197 int rn
= extract32(insn
, 5, 5);
10198 int rd
= extract32(insn
, 0, 5);
10199 bool is_long
= false;
10200 bool is_fp
= false;
10205 case 0x0: /* MLA */
10206 case 0x4: /* MLS */
10207 if (!u
|| is_scalar
) {
10208 unallocated_encoding(s
);
10212 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10213 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10214 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10216 unallocated_encoding(s
);
10221 case 0x3: /* SQDMLAL, SQDMLAL2 */
10222 case 0x7: /* SQDMLSL, SQDMLSL2 */
10223 case 0xb: /* SQDMULL, SQDMULL2 */
10226 case 0xc: /* SQDMULH */
10227 case 0xd: /* SQRDMULH */
10229 unallocated_encoding(s
);
10233 case 0x8: /* MUL */
10234 if (u
|| is_scalar
) {
10235 unallocated_encoding(s
);
10239 case 0x1: /* FMLA */
10240 case 0x5: /* FMLS */
10242 unallocated_encoding(s
);
10246 case 0x9: /* FMUL, FMULX */
10247 if (!extract32(size
, 1, 1)) {
10248 unallocated_encoding(s
);
10254 unallocated_encoding(s
);
10259 /* low bit of size indicates single/double */
10260 size
= extract32(size
, 0, 1) ? 3 : 2;
10262 index
= h
<< 1 | l
;
10265 unallocated_encoding(s
);
10274 index
= h
<< 2 | l
<< 1 | m
;
10277 index
= h
<< 1 | l
;
10281 unallocated_encoding(s
);
10286 if (!fp_access_check(s
)) {
10291 fpst
= get_fpstatus_ptr();
10293 TCGV_UNUSED_PTR(fpst
);
10297 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10300 assert(is_fp
&& is_q
&& !is_long
);
10302 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10304 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10305 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10306 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10308 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10311 case 0x5: /* FMLS */
10312 /* As usual for ARM, separate negation for fused multiply-add */
10313 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10315 case 0x1: /* FMLA */
10316 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10317 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10319 case 0x9: /* FMUL, FMULX */
10321 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10323 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10327 g_assert_not_reached();
10330 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10331 tcg_temp_free_i64(tcg_op
);
10332 tcg_temp_free_i64(tcg_res
);
10336 clear_vec_high(s
, rd
);
10339 tcg_temp_free_i64(tcg_idx
);
10340 } else if (!is_long
) {
10341 /* 32 bit floating point, or 16 or 32 bit integer.
10342 * For the 16 bit scalar case we use the usual Neon helpers and
10343 * rely on the fact that 0 op 0 == 0 with no side effects.
10345 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10346 int pass
, maxpasses
;
10351 maxpasses
= is_q
? 4 : 2;
10354 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10356 if (size
== 1 && !is_scalar
) {
10357 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10358 * the index into both halves of the 32 bit tcg_idx and then use
10359 * the usual Neon helpers.
10361 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10364 for (pass
= 0; pass
< maxpasses
; pass
++) {
10365 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10366 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10368 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10371 case 0x0: /* MLA */
10372 case 0x4: /* MLS */
10373 case 0x8: /* MUL */
10375 static NeonGenTwoOpFn
* const fns
[2][2] = {
10376 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10377 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10379 NeonGenTwoOpFn
*genfn
;
10380 bool is_sub
= opcode
== 0x4;
10383 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10385 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10387 if (opcode
== 0x8) {
10390 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10391 genfn
= fns
[size
- 1][is_sub
];
10392 genfn(tcg_res
, tcg_op
, tcg_res
);
10395 case 0x5: /* FMLS */
10396 /* As usual for ARM, separate negation for fused multiply-add */
10397 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10399 case 0x1: /* FMLA */
10400 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10401 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10403 case 0x9: /* FMUL, FMULX */
10405 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10407 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10410 case 0xc: /* SQDMULH */
10412 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10415 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10419 case 0xd: /* SQRDMULH */
10421 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10424 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10429 g_assert_not_reached();
10433 write_fp_sreg(s
, rd
, tcg_res
);
10435 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10438 tcg_temp_free_i32(tcg_op
);
10439 tcg_temp_free_i32(tcg_res
);
10442 tcg_temp_free_i32(tcg_idx
);
10445 clear_vec_high(s
, rd
);
10448 /* long ops: 16x16->32 or 32x32->64 */
10449 TCGv_i64 tcg_res
[2];
10451 bool satop
= extract32(opcode
, 0, 1);
10452 TCGMemOp memop
= MO_32
;
10459 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10461 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10463 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10464 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10465 TCGv_i64 tcg_passres
;
10471 passelt
= pass
+ (is_q
* 2);
10474 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10476 tcg_res
[pass
] = tcg_temp_new_i64();
10478 if (opcode
== 0xa || opcode
== 0xb) {
10479 /* Non-accumulating ops */
10480 tcg_passres
= tcg_res
[pass
];
10482 tcg_passres
= tcg_temp_new_i64();
10485 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10486 tcg_temp_free_i64(tcg_op
);
10489 /* saturating, doubling */
10490 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10491 tcg_passres
, tcg_passres
);
10494 if (opcode
== 0xa || opcode
== 0xb) {
10498 /* Accumulating op: handle accumulate step */
10499 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10502 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10503 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10505 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10506 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10508 case 0x7: /* SQDMLSL, SQDMLSL2 */
10509 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10511 case 0x3: /* SQDMLAL, SQDMLAL2 */
10512 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10517 g_assert_not_reached();
10519 tcg_temp_free_i64(tcg_passres
);
10521 tcg_temp_free_i64(tcg_idx
);
10524 clear_vec_high(s
, rd
);
10527 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10530 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10533 /* The simplest way to handle the 16x16 indexed ops is to
10534 * duplicate the index into both halves of the 32 bit tcg_idx
10535 * and then use the usual Neon helpers.
10537 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10540 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10541 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10542 TCGv_i64 tcg_passres
;
10545 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10547 read_vec_element_i32(s
, tcg_op
, rn
,
10548 pass
+ (is_q
* 2), MO_32
);
10551 tcg_res
[pass
] = tcg_temp_new_i64();
10553 if (opcode
== 0xa || opcode
== 0xb) {
10554 /* Non-accumulating ops */
10555 tcg_passres
= tcg_res
[pass
];
10557 tcg_passres
= tcg_temp_new_i64();
10560 if (memop
& MO_SIGN
) {
10561 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10563 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10566 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10567 tcg_passres
, tcg_passres
);
10569 tcg_temp_free_i32(tcg_op
);
10571 if (opcode
== 0xa || opcode
== 0xb) {
10575 /* Accumulating op: handle accumulate step */
10576 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10579 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10580 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10583 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10584 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10587 case 0x7: /* SQDMLSL, SQDMLSL2 */
10588 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10590 case 0x3: /* SQDMLAL, SQDMLAL2 */
10591 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10596 g_assert_not_reached();
10598 tcg_temp_free_i64(tcg_passres
);
10600 tcg_temp_free_i32(tcg_idx
);
10603 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10608 tcg_res
[1] = tcg_const_i64(0);
10611 for (pass
= 0; pass
< 2; pass
++) {
10612 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10613 tcg_temp_free_i64(tcg_res
[pass
]);
10617 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10618 tcg_temp_free_ptr(fpst
);
10622 /* C3.6.19 Crypto AES
10623 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10624 * +-----------------+------+-----------+--------+-----+------+------+
10625 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10626 * +-----------------+------+-----------+--------+-----+------+------+
10628 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10630 int size
= extract32(insn
, 22, 2);
10631 int opcode
= extract32(insn
, 12, 5);
10632 int rn
= extract32(insn
, 5, 5);
10633 int rd
= extract32(insn
, 0, 5);
10635 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10636 CryptoThreeOpEnvFn
*genfn
;
10638 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10640 unallocated_encoding(s
);
10645 case 0x4: /* AESE */
10647 genfn
= gen_helper_crypto_aese
;
10649 case 0x6: /* AESMC */
10651 genfn
= gen_helper_crypto_aesmc
;
10653 case 0x5: /* AESD */
10655 genfn
= gen_helper_crypto_aese
;
10657 case 0x7: /* AESIMC */
10659 genfn
= gen_helper_crypto_aesmc
;
10662 unallocated_encoding(s
);
10666 /* Note that we convert the Vx register indexes into the
10667 * index within the vfp.regs[] array, so we can share the
10668 * helper with the AArch32 instructions.
10670 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10671 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10672 tcg_decrypt
= tcg_const_i32(decrypt
);
10674 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10676 tcg_temp_free_i32(tcg_rd_regno
);
10677 tcg_temp_free_i32(tcg_rn_regno
);
10678 tcg_temp_free_i32(tcg_decrypt
);
10681 /* C3.6.20 Crypto three-reg SHA
10682 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10683 * +-----------------+------+---+------+---+--------+-----+------+------+
10684 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10685 * +-----------------+------+---+------+---+--------+-----+------+------+
10687 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10689 int size
= extract32(insn
, 22, 2);
10690 int opcode
= extract32(insn
, 12, 3);
10691 int rm
= extract32(insn
, 16, 5);
10692 int rn
= extract32(insn
, 5, 5);
10693 int rd
= extract32(insn
, 0, 5);
10694 CryptoThreeOpEnvFn
*genfn
;
10695 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10696 int feature
= ARM_FEATURE_V8_SHA256
;
10699 unallocated_encoding(s
);
10704 case 0: /* SHA1C */
10705 case 1: /* SHA1P */
10706 case 2: /* SHA1M */
10707 case 3: /* SHA1SU0 */
10709 feature
= ARM_FEATURE_V8_SHA1
;
10711 case 4: /* SHA256H */
10712 genfn
= gen_helper_crypto_sha256h
;
10714 case 5: /* SHA256H2 */
10715 genfn
= gen_helper_crypto_sha256h2
;
10717 case 6: /* SHA256SU1 */
10718 genfn
= gen_helper_crypto_sha256su1
;
10721 unallocated_encoding(s
);
10725 if (!arm_dc_feature(s
, feature
)) {
10726 unallocated_encoding(s
);
10730 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10731 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10732 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
10735 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
10737 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
10739 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
10740 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
10741 tcg_temp_free_i32(tcg_opcode
);
10744 tcg_temp_free_i32(tcg_rd_regno
);
10745 tcg_temp_free_i32(tcg_rn_regno
);
10746 tcg_temp_free_i32(tcg_rm_regno
);
10749 /* C3.6.21 Crypto two-reg SHA
10750 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10751 * +-----------------+------+-----------+--------+-----+------+------+
10752 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10753 * +-----------------+------+-----------+--------+-----+------+------+
10755 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10757 int size
= extract32(insn
, 22, 2);
10758 int opcode
= extract32(insn
, 12, 5);
10759 int rn
= extract32(insn
, 5, 5);
10760 int rd
= extract32(insn
, 0, 5);
10761 CryptoTwoOpEnvFn
*genfn
;
10763 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
10766 unallocated_encoding(s
);
10771 case 0: /* SHA1H */
10772 feature
= ARM_FEATURE_V8_SHA1
;
10773 genfn
= gen_helper_crypto_sha1h
;
10775 case 1: /* SHA1SU1 */
10776 feature
= ARM_FEATURE_V8_SHA1
;
10777 genfn
= gen_helper_crypto_sha1su1
;
10779 case 2: /* SHA256SU0 */
10780 feature
= ARM_FEATURE_V8_SHA256
;
10781 genfn
= gen_helper_crypto_sha256su0
;
10784 unallocated_encoding(s
);
10788 if (!arm_dc_feature(s
, feature
)) {
10789 unallocated_encoding(s
);
10793 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10794 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10796 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
10798 tcg_temp_free_i32(tcg_rd_regno
);
10799 tcg_temp_free_i32(tcg_rn_regno
);
10802 /* C3.6 Data processing - SIMD, inc Crypto
10804 * As the decode gets a little complex we are using a table based
10805 * approach for this part of the decode.
10807 static const AArch64DecodeTable data_proc_simd
[] = {
10808 /* pattern , mask , fn */
10809 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10810 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10811 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10812 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10813 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10814 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10815 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10816 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10817 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10818 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10819 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10820 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10821 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10822 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10823 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10824 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10825 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10826 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10827 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10828 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10829 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10830 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10831 { 0x00000000, 0x00000000, NULL
}
10834 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10836 /* Note that this is called with all non-FP cases from
10837 * table C3-6 so it must UNDEF for entries not specifically
10838 * allocated to instructions in that table.
10840 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10844 unallocated_encoding(s
);
10848 /* C3.6 Data processing - SIMD and floating point */
10849 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10851 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10852 disas_data_proc_fp(s
, insn
);
10854 /* SIMD, including crypto */
10855 disas_data_proc_simd(s
, insn
);
10859 /* C3.1 A64 instruction index by encoding */
10860 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10864 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10868 s
->fp_access_checked
= false;
10870 switch (extract32(insn
, 25, 4)) {
10871 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10872 unallocated_encoding(s
);
10874 case 0x8: case 0x9: /* Data processing - immediate */
10875 disas_data_proc_imm(s
, insn
);
10877 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10878 disas_b_exc_sys(s
, insn
);
10883 case 0xe: /* Loads and stores */
10884 disas_ldst(s
, insn
);
10887 case 0xd: /* Data processing - register */
10888 disas_data_proc_reg(s
, insn
);
10891 case 0xf: /* Data processing - SIMD and floating point */
10892 disas_data_proc_simd_fp(s
, insn
);
10895 assert(FALSE
); /* all 15 cases should be handled above */
10899 /* if we allocated any temporaries, free them here */
10903 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
10904 TranslationBlock
*tb
,
10907 CPUState
*cs
= CPU(cpu
);
10908 CPUARMState
*env
= &cpu
->env
;
10909 DisasContext dc1
, *dc
= &dc1
;
10912 target_ulong pc_start
;
10913 target_ulong next_page_start
;
10921 dc
->is_jmp
= DISAS_NEXT
;
10923 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10927 dc
->el3_is_aa64
= arm_el_is_aa64(env
, 3);
10929 dc
->bswap_code
= 0;
10930 dc
->condexec_mask
= 0;
10931 dc
->condexec_cond
= 0;
10932 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
10933 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
10934 #if !defined(CONFIG_USER_ONLY)
10935 dc
->user
= (dc
->current_el
== 0);
10937 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
10939 dc
->vec_stride
= 0;
10940 dc
->cp_regs
= cpu
->cp_regs
;
10941 dc
->features
= env
->features
;
10943 /* Single step state. The code-generation logic here is:
10945 * generate code with no special handling for single-stepping (except
10946 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
10947 * this happens anyway because those changes are all system register or
10949 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
10950 * emit code for one insn
10951 * emit code to clear PSTATE.SS
10952 * emit code to generate software step exception for completed step
10953 * end TB (as usual for having generated an exception)
10954 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
10955 * emit code to generate a software step exception
10958 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
10959 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
10960 dc
->is_ldex
= false;
10961 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
10963 init_tmp_a64_array(dc
);
10965 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10968 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10969 if (max_insns
== 0) {
10970 max_insns
= CF_COUNT_MASK
;
10975 tcg_clear_temp_count();
10978 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
10979 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
10980 if (bp
->pc
== dc
->pc
) {
10981 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
10982 /* Advance PC so that clearing the breakpoint will
10983 invalidate this TB. */
10985 goto done_generating
;
10991 j
= tcg_op_buf_count();
10995 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10998 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
10999 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
11000 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
11003 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11007 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
11008 tcg_gen_debug_insn_start(dc
->pc
);
11011 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11012 /* Singlestep state is Active-pending.
11013 * If we're in this state at the start of a TB then either
11014 * a) we just took an exception to an EL which is being debugged
11015 * and this is the first insn in the exception handler
11016 * b) debug exceptions were masked and we just unmasked them
11017 * without changing EL (eg by clearing PSTATE.D)
11018 * In either case we're going to take a swstep exception in the
11019 * "did not step an insn" case, and so the syndrome ISV and EX
11020 * bits should be zero.
11022 assert(num_insns
== 0);
11023 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11024 default_exception_el(dc
));
11025 dc
->is_jmp
= DISAS_EXC
;
11029 disas_a64_insn(env
, dc
);
11031 if (tcg_check_temp_count()) {
11032 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11036 /* Translation stops when a conditional branch is encountered.
11037 * Otherwise the subsequent code could get translated several times.
11038 * Also stop translation when a page boundary is reached. This
11039 * ensures prefetch aborts occur at the right place.
11042 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11043 !cs
->singlestep_enabled
&&
11046 dc
->pc
< next_page_start
&&
11047 num_insns
< max_insns
);
11049 if (tb
->cflags
& CF_LAST_IO
) {
11053 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11054 && dc
->is_jmp
!= DISAS_EXC
) {
11055 /* Note that this means single stepping WFI doesn't halt the CPU.
11056 * For conditional branch insns this is harmless unreachable code as
11057 * gen_goto_tb() has already handled emitting the debug exception
11058 * (and thus a tb-jump is not possible when singlestepping).
11060 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11061 if (dc
->is_jmp
!= DISAS_JUMP
) {
11062 gen_a64_set_pc_im(dc
->pc
);
11064 if (cs
->singlestep_enabled
) {
11065 gen_exception_internal(EXCP_DEBUG
);
11067 gen_step_complete_exception(dc
);
11070 switch (dc
->is_jmp
) {
11072 gen_goto_tb(dc
, 1, dc
->pc
);
11076 gen_a64_set_pc_im(dc
->pc
);
11079 /* indicate that the hash table must be used to find the next TB */
11080 tcg_gen_exit_tb(0);
11082 case DISAS_TB_JUMP
:
11087 gen_a64_set_pc_im(dc
->pc
);
11088 gen_helper_wfe(cpu_env
);
11091 gen_a64_set_pc_im(dc
->pc
);
11092 gen_helper_yield(cpu_env
);
11095 /* This is a special case because we don't want to just halt the CPU
11096 * if trying to debug across a WFI.
11098 gen_a64_set_pc_im(dc
->pc
);
11099 gen_helper_wfi(cpu_env
);
11100 /* The helper doesn't necessarily throw an exception, but we
11101 * must go back to the main loop to check for interrupts anyway.
11103 tcg_gen_exit_tb(0);
11109 gen_tb_end(tb
, num_insns
);
11112 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
11113 qemu_log("----------------\n");
11114 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11115 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11116 4 | (dc
->bswap_code
<< 1));
11121 j
= tcg_op_buf_count();
11124 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
11127 tb
->size
= dc
->pc
- pc_start
;
11128 tb
->icount
= num_insns
;