exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* is_jmp field values */
  29 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  30 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  31 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  32 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  33
  34 typedef struct TranslationBlock TranslationBlock;
  35
  36 /* XXX: make safe guess about sizes */
  37 #define MAX_OP_PER_INSTR 96
  38 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  39 #define MAX_OPC_PARAM 10
  40 #define OPC_BUF_SIZE 640
  41 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  42
  43 /* Maximum size a TCG op can expand to.  This is complicated because a
  44    single op may require several host instructions and register reloads.
  45    For now take a wild guess at 192 bytes, which should allow at least
  46    a couple of fixup instructions per argument.  */
  47 #define TCG_MAX_OP_SIZE 192
  48
  49 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  50
  51 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  52 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  53 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  54 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  55 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  56 extern target_ulong gen_opc_jump_pc[2];
  57 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  58
  59 #include "qemu-log.h"
  60
  61 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  62 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  63 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  64                  unsigned long searched_pc, int pc_pos, void *puc);
  65
  66 unsigned long code_gen_max_block_size(void);
  67 void cpu_gen_init(void);
  68 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  69                  int *gen_code_size_ptr);
  70 int cpu_restore_state(struct TranslationBlock *tb,
  71                       CPUState *env, unsigned long searched_pc,
  72                       void *puc);
  73 int cpu_restore_state_copy(struct TranslationBlock *tb,
  74                            CPUState *env, unsigned long searched_pc,
  75                            void *puc);
  76 void cpu_resume_from_signal(CPUState *env1, void *puc);
  77 void cpu_io_recompile(CPUState *env, void *retaddr);
  78 TranslationBlock *tb_gen_code(CPUState *env,
  79                               target_ulong pc, target_ulong cs_base, int flags,
  80                               int cflags);
  81 void cpu_exec_init(CPUState *env);
  82 void QEMU_NORETURN cpu_loop_exit(void);
  83 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  84 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  85                                    int is_cpu_write_access);
  86 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  87 void tlb_flush_page(CPUState *env, target_ulong addr);
  88 void tlb_flush(CPUState *env, int flush_global);
  89 #if !defined(CONFIG_USER_ONLY)
  90 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  91                       target_phys_addr_t paddr, int prot,
  92                       int mmu_idx, int is_softmmu);
  93 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
  94                                target_phys_addr_t paddr, int prot,
  95                                int mmu_idx, int is_softmmu)
  96 {
  97     if (prot & PAGE_READ)
  98         prot |= PAGE_EXEC;
  99     return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
 100 }
 101 #endif
 102
 103 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 104
 105 #define CODE_GEN_PHYS_HASH_BITS     15
 106 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 107
 108 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 109
 110 /* estimated block size for TB allocation */
 111 /* XXX: use a per code average code fragment size and modulate it
 112    according to the host CPU */
 113 #if defined(CONFIG_SOFTMMU)
 114 #define CODE_GEN_AVG_BLOCK_SIZE 128
 115 #else
 116 #define CODE_GEN_AVG_BLOCK_SIZE 64
 117 #endif
 118
 119 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
 120 #define USE_DIRECT_JUMP
 121 #endif
 122
 123 struct TranslationBlock {
 124     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 125     target_ulong cs_base; /* CS base for this block */
 126     uint64_t flags; /* flags defining in which context the code was generated */
 127     uint16_t size;      /* size of target code for this block (1 <=
 128                            size <= TARGET_PAGE_SIZE) */
 129     uint16_t cflags;    /* compile flags */
 130 #define CF_COUNT_MASK  0x7fff
 131 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 132
 133     uint8_t *tc_ptr;    /* pointer to the translated code */
 134     /* next matching tb for physical address. */
 135     struct TranslationBlock *phys_hash_next;
 136     /* first and second physical page containing code. The lower bit
 137        of the pointer tells the index in page_next[] */
 138     struct TranslationBlock *page_next[2];
 139     target_ulong page_addr[2];
 140
 141     /* the following data are used to directly call another TB from
 142        the code of this one. */
 143     uint16_t tb_next_offset[2]; /* offset of original jump target */
 144 #ifdef USE_DIRECT_JUMP
 145     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 146 #else
 147     unsigned long tb_next[2]; /* address of jump generated code */
 148 #endif
 149     /* list of TBs jumping to this one. This is a circular list using
 150        the two least significant bits of the pointers to tell what is
 151        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 152        jmp_first */
 153     struct TranslationBlock *jmp_next[2];
 154     struct TranslationBlock *jmp_first;
 155     uint32_t icount;
 156 };
 157
 158 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 159 {
 160     target_ulong tmp;
 161     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 162     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 163 }
 164
 165 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 166 {
 167     target_ulong tmp;
 168     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 169     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 170             | (tmp & TB_JMP_ADDR_MASK));
 171 }
 172
 173 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 174 {
 175     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 176 }
 177
 178 TranslationBlock *tb_alloc(target_ulong pc);
 179 void tb_free(TranslationBlock *tb);
 180 void tb_flush(CPUState *env);
 181 void tb_link_phys(TranslationBlock *tb,
 182                   target_ulong phys_pc, target_ulong phys_page2);
 183 void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
 184
 185 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 186 extern uint8_t *code_gen_ptr;
 187 extern int code_gen_max_blocks;
 188
 189 #if defined(USE_DIRECT_JUMP)
 190
 191 #if defined(_ARCH_PPC)
 192 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 193 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 194 #elif defined(__i386__) || defined(__x86_64__)
 195 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 196 {
 197     /* patch the branch destination */
 198     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 199     /* no need to flush icache explicitly */
 200 }
 201 #elif defined(__arm__)
 202 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 203 {
 204 #if QEMU_GNUC_PREREQ(4, 1)
 205     void __clear_cache(char *beg, char *end);
 206 #else
 207     register unsigned long _beg __asm ("a1");
 208     register unsigned long _end __asm ("a2");
 209     register unsigned long _flg __asm ("a3");
 210 #endif
 211
 212     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 213     *(uint32_t *)jmp_addr =
 214         (*(uint32_t *)jmp_addr & ~0xffffff)
 215         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 216
 217 #if QEMU_GNUC_PREREQ(4, 1)
 218     __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 219 #else
 220     /* flush icache */
 221     _beg = jmp_addr;
 222     _end = jmp_addr + 4;
 223     _flg = 0;
 224     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 225 #endif
 226 }
 227 #endif
 228
 229 static inline void tb_set_jmp_target(TranslationBlock *tb,
 230                                      int n, unsigned long addr)
 231 {
 232     unsigned long offset;
 233
 234     offset = tb->tb_jmp_offset[n];
 235     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 236     offset = tb->tb_jmp_offset[n + 2];
 237     if (offset != 0xffff)
 238         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 239 }
 240
 241 #else
 242
 243 /* set the jump target */
 244 static inline void tb_set_jmp_target(TranslationBlock *tb,
 245                                      int n, unsigned long addr)
 246 {
 247     tb->tb_next[n] = addr;
 248 }
 249
 250 #endif
 251
 252 static inline void tb_add_jump(TranslationBlock *tb, int n,
 253                                TranslationBlock *tb_next)
 254 {
 255     /* NOTE: this test is only needed for thread safety */
 256     if (!tb->jmp_next[n]) {
 257         /* patch the native jump address */
 258         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 259
 260         /* add in TB jmp circular list */
 261         tb->jmp_next[n] = tb_next->jmp_first;
 262         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 263     }
 264 }
 265
 266 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 267
 268 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 269 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 270 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 271
 272 #include "qemu-lock.h"
 273
 274 extern spinlock_t tb_lock;
 275
 276 extern int tb_invalidated_flag;
 277
 278 #if !defined(CONFIG_USER_ONLY)
 279
 280 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 281               void *retaddr);
 282
 283 #include "softmmu_defs.h"
 284
 285 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 286 #define MEMSUFFIX _code
 287 #define env cpu_single_env
 288
 289 #define DATA_SIZE 1
 290 #include "softmmu_header.h"
 291
 292 #define DATA_SIZE 2
 293 #include "softmmu_header.h"
 294
 295 #define DATA_SIZE 4
 296 #include "softmmu_header.h"
 297
 298 #define DATA_SIZE 8
 299 #include "softmmu_header.h"
 300
 301 #undef ACCESS_TYPE
 302 #undef MEMSUFFIX
 303 #undef env
 304
 305 #endif
 306
 307 #if defined(CONFIG_USER_ONLY)
 308 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 309 {
 310     return addr;
 311 }
 312 #else
 313 /* NOTE: this function can trigger an exception */
 314 /* NOTE2: the returned address is not exactly the physical address: it
 315    is the offset relative to phys_ram_base */
 316 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 317 {
 318     int mmu_idx, page_index, pd;
 319     void *p;
 320
 321     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 322     mmu_idx = cpu_mmu_index(env1);
 323     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 324                  (addr & TARGET_PAGE_MASK))) {
 325         ldub_code(addr);
 326     }
 327     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 328     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 329 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 330         do_unassigned_access(addr, 0, 1, 0, 4);
 331 #else
 332         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 333 #endif
 334     }
 335     p = (void *)(unsigned long)addr
 336         + env1->tlb_table[mmu_idx][page_index].addend;
 337     return qemu_ram_addr_from_host(p);
 338 }
 339
 340 /* Deterministic execution requires that IO only be performed on the last
 341    instruction of a TB so that interrupts take effect immediately.  */
 342 static inline int can_do_io(CPUState *env)
 343 {
 344     if (!use_icount)
 345         return 1;
 346
 347     /* If not executing code then assume we are ok.  */
 348     if (!env->current_tb)
 349         return 1;
 350
 351     return env->can_do_io != 0;
 352 }
 353 #endif
 354
 355 typedef void (CPUDebugExcpHandler)(CPUState *env);
 356
 357 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
 358
 359 /* vl.c */
 360 extern int singlestep;
 361
 362 #endif