target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31
  32 #define CPUArchState struct CPUS390XState
  33
  34 #include "exec/cpu-defs.h"
  35 #define TARGET_PAGE_BITS 12
  36
  37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  39
  40 #include "exec/cpu-all.h"
  41
  42 #include "fpu/softfloat.h"
  43
  44 #define NB_MMU_MODES 3
  45
  46 #define MMU_MODE0_SUFFIX _primary
  47 #define MMU_MODE1_SUFFIX _secondary
  48 #define MMU_MODE2_SUFFIX _home
  49
  50 #define MMU_USER_IDX 1
  51
  52 #define MAX_EXT_QUEUE 16
  53 #define MAX_IO_QUEUE 16
  54 #define MAX_MCHK_QUEUE 16
  55
  56 #define PSW_MCHK_MASK 0x0004000000000000
  57 #define PSW_IO_MASK 0x0200000000000000
  58
  59 typedef struct PSW {
  60     uint64_t mask;
  61     uint64_t addr;
  62 } PSW;
  63
  64 typedef struct ExtQueue {
  65     uint32_t code;
  66     uint32_t param;
  67     uint32_t param64;
  68 } ExtQueue;
  69
  70 typedef struct IOIntQueue {
  71     uint16_t id;
  72     uint16_t nr;
  73     uint32_t parm;
  74     uint32_t word;
  75 } IOIntQueue;
  76
  77 typedef struct MchkQueue {
  78     uint16_t type;
  79 } MchkQueue;
  80
  81 typedef struct CPUS390XState {
  82     uint64_t regs[16];     /* GP registers */
  83     CPU_DoubleU fregs[16]; /* FP registers */
  84     uint32_t aregs[16];    /* access registers */
  85
  86     uint32_t fpc;          /* floating-point control register */
  87     uint32_t cc_op;
  88
  89     float_status fpu_status; /* passed to softfloat lib */
  90
  91     /* The low part of a 128-bit return, or remainder of a divide.  */
  92     uint64_t retxl;
  93
  94     PSW psw;
  95
  96     uint64_t cc_src;
  97     uint64_t cc_dst;
  98     uint64_t cc_vr;
  99
 100     uint64_t __excp_addr;
 101     uint64_t psa;
 102
 103     uint32_t int_pgm_code;
 104     uint32_t int_pgm_ilen;
 105
 106     uint32_t int_svc_code;
 107     uint32_t int_svc_ilen;
 108
 109     uint64_t cregs[16]; /* control registers */
 110
 111     ExtQueue ext_queue[MAX_EXT_QUEUE];
 112     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 113     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 114
 115     int pending_int;
 116     int ext_index;
 117     int io_index[8];
 118     int mchk_index;
 119
 120     uint64_t ckc;
 121     uint64_t cputm;
 122     uint32_t todpr;
 123
 124     CPU_COMMON
 125
 126     /* reset does memset(0) up to here */
 127
 128     int cpu_num;
 129     uint8_t *storage_keys;
 130
 131     uint64_t tod_offset;
 132     uint64_t tod_basetime;
 133     QEMUTimer *tod_timer;
 134
 135     QEMUTimer *cpu_timer;
 136 } CPUS390XState;
 137
 138 #include "cpu-qom.h"
 139
 140 #if defined(CONFIG_USER_ONLY)
 141 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
 142 {
 143     if (newsp) {
 144         env->regs[15] = newsp;
 145     }
 146     env->regs[2] = 0;
 147 }
 148 #endif
 149
 150 /* distinguish between 24 bit and 31 bit addressing */
 151 #define HIGH_ORDER_BIT 0x80000000
 152
 153 /* Interrupt Codes */
 154 /* Program Interrupts */
 155 #define PGM_OPERATION                   0x0001
 156 #define PGM_PRIVILEGED                  0x0002
 157 #define PGM_EXECUTE                     0x0003
 158 #define PGM_PROTECTION                  0x0004
 159 #define PGM_ADDRESSING                  0x0005
 160 #define PGM_SPECIFICATION               0x0006
 161 #define PGM_DATA                        0x0007
 162 #define PGM_FIXPT_OVERFLOW              0x0008
 163 #define PGM_FIXPT_DIVIDE                0x0009
 164 #define PGM_DEC_OVERFLOW                0x000a
 165 #define PGM_DEC_DIVIDE                  0x000b
 166 #define PGM_HFP_EXP_OVERFLOW            0x000c
 167 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 168 #define PGM_HFP_SIGNIFICANCE            0x000e
 169 #define PGM_HFP_DIVIDE                  0x000f
 170 #define PGM_SEGMENT_TRANS               0x0010
 171 #define PGM_PAGE_TRANS                  0x0011
 172 #define PGM_TRANS_SPEC                  0x0012
 173 #define PGM_SPECIAL_OP                  0x0013
 174 #define PGM_OPERAND                     0x0015
 175 #define PGM_TRACE_TABLE                 0x0016
 176 #define PGM_SPACE_SWITCH                0x001c
 177 #define PGM_HFP_SQRT                    0x001d
 178 #define PGM_PC_TRANS_SPEC               0x001f
 179 #define PGM_AFX_TRANS                   0x0020
 180 #define PGM_ASX_TRANS                   0x0021
 181 #define PGM_LX_TRANS                    0x0022
 182 #define PGM_EX_TRANS                    0x0023
 183 #define PGM_PRIM_AUTH                   0x0024
 184 #define PGM_SEC_AUTH                    0x0025
 185 #define PGM_ALET_SPEC                   0x0028
 186 #define PGM_ALEN_SPEC                   0x0029
 187 #define PGM_ALE_SEQ                     0x002a
 188 #define PGM_ASTE_VALID                  0x002b
 189 #define PGM_ASTE_SEQ                    0x002c
 190 #define PGM_EXT_AUTH                    0x002d
 191 #define PGM_STACK_FULL                  0x0030
 192 #define PGM_STACK_EMPTY                 0x0031
 193 #define PGM_STACK_SPEC                  0x0032
 194 #define PGM_STACK_TYPE                  0x0033
 195 #define PGM_STACK_OP                    0x0034
 196 #define PGM_ASCE_TYPE                   0x0038
 197 #define PGM_REG_FIRST_TRANS             0x0039
 198 #define PGM_REG_SEC_TRANS               0x003a
 199 #define PGM_REG_THIRD_TRANS             0x003b
 200 #define PGM_MONITOR                     0x0040
 201 #define PGM_PER                         0x0080
 202 #define PGM_CRYPTO                      0x0119
 203
 204 /* External Interrupts */
 205 #define EXT_INTERRUPT_KEY               0x0040
 206 #define EXT_CLOCK_COMP                  0x1004
 207 #define EXT_CPU_TIMER                   0x1005
 208 #define EXT_MALFUNCTION                 0x1200
 209 #define EXT_EMERGENCY                   0x1201
 210 #define EXT_EXTERNAL_CALL               0x1202
 211 #define EXT_ETR                         0x1406
 212 #define EXT_SERVICE                     0x2401
 213 #define EXT_VIRTIO                      0x2603
 214
 215 /* PSW defines */
 216 #undef PSW_MASK_PER
 217 #undef PSW_MASK_DAT
 218 #undef PSW_MASK_IO
 219 #undef PSW_MASK_EXT
 220 #undef PSW_MASK_KEY
 221 #undef PSW_SHIFT_KEY
 222 #undef PSW_MASK_MCHECK
 223 #undef PSW_MASK_WAIT
 224 #undef PSW_MASK_PSTATE
 225 #undef PSW_MASK_ASC
 226 #undef PSW_MASK_CC
 227 #undef PSW_MASK_PM
 228 #undef PSW_MASK_64
 229
 230 #define PSW_MASK_PER            0x4000000000000000ULL
 231 #define PSW_MASK_DAT            0x0400000000000000ULL
 232 #define PSW_MASK_IO             0x0200000000000000ULL
 233 #define PSW_MASK_EXT            0x0100000000000000ULL
 234 #define PSW_MASK_KEY            0x00F0000000000000ULL
 235 #define PSW_SHIFT_KEY           56
 236 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 237 #define PSW_MASK_WAIT           0x0002000000000000ULL
 238 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 239 #define PSW_MASK_ASC            0x0000C00000000000ULL
 240 #define PSW_MASK_CC             0x0000300000000000ULL
 241 #define PSW_MASK_PM             0x00000F0000000000ULL
 242 #define PSW_MASK_64             0x0000000100000000ULL
 243 #define PSW_MASK_32             0x0000000080000000ULL
 244
 245 #undef PSW_ASC_PRIMARY
 246 #undef PSW_ASC_ACCREG
 247 #undef PSW_ASC_SECONDARY
 248 #undef PSW_ASC_HOME
 249
 250 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 251 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 252 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 253 #define PSW_ASC_HOME            0x0000C00000000000ULL
 254
 255 /* tb flags */
 256
 257 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 258 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 259 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 260 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 261 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 262 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 263 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 264 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 265 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 266 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 267 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 268 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 269 #define FLAG_MASK_32            0x00001000
 270
 271 static inline int cpu_mmu_index (CPUS390XState *env)
 272 {
 273     if (env->psw.mask & PSW_MASK_PSTATE) {
 274         return 1;
 275     }
 276
 277     return 0;
 278 }
 279
 280 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 281                                         target_ulong *cs_base, int *flags)
 282 {
 283     *pc = env->psw.addr;
 284     *cs_base = 0;
 285     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 286              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 287 }
 288
 289 /* While the PoO talks about ILC (a number between 1-3) what is actually
 290    stored in LowCore is shifted left one bit (an even between 2-6).  As
 291    this is the actual length of the insn and therefore more useful, that
 292    is what we want to pass around and manipulate.  To make sure that we
 293    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 294 static inline int get_ilen(uint8_t opc)
 295 {
 296     switch (opc >> 6) {
 297     case 0:
 298         return 2;
 299     case 1:
 300     case 2:
 301         return 4;
 302     default:
 303         return 6;
 304     }
 305 }
 306
 307 #ifndef CONFIG_USER_ONLY
 308 /* In several cases of runtime exceptions, we havn't recorded the true
 309    instruction length.  Use these codes when raising exceptions in order
 310    to re-compute the length by examining the insn in memory.  */
 311 #define ILEN_LATER       0x20
 312 #define ILEN_LATER_INC   0x21
 313 #endif
 314
 315 S390CPU *cpu_s390x_init(const char *cpu_model);
 316 void s390x_translate_init(void);
 317 int cpu_s390x_exec(CPUS390XState *s);
 318 void cpu_s390x_close(CPUS390XState *s);
 319 void do_interrupt (CPUS390XState *env);
 320
 321 /* you can call this signal handler from your SIGBUS and SIGSEGV
 322    signal handlers to inform the virtual CPU of exceptions. non zero
 323    is returned if the signal was handled by the virtual CPU.  */
 324 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 325                            void *puc);
 326 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
 327                                 int mmu_idx);
 328 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
 329
 330 #include "ioinst.h"
 331
 332 #ifndef CONFIG_USER_ONLY
 333 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 334                                    int is_write);
 335 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 336                                     int is_write);
 337 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 338 {
 339     hwaddr addr = 0;
 340     uint8_t reg;
 341
 342     reg = ipb >> 28;
 343     if (reg > 0) {
 344         addr = env->regs[reg];
 345     }
 346     addr += (ipb >> 16) & 0xfff;
 347
 348     return addr;
 349 }
 350
 351 void s390x_tod_timer(void *opaque);
 352 void s390x_cpu_timer(void *opaque);
 353
 354 int s390_virtio_hypercall(CPUS390XState *env);
 355
 356 #ifdef CONFIG_KVM
 357 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
 358 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
 359 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
 360                                  uint64_t parm64, int vm);
 361 #else
 362 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
 363 {
 364 }
 365
 366 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
 367                                        uint64_t token)
 368 {
 369 }
 370
 371 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
 372                                                uint32_t parm, uint64_t parm64,
 373                                                int vm)
 374 {
 375 }
 376 #endif
 377 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 378 void s390_add_running_cpu(CPUS390XState *env);
 379 unsigned s390_del_running_cpu(CPUS390XState *env);
 380
 381 /* service interrupts are floating therefore we must not pass an cpustate */
 382 void s390_sclp_extint(uint32_t parm);
 383
 384 /* from s390-virtio-bus */
 385 extern const hwaddr virtio_size;
 386
 387 #else
 388 static inline void s390_add_running_cpu(CPUS390XState *env)
 389 {
 390 }
 391
 392 static inline unsigned s390_del_running_cpu(CPUS390XState *env)
 393 {
 394     return 0;
 395 }
 396 #endif
 397 void cpu_lock(void);
 398 void cpu_unlock(void);
 399
 400 typedef struct SubchDev SubchDev;
 401
 402 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 403                                        uint16_t schid)
 404 {
 405     return NULL;
 406 }
 407 static inline bool css_subch_visible(SubchDev *sch)
 408 {
 409     return false;
 410 }
 411 static inline void css_conditional_io_interrupt(SubchDev *sch)
 412 {
 413 }
 414 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
 415 {
 416     return -ENODEV;
 417 }
 418 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
 419 {
 420     return true;
 421 }
 422 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
 423 {
 424     return -ENODEV;
 425 }
 426 static inline int css_do_xsch(SubchDev *sch)
 427 {
 428     return -ENODEV;
 429 }
 430 static inline int css_do_csch(SubchDev *sch)
 431 {
 432     return -ENODEV;
 433 }
 434 static inline int css_do_hsch(SubchDev *sch)
 435 {
 436     return -ENODEV;
 437 }
 438 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
 439 {
 440     return -ENODEV;
 441 }
 442 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
 443 {
 444     return -ENODEV;
 445 }
 446 static inline int css_do_stcrw(CRW *crw)
 447 {
 448     return 1;
 449 }
 450 static inline int css_do_tpi(uint64_t addr, int lowcore)
 451 {
 452     return 0;
 453 }
 454 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
 455                                        int rfmt, uint8_t l_chpid, void *buf)
 456 {
 457     return 0;
 458 }
 459 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
 460 {
 461 }
 462 static inline int css_enable_mss(void)
 463 {
 464     return -EINVAL;
 465 }
 466 static inline int css_enable_mcsse(void)
 467 {
 468     return -EINVAL;
 469 }
 470 static inline int css_do_rsch(SubchDev *sch)
 471 {
 472     return -ENODEV;
 473 }
 474 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
 475 {
 476     return -ENODEV;
 477 }
 478 static inline bool css_present(uint8_t cssid)
 479 {
 480     return false;
 481 }
 482
 483 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
 484 {
 485     env->aregs[0] = newtls >> 32;
 486     env->aregs[1] = newtls & 0xffffffffULL;
 487 }
 488
 489 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 490 #define cpu_exec cpu_s390x_exec
 491 #define cpu_gen_code cpu_s390x_gen_code
 492 #define cpu_signal_handler cpu_s390x_signal_handler
 493
 494 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 495 #define cpu_list s390_cpu_list
 496
 497 #include "exec/exec-all.h"
 498
 499 #define EXCP_EXT 1 /* external interrupt */
 500 #define EXCP_SVC 2 /* supervisor call (syscall) */
 501 #define EXCP_PGM 3 /* program interruption */
 502 #define EXCP_IO  7 /* I/O interrupt */
 503 #define EXCP_MCHK 8 /* machine check */
 504
 505 #define INTERRUPT_EXT        (1 << 0)
 506 #define INTERRUPT_TOD        (1 << 1)
 507 #define INTERRUPT_CPUTIMER   (1 << 2)
 508 #define INTERRUPT_IO         (1 << 3)
 509 #define INTERRUPT_MCHK       (1 << 4)
 510
 511 /* Program Status Word.  */
 512 #define S390_PSWM_REGNUM 0
 513 #define S390_PSWA_REGNUM 1
 514 /* General Purpose Registers.  */
 515 #define S390_R0_REGNUM 2
 516 #define S390_R1_REGNUM 3
 517 #define S390_R2_REGNUM 4
 518 #define S390_R3_REGNUM 5
 519 #define S390_R4_REGNUM 6
 520 #define S390_R5_REGNUM 7
 521 #define S390_R6_REGNUM 8
 522 #define S390_R7_REGNUM 9
 523 #define S390_R8_REGNUM 10
 524 #define S390_R9_REGNUM 11
 525 #define S390_R10_REGNUM 12
 526 #define S390_R11_REGNUM 13
 527 #define S390_R12_REGNUM 14
 528 #define S390_R13_REGNUM 15
 529 #define S390_R14_REGNUM 16
 530 #define S390_R15_REGNUM 17
 531 /* Access Registers.  */
 532 #define S390_A0_REGNUM 18
 533 #define S390_A1_REGNUM 19
 534 #define S390_A2_REGNUM 20
 535 #define S390_A3_REGNUM 21
 536 #define S390_A4_REGNUM 22
 537 #define S390_A5_REGNUM 23
 538 #define S390_A6_REGNUM 24
 539 #define S390_A7_REGNUM 25
 540 #define S390_A8_REGNUM 26
 541 #define S390_A9_REGNUM 27
 542 #define S390_A10_REGNUM 28
 543 #define S390_A11_REGNUM 29
 544 #define S390_A12_REGNUM 30
 545 #define S390_A13_REGNUM 31
 546 #define S390_A14_REGNUM 32
 547 #define S390_A15_REGNUM 33
 548 /* Floating Point Control Word.  */
 549 #define S390_FPC_REGNUM 34
 550 /* Floating Point Registers.  */
 551 #define S390_F0_REGNUM 35
 552 #define S390_F1_REGNUM 36
 553 #define S390_F2_REGNUM 37
 554 #define S390_F3_REGNUM 38
 555 #define S390_F4_REGNUM 39
 556 #define S390_F5_REGNUM 40
 557 #define S390_F6_REGNUM 41
 558 #define S390_F7_REGNUM 42
 559 #define S390_F8_REGNUM 43
 560 #define S390_F9_REGNUM 44
 561 #define S390_F10_REGNUM 45
 562 #define S390_F11_REGNUM 46
 563 #define S390_F12_REGNUM 47
 564 #define S390_F13_REGNUM 48
 565 #define S390_F14_REGNUM 49
 566 #define S390_F15_REGNUM 50
 567 /* Total.  */
 568 #define S390_NUM_REGS 51
 569
 570 /* CC optimization */
 571
 572 enum cc_op {
 573     CC_OP_CONST0 = 0,           /* CC is 0 */
 574     CC_OP_CONST1,               /* CC is 1 */
 575     CC_OP_CONST2,               /* CC is 2 */
 576     CC_OP_CONST3,               /* CC is 3 */
 577
 578     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 579     CC_OP_STATIC,               /* CC value is env->cc_op */
 580
 581     CC_OP_NZ,                   /* env->cc_dst != 0 */
 582     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 583     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 584     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 585     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 586     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 587     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 588
 589     CC_OP_ADD_64,               /* overflow on add (64bit) */
 590     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 591     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 592     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 593     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 594     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 595     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 596     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 597
 598     CC_OP_ADD_32,               /* overflow on add (32bit) */
 599     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 600     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 601     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 602     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 603     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 604     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 605     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 606
 607     CC_OP_COMP_32,              /* complement */
 608     CC_OP_COMP_64,              /* complement */
 609
 610     CC_OP_TM_32,                /* test under mask (32bit) */
 611     CC_OP_TM_64,                /* test under mask (64bit) */
 612
 613     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 614     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 615     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 616
 617     CC_OP_ICM,                  /* insert characters under mask */
 618     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 619     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 620     CC_OP_FLOGR,                /* find leftmost one */
 621     CC_OP_MAX
 622 };
 623
 624 static const char *cc_names[] = {
 625     [CC_OP_CONST0]    = "CC_OP_CONST0",
 626     [CC_OP_CONST1]    = "CC_OP_CONST1",
 627     [CC_OP_CONST2]    = "CC_OP_CONST2",
 628     [CC_OP_CONST3]    = "CC_OP_CONST3",
 629     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 630     [CC_OP_STATIC]    = "CC_OP_STATIC",
 631     [CC_OP_NZ]        = "CC_OP_NZ",
 632     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 633     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 634     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 635     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 636     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 637     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 638     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 639     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 640     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 641     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 642     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 643     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 644     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 645     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 646     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 647     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 648     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 649     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 650     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 651     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 652     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 653     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 654     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 655     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 656     [CC_OP_TM_32]     = "CC_OP_TM_32",
 657     [CC_OP_TM_64]     = "CC_OP_TM_64",
 658     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 659     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 660     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 661     [CC_OP_ICM]       = "CC_OP_ICM",
 662     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 663     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 664     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 665 };
 666
 667 static inline const char *cc_name(int cc_op)
 668 {
 669     return cc_names[cc_op];
 670 }
 671
 672 typedef struct LowCore
 673 {
 674     /* prefix area: defined by architecture */
 675     uint32_t        ccw1[2];                  /* 0x000 */
 676     uint32_t        ccw2[4];                  /* 0x008 */
 677     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 678     uint32_t        ext_params;               /* 0x080 */
 679     uint16_t        cpu_addr;                 /* 0x084 */
 680     uint16_t        ext_int_code;             /* 0x086 */
 681     uint16_t        svc_ilen;                 /* 0x088 */
 682     uint16_t        svc_code;                 /* 0x08a */
 683     uint16_t        pgm_ilen;                 /* 0x08c */
 684     uint16_t        pgm_code;                 /* 0x08e */
 685     uint32_t        data_exc_code;            /* 0x090 */
 686     uint16_t        mon_class_num;            /* 0x094 */
 687     uint16_t        per_perc_atmid;           /* 0x096 */
 688     uint64_t        per_address;              /* 0x098 */
 689     uint8_t         exc_access_id;            /* 0x0a0 */
 690     uint8_t         per_access_id;            /* 0x0a1 */
 691     uint8_t         op_access_id;             /* 0x0a2 */
 692     uint8_t         ar_access_id;             /* 0x0a3 */
 693     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 694     uint64_t        trans_exc_code;           /* 0x0a8 */
 695     uint64_t        monitor_code;             /* 0x0b0 */
 696     uint16_t        subchannel_id;            /* 0x0b8 */
 697     uint16_t        subchannel_nr;            /* 0x0ba */
 698     uint32_t        io_int_parm;              /* 0x0bc */
 699     uint32_t        io_int_word;              /* 0x0c0 */
 700     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 701     uint32_t        stfl_fac_list;            /* 0x0c8 */
 702     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 703     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 704     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 705     uint32_t        external_damage_code;     /* 0x0f4 */
 706     uint64_t        failing_storage_address;  /* 0x0f8 */
 707     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 708     PSW             restart_old_psw;          /* 0x120 */
 709     PSW             external_old_psw;         /* 0x130 */
 710     PSW             svc_old_psw;              /* 0x140 */
 711     PSW             program_old_psw;          /* 0x150 */
 712     PSW             mcck_old_psw;             /* 0x160 */
 713     PSW             io_old_psw;               /* 0x170 */
 714     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 715     PSW             restart_psw;              /* 0x1a0 */
 716     PSW             external_new_psw;         /* 0x1b0 */
 717     PSW             svc_new_psw;              /* 0x1c0 */
 718     PSW             program_new_psw;          /* 0x1d0 */
 719     PSW             mcck_new_psw;             /* 0x1e0 */
 720     PSW             io_new_psw;               /* 0x1f0 */
 721     PSW             return_psw;               /* 0x200 */
 722     uint8_t         irb[64];                  /* 0x210 */
 723     uint64_t        sync_enter_timer;         /* 0x250 */
 724     uint64_t        async_enter_timer;        /* 0x258 */
 725     uint64_t        exit_timer;               /* 0x260 */
 726     uint64_t        last_update_timer;        /* 0x268 */
 727     uint64_t        user_timer;               /* 0x270 */
 728     uint64_t        system_timer;             /* 0x278 */
 729     uint64_t        last_update_clock;        /* 0x280 */
 730     uint64_t        steal_clock;              /* 0x288 */
 731     PSW             return_mcck_psw;          /* 0x290 */
 732     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 733     /* System info area */
 734     uint64_t        save_area[16];            /* 0xc00 */
 735     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 736     uint64_t        kernel_stack;             /* 0xd40 */
 737     uint64_t        thread_info;              /* 0xd48 */
 738     uint64_t        async_stack;              /* 0xd50 */
 739     uint64_t        kernel_asce;              /* 0xd58 */
 740     uint64_t        user_asce;                /* 0xd60 */
 741     uint64_t        panic_stack;              /* 0xd68 */
 742     uint64_t        user_exec_asce;           /* 0xd70 */
 743     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 744
 745     /* SMP info area: defined by DJB */
 746     uint64_t        clock_comparator;         /* 0xdc0 */
 747     uint64_t        ext_call_fast;            /* 0xdc8 */
 748     uint64_t        percpu_offset;            /* 0xdd0 */
 749     uint64_t        current_task;             /* 0xdd8 */
 750     uint32_t        softirq_pending;          /* 0xde0 */
 751     uint32_t        pad_0x0de4;               /* 0xde4 */
 752     uint64_t        int_clock;                /* 0xde8 */
 753     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 754
 755     /* 0xe00 is used as indicator for dump tools */
 756     /* whether the kernel died with panic() or not */
 757     uint32_t        panic_magic;              /* 0xe00 */
 758
 759     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 760
 761     /* 64 bit extparam used for pfault, diag 250 etc  */
 762     uint64_t        ext_params2;               /* 0x11B8 */
 763
 764     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 765
 766     /* System info area */
 767
 768     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 769     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 770     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 771     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 772     uint32_t        prefixreg_save_area;       /* 0x1318 */
 773     uint32_t        fpt_creg_save_area;        /* 0x131c */
 774     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 775     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 776     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 777     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 778     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 779     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 780     uint64_t        cregs_save_area[16];       /* 0x1380 */
 781
 782     /* align to the top of the prefix area */
 783
 784     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 785 } QEMU_PACKED LowCore;
 786
 787 /* STSI */
 788 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 789 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 790 #define STSI_LEVEL_1            0x0000000010000000ULL
 791 #define STSI_LEVEL_2            0x0000000020000000ULL
 792 #define STSI_LEVEL_3            0x0000000030000000ULL
 793 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 794 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 795 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 796 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 797
 798 /* Basic Machine Configuration */
 799 struct sysib_111 {
 800     uint32_t res1[8];
 801     uint8_t  manuf[16];
 802     uint8_t  type[4];
 803     uint8_t  res2[12];
 804     uint8_t  model[16];
 805     uint8_t  sequence[16];
 806     uint8_t  plant[4];
 807     uint8_t  res3[156];
 808 };
 809
 810 /* Basic Machine CPU */
 811 struct sysib_121 {
 812     uint32_t res1[80];
 813     uint8_t  sequence[16];
 814     uint8_t  plant[4];
 815     uint8_t  res2[2];
 816     uint16_t cpu_addr;
 817     uint8_t  res3[152];
 818 };
 819
 820 /* Basic Machine CPUs */
 821 struct sysib_122 {
 822     uint8_t res1[32];
 823     uint32_t capability;
 824     uint16_t total_cpus;
 825     uint16_t active_cpus;
 826     uint16_t standby_cpus;
 827     uint16_t reserved_cpus;
 828     uint16_t adjustments[2026];
 829 };
 830
 831 /* LPAR CPU */
 832 struct sysib_221 {
 833     uint32_t res1[80];
 834     uint8_t  sequence[16];
 835     uint8_t  plant[4];
 836     uint16_t cpu_id;
 837     uint16_t cpu_addr;
 838     uint8_t  res3[152];
 839 };
 840
 841 /* LPAR CPUs */
 842 struct sysib_222 {
 843     uint32_t res1[32];
 844     uint16_t lpar_num;
 845     uint8_t  res2;
 846     uint8_t  lcpuc;
 847     uint16_t total_cpus;
 848     uint16_t conf_cpus;
 849     uint16_t standby_cpus;
 850     uint16_t reserved_cpus;
 851     uint8_t  name[8];
 852     uint32_t caf;
 853     uint8_t  res3[16];
 854     uint16_t dedicated_cpus;
 855     uint16_t shared_cpus;
 856     uint8_t  res4[180];
 857 };
 858
 859 /* VM CPUs */
 860 struct sysib_322 {
 861     uint8_t  res1[31];
 862     uint8_t  count;
 863     struct {
 864         uint8_t  res2[4];
 865         uint16_t total_cpus;
 866         uint16_t conf_cpus;
 867         uint16_t standby_cpus;
 868         uint16_t reserved_cpus;
 869         uint8_t  name[8];
 870         uint32_t caf;
 871         uint8_t  cpi[16];
 872         uint8_t  res3[24];
 873     } vm[8];
 874     uint8_t res4[3552];
 875 };
 876
 877 /* MMU defines */
 878 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 879 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 880 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 881 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 882 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 883 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 884 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 885 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 886 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 887 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 888 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 889 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 890
 891 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 892 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 893 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 894 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 895 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 896 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 897 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 898
 899 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 900 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 901 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 902
 903 #define _PAGE_RO        0x200            /* HW read-only bit  */
 904 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 905
 906 #define SK_C                    (0x1 << 1)
 907 #define SK_R                    (0x1 << 2)
 908 #define SK_F                    (0x1 << 3)
 909 #define SK_ACC_MASK             (0xf << 4)
 910
 911 #define SIGP_SENSE             0x01
 912 #define SIGP_EXTERNAL_CALL     0x02
 913 #define SIGP_EMERGENCY         0x03
 914 #define SIGP_START             0x04
 915 #define SIGP_STOP              0x05
 916 #define SIGP_RESTART           0x06
 917 #define SIGP_STOP_STORE_STATUS 0x09
 918 #define SIGP_INITIAL_CPU_RESET 0x0b
 919 #define SIGP_CPU_RESET         0x0c
 920 #define SIGP_SET_PREFIX        0x0d
 921 #define SIGP_STORE_STATUS_ADDR 0x0e
 922 #define SIGP_SET_ARCH          0x12
 923
 924 /* cpu status bits */
 925 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 926 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 927 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 928 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 929 #define SIGP_STAT_STOPPED           0x00000040UL
 930 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 931 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 932 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 933 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 934 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 935
 936 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 937 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 938                   target_ulong *raddr, int *flags);
 939 int sclp_service_call(uint32_t sccb, uint64_t code);
 940 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 941                  uint64_t vr);
 942
 943 #define TARGET_HAS_ICE 1
 944
 945 /* The value of the TOD clock for 1.1.1970. */
 946 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 947
 948 /* Converts ns to s390's clock format */
 949 static inline uint64_t time2tod(uint64_t ns) {
 950     return (ns << 9) / 125;
 951 }
 952
 953 static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param,
 954                                   uint64_t param64)
 955 {
 956     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 957         /* ugh - can't queue anymore. Let's drop. */
 958         return;
 959     }
 960
 961     env->ext_index++;
 962     assert(env->ext_index < MAX_EXT_QUEUE);
 963
 964     env->ext_queue[env->ext_index].code = code;
 965     env->ext_queue[env->ext_index].param = param;
 966     env->ext_queue[env->ext_index].param64 = param64;
 967
 968     env->pending_int |= INTERRUPT_EXT;
 969     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 970 }
 971
 972 static inline void cpu_inject_io(CPUS390XState *env, uint16_t subchannel_id,
 973                                  uint16_t subchannel_number,
 974                                  uint32_t io_int_parm, uint32_t io_int_word)
 975 {
 976     int isc = ffs(io_int_word << 2) - 1;
 977
 978     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
 979         /* ugh - can't queue anymore. Let's drop. */
 980         return;
 981     }
 982
 983     env->io_index[isc]++;
 984     assert(env->io_index[isc] < MAX_IO_QUEUE);
 985
 986     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
 987     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
 988     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
 989     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
 990
 991     env->pending_int |= INTERRUPT_IO;
 992     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 993 }
 994
 995 static inline void cpu_inject_crw_mchk(CPUS390XState *env)
 996 {
 997     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
 998         /* ugh - can't queue anymore. Let's drop. */
 999         return;
1000     }
1001
1002     env->mchk_index++;
1003     assert(env->mchk_index < MAX_MCHK_QUEUE);
1004
1005     env->mchk_queue[env->mchk_index].type = 1;
1006
1007     env->pending_int |= INTERRUPT_MCHK;
1008     cpu_interrupt(env, CPU_INTERRUPT_HARD);
1009 }
1010
1011 static inline bool cpu_has_work(CPUState *cpu)
1012 {
1013     CPUS390XState *env = &S390_CPU(cpu)->env;
1014
1015     return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1016         (env->psw.mask & PSW_MASK_EXT);
1017 }
1018
1019 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
1020 {
1021     env->psw.addr = tb->pc;
1022 }
1023
1024 /* fpu_helper.c */
1025 uint32_t set_cc_nz_f32(float32 v);
1026 uint32_t set_cc_nz_f64(float64 v);
1027 uint32_t set_cc_nz_f128(float128 v);
1028
1029 /* misc_helper.c */
1030 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1031 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1032                                      uintptr_t retaddr);
1033
1034 #endif