hw/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "sysbus.h"
  25 #include "arm-misc.h"
  26 #include "primecell.h"
  27 #include "devices.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "exec-memory.h"
  32
  33 #define VEXPRESS_BOARD_ID 0x8e0
  34
  35 static struct arm_boot_info vexpress_binfo;
  36
  37 /* Address maps for peripherals:
  38  * the Versatile Express motherboard has two possible maps,
  39  * the "legacy" one (used for A9) and the "Cortex-A Series"
  40  * map (used for newer cores).
  41  * Individual daughterboards can also have different maps for
  42  * their peripherals.
  43  */
  44
  45 enum {
  46     VE_SYSREGS,
  47     VE_SP810,
  48     VE_SERIALPCI,
  49     VE_PL041,
  50     VE_MMCI,
  51     VE_KMI0,
  52     VE_KMI1,
  53     VE_UART0,
  54     VE_UART1,
  55     VE_UART2,
  56     VE_UART3,
  57     VE_WDT,
  58     VE_TIMER01,
  59     VE_TIMER23,
  60     VE_SERIALDVI,
  61     VE_RTC,
  62     VE_COMPACTFLASH,
  63     VE_CLCD,
  64     VE_NORFLASH0,
  65     VE_NORFLASH0ALIAS,
  66     VE_NORFLASH1,
  67     VE_SRAM,
  68     VE_VIDEORAM,
  69     VE_ETHERNET,
  70     VE_USB,
  71     VE_DAPROM,
  72 };
  73
  74 static target_phys_addr_t motherboard_legacy_map[] = {
  75     /* CS7: 0x10000000 .. 0x10020000 */
  76     [VE_SYSREGS] = 0x10000000,
  77     [VE_SP810] = 0x10001000,
  78     [VE_SERIALPCI] = 0x10002000,
  79     [VE_PL041] = 0x10004000,
  80     [VE_MMCI] = 0x10005000,
  81     [VE_KMI0] = 0x10006000,
  82     [VE_KMI1] = 0x10007000,
  83     [VE_UART0] = 0x10009000,
  84     [VE_UART1] = 0x1000a000,
  85     [VE_UART2] = 0x1000b000,
  86     [VE_UART3] = 0x1000c000,
  87     [VE_WDT] = 0x1000f000,
  88     [VE_TIMER01] = 0x10011000,
  89     [VE_TIMER23] = 0x10012000,
  90     [VE_SERIALDVI] = 0x10016000,
  91     [VE_RTC] = 0x10017000,
  92     [VE_COMPACTFLASH] = 0x1001a000,
  93     [VE_CLCD] = 0x1001f000,
  94     /* CS0: 0x40000000 .. 0x44000000 */
  95     [VE_NORFLASH0] = 0x40000000,
  96     /* CS1: 0x44000000 .. 0x48000000 */
  97     [VE_NORFLASH1] = 0x44000000,
  98     /* CS2: 0x48000000 .. 0x4a000000 */
  99     [VE_SRAM] = 0x48000000,
 100     /* CS3: 0x4c000000 .. 0x50000000 */
 101     [VE_VIDEORAM] = 0x4c000000,
 102     [VE_ETHERNET] = 0x4e000000,
 103     [VE_USB] = 0x4f000000,
 104 };
 105
 106 static target_phys_addr_t motherboard_aseries_map[] = {
 107     /* CS0: 0x00000000 .. 0x0c000000 */
 108     [VE_NORFLASH0] = 0x00000000,
 109     [VE_NORFLASH0ALIAS] = 0x08000000,
 110     /* CS4: 0x0c000000 .. 0x10000000 */
 111     [VE_NORFLASH1] = 0x0c000000,
 112     /* CS5: 0x10000000 .. 0x14000000 */
 113     /* CS1: 0x14000000 .. 0x18000000 */
 114     [VE_SRAM] = 0x14000000,
 115     /* CS2: 0x18000000 .. 0x1c000000 */
 116     [VE_VIDEORAM] = 0x18000000,
 117     [VE_ETHERNET] = 0x1a000000,
 118     [VE_USB] = 0x1b000000,
 119     /* CS3: 0x1c000000 .. 0x20000000 */
 120     [VE_DAPROM] = 0x1c000000,
 121     [VE_SYSREGS] = 0x1c010000,
 122     [VE_SP810] = 0x1c020000,
 123     [VE_SERIALPCI] = 0x1c030000,
 124     [VE_PL041] = 0x1c040000,
 125     [VE_MMCI] = 0x1c050000,
 126     [VE_KMI0] = 0x1c060000,
 127     [VE_KMI1] = 0x1c070000,
 128     [VE_UART0] = 0x1c090000,
 129     [VE_UART1] = 0x1c0a0000,
 130     [VE_UART2] = 0x1c0b0000,
 131     [VE_UART3] = 0x1c0c0000,
 132     [VE_WDT] = 0x1c0f0000,
 133     [VE_TIMER01] = 0x1c110000,
 134     [VE_TIMER23] = 0x1c120000,
 135     [VE_SERIALDVI] = 0x1c160000,
 136     [VE_RTC] = 0x1c170000,
 137     [VE_COMPACTFLASH] = 0x1c1a0000,
 138     [VE_CLCD] = 0x1c1f0000,
 139 };
 140
 141 /* Structure defining the peculiarities of a specific daughterboard */
 142
 143 typedef struct VEDBoardInfo VEDBoardInfo;
 144
 145 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
 146                           ram_addr_t ram_size,
 147                           const char *cpu_model,
 148                           qemu_irq *pic, uint32_t *proc_id);
 149
 150 struct VEDBoardInfo {
 151     const target_phys_addr_t *motherboard_map;
 152     target_phys_addr_t loader_start;
 153     const target_phys_addr_t gic_cpu_if_addr;
 154     DBoardInitFn *init;
 155 };
 156
 157 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
 158                                   ram_addr_t ram_size,
 159                                   const char *cpu_model,
 160                                   qemu_irq *pic, uint32_t *proc_id)
 161 {
 162     MemoryRegion *sysmem = get_system_memory();
 163     MemoryRegion *ram = g_new(MemoryRegion, 1);
 164     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 165     DeviceState *dev;
 166     SysBusDevice *busdev;
 167     qemu_irq *irqp;
 168     int n;
 169     qemu_irq cpu_irq[4];
 170     ram_addr_t low_ram_size;
 171
 172     if (!cpu_model) {
 173         cpu_model = "cortex-a9";
 174     }
 175
 176     *proc_id = 0x0c000191;
 177
 178     for (n = 0; n < smp_cpus; n++) {
 179         ARMCPU *cpu = cpu_arm_init(cpu_model);
 180         if (!cpu) {
 181             fprintf(stderr, "Unable to find CPU definition\n");
 182             exit(1);
 183         }
 184         irqp = arm_pic_init_cpu(cpu);
 185         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 186     }
 187
 188     if (ram_size > 0x40000000) {
 189         /* 1GB is the maximum the address space permits */
 190         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 191         exit(1);
 192     }
 193
 194     memory_region_init_ram(ram, "vexpress.highmem", ram_size);
 195     vmstate_register_ram_global(ram);
 196     low_ram_size = ram_size;
 197     if (low_ram_size > 0x4000000) {
 198         low_ram_size = 0x4000000;
 199     }
 200     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 201      * address space should in theory be remappable to various
 202      * things including ROM or RAM; we always map the RAM there.
 203      */
 204     memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size);
 205     memory_region_add_subregion(sysmem, 0x0, lowram);
 206     memory_region_add_subregion(sysmem, 0x60000000, ram);
 207
 208     /* 0x1e000000 A9MPCore (SCU) private memory region */
 209     dev = qdev_create(NULL, "a9mpcore_priv");
 210     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 211     qdev_init_nofail(dev);
 212     busdev = sysbus_from_qdev(dev);
 213     sysbus_mmio_map(busdev, 0, 0x1e000000);
 214     for (n = 0; n < smp_cpus; n++) {
 215         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 216     }
 217     /* Interrupts [42:0] are from the motherboard;
 218      * [47:43] are reserved; [63:48] are daughterboard
 219      * peripherals. Note that some documentation numbers
 220      * external interrupts starting from 32 (because the
 221      * A9MP has internal interrupts 0..31).
 222      */
 223     for (n = 0; n < 64; n++) {
 224         pic[n] = qdev_get_gpio_in(dev, n);
 225     }
 226
 227     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 228
 229     /* 0x10020000 PL111 CLCD (daughterboard) */
 230     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 231
 232     /* 0x10060000 AXI RAM */
 233     /* 0x100e0000 PL341 Dynamic Memory Controller */
 234     /* 0x100e1000 PL354 Static Memory Controller */
 235     /* 0x100e2000 System Configuration Controller */
 236
 237     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 238     /* 0x100e5000 SP805 Watchdog module */
 239     /* 0x100e6000 BP147 TrustZone Protection Controller */
 240     /* 0x100e9000 PL301 'Fast' AXI matrix */
 241     /* 0x100ea000 PL301 'Slow' AXI matrix */
 242     /* 0x100ec000 TrustZone Address Space Controller */
 243     /* 0x10200000 CoreSight debug APB */
 244     /* 0x1e00a000 PL310 L2 Cache Controller */
 245     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 246 }
 247
 248 static const VEDBoardInfo a9_daughterboard = {
 249     .motherboard_map = motherboard_legacy_map,
 250     .loader_start = 0x60000000,
 251     .gic_cpu_if_addr = 0x1e000100,
 252     .init = a9_daughterboard_init,
 253 };
 254
 255 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
 256                                    ram_addr_t ram_size,
 257                                    const char *cpu_model,
 258                                    qemu_irq *pic, uint32_t *proc_id)
 259 {
 260     int n;
 261     MemoryRegion *sysmem = get_system_memory();
 262     MemoryRegion *ram = g_new(MemoryRegion, 1);
 263     MemoryRegion *sram = g_new(MemoryRegion, 1);
 264     qemu_irq cpu_irq[4];
 265     DeviceState *dev;
 266     SysBusDevice *busdev;
 267
 268     if (!cpu_model) {
 269         cpu_model = "cortex-a15";
 270     }
 271
 272     *proc_id = 0x14000217;
 273
 274     for (n = 0; n < smp_cpus; n++) {
 275         ARMCPU *cpu;
 276         qemu_irq *irqp;
 277
 278         cpu = cpu_arm_init(cpu_model);
 279         if (!cpu) {
 280             fprintf(stderr, "Unable to find CPU definition\n");
 281             exit(1);
 282         }
 283         irqp = arm_pic_init_cpu(cpu);
 284         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 285     }
 286
 287     {
 288         /* We have to use a separate 64 bit variable here to avoid the gcc
 289          * "comparison is always false due to limited range of data type"
 290          * warning if we are on a host where ram_addr_t is 32 bits.
 291          */
 292         uint64_t rsz = ram_size;
 293         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 294             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 295             exit(1);
 296         }
 297     }
 298
 299     memory_region_init_ram(ram, "vexpress.highmem", ram_size);
 300     vmstate_register_ram_global(ram);
 301     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 302     memory_region_add_subregion(sysmem, 0x80000000, ram);
 303
 304     /* 0x2c000000 A15MPCore private memory region (GIC) */
 305     dev = qdev_create(NULL, "a15mpcore_priv");
 306     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 307     qdev_init_nofail(dev);
 308     busdev = sysbus_from_qdev(dev);
 309     sysbus_mmio_map(busdev, 0, 0x2c000000);
 310     for (n = 0; n < smp_cpus; n++) {
 311         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 312     }
 313     /* Interrupts [42:0] are from the motherboard;
 314      * [47:43] are reserved; [63:48] are daughterboard
 315      * peripherals. Note that some documentation numbers
 316      * external interrupts starting from 32 (because there
 317      * are internal interrupts 0..31).
 318      */
 319     for (n = 0; n < 64; n++) {
 320         pic[n] = qdev_get_gpio_in(dev, n);
 321     }
 322
 323     /* A15 daughterboard peripherals: */
 324
 325     /* 0x20000000: CoreSight interfaces: not modelled */
 326     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 327     /* 0x2a420000: SCC: not modelled */
 328     /* 0x2a430000: system counter: not modelled */
 329     /* 0x2b000000: HDLCD controller: not modelled */
 330     /* 0x2b060000: SP805 watchdog: not modelled */
 331     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 332     /* 0x2e000000: system SRAM */
 333     memory_region_init_ram(sram, "vexpress.a15sram", 0x10000);
 334     vmstate_register_ram_global(sram);
 335     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 336
 337     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 338     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 339 }
 340
 341 static const VEDBoardInfo a15_daughterboard = {
 342     .motherboard_map = motherboard_aseries_map,
 343     .loader_start = 0x80000000,
 344     .gic_cpu_if_addr = 0x2c002000,
 345     .init = a15_daughterboard_init,
 346 };
 347
 348 static void vexpress_common_init(const VEDBoardInfo *daughterboard,
 349                                  ram_addr_t ram_size,
 350                                  const char *boot_device,
 351                                  const char *kernel_filename,
 352                                  const char *kernel_cmdline,
 353                                  const char *initrd_filename,
 354                                  const char *cpu_model)
 355 {
 356     DeviceState *dev, *sysctl, *pl041;
 357     qemu_irq pic[64];
 358     uint32_t proc_id;
 359     uint32_t sys_id;
 360     ram_addr_t vram_size, sram_size;
 361     MemoryRegion *sysmem = get_system_memory();
 362     MemoryRegion *vram = g_new(MemoryRegion, 1);
 363     MemoryRegion *sram = g_new(MemoryRegion, 1);
 364     const target_phys_addr_t *map = daughterboard->motherboard_map;
 365
 366     daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id);
 367
 368     /* Motherboard peripherals: the wiring is the same but the
 369      * addresses vary between the legacy and A-Series memory maps.
 370      */
 371
 372     sys_id = 0x1190f500;
 373
 374     sysctl = qdev_create(NULL, "realview_sysctl");
 375     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 376     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 377     qdev_init_nofail(sysctl);
 378     sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, map[VE_SYSREGS]);
 379
 380     /* VE_SP810: not modelled */
 381     /* VE_SERIALPCI: not modelled */
 382
 383     pl041 = qdev_create(NULL, "pl041");
 384     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 385     qdev_init_nofail(pl041);
 386     sysbus_mmio_map(sysbus_from_qdev(pl041), 0, map[VE_PL041]);
 387     sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]);
 388
 389     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 390     /* Wire up MMC card detect and read-only signals */
 391     qdev_connect_gpio_out(dev, 0,
 392                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 393     qdev_connect_gpio_out(dev, 1,
 394                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 395
 396     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 397     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 398
 399     sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
 400     sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
 401     sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
 402     sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
 403
 404     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 405     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 406
 407     /* VE_SERIALDVI: not modelled */
 408
 409     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 410
 411     /* VE_COMPACTFLASH: not modelled */
 412
 413     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 414
 415     /* VE_NORFLASH0: not modelled */
 416     /* VE_NORFLASH0ALIAS: not modelled */
 417     /* VE_NORFLASH1: not modelled */
 418
 419     sram_size = 0x2000000;
 420     memory_region_init_ram(sram, "vexpress.sram", sram_size);
 421     vmstate_register_ram_global(sram);
 422     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 423
 424     vram_size = 0x800000;
 425     memory_region_init_ram(vram, "vexpress.vram", vram_size);
 426     vmstate_register_ram_global(vram);
 427     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 428
 429     /* 0x4e000000 LAN9118 Ethernet */
 430     if (nd_table[0].used) {
 431         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 432     }
 433
 434     /* VE_USB: not modelled */
 435
 436     /* VE_DAPROM: not modelled */
 437
 438     vexpress_binfo.ram_size = ram_size;
 439     vexpress_binfo.kernel_filename = kernel_filename;
 440     vexpress_binfo.kernel_cmdline = kernel_cmdline;
 441     vexpress_binfo.initrd_filename = initrd_filename;
 442     vexpress_binfo.nb_cpus = smp_cpus;
 443     vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
 444     vexpress_binfo.loader_start = daughterboard->loader_start;
 445     vexpress_binfo.smp_loader_start = map[VE_SRAM];
 446     vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 447     vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 448     arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo);
 449 }
 450
 451 static void vexpress_a9_init(ram_addr_t ram_size,
 452                              const char *boot_device,
 453                              const char *kernel_filename,
 454                              const char *kernel_cmdline,
 455                              const char *initrd_filename,
 456                              const char *cpu_model)
 457 {
 458     vexpress_common_init(&a9_daughterboard,
 459                          ram_size, boot_device, kernel_filename,
 460                          kernel_cmdline, initrd_filename, cpu_model);
 461 }
 462
 463 static void vexpress_a15_init(ram_addr_t ram_size,
 464                               const char *boot_device,
 465                               const char *kernel_filename,
 466                               const char *kernel_cmdline,
 467                               const char *initrd_filename,
 468                               const char *cpu_model)
 469 {
 470     vexpress_common_init(&a15_daughterboard,
 471                          ram_size, boot_device, kernel_filename,
 472                          kernel_cmdline, initrd_filename, cpu_model);
 473 }
 474
 475 static QEMUMachine vexpress_a9_machine = {
 476     .name = "vexpress-a9",
 477     .desc = "ARM Versatile Express for Cortex-A9",
 478     .init = vexpress_a9_init,
 479     .use_scsi = 1,
 480     .max_cpus = 4,
 481 };
 482
 483 static QEMUMachine vexpress_a15_machine = {
 484     .name = "vexpress-a15",
 485     .desc = "ARM Versatile Express for Cortex-A15",
 486     .init = vexpress_a15_init,
 487     .use_scsi = 1,
 488     .max_cpus = 4,
 489 };
 490
 491 static void vexpress_machine_init(void)
 492 {
 493     qemu_register_machine(&vexpress_a9_machine);
 494     qemu_register_machine(&vexpress_a15_machine);
 495 }
 496
 497 machine_init(vexpress_machine_init);