hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/ppc/mac.h"
  27 #include "hw/ppc/mac_dbdma.h"
  28 #include "sysemu/block-backend.h"
  29 #include "sysemu/dma.h"
  30
  31 #include <hw/ide/internal.h>
  32
  33 /* debug MACIO */
  34 // #define DEBUG_MACIO
  35
  36 #ifdef DEBUG_MACIO
  37 static const int debug_macio = 1;
  38 #else
  39 static const int debug_macio = 0;
  40 #endif
  41
  42 #define MACIO_DPRINTF(fmt, ...) do { \
  43         if (debug_macio) { \
  44             printf(fmt , ## __VA_ARGS__); \
  45         } \
  46     } while (0)
  47
  48
  49 /***********************************************************/
  50 /* MacIO based PowerPC IDE */
  51
  52 #define MACIO_PAGE_SIZE 4096
  53
  54 /*
  55  * Unaligned DMA read/write access functions required for OS X/Darwin which
  56  * don't perform DMA transactions on sector boundaries. These functions are
  57  * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
  58  * easy to remove if the unaligned block APIs are ever exposed.
  59  */
  60
  61 static void pmac_dma_read(BlockBackend *blk,
  62                           int64_t offset, unsigned int bytes,
  63                           void (*cb)(void *opaque, int ret), void *opaque)
  64 {
  65     DBDMA_io *io = opaque;
  66     MACIOIDEState *m = io->opaque;
  67     IDEState *s = idebus_active_if(&m->bus);
  68     dma_addr_t dma_addr, dma_len;
  69     void *mem;
  70     int64_t sector_num;
  71     int nsector;
  72     uint64_t align = BDRV_SECTOR_SIZE;
  73     size_t head_bytes, tail_bytes;
  74
  75     qemu_iovec_destroy(&io->iov);
  76     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
  77
  78     sector_num = (offset >> 9);
  79     nsector = (io->len >> 9);
  80
  81     MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
  82                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
  83                   sector_num, nsector);
  84
  85     dma_addr = io->addr;
  86     dma_len = io->len;
  87     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
  88                          DMA_DIRECTION_FROM_DEVICE);
  89
  90     if (offset & (align - 1)) {
  91         head_bytes = offset & (align - 1);
  92
  93         MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
  94                       "discarding %zu bytes\n", sector_num, head_bytes);
  95
  96         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
  97
  98         bytes += offset & (align - 1);
  99         offset = offset & ~(align - 1);
 100     }
 101
 102     qemu_iovec_add(&io->iov, mem, io->len);
 103
 104     if ((offset + bytes) & (align - 1)) {
 105         tail_bytes = (offset + bytes) & (align - 1);
 106
 107         MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
 108                       "discarding bytes %zu\n", sector_num, tail_bytes);
 109
 110         qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
 111         bytes = ROUND_UP(bytes, align);
 112     }
 113
 114     s->io_buffer_size -= io->len;
 115     s->io_buffer_index += io->len;
 116
 117     io->len = 0;
 118
 119     MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 "  "
 120                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 121
 122     m->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov, (bytes >> 9),
 123                              cb, io);
 124 }
 125
 126 static void pmac_dma_write(BlockBackend *blk,
 127                          int64_t offset, int bytes,
 128                          void (*cb)(void *opaque, int ret), void *opaque)
 129 {
 130     DBDMA_io *io = opaque;
 131     MACIOIDEState *m = io->opaque;
 132     IDEState *s = idebus_active_if(&m->bus);
 133     dma_addr_t dma_addr, dma_len;
 134     void *mem;
 135     int64_t sector_num;
 136     int nsector;
 137     uint64_t align = BDRV_SECTOR_SIZE;
 138     size_t head_bytes, tail_bytes;
 139     bool unaligned_head = false, unaligned_tail = false;
 140
 141     qemu_iovec_destroy(&io->iov);
 142     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
 143
 144     sector_num = (offset >> 9);
 145     nsector = (io->len >> 9);
 146
 147     MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
 148                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
 149                   sector_num, nsector);
 150
 151     dma_addr = io->addr;
 152     dma_len = io->len;
 153     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
 154                          DMA_DIRECTION_TO_DEVICE);
 155
 156     if (offset & (align - 1)) {
 157         head_bytes = offset & (align - 1);
 158         sector_num = ((offset & ~(align - 1)) >> 9);
 159
 160         MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
 161                       PRId64 "\n", sector_num);
 162
 163         blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
 164
 165         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
 166         qemu_iovec_add(&io->iov, mem, io->len);
 167
 168         bytes += offset & (align - 1);
 169         offset = offset & ~(align - 1);
 170
 171         unaligned_head = true;
 172     }
 173
 174     if ((offset + bytes) & (align - 1)) {
 175         tail_bytes = (offset + bytes) & (align - 1);
 176         sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
 177
 178         MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
 179                       PRId64 "\n", sector_num);
 180
 181         blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
 182
 183         if (!unaligned_head) {
 184             qemu_iovec_add(&io->iov, mem, io->len);
 185         }
 186
 187         qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
 188                        align - tail_bytes);
 189
 190         bytes = ROUND_UP(bytes, align);
 191
 192         unaligned_tail = true;
 193     }
 194
 195     if (!unaligned_head && !unaligned_tail) {
 196         qemu_iovec_add(&io->iov, mem, io->len);
 197     }
 198
 199     s->io_buffer_size -= io->len;
 200     s->io_buffer_index += io->len;
 201
 202     io->len = 0;
 203
 204     MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 "  "
 205                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 206
 207     m->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov, (bytes >> 9),
 208                               cb, io);
 209 }
 210
 211 static void pmac_dma_trim(BlockBackend *blk,
 212                         int64_t offset, int bytes,
 213                         void (*cb)(void *opaque, int ret), void *opaque)
 214 {
 215     DBDMA_io *io = opaque;
 216     MACIOIDEState *m = io->opaque;
 217     IDEState *s = idebus_active_if(&m->bus);
 218     dma_addr_t dma_addr, dma_len;
 219     void *mem;
 220
 221     qemu_iovec_destroy(&io->iov);
 222     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
 223
 224     dma_addr = io->addr;
 225     dma_len = io->len;
 226     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
 227                          DMA_DIRECTION_TO_DEVICE);
 228
 229     qemu_iovec_add(&io->iov, mem, io->len);
 230     s->io_buffer_size -= io->len;
 231     s->io_buffer_index += io->len;
 232     io->len = 0;
 233
 234     m->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov, (bytes >> 9),
 235                               cb, io);
 236 }
 237
 238 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
 239 {
 240     DBDMA_io *io = opaque;
 241     MACIOIDEState *m = io->opaque;
 242     IDEState *s = idebus_active_if(&m->bus);
 243     int64_t offset;
 244
 245     MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
 246
 247     if (ret < 0) {
 248         MACIO_DPRINTF("DMA error: %d\n", ret);
 249         ide_atapi_io_error(s, ret);
 250         goto done;
 251     }
 252
 253     if (!m->dma_active) {
 254         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 255                       s->nsector, io->len, s->status);
 256         /* data not ready yet, wait for the channel to get restarted */
 257         io->processing = false;
 258         return;
 259     }
 260
 261     if (s->io_buffer_size <= 0) {
 262         MACIO_DPRINTF("End of IDE transfer\n");
 263         ide_atapi_cmd_ok(s);
 264         m->dma_active = false;
 265         goto done;
 266     }
 267
 268     if (io->len == 0) {
 269         MACIO_DPRINTF("End of DMA transfer\n");
 270         goto done;
 271     }
 272
 273     if (s->lba == -1) {
 274         /* Non-block ATAPI transfer - just copy to RAM */
 275         s->io_buffer_size = MIN(s->io_buffer_size, io->len);
 276         cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
 277         ide_atapi_cmd_ok(s);
 278         m->dma_active = false;
 279         goto done;
 280     }
 281
 282     /* Calculate current offset */
 283     offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
 284
 285     pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
 286     return;
 287
 288 done:
 289     if (ret < 0) {
 290         block_acct_failed(blk_get_stats(s->blk), &s->acct);
 291     } else {
 292         block_acct_done(blk_get_stats(s->blk), &s->acct);
 293     }
 294     io->dma_end(opaque);
 295 }
 296
 297 static void pmac_ide_transfer_cb(void *opaque, int ret)
 298 {
 299     DBDMA_io *io = opaque;
 300     MACIOIDEState *m = io->opaque;
 301     IDEState *s = idebus_active_if(&m->bus);
 302     int64_t offset;
 303
 304     MACIO_DPRINTF("pmac_ide_transfer_cb\n");
 305
 306     if (ret < 0) {
 307         MACIO_DPRINTF("DMA error: %d\n", ret);
 308         m->aiocb = NULL;
 309         ide_dma_error(s);
 310         goto done;
 311     }
 312
 313     if (!m->dma_active) {
 314         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 315                       s->nsector, io->len, s->status);
 316         /* data not ready yet, wait for the channel to get restarted */
 317         io->processing = false;
 318         return;
 319     }
 320
 321     if (s->io_buffer_size <= 0) {
 322         MACIO_DPRINTF("End of IDE transfer\n");
 323         s->status = READY_STAT | SEEK_STAT;
 324         ide_set_irq(s->bus);
 325         m->dma_active = false;
 326         goto done;
 327     }
 328
 329     if (io->len == 0) {
 330         MACIO_DPRINTF("End of DMA transfer\n");
 331         goto done;
 332     }
 333
 334     /* Calculate number of sectors */
 335     offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
 336
 337     switch (s->dma_cmd) {
 338     case IDE_DMA_READ:
 339         pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 340         break;
 341     case IDE_DMA_WRITE:
 342         pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 343         break;
 344     case IDE_DMA_TRIM:
 345         pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 346         break;
 347     }
 348
 349     return;
 350
 351 done:
 352     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 353         if (ret < 0) {
 354             block_acct_failed(blk_get_stats(s->blk), &s->acct);
 355         } else {
 356             block_acct_done(blk_get_stats(s->blk), &s->acct);
 357         }
 358     }
 359     io->dma_end(opaque);
 360 }
 361
 362 static void pmac_ide_transfer(DBDMA_io *io)
 363 {
 364     MACIOIDEState *m = io->opaque;
 365     IDEState *s = idebus_active_if(&m->bus);
 366
 367     MACIO_DPRINTF("\n");
 368
 369     if (s->drive_kind == IDE_CD) {
 370         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 371                          BLOCK_ACCT_READ);
 372
 373         pmac_ide_atapi_transfer_cb(io, 0);
 374         return;
 375     }
 376
 377     switch (s->dma_cmd) {
 378     case IDE_DMA_READ:
 379         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 380                          BLOCK_ACCT_READ);
 381         break;
 382     case IDE_DMA_WRITE:
 383         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 384                          BLOCK_ACCT_WRITE);
 385         break;
 386     default:
 387         break;
 388     }
 389
 390     pmac_ide_transfer_cb(io, 0);
 391 }
 392
 393 static void pmac_ide_flush(DBDMA_io *io)
 394 {
 395     MACIOIDEState *m = io->opaque;
 396
 397     if (m->aiocb) {
 398         blk_drain_all();
 399     }
 400 }
 401
 402 /* PowerMac IDE memory IO */
 403 static void pmac_ide_writeb (void *opaque,
 404                              hwaddr addr, uint32_t val)
 405 {
 406     MACIOIDEState *d = opaque;
 407
 408     addr = (addr & 0xFFF) >> 4;
 409     switch (addr) {
 410     case 1 ... 7:
 411         ide_ioport_write(&d->bus, addr, val);
 412         break;
 413     case 8:
 414     case 22:
 415         ide_cmd_write(&d->bus, 0, val);
 416         break;
 417     default:
 418         break;
 419     }
 420 }
 421
 422 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
 423 {
 424     uint8_t retval;
 425     MACIOIDEState *d = opaque;
 426
 427     addr = (addr & 0xFFF) >> 4;
 428     switch (addr) {
 429     case 1 ... 7:
 430         retval = ide_ioport_read(&d->bus, addr);
 431         break;
 432     case 8:
 433     case 22:
 434         retval = ide_status_read(&d->bus, 0);
 435         break;
 436     default:
 437         retval = 0xFF;
 438         break;
 439     }
 440     return retval;
 441 }
 442
 443 static void pmac_ide_writew (void *opaque,
 444                              hwaddr addr, uint32_t val)
 445 {
 446     MACIOIDEState *d = opaque;
 447
 448     addr = (addr & 0xFFF) >> 4;
 449     val = bswap16(val);
 450     if (addr == 0) {
 451         ide_data_writew(&d->bus, 0, val);
 452     }
 453 }
 454
 455 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
 456 {
 457     uint16_t retval;
 458     MACIOIDEState *d = opaque;
 459
 460     addr = (addr & 0xFFF) >> 4;
 461     if (addr == 0) {
 462         retval = ide_data_readw(&d->bus, 0);
 463     } else {
 464         retval = 0xFFFF;
 465     }
 466     retval = bswap16(retval);
 467     return retval;
 468 }
 469
 470 static void pmac_ide_writel (void *opaque,
 471                              hwaddr addr, uint32_t val)
 472 {
 473     MACIOIDEState *d = opaque;
 474
 475     addr = (addr & 0xFFF) >> 4;
 476     val = bswap32(val);
 477     if (addr == 0) {
 478         ide_data_writel(&d->bus, 0, val);
 479     }
 480 }
 481
 482 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
 483 {
 484     uint32_t retval;
 485     MACIOIDEState *d = opaque;
 486
 487     addr = (addr & 0xFFF) >> 4;
 488     if (addr == 0) {
 489         retval = ide_data_readl(&d->bus, 0);
 490     } else {
 491         retval = 0xFFFFFFFF;
 492     }
 493     retval = bswap32(retval);
 494     return retval;
 495 }
 496
 497 static const MemoryRegionOps pmac_ide_ops = {
 498     .old_mmio = {
 499         .write = {
 500             pmac_ide_writeb,
 501             pmac_ide_writew,
 502             pmac_ide_writel,
 503         },
 504         .read = {
 505             pmac_ide_readb,
 506             pmac_ide_readw,
 507             pmac_ide_readl,
 508         },
 509     },
 510     .endianness = DEVICE_NATIVE_ENDIAN,
 511 };
 512
 513 static const VMStateDescription vmstate_pmac = {
 514     .name = "ide",
 515     .version_id = 3,
 516     .minimum_version_id = 0,
 517     .fields = (VMStateField[]) {
 518         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 519         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 520         VMSTATE_END_OF_LIST()
 521     }
 522 };
 523
 524 static void macio_ide_reset(DeviceState *dev)
 525 {
 526     MACIOIDEState *d = MACIO_IDE(dev);
 527
 528     ide_bus_reset(&d->bus);
 529 }
 530
 531 static int ide_nop_int(IDEDMA *dma, int x)
 532 {
 533     return 0;
 534 }
 535
 536 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
 537 {
 538     return 0;
 539 }
 540
 541 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
 542                             BlockCompletionFunc *cb)
 543 {
 544     MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
 545
 546     s->io_buffer_index = 0;
 547     if (s->drive_kind == IDE_CD) {
 548         s->io_buffer_size = s->packet_transfer_size;
 549     } else {
 550         s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
 551     }
 552
 553     MACIO_DPRINTF("\n\n------------ IDE transfer\n");
 554     MACIO_DPRINTF("buffer_size: %x   buffer_index: %x\n",
 555                   s->io_buffer_size, s->io_buffer_index);
 556     MACIO_DPRINTF("lba: %x    size: %x\n", s->lba, s->io_buffer_size);
 557     MACIO_DPRINTF("-------------------------\n");
 558
 559     m->dma_active = true;
 560     DBDMA_kick(m->dbdma);
 561 }
 562
 563 static const IDEDMAOps dbdma_ops = {
 564     .start_dma      = ide_dbdma_start,
 565     .prepare_buf    = ide_nop_int32,
 566     .rw_buf         = ide_nop_int,
 567 };
 568
 569 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
 570 {
 571     MACIOIDEState *s = MACIO_IDE(dev);
 572
 573     ide_init2(&s->bus, s->irq);
 574
 575     /* Register DMA callbacks */
 576     s->dma.ops = &dbdma_ops;
 577     s->bus.dma = &s->dma;
 578 }
 579
 580 static void macio_ide_initfn(Object *obj)
 581 {
 582     SysBusDevice *d = SYS_BUS_DEVICE(obj);
 583     MACIOIDEState *s = MACIO_IDE(obj);
 584
 585     ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
 586     memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
 587     sysbus_init_mmio(d, &s->mem);
 588     sysbus_init_irq(d, &s->irq);
 589     sysbus_init_irq(d, &s->dma_irq);
 590 }
 591
 592 static void macio_ide_class_init(ObjectClass *oc, void *data)
 593 {
 594     DeviceClass *dc = DEVICE_CLASS(oc);
 595
 596     dc->realize = macio_ide_realizefn;
 597     dc->reset = macio_ide_reset;
 598     dc->vmsd = &vmstate_pmac;
 599     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 600 }
 601
 602 static const TypeInfo macio_ide_type_info = {
 603     .name = TYPE_MACIO_IDE,
 604     .parent = TYPE_SYS_BUS_DEVICE,
 605     .instance_size = sizeof(MACIOIDEState),
 606     .instance_init = macio_ide_initfn,
 607     .class_init = macio_ide_class_init,
 608 };
 609
 610 static void macio_ide_register_types(void)
 611 {
 612     type_register_static(&macio_ide_type_info);
 613 }
 614
 615 /* hd_table must contain 2 block drivers */
 616 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
 617 {
 618     int i;
 619
 620     for (i = 0; i < 2; i++) {
 621         if (hd_table[i]) {
 622             ide_create_drive(&s->bus, i, hd_table[i]);
 623         }
 624     }
 625 }
 626
 627 void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
 628 {
 629     s->dbdma = dbdma;
 630     DBDMA_register_channel(dbdma, channel, s->dma_irq,
 631                            pmac_ide_transfer, pmac_ide_flush, s);
 632 }
 633
 634 type_init(macio_ide_register_types)