hw/pci/pcie.c

   1 /*
   2  * pcie.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu-common.h"
  24 #include "hw/pci/pci_bridge.h"
  25 #include "hw/pci/pcie.h"
  26 #include "hw/pci/msix.h"
  27 #include "hw/pci/msi.h"
  28 #include "hw/pci/pci_bus.h"
  29 #include "hw/pci/pcie_regs.h"
  30 #include "qemu/range.h"
  31
  32 //#define DEBUG_PCIE
  33 #ifdef DEBUG_PCIE
  34 # define PCIE_DPRINTF(fmt, ...)                                         \
  35     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  36 #else
  37 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  38 #endif
  39 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  40     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  41
  42
  43 /***************************************************************************
  44  * pci express capability helper functions
  45  */
  46
  47 static void
  48 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
  49 {
  50     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
  51     uint8_t *cmask = dev->cmask + dev->exp.exp_cap;
  52
  53     /* capability register
  54     interrupt message number defaults to 0 */
  55     pci_set_word(exp_cap + PCI_EXP_FLAGS,
  56                  ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  57                  version);
  58
  59     /* device capability register
  60      * table 7-12:
  61      * roll based error reporting bit must be set by all
  62      * Functions conforming to the ECN, PCI Express Base
  63      * Specification, Revision 1.1., or subsequent PCI Express Base
  64      * Specification revisions.
  65      */
  66     pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  67
  68     pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  69                  (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  70                  PCI_EXP_LNKCAP_ASPMS_0S |
  71                  PCI_EXP_LNK_MLW_1 |
  72                  PCI_EXP_LNK_LS_25);
  73
  74     pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  75                  PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  76
  77     if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
  78         pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
  79                                    PCI_EXP_LNKSTA_DLLLA);
  80     }
  81
  82     /* We changed link status bits over time, and changing them across
  83      * migrations is generally fine as hardware changes them too.
  84      * Let's not bother checking.
  85      */
  86     pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
  87 }
  88
  89 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
  90 {
  91     /* PCIe cap v2 init */
  92     int pos;
  93     uint8_t *exp_cap;
  94
  95     assert(pci_is_express(dev));
  96
  97     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF);
  98     if (pos < 0) {
  99         return pos;
 100     }
 101     dev->exp.exp_cap = pos;
 102     exp_cap = dev->config + pos;
 103
 104     /* Filling values common with v1 */
 105     pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2);
 106
 107     /* Filling v2 specific values */
 108     pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
 109                  PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
 110
 111     pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
 112     return pos;
 113 }
 114
 115 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
 116                      uint8_t port)
 117 {
 118     /* PCIe cap v1 init */
 119     int pos;
 120
 121     assert(pci_is_express(dev));
 122
 123     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF);
 124     if (pos < 0) {
 125         return pos;
 126     }
 127     dev->exp.exp_cap = pos;
 128
 129     pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1);
 130
 131     return pos;
 132 }
 133
 134 static int
 135 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
 136 {
 137     uint8_t type = PCI_EXP_TYPE_ENDPOINT;
 138
 139     /*
 140      * Windows guests will report Code 10, device cannot start, if
 141      * a regular Endpoint type is exposed on a root complex.  These
 142      * should instead be Root Complex Integrated Endpoints.
 143      */
 144     if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) {
 145         type = PCI_EXP_TYPE_RC_END;
 146     }
 147
 148     return (cap_size == PCI_EXP_VER1_SIZEOF)
 149         ? pcie_cap_v1_init(dev, offset, type, 0)
 150         : pcie_cap_init(dev, offset, type, 0);
 151 }
 152
 153 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
 154 {
 155     return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
 156 }
 157
 158 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
 159 {
 160     return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
 161 }
 162
 163 void pcie_cap_exit(PCIDevice *dev)
 164 {
 165     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
 166 }
 167
 168 void pcie_cap_v1_exit(PCIDevice *dev)
 169 {
 170     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
 171 }
 172
 173 uint8_t pcie_cap_get_type(const PCIDevice *dev)
 174 {
 175     uint32_t pos = dev->exp.exp_cap;
 176     assert(pos > 0);
 177     return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
 178             PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 179 }
 180
 181 /* MSI/MSI-X */
 182 /* pci express interrupt message number */
 183 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 184 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 185 {
 186     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 187     assert(vector < 32);
 188     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 189     pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 190                                vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 191 }
 192
 193 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 194 {
 195     return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 196             PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 197 }
 198
 199 void pcie_cap_deverr_init(PCIDevice *dev)
 200 {
 201     uint32_t pos = dev->exp.exp_cap;
 202     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 203                                PCI_EXP_DEVCAP_RBER);
 204     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 205                                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 206                                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 207     pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 208                                PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 209                                PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
 210 }
 211
 212 void pcie_cap_deverr_reset(PCIDevice *dev)
 213 {
 214     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 215     pci_long_test_and_clear_mask(devctl,
 216                                  PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 217                                  PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 218 }
 219
 220 static void hotplug_event_update_event_status(PCIDevice *dev)
 221 {
 222     uint32_t pos = dev->exp.exp_cap;
 223     uint8_t *exp_cap = dev->config + pos;
 224     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 225     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 226
 227     dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 228         (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
 229 }
 230
 231 static void hotplug_event_notify(PCIDevice *dev)
 232 {
 233     bool prev = dev->exp.hpev_notified;
 234
 235     hotplug_event_update_event_status(dev);
 236
 237     if (prev == dev->exp.hpev_notified) {
 238         return;
 239     }
 240
 241     /* Note: the logic above does not take into account whether interrupts
 242      * are masked. The result is that interrupt will be sent when it is
 243      * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
 244      * The Port may optionally send an MSI when there are hot-plug events that
 245      * occur while interrupt generation is disabled, and interrupt generation is
 246      * subsequently enabled. */
 247     if (msix_enabled(dev)) {
 248         msix_notify(dev, pcie_cap_flags_get_vector(dev));
 249     } else if (msi_enabled(dev)) {
 250         msi_notify(dev, pcie_cap_flags_get_vector(dev));
 251     } else {
 252         pci_set_irq(dev, dev->exp.hpev_notified);
 253     }
 254 }
 255
 256 static void hotplug_event_clear(PCIDevice *dev)
 257 {
 258     hotplug_event_update_event_status(dev);
 259     if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
 260         pci_irq_deassert(dev);
 261     }
 262 }
 263
 264 /*
 265  * A PCI Express Hot-Plug Event has occurred, so update slot status register
 266  * and notify OS of the event if necessary.
 267  *
 268  * 6.7.3 PCI Express Hot-Plug Events
 269  * 6.7.3.4 Software Notification of Hot-Plug Events
 270  */
 271 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 272 {
 273     /* Minor optimization: if nothing changed - no event is needed. */
 274     if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
 275                                    PCI_EXP_SLTSTA, event)) {
 276         return;
 277     }
 278     hotplug_event_notify(dev);
 279 }
 280
 281 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev,
 282                                          DeviceState *dev,
 283                                          uint8_t **exp_cap, Error **errp)
 284 {
 285     *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
 286     uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA);
 287
 288     PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
 289     if (sltsta & PCI_EXP_SLTSTA_EIS) {
 290         /* the slot is electromechanically locked.
 291          * This error is propagated up to qdev and then to HMP/QMP.
 292          */
 293         error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
 294     }
 295 }
 296
 297 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
 298                               Error **errp)
 299 {
 300     uint8_t *exp_cap;
 301     PCIDevice *pci_dev = PCI_DEVICE(dev);
 302
 303     pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
 304
 305     /* Don't send event when device is enabled during qemu machine creation:
 306      * it is present on boot, no hotplug event is necessary. We do send an
 307      * event when the device is disabled later. */
 308     if (!dev->hotplugged) {
 309         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 310                                    PCI_EXP_SLTSTA_PDS);
 311         return;
 312     }
 313
 314     /* To enable multifunction hot-plug, we just ensure the function
 315      * 0 added last. When function 0 is added, we set the sltsta and
 316      * inform OS via event notification.
 317      */
 318     if (pci_get_function_0(pci_dev)) {
 319         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 320                                    PCI_EXP_SLTSTA_PDS);
 321         pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
 322                             PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
 323     }
 324 }
 325
 326 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
 327 {
 328     object_unparent(OBJECT(dev));
 329 }
 330
 331 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev,
 332                                          DeviceState *dev, Error **errp)
 333 {
 334     uint8_t *exp_cap;
 335     PCIDevice *pci_dev = PCI_DEVICE(dev);
 336     PCIBus *bus = pci_dev->bus;
 337
 338     pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
 339
 340     /* In case user cancel the operation of multi-function hot-add,
 341      * remove the function that is unexposed to guest individually,
 342      * without interaction with guest.
 343      */
 344     if (pci_dev->devfn &&
 345         !bus->devices[0]) {
 346         pcie_unplug_device(bus, pci_dev, NULL);
 347
 348         return;
 349     }
 350
 351     pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
 352 }
 353
 354 /* pci express slot for pci express root/downstream port
 355    PCI express capability slot registers */
 356 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 357 {
 358     uint32_t pos = dev->exp.exp_cap;
 359
 360     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 361                                PCI_EXP_FLAGS_SLOT);
 362
 363     pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 364                                  ~PCI_EXP_SLTCAP_PSN);
 365     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 366                                (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 367                                PCI_EXP_SLTCAP_EIP |
 368                                PCI_EXP_SLTCAP_HPS |
 369                                PCI_EXP_SLTCAP_HPC |
 370                                PCI_EXP_SLTCAP_PIP |
 371                                PCI_EXP_SLTCAP_AIP |
 372                                PCI_EXP_SLTCAP_ABP);
 373
 374     if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
 375         pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 376                                    PCI_EXP_SLTCAP_PCP);
 377         pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 378                                      PCI_EXP_SLTCTL_PCC);
 379         pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 380                                    PCI_EXP_SLTCTL_PCC);
 381     }
 382
 383     pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 384                                  PCI_EXP_SLTCTL_PIC |
 385                                  PCI_EXP_SLTCTL_AIC);
 386     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 387                                PCI_EXP_SLTCTL_PIC_OFF |
 388                                PCI_EXP_SLTCTL_AIC_OFF);
 389     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 390                                PCI_EXP_SLTCTL_PIC |
 391                                PCI_EXP_SLTCTL_AIC |
 392                                PCI_EXP_SLTCTL_HPIE |
 393                                PCI_EXP_SLTCTL_CCIE |
 394                                PCI_EXP_SLTCTL_PDCE |
 395                                PCI_EXP_SLTCTL_ABPE);
 396     /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 397      * make the bit writable here in order to detect 1b is written.
 398      * pcie_cap_slot_write_config() test-and-clear the bit, so
 399      * this bit always returns 0 to the guest.
 400      */
 401     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 402                                PCI_EXP_SLTCTL_EIC);
 403
 404     pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 405                                PCI_EXP_HP_EV_SUPPORTED);
 406
 407     dev->exp.hpev_notified = false;
 408
 409     qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
 410                              DEVICE(dev), NULL);
 411 }
 412
 413 void pcie_cap_slot_reset(PCIDevice *dev)
 414 {
 415     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 416     uint8_t port_type = pcie_cap_get_type(dev);
 417
 418     assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
 419            port_type == PCI_EXP_TYPE_ROOT_PORT);
 420
 421     PCIE_DEV_PRINTF(dev, "reset\n");
 422
 423     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 424                                  PCI_EXP_SLTCTL_EIC |
 425                                  PCI_EXP_SLTCTL_PIC |
 426                                  PCI_EXP_SLTCTL_AIC |
 427                                  PCI_EXP_SLTCTL_HPIE |
 428                                  PCI_EXP_SLTCTL_CCIE |
 429                                  PCI_EXP_SLTCTL_PDCE |
 430                                  PCI_EXP_SLTCTL_ABPE);
 431     pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 432                                PCI_EXP_SLTCTL_AIC_OFF);
 433
 434     if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
 435         /* Downstream ports enforce device number 0. */
 436         bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
 437         uint16_t pic;
 438
 439         if (populated) {
 440             pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 441                                          PCI_EXP_SLTCTL_PCC);
 442         } else {
 443             pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 444                                        PCI_EXP_SLTCTL_PCC);
 445         }
 446
 447         pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
 448         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
 449     }
 450
 451     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 452                                  PCI_EXP_SLTSTA_EIS |/* on reset,
 453                                                         the lock is released */
 454                                  PCI_EXP_SLTSTA_CC |
 455                                  PCI_EXP_SLTSTA_PDC |
 456                                  PCI_EXP_SLTSTA_ABP);
 457
 458     hotplug_event_update_event_status(dev);
 459 }
 460
 461 void pcie_cap_slot_write_config(PCIDevice *dev,
 462                                 uint32_t addr, uint32_t val, int len)
 463 {
 464     uint32_t pos = dev->exp.exp_cap;
 465     uint8_t *exp_cap = dev->config + pos;
 466     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 467
 468     if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
 469         hotplug_event_clear(dev);
 470     }
 471
 472     if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 473         return;
 474     }
 475
 476     if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 477                                      PCI_EXP_SLTCTL_EIC)) {
 478         sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 479         pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 480         PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 481                         "sltsta -> 0x%02"PRIx16"\n",
 482                         sltsta);
 483     }
 484
 485     /*
 486      * If the slot is polulated, power indicator is off and power
 487      * controller is off, it is safe to detach the devices.
 488      */
 489     if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
 490         ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) {
 491         PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
 492         pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
 493                             pcie_unplug_device, NULL);
 494
 495         pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 496                                      PCI_EXP_SLTSTA_PDS);
 497         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 498                                        PCI_EXP_SLTSTA_PDC);
 499     }
 500
 501     hotplug_event_notify(dev);
 502
 503     /*
 504      * 6.7.3.2 Command Completed Events
 505      *
 506      * Software issues a command to a hot-plug capable Downstream Port by
 507      * issuing a write transaction that targets any portion of the Port’s Slot
 508      * Control register. A single write to the Slot Control register is
 509      * considered to be a single command, even if the write affects more than
 510      * one field in the Slot Control register. In response to this transaction,
 511      * the Port must carry out the requested actions and then set the
 512      * associated status field for the command completed event. */
 513
 514     /* Real hardware might take a while to complete requested command because
 515      * physical movement would be involved like locking the electromechanical
 516      * lock.  However in our case, command is completed instantaneously above,
 517      * so send a command completion event right now.
 518      */
 519     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 520 }
 521
 522 int pcie_cap_slot_post_load(void *opaque, int version_id)
 523 {
 524     PCIDevice *dev = opaque;
 525     hotplug_event_update_event_status(dev);
 526     return 0;
 527 }
 528
 529 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 530 {
 531     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 532 }
 533
 534 /* root control/capabilities/status. PME isn't emulated for now */
 535 void pcie_cap_root_init(PCIDevice *dev)
 536 {
 537     pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 538                  PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 539                  PCI_EXP_RTCTL_SEFEE);
 540 }
 541
 542 void pcie_cap_root_reset(PCIDevice *dev)
 543 {
 544     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 545 }
 546
 547 /* function level reset(FLR) */
 548 void pcie_cap_flr_init(PCIDevice *dev)
 549 {
 550     pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 551                                PCI_EXP_DEVCAP_FLR);
 552
 553     /* Although reading BCR_FLR returns always 0,
 554      * the bit is made writable here in order to detect the 1b is written
 555      * pcie_cap_flr_write_config() test-and-clear the bit, so
 556      * this bit always returns 0 to the guest.
 557      */
 558     pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 559                                PCI_EXP_DEVCTL_BCR_FLR);
 560 }
 561
 562 void pcie_cap_flr_write_config(PCIDevice *dev,
 563                                uint32_t addr, uint32_t val, int len)
 564 {
 565     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 566     if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
 567         /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
 568            so the handler can detect FLR by looking at this bit. */
 569         pci_device_reset(dev);
 570         pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
 571     }
 572 }
 573
 574 /* Alternative Routing-ID Interpretation (ARI)
 575  * forwarding support for root and downstream ports
 576  */
 577 void pcie_cap_arifwd_init(PCIDevice *dev)
 578 {
 579     uint32_t pos = dev->exp.exp_cap;
 580     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 581                                PCI_EXP_DEVCAP2_ARI);
 582     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 583                                PCI_EXP_DEVCTL2_ARI);
 584 }
 585
 586 void pcie_cap_arifwd_reset(PCIDevice *dev)
 587 {
 588     uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 589     pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 590 }
 591
 592 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
 593 {
 594     if (!pci_is_express(dev)) {
 595         return false;
 596     }
 597     if (!dev->exp.exp_cap) {
 598         return false;
 599     }
 600
 601     return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 602         PCI_EXP_DEVCTL2_ARI;
 603 }
 604
 605 /**************************************************************************
 606  * pci express extended capability list management functions
 607  * uint16_t ext_cap_id (16 bit)
 608  * uint8_t cap_ver (4 bit)
 609  * uint16_t cap_offset (12 bit)
 610  * uint16_t ext_cap_size
 611  */
 612
 613 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
 614                                           uint16_t *prev_p)
 615 {
 616     uint16_t prev = 0;
 617     uint16_t next;
 618     uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 619
 620     if (!header) {
 621         /* no extended capability */
 622         next = 0;
 623         goto out;
 624     }
 625     for (next = PCI_CONFIG_SPACE_SIZE; next;
 626          prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 627
 628         assert(next >= PCI_CONFIG_SPACE_SIZE);
 629         assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 630
 631         header = pci_get_long(dev->config + next);
 632         if (PCI_EXT_CAP_ID(header) == cap_id) {
 633             break;
 634         }
 635     }
 636
 637 out:
 638     if (prev_p) {
 639         *prev_p = prev;
 640     }
 641     return next;
 642 }
 643
 644 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 645 {
 646     return pcie_find_capability_list(dev, cap_id, NULL);
 647 }
 648
 649 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 650 {
 651     uint32_t header = pci_get_long(dev->config + pos);
 652     assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 653     header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 654         ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 655     pci_set_long(dev->config + pos, header);
 656 }
 657
 658 /*
 659  * caller must supply valid (offset, size) * such that the range shouldn't
 660  * overlap with other capability or other registers.
 661  * This function doesn't check it.
 662  */
 663 void pcie_add_capability(PCIDevice *dev,
 664                          uint16_t cap_id, uint8_t cap_ver,
 665                          uint16_t offset, uint16_t size)
 666 {
 667     uint32_t header;
 668     uint16_t next;
 669
 670     assert(offset >= PCI_CONFIG_SPACE_SIZE);
 671     assert(offset < offset + size);
 672     assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
 673     assert(size >= 8);
 674     assert(pci_is_express(dev));
 675
 676     if (offset == PCI_CONFIG_SPACE_SIZE) {
 677         header = pci_get_long(dev->config + offset);
 678         next = PCI_EXT_CAP_NEXT(header);
 679     } else {
 680         uint16_t prev;
 681
 682         /* 0 is reserved cap id. use internally to find the last capability
 683            in the linked list */
 684         next = pcie_find_capability_list(dev, 0, &prev);
 685
 686         assert(prev >= PCI_CONFIG_SPACE_SIZE);
 687         assert(next == 0);
 688         pcie_ext_cap_set_next(dev, prev, offset);
 689     }
 690     pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
 691
 692     /* Make capability read-only by default */
 693     memset(dev->wmask + offset, 0, size);
 694     memset(dev->w1cmask + offset, 0, size);
 695     /* Check capability by default */
 696     memset(dev->cmask + offset, 0xFF, size);
 697 }
 698
 699 /**************************************************************************
 700  * pci express extended capability helper functions
 701  */
 702
 703 /* ARI */
 704 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 705 {
 706     pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 707                         offset, PCI_ARI_SIZEOF);
 708     pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
 709 }
 710
 711 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
 712 {
 713     static const int pci_dsn_ver = 1;
 714     static const int pci_dsn_cap = 4;
 715
 716     pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset,
 717                         PCI_EXT_CAP_DSN_SIZEOF);
 718     pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
 719 }