include/hw/i386/ioapic_internal.h

   1 /*
   2  *  IOAPIC emulation logic - internal interfaces
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2009      Xiantao Zhang, Intel
   6  *  Copyright (c) 2011 Jan Kiszka, Siemens AG
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2.1 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef QEMU_IOAPIC_INTERNAL_H
  23 #define QEMU_IOAPIC_INTERNAL_H
  24
  25 #include "exec/memory.h"
  26 #include "hw/i386/ioapic.h"
  27 #include "hw/sysbus.h"
  28 #include "qemu/notify.h"
  29 #include "qom/object.h"
  30
  31 #define MAX_IOAPICS                     2
  32
  33 #define IOAPIC_LVT_DEST_SHIFT           56
  34 #define IOAPIC_LVT_DEST_IDX_SHIFT       48
  35 #define IOAPIC_LVT_MASKED_SHIFT         16
  36 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT   15
  37 #define IOAPIC_LVT_REMOTE_IRR_SHIFT     14
  38 #define IOAPIC_LVT_POLARITY_SHIFT       13
  39 #define IOAPIC_LVT_DELIV_STATUS_SHIFT   12
  40 #define IOAPIC_LVT_DEST_MODE_SHIFT      11
  41 #define IOAPIC_LVT_DELIV_MODE_SHIFT     8
  42
  43 #define IOAPIC_LVT_MASKED               (1 << IOAPIC_LVT_MASKED_SHIFT)
  44 #define IOAPIC_LVT_TRIGGER_MODE         (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
  45 #define IOAPIC_LVT_REMOTE_IRR           (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
  46 #define IOAPIC_LVT_POLARITY             (1 << IOAPIC_LVT_POLARITY_SHIFT)
  47 #define IOAPIC_LVT_DELIV_STATUS         (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
  48 #define IOAPIC_LVT_DEST_MODE            (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
  49 #define IOAPIC_LVT_DELIV_MODE           (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
  50
  51 /* Bits that are read-only for IOAPIC entry */
  52 #define IOAPIC_RO_BITS                  (IOAPIC_LVT_REMOTE_IRR | \
  53                                          IOAPIC_LVT_DELIV_STATUS)
  54 #define IOAPIC_RW_BITS                  (~(uint64_t)IOAPIC_RO_BITS)
  55
  56 #define IOAPIC_TRIGGER_EDGE             0
  57 #define IOAPIC_TRIGGER_LEVEL            1
  58
  59 /*io{apic,sapic} delivery mode*/
  60 #define IOAPIC_DM_FIXED                 0x0
  61 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  62 #define IOAPIC_DM_PMI                   0x2
  63 #define IOAPIC_DM_NMI                   0x4
  64 #define IOAPIC_DM_INIT                  0x5
  65 #define IOAPIC_DM_SIPI                  0x6
  66 #define IOAPIC_DM_EXTINT                0x7
  67 #define IOAPIC_DM_MASK                  0x7
  68
  69 #define IOAPIC_VECTOR_MASK              0xff
  70
  71 #define IOAPIC_IOREGSEL                 0x00
  72 #define IOAPIC_IOWIN                    0x10
  73 #define IOAPIC_EOI                      0x40
  74
  75 #define IOAPIC_REG_ID                   0x00
  76 #define IOAPIC_REG_VER                  0x01
  77 #define IOAPIC_REG_ARB                  0x02
  78 #define IOAPIC_REG_REDTBL_BASE          0x10
  79 #define IOAPIC_ID                       0x00
  80
  81 #define IOAPIC_ID_SHIFT                 24
  82 #define IOAPIC_ID_MASK                  0xf
  83
  84 #define IOAPIC_VER_ENTRIES_SHIFT        16
  85
  86
  87 #define TYPE_IOAPIC_COMMON "ioapic-common"
  88 OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON)
  89
  90 struct IOAPICCommonClass {
  91     SysBusDeviceClass parent_class;
  92
  93     DeviceRealize realize;
  94     DeviceUnrealize unrealize;
  95     void (*pre_save)(IOAPICCommonState *s);
  96     void (*post_load)(IOAPICCommonState *s);
  97 };
  98
  99 struct IOAPICCommonState {
 100     SysBusDevice busdev;
 101     MemoryRegion io_memory;
 102     uint8_t id;
 103     uint8_t ioregsel;
 104     uint32_t irr;
 105     uint64_t ioredtbl[IOAPIC_NUM_PINS];
 106     Notifier machine_done;
 107     uint8_t version;
 108     uint64_t irq_count[IOAPIC_NUM_PINS];
 109     int irq_level[IOAPIC_NUM_PINS];
 110     int irq_eoi[IOAPIC_NUM_PINS];
 111     QEMUTimer *delayed_ioapic_service_timer;
 112 };
 113
 114 void ioapic_reset_common(DeviceState *dev);
 115
 116 void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
 117
 118 #endif /* QEMU_IOAPIC_INTERNAL_H */