hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40 #include "blockdev.h"
  41
  42 //#define DEBUG_IRQ
  43 //#define DEBUG_EBUS
  44 //#define DEBUG_TIMER
  45
  46 #ifdef DEBUG_IRQ
  47 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  48     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  49 #else
  50 #define CPUIRQ_DPRINTF(fmt, ...)
  51 #endif
  52
  53 #ifdef DEBUG_EBUS
  54 #define EBUS_DPRINTF(fmt, ...)                                  \
  55     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  56 #else
  57 #define EBUS_DPRINTF(fmt, ...)
  58 #endif
  59
  60 #ifdef DEBUG_TIMER
  61 #define TIMER_DPRINTF(fmt, ...)                                  \
  62     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  63 #else
  64 #define TIMER_DPRINTF(fmt, ...)
  65 #endif
  66
  67 #define KERNEL_LOAD_ADDR     0x00404000
  68 #define CMDLINE_ADDR         0x003ff000
  69 #define INITRD_LOAD_ADDR     0x00300000
  70 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  71 #define PROM_VADDR           0x000ffd00000ULL
  72 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  73 #define APB_MEM_BASE         0x1ff00000000ULL
  74 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  75 #define PROM_FILENAME        "openbios-sparc64"
  76 #define NVRAM_SIZE           0x2000
  77 #define MAX_IDE_BUS          2
  78 #define BIOS_CFG_IOPORT      0x510
  79 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  80 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  81 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  82
  83 #define MAX_PILS 16
  84
  85 #define TICK_MAX             0x7fffffffffffffffULL
  86
  87 struct hwdef {
  88     const char * const default_cpu_model;
  89     uint16_t machine_id;
  90     uint64_t prom_addr;
  91     uint64_t console_serial_base;
  92 };
  93
  94 typedef struct EbusState {
  95     PCIDevice pci_dev;
  96     MemoryRegion bar0;
  97     MemoryRegion bar1;
  98 } EbusState;
  99
 100 int DMA_get_channel_mode (int nchan)
 101 {
 102     return 0;
 103 }
 104 int DMA_read_memory (int nchan, void *buf, int pos, int size)
 105 {
 106     return 0;
 107 }
 108 int DMA_write_memory (int nchan, void *buf, int pos, int size)
 109 {
 110     return 0;
 111 }
 112 void DMA_hold_DREQ (int nchan) {}
 113 void DMA_release_DREQ (int nchan) {}
 114 void DMA_schedule(int nchan) {}
 115
 116 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
 117 {
 118 }
 119
 120 void DMA_register_channel (int nchan,
 121                            DMA_transfer_handler transfer_handler,
 122                            void *opaque)
 123 {
 124 }
 125
 126 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 127 {
 128     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 129     return 0;
 130 }
 131
 132 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
 133                                   const char *arch, ram_addr_t RAM_size,
 134                                   const char *boot_devices,
 135                                   uint32_t kernel_image, uint32_t kernel_size,
 136                                   const char *cmdline,
 137                                   uint32_t initrd_image, uint32_t initrd_size,
 138                                   uint32_t NVRAM_image,
 139                                   int width, int height, int depth,
 140                                   const uint8_t *macaddr)
 141 {
 142     unsigned int i;
 143     uint32_t start, end;
 144     uint8_t image[0x1ff0];
 145     struct OpenBIOS_nvpart_v1 *part_header;
 146
 147     memset(image, '\0', sizeof(image));
 148
 149     start = 0;
 150
 151     // OpenBIOS nvram variables
 152     // Variable partition
 153     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 154     part_header->signature = OPENBIOS_PART_SYSTEM;
 155     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 156
 157     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 158     for (i = 0; i < nb_prom_envs; i++)
 159         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 160
 161     // End marker
 162     image[end++] = '\0';
 163
 164     end = start + ((end - start + 15) & ~15);
 165     OpenBIOS_finish_partition(part_header, end - start);
 166
 167     // free partition
 168     start = end;
 169     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 170     part_header->signature = OPENBIOS_PART_FREE;
 171     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 172
 173     end = 0x1fd0;
 174     OpenBIOS_finish_partition(part_header, end - start);
 175
 176     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 177
 178     for (i = 0; i < sizeof(image); i++)
 179         m48t59_write(nvram, i, image[i]);
 180
 181     return 0;
 182 }
 183 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 184                                        const char *initrd_filename,
 185                                        ram_addr_t RAM_size, long *initrd_size)
 186 {
 187     int linux_boot;
 188     unsigned int i;
 189     long kernel_size;
 190     uint8_t *ptr;
 191
 192     linux_boot = (kernel_filename != NULL);
 193
 194     kernel_size = 0;
 195     if (linux_boot) {
 196         int bswap_needed;
 197
 198 #ifdef BSWAP_NEEDED
 199         bswap_needed = 1;
 200 #else
 201         bswap_needed = 0;
 202 #endif
 203         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 204                                NULL, NULL, 1, ELF_MACHINE, 0);
 205         if (kernel_size < 0)
 206             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 207                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 208                                     TARGET_PAGE_SIZE);
 209         if (kernel_size < 0)
 210             kernel_size = load_image_targphys(kernel_filename,
 211                                               KERNEL_LOAD_ADDR,
 212                                               RAM_size - KERNEL_LOAD_ADDR);
 213         if (kernel_size < 0) {
 214             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 215                     kernel_filename);
 216             exit(1);
 217         }
 218
 219         /* load initrd */
 220         *initrd_size = 0;
 221         if (initrd_filename) {
 222             *initrd_size = load_image_targphys(initrd_filename,
 223                                                INITRD_LOAD_ADDR,
 224                                                RAM_size - INITRD_LOAD_ADDR);
 225             if (*initrd_size < 0) {
 226                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 227                         initrd_filename);
 228                 exit(1);
 229             }
 230         }
 231         if (*initrd_size > 0) {
 232             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 233                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
 234                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 235                     stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
 236                     stl_p(ptr + 28, *initrd_size);
 237                     break;
 238                 }
 239             }
 240         }
 241     }
 242     return kernel_size;
 243 }
 244
 245 void pic_info(Monitor *mon)
 246 {
 247 }
 248
 249 void irq_info(Monitor *mon)
 250 {
 251 }
 252
 253 void cpu_check_irqs(CPUState *env)
 254 {
 255     uint32_t pil = env->pil_in |
 256                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 257
 258     /* check if TM or SM in SOFTINT are set
 259        setting these also causes interrupt 14 */
 260     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 261         pil |= 1 << 14;
 262     }
 263
 264     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
 265        is (2 << psrpil). */
 266     if (pil < (2 << env->psrpil)){
 267         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 268             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 269                            env->interrupt_index);
 270             env->interrupt_index = 0;
 271             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 272         }
 273         return;
 274     }
 275
 276     if (cpu_interrupts_enabled(env)) {
 277
 278         unsigned int i;
 279
 280         for (i = 15; i > env->psrpil; i--) {
 281             if (pil & (1 << i)) {
 282                 int old_interrupt = env->interrupt_index;
 283                 int new_interrupt = TT_EXTINT | i;
 284
 285                 if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
 286                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 287                                    "current %x >= pending %x\n",
 288                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 289                 } else if (old_interrupt != new_interrupt) {
 290                     env->interrupt_index = new_interrupt;
 291                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 292                                    old_interrupt, new_interrupt);
 293                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 294                 }
 295                 break;
 296             }
 297         }
 298     } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 299         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 300                        "current interrupt %x\n",
 301                        pil, env->pil_in, env->softint, env->interrupt_index);
 302         env->interrupt_index = 0;
 303         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 304     }
 305 }
 306
 307 static void cpu_kick_irq(CPUState *env)
 308 {
 309     env->halted = 0;
 310     cpu_check_irqs(env);
 311     qemu_cpu_kick(env);
 312 }
 313
 314 static void cpu_set_irq(void *opaque, int irq, int level)
 315 {
 316     CPUState *env = opaque;
 317
 318     if (level) {
 319         CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
 320         env->pil_in |= 1 << irq;
 321         cpu_kick_irq(env);
 322     } else {
 323         CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
 324         env->pil_in &= ~(1 << irq);
 325         cpu_check_irqs(env);
 326     }
 327 }
 328
 329 typedef struct ResetData {
 330     CPUState *env;
 331     uint64_t prom_addr;
 332 } ResetData;
 333
 334 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
 335 {
 336     qemu_put_be32s(f, &s->frequency);
 337     qemu_put_be32s(f, &s->disabled);
 338     qemu_put_be64s(f, &s->disabled_mask);
 339     qemu_put_sbe64s(f, &s->clock_offset);
 340
 341     qemu_put_timer(f, s->qtimer);
 342 }
 343
 344 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
 345 {
 346     qemu_get_be32s(f, &s->frequency);
 347     qemu_get_be32s(f, &s->disabled);
 348     qemu_get_be64s(f, &s->disabled_mask);
 349     qemu_get_sbe64s(f, &s->clock_offset);
 350
 351     qemu_get_timer(f, s->qtimer);
 352 }
 353
 354 static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
 355                                   QEMUBHFunc *cb, uint32_t frequency,
 356                                   uint64_t disabled_mask)
 357 {
 358     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 359
 360     timer->name = name;
 361     timer->frequency = frequency;
 362     timer->disabled_mask = disabled_mask;
 363
 364     timer->disabled = 1;
 365     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 366
 367     timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env);
 368
 369     return timer;
 370 }
 371
 372 static void cpu_timer_reset(CPUTimer *timer)
 373 {
 374     timer->disabled = 1;
 375     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 376
 377     qemu_del_timer(timer->qtimer);
 378 }
 379
 380 static void main_cpu_reset(void *opaque)
 381 {
 382     ResetData *s = (ResetData *)opaque;
 383     CPUState *env = s->env;
 384     static unsigned int nr_resets;
 385
 386     cpu_reset(env);
 387
 388     cpu_timer_reset(env->tick);
 389     cpu_timer_reset(env->stick);
 390     cpu_timer_reset(env->hstick);
 391
 392     env->gregs[1] = 0; // Memory start
 393     env->gregs[2] = ram_size; // Memory size
 394     env->gregs[3] = 0; // Machine description XXX
 395     if (nr_resets++ == 0) {
 396         /* Power on reset */
 397         env->pc = s->prom_addr + 0x20ULL;
 398     } else {
 399         env->pc = s->prom_addr + 0x40ULL;
 400     }
 401     env->npc = env->pc + 4;
 402 }
 403
 404 static void tick_irq(void *opaque)
 405 {
 406     CPUState *env = opaque;
 407
 408     CPUTimer* timer = env->tick;
 409
 410     if (timer->disabled) {
 411         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 412         return;
 413     } else {
 414         CPUIRQ_DPRINTF("tick: fire\n");
 415     }
 416
 417     env->softint |= SOFTINT_TIMER;
 418     cpu_kick_irq(env);
 419 }
 420
 421 static void stick_irq(void *opaque)
 422 {
 423     CPUState *env = opaque;
 424
 425     CPUTimer* timer = env->stick;
 426
 427     if (timer->disabled) {
 428         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 429         return;
 430     } else {
 431         CPUIRQ_DPRINTF("stick: fire\n");
 432     }
 433
 434     env->softint |= SOFTINT_STIMER;
 435     cpu_kick_irq(env);
 436 }
 437
 438 static void hstick_irq(void *opaque)
 439 {
 440     CPUState *env = opaque;
 441
 442     CPUTimer* timer = env->hstick;
 443
 444     if (timer->disabled) {
 445         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 446         return;
 447     } else {
 448         CPUIRQ_DPRINTF("hstick: fire\n");
 449     }
 450
 451     env->softint |= SOFTINT_STIMER;
 452     cpu_kick_irq(env);
 453 }
 454
 455 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 456 {
 457     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 458 }
 459
 460 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 461 {
 462     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 463 }
 464
 465 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 466 {
 467     uint64_t real_count = count & ~timer->disabled_mask;
 468     uint64_t disabled_bit = count & timer->disabled_mask;
 469
 470     int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
 471                     cpu_to_timer_ticks(real_count, timer->frequency);
 472
 473     TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
 474                   timer->name, real_count,
 475                   timer->disabled?"disabled":"enabled", timer);
 476
 477     timer->disabled = disabled_bit ? 1 : 0;
 478     timer->clock_offset = vm_clock_offset;
 479 }
 480
 481 uint64_t cpu_tick_get_count(CPUTimer *timer)
 482 {
 483     uint64_t real_count = timer_to_cpu_ticks(
 484                     qemu_get_clock_ns(vm_clock) - timer->clock_offset,
 485                     timer->frequency);
 486
 487     TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
 488            timer->name, real_count,
 489            timer->disabled?"disabled":"enabled", timer);
 490
 491     if (timer->disabled)
 492         real_count |= timer->disabled_mask;
 493
 494     return real_count;
 495 }
 496
 497 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 498 {
 499     int64_t now = qemu_get_clock_ns(vm_clock);
 500
 501     uint64_t real_limit = limit & ~timer->disabled_mask;
 502     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 503
 504     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 505                     timer->clock_offset;
 506
 507     if (expires < now) {
 508         expires = now + 1;
 509     }
 510
 511     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 512                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 513                   timer->name, real_limit,
 514                   timer->disabled?"disabled":"enabled",
 515                   timer, limit,
 516                   timer_to_cpu_ticks(now - timer->clock_offset,
 517                                      timer->frequency),
 518                   timer_to_cpu_ticks(expires - now, timer->frequency));
 519
 520     if (!real_limit) {
 521         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 522                 timer->name);
 523         qemu_del_timer(timer->qtimer);
 524     } else if (timer->disabled) {
 525         qemu_del_timer(timer->qtimer);
 526     } else {
 527         qemu_mod_timer(timer->qtimer, expires);
 528     }
 529 }
 530
 531 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 532 {
 533 }
 534
 535 /* EBUS (Eight bit bus) bridge */
 536 static void
 537 pci_ebus_init(PCIBus *bus, int devfn)
 538 {
 539     qemu_irq *isa_irq;
 540
 541     pci_create_simple(bus, devfn, "ebus");
 542     isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
 543     isa_bus_irqs(isa_irq);
 544 }
 545
 546 static int
 547 pci_ebus_init1(PCIDevice *pci_dev)
 548 {
 549     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 550
 551     isa_bus_new(&pci_dev->qdev);
 552
 553     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 554     pci_dev->config[0x05] = 0x00;
 555     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 556     pci_dev->config[0x07] = 0x03; // status = medium devsel
 557     pci_dev->config[0x09] = 0x00; // programming i/f
 558     pci_dev->config[0x0D] = 0x0a; // latency_timer
 559
 560     isa_mmio_setup(&s->bar0, 0x1000000);
 561     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 562     isa_mmio_setup(&s->bar1, 0x800000);
 563     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
 564     return 0;
 565 }
 566
 567 static PCIDeviceInfo ebus_info = {
 568     .qdev.name = "ebus",
 569     .qdev.size = sizeof(EbusState),
 570     .init = pci_ebus_init1,
 571     .vendor_id = PCI_VENDOR_ID_SUN,
 572     .device_id = PCI_DEVICE_ID_SUN_EBUS,
 573     .revision = 0x01,
 574     .class_id = PCI_CLASS_BRIDGE_OTHER,
 575 };
 576
 577 static void pci_ebus_register(void)
 578 {
 579     pci_qdev_register(&ebus_info);
 580 }
 581
 582 device_init(pci_ebus_register);
 583
 584 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 585 {
 586     target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
 587     return addr + *base_addr - PROM_VADDR;
 588 }
 589
 590 /* Boot PROM (OpenBIOS) */
 591 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 592 {
 593     DeviceState *dev;
 594     SysBusDevice *s;
 595     char *filename;
 596     int ret;
 597
 598     dev = qdev_create(NULL, "openprom");
 599     qdev_init_nofail(dev);
 600     s = sysbus_from_qdev(dev);
 601
 602     sysbus_mmio_map(s, 0, addr);
 603
 604     /* load boot prom */
 605     if (bios_name == NULL) {
 606         bios_name = PROM_FILENAME;
 607     }
 608     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 609     if (filename) {
 610         ret = load_elf(filename, translate_prom_address, &addr,
 611                        NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 612         if (ret < 0 || ret > PROM_SIZE_MAX) {
 613             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 614         }
 615         g_free(filename);
 616     } else {
 617         ret = -1;
 618     }
 619     if (ret < 0 || ret > PROM_SIZE_MAX) {
 620         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 621         exit(1);
 622     }
 623 }
 624
 625 static int prom_init1(SysBusDevice *dev)
 626 {
 627     ram_addr_t prom_offset;
 628
 629     prom_offset = qemu_ram_alloc(NULL, "sun4u.prom", PROM_SIZE_MAX);
 630     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 631     return 0;
 632 }
 633
 634 static SysBusDeviceInfo prom_info = {
 635     .init = prom_init1,
 636     .qdev.name  = "openprom",
 637     .qdev.size  = sizeof(SysBusDevice),
 638     .qdev.props = (Property[]) {
 639         {/* end of property list */}
 640     }
 641 };
 642
 643 static void prom_register_devices(void)
 644 {
 645     sysbus_register_withprop(&prom_info);
 646 }
 647
 648 device_init(prom_register_devices);
 649
 650
 651 typedef struct RamDevice
 652 {
 653     SysBusDevice busdev;
 654     uint64_t size;
 655 } RamDevice;
 656
 657 /* System RAM */
 658 static int ram_init1(SysBusDevice *dev)
 659 {
 660     ram_addr_t RAM_size, ram_offset;
 661     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 662
 663     RAM_size = d->size;
 664
 665     ram_offset = qemu_ram_alloc(NULL, "sun4u.ram", RAM_size);
 666     sysbus_init_mmio(dev, RAM_size, ram_offset);
 667     return 0;
 668 }
 669
 670 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 671 {
 672     DeviceState *dev;
 673     SysBusDevice *s;
 674     RamDevice *d;
 675
 676     /* allocate RAM */
 677     dev = qdev_create(NULL, "memory");
 678     s = sysbus_from_qdev(dev);
 679
 680     d = FROM_SYSBUS(RamDevice, s);
 681     d->size = RAM_size;
 682     qdev_init_nofail(dev);
 683
 684     sysbus_mmio_map(s, 0, addr);
 685 }
 686
 687 static SysBusDeviceInfo ram_info = {
 688     .init = ram_init1,
 689     .qdev.name  = "memory",
 690     .qdev.size  = sizeof(RamDevice),
 691     .qdev.props = (Property[]) {
 692         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 693         DEFINE_PROP_END_OF_LIST(),
 694     }
 695 };
 696
 697 static void ram_register_devices(void)
 698 {
 699     sysbus_register_withprop(&ram_info);
 700 }
 701
 702 device_init(ram_register_devices);
 703
 704 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 705 {
 706     CPUState *env;
 707     ResetData *reset_info;
 708
 709     uint32_t   tick_frequency = 100*1000000;
 710     uint32_t  stick_frequency = 100*1000000;
 711     uint32_t hstick_frequency = 100*1000000;
 712
 713     if (!cpu_model)
 714         cpu_model = hwdef->default_cpu_model;
 715     env = cpu_init(cpu_model);
 716     if (!env) {
 717         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 718         exit(1);
 719     }
 720
 721     env->tick = cpu_timer_create("tick", env, tick_irq,
 722                                   tick_frequency, TICK_NPT_MASK);
 723
 724     env->stick = cpu_timer_create("stick", env, stick_irq,
 725                                    stick_frequency, TICK_INT_DIS);
 726
 727     env->hstick = cpu_timer_create("hstick", env, hstick_irq,
 728                                     hstick_frequency, TICK_INT_DIS);
 729
 730     reset_info = g_malloc0(sizeof(ResetData));
 731     reset_info->env = env;
 732     reset_info->prom_addr = hwdef->prom_addr;
 733     qemu_register_reset(main_cpu_reset, reset_info);
 734
 735     return env;
 736 }
 737
 738 static void sun4uv_init(ram_addr_t RAM_size,
 739                         const char *boot_devices,
 740                         const char *kernel_filename, const char *kernel_cmdline,
 741                         const char *initrd_filename, const char *cpu_model,
 742                         const struct hwdef *hwdef)
 743 {
 744     CPUState *env;
 745     M48t59State *nvram;
 746     unsigned int i;
 747     long initrd_size, kernel_size;
 748     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 749     qemu_irq *irq;
 750     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 751     DriveInfo *fd[MAX_FD];
 752     void *fw_cfg;
 753
 754     /* init CPUs */
 755     env = cpu_devinit(cpu_model, hwdef);
 756
 757     /* set up devices */
 758     ram_init(0, RAM_size);
 759
 760     prom_init(hwdef->prom_addr, bios_name);
 761
 762
 763     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 764     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 765                            &pci_bus3);
 766     isa_mem_base = APB_PCI_IO_BASE;
 767     pci_vga_init(pci_bus);
 768
 769     // XXX Should be pci_bus3
 770     pci_ebus_init(pci_bus, -1);
 771
 772     i = 0;
 773     if (hwdef->console_serial_base) {
 774         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 775                        serial_hds[i], 1, 1);
 776         i++;
 777     }
 778     for(; i < MAX_SERIAL_PORTS; i++) {
 779         if (serial_hds[i]) {
 780             serial_isa_init(i, serial_hds[i]);
 781         }
 782     }
 783
 784     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 785         if (parallel_hds[i]) {
 786             parallel_init(i, parallel_hds[i]);
 787         }
 788     }
 789
 790     for(i = 0; i < nb_nics; i++)
 791         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 792
 793     ide_drive_get(hd, MAX_IDE_BUS);
 794
 795     pci_cmd646_ide_init(pci_bus, hd, 1);
 796
 797     isa_create_simple("i8042");
 798     for(i = 0; i < MAX_FD; i++) {
 799         fd[i] = drive_get(IF_FLOPPY, 0, i);
 800     }
 801     fdctrl_init_isa(fd);
 802     nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
 803
 804     initrd_size = 0;
 805     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 806                                     ram_size, &initrd_size);
 807
 808     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 809                            KERNEL_LOAD_ADDR, kernel_size,
 810                            kernel_cmdline,
 811                            INITRD_LOAD_ADDR, initrd_size,
 812                            /* XXX: need an option to load a NVRAM image */
 813                            0,
 814                            graphic_width, graphic_height, graphic_depth,
 815                            (uint8_t *)&nd_table[0].macaddr);
 816
 817     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 818     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 819     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 820     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 821     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 822     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 823     if (kernel_cmdline) {
 824         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 825                        strlen(kernel_cmdline) + 1);
 826         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 827                          (uint8_t*)strdup(kernel_cmdline),
 828                          strlen(kernel_cmdline) + 1);
 829     } else {
 830         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 831     }
 832     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 833     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 834     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 835
 836     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 837     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 838     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 839
 840     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 841 }
 842
 843 enum {
 844     sun4u_id = 0,
 845     sun4v_id = 64,
 846     niagara_id,
 847 };
 848
 849 static const struct hwdef hwdefs[] = {
 850     /* Sun4u generic PC-like machine */
 851     {
 852         .default_cpu_model = "TI UltraSparc IIi",
 853         .machine_id = sun4u_id,
 854         .prom_addr = 0x1fff0000000ULL,
 855         .console_serial_base = 0,
 856     },
 857     /* Sun4v generic PC-like machine */
 858     {
 859         .default_cpu_model = "Sun UltraSparc T1",
 860         .machine_id = sun4v_id,
 861         .prom_addr = 0x1fff0000000ULL,
 862         .console_serial_base = 0,
 863     },
 864     /* Sun4v generic Niagara machine */
 865     {
 866         .default_cpu_model = "Sun UltraSparc T1",
 867         .machine_id = niagara_id,
 868         .prom_addr = 0xfff0000000ULL,
 869         .console_serial_base = 0xfff0c2c000ULL,
 870     },
 871 };
 872
 873 /* Sun4u hardware initialisation */
 874 static void sun4u_init(ram_addr_t RAM_size,
 875                        const char *boot_devices,
 876                        const char *kernel_filename, const char *kernel_cmdline,
 877                        const char *initrd_filename, const char *cpu_model)
 878 {
 879     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 880                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 881 }
 882
 883 /* Sun4v hardware initialisation */
 884 static void sun4v_init(ram_addr_t RAM_size,
 885                        const char *boot_devices,
 886                        const char *kernel_filename, const char *kernel_cmdline,
 887                        const char *initrd_filename, const char *cpu_model)
 888 {
 889     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 890                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 891 }
 892
 893 /* Niagara hardware initialisation */
 894 static void niagara_init(ram_addr_t RAM_size,
 895                          const char *boot_devices,
 896                          const char *kernel_filename, const char *kernel_cmdline,
 897                          const char *initrd_filename, const char *cpu_model)
 898 {
 899     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 900                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 901 }
 902
 903 static QEMUMachine sun4u_machine = {
 904     .name = "sun4u",
 905     .desc = "Sun4u platform",
 906     .init = sun4u_init,
 907     .max_cpus = 1, // XXX for now
 908     .is_default = 1,
 909 };
 910
 911 static QEMUMachine sun4v_machine = {
 912     .name = "sun4v",
 913     .desc = "Sun4v platform",
 914     .init = sun4v_init,
 915     .max_cpus = 1, // XXX for now
 916 };
 917
 918 static QEMUMachine niagara_machine = {
 919     .name = "Niagara",
 920     .desc = "Sun4v platform, Niagara",
 921     .init = niagara_init,
 922     .max_cpus = 1, // XXX for now
 923 };
 924
 925 static void sun4u_machine_init(void)
 926 {
 927     qemu_register_machine(&sun4u_machine);
 928     qemu_register_machine(&sun4v_machine);
 929     qemu_register_machine(&niagara_machine);
 930 }
 931
 932 machine_init(sun4u_machine_init);