target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20
  21 #include "cpu.h"
  22 #include "sysemu/kvm.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "exec/log.h"
  25
  26 enum {
  27     TLBRET_XI = -6,
  28     TLBRET_RI = -5,
  29     TLBRET_DIRTY = -4,
  30     TLBRET_INVALID = -3,
  31     TLBRET_NOMATCH = -2,
  32     TLBRET_BADADDR = -1,
  33     TLBRET_MATCH = 0
  34 };
  35
  36 #if !defined(CONFIG_USER_ONLY)
  37
  38 /* no MMU emulation */
  39 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  40                         target_ulong address, int rw, int access_type)
  41 {
  42     *physical = address;
  43     *prot = PAGE_READ | PAGE_WRITE;
  44     return TLBRET_MATCH;
  45 }
  46
  47 /* fixed mapping MMU emulation */
  48 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  49                            target_ulong address, int rw, int access_type)
  50 {
  51     if (address <= (int32_t)0x7FFFFFFFUL) {
  52         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  53             *physical = address + 0x40000000UL;
  54         else
  55             *physical = address;
  56     } else if (address <= (int32_t)0xBFFFFFFFUL)
  57         *physical = address & 0x1FFFFFFF;
  58     else
  59         *physical = address;
  60
  61     *prot = PAGE_READ | PAGE_WRITE;
  62     return TLBRET_MATCH;
  63 }
  64
  65 /* MIPS32/MIPS64 R4000-style MMU emulation */
  66 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  67                      target_ulong address, int rw, int access_type)
  68 {
  69     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  70     int i;
  71
  72     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  73         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  74         /* 1k pages are not supported. */
  75         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  76         target_ulong tag = address & ~mask;
  77         target_ulong VPN = tlb->VPN & ~mask;
  78 #if defined(TARGET_MIPS64)
  79         tag &= env->SEGMask;
  80 #endif
  81
  82         /* Check ASID, virtual page number & size */
  83         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
  84             /* TLB match */
  85             int n = !!(address & mask & ~(mask >> 1));
  86             /* Check access rights */
  87             if (!(n ? tlb->V1 : tlb->V0)) {
  88                 return TLBRET_INVALID;
  89             }
  90             if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
  91                 return TLBRET_XI;
  92             }
  93             if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
  94                 return TLBRET_RI;
  95             }
  96             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
  97                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  98                 *prot = PAGE_READ;
  99                 if (n ? tlb->D1 : tlb->D0)
 100                     *prot |= PAGE_WRITE;
 101                 return TLBRET_MATCH;
 102             }
 103             return TLBRET_DIRTY;
 104         }
 105     }
 106     return TLBRET_NOMATCH;
 107 }
 108
 109 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 110                                 int *prot, target_ulong real_address,
 111                                 int rw, int access_type)
 112 {
 113     /* User mode can only access useg/xuseg */
 114     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 115     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 116     int kernel_mode = !user_mode && !supervisor_mode;
 117 #if defined(TARGET_MIPS64)
 118     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 119     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 120     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 121 #endif
 122     int ret = TLBRET_MATCH;
 123     /* effective address (modified for KVM T&E kernel segments) */
 124     target_ulong address = real_address;
 125
 126 #define USEG_LIMIT      0x7FFFFFFFUL
 127 #define KSEG0_BASE      0x80000000UL
 128 #define KSEG1_BASE      0xA0000000UL
 129 #define KSEG2_BASE      0xC0000000UL
 130 #define KSEG3_BASE      0xE0000000UL
 131
 132 #define KVM_KSEG0_BASE  0x40000000UL
 133 #define KVM_KSEG2_BASE  0x60000000UL
 134
 135     if (kvm_enabled()) {
 136         /* KVM T&E adds guest kernel segments in useg */
 137         if (real_address >= KVM_KSEG0_BASE) {
 138             if (real_address < KVM_KSEG2_BASE) {
 139                 /* kseg0 */
 140                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 141             } else if (real_address <= USEG_LIMIT) {
 142                 /* kseg2/3 */
 143                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 144             }
 145         }
 146     }
 147
 148     if (address <= USEG_LIMIT) {
 149         /* useg */
 150         if (env->CP0_Status & (1 << CP0St_ERL)) {
 151             *physical = address & 0xFFFFFFFF;
 152             *prot = PAGE_READ | PAGE_WRITE;
 153         } else {
 154             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 155         }
 156 #if defined(TARGET_MIPS64)
 157     } else if (address < 0x4000000000000000ULL) {
 158         /* xuseg */
 159         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 160             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 161         } else {
 162             ret = TLBRET_BADADDR;
 163         }
 164     } else if (address < 0x8000000000000000ULL) {
 165         /* xsseg */
 166         if ((supervisor_mode || kernel_mode) &&
 167             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 168             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 169         } else {
 170             ret = TLBRET_BADADDR;
 171         }
 172     } else if (address < 0xC000000000000000ULL) {
 173         /* xkphys */
 174         if (kernel_mode && KX &&
 175             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 176             *physical = address & env->PAMask;
 177             *prot = PAGE_READ | PAGE_WRITE;
 178         } else {
 179             ret = TLBRET_BADADDR;
 180         }
 181     } else if (address < 0xFFFFFFFF80000000ULL) {
 182         /* xkseg */
 183         if (kernel_mode && KX &&
 184             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 185             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 186         } else {
 187             ret = TLBRET_BADADDR;
 188         }
 189 #endif
 190     } else if (address < (int32_t)KSEG1_BASE) {
 191         /* kseg0 */
 192         if (kernel_mode) {
 193             *physical = address - (int32_t)KSEG0_BASE;
 194             *prot = PAGE_READ | PAGE_WRITE;
 195         } else {
 196             ret = TLBRET_BADADDR;
 197         }
 198     } else if (address < (int32_t)KSEG2_BASE) {
 199         /* kseg1 */
 200         if (kernel_mode) {
 201             *physical = address - (int32_t)KSEG1_BASE;
 202             *prot = PAGE_READ | PAGE_WRITE;
 203         } else {
 204             ret = TLBRET_BADADDR;
 205         }
 206     } else if (address < (int32_t)KSEG3_BASE) {
 207         /* sseg (kseg2) */
 208         if (supervisor_mode || kernel_mode) {
 209             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 210         } else {
 211             ret = TLBRET_BADADDR;
 212         }
 213     } else {
 214         /* kseg3 */
 215         /* XXX: debug segment is not emulated */
 216         if (kernel_mode) {
 217             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 218         } else {
 219             ret = TLBRET_BADADDR;
 220         }
 221     }
 222     return ret;
 223 }
 224 #endif
 225
 226 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 227                                 int rw, int tlb_error)
 228 {
 229     CPUState *cs = CPU(mips_env_get_cpu(env));
 230     int exception = 0, error_code = 0;
 231
 232     if (rw == MMU_INST_FETCH) {
 233         error_code |= EXCP_INST_NOTAVAIL;
 234     }
 235
 236     switch (tlb_error) {
 237     default:
 238     case TLBRET_BADADDR:
 239         /* Reference to kernel address from user mode or supervisor mode */
 240         /* Reference to supervisor address from user mode */
 241         if (rw == MMU_DATA_STORE) {
 242             exception = EXCP_AdES;
 243         } else {
 244             exception = EXCP_AdEL;
 245         }
 246         break;
 247     case TLBRET_NOMATCH:
 248         /* No TLB match for a mapped address */
 249         if (rw == MMU_DATA_STORE) {
 250             exception = EXCP_TLBS;
 251         } else {
 252             exception = EXCP_TLBL;
 253         }
 254         error_code |= EXCP_TLB_NOMATCH;
 255         break;
 256     case TLBRET_INVALID:
 257         /* TLB match with no valid bit */
 258         if (rw == MMU_DATA_STORE) {
 259             exception = EXCP_TLBS;
 260         } else {
 261             exception = EXCP_TLBL;
 262         }
 263         break;
 264     case TLBRET_DIRTY:
 265         /* TLB match but 'D' bit is cleared */
 266         exception = EXCP_LTLBL;
 267         break;
 268     case TLBRET_XI:
 269         /* Execute-Inhibit Exception */
 270         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 271             exception = EXCP_TLBXI;
 272         } else {
 273             exception = EXCP_TLBL;
 274         }
 275         break;
 276     case TLBRET_RI:
 277         /* Read-Inhibit Exception */
 278         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 279             exception = EXCP_TLBRI;
 280         } else {
 281             exception = EXCP_TLBL;
 282         }
 283         break;
 284     }
 285     /* Raise exception */
 286     env->CP0_BadVAddr = address;
 287     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 288                        ((address >> 9) & 0x007ffff0);
 289     env->CP0_EntryHi =
 290         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 291 #if defined(TARGET_MIPS64)
 292     env->CP0_EntryHi &= env->SEGMask;
 293     env->CP0_XContext =
 294         /* PTEBase */   (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 295         /* R */         (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
 296         /* BadVPN2 */   (extract64(address, 13, env->SEGBITS - 13) << 4);
 297 #endif
 298     cs->exception_index = exception;
 299     env->error_code = error_code;
 300 }
 301
 302 #if !defined(CONFIG_USER_ONLY)
 303 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 304 {
 305     MIPSCPU *cpu = MIPS_CPU(cs);
 306     hwaddr phys_addr;
 307     int prot;
 308
 309     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 310                              ACCESS_INT) != 0) {
 311         return -1;
 312     }
 313     return phys_addr;
 314 }
 315 #endif
 316
 317 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 318                               int mmu_idx)
 319 {
 320     MIPSCPU *cpu = MIPS_CPU(cs);
 321     CPUMIPSState *env = &cpu->env;
 322 #if !defined(CONFIG_USER_ONLY)
 323     hwaddr physical;
 324     int prot;
 325     int access_type;
 326 #endif
 327     int ret = 0;
 328
 329 #if 0
 330     log_cpu_state(cs, 0);
 331 #endif
 332     qemu_log_mask(CPU_LOG_MMU,
 333               "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 334               __func__, env->active_tc.PC, address, rw, mmu_idx);
 335
 336     /* data access */
 337 #if !defined(CONFIG_USER_ONLY)
 338     /* XXX: put correct access by using cpu_restore_state()
 339        correctly */
 340     access_type = ACCESS_INT;
 341     ret = get_physical_address(env, &physical, &prot,
 342                                address, rw, access_type);
 343     qemu_log_mask(CPU_LOG_MMU,
 344              "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 345              " prot %d\n",
 346              __func__, address, ret, physical, prot);
 347     if (ret == TLBRET_MATCH) {
 348         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 349                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 350                      mmu_idx, TARGET_PAGE_SIZE);
 351         ret = 0;
 352     } else if (ret < 0)
 353 #endif
 354     {
 355         raise_mmu_exception(env, address, rw, ret);
 356         ret = 1;
 357     }
 358
 359     return ret;
 360 }
 361
 362 #if !defined(CONFIG_USER_ONLY)
 363 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 364 {
 365     hwaddr physical;
 366     int prot;
 367     int access_type;
 368     int ret = 0;
 369
 370     /* data access */
 371     access_type = ACCESS_INT;
 372     ret = get_physical_address(env, &physical, &prot,
 373                                address, rw, access_type);
 374     if (ret != TLBRET_MATCH) {
 375         raise_mmu_exception(env, address, rw, ret);
 376         return -1LL;
 377     } else {
 378         return physical;
 379     }
 380 }
 381
 382 static const char * const excp_names[EXCP_LAST + 1] = {
 383     [EXCP_RESET] = "reset",
 384     [EXCP_SRESET] = "soft reset",
 385     [EXCP_DSS] = "debug single step",
 386     [EXCP_DINT] = "debug interrupt",
 387     [EXCP_NMI] = "non-maskable interrupt",
 388     [EXCP_MCHECK] = "machine check",
 389     [EXCP_EXT_INTERRUPT] = "interrupt",
 390     [EXCP_DFWATCH] = "deferred watchpoint",
 391     [EXCP_DIB] = "debug instruction breakpoint",
 392     [EXCP_IWATCH] = "instruction fetch watchpoint",
 393     [EXCP_AdEL] = "address error load",
 394     [EXCP_AdES] = "address error store",
 395     [EXCP_TLBF] = "TLB refill",
 396     [EXCP_IBE] = "instruction bus error",
 397     [EXCP_DBp] = "debug breakpoint",
 398     [EXCP_SYSCALL] = "syscall",
 399     [EXCP_BREAK] = "break",
 400     [EXCP_CpU] = "coprocessor unusable",
 401     [EXCP_RI] = "reserved instruction",
 402     [EXCP_OVERFLOW] = "arithmetic overflow",
 403     [EXCP_TRAP] = "trap",
 404     [EXCP_FPE] = "floating point",
 405     [EXCP_DDBS] = "debug data break store",
 406     [EXCP_DWATCH] = "data watchpoint",
 407     [EXCP_LTLBL] = "TLB modify",
 408     [EXCP_TLBL] = "TLB load",
 409     [EXCP_TLBS] = "TLB store",
 410     [EXCP_DBE] = "data bus error",
 411     [EXCP_DDBL] = "debug data break load",
 412     [EXCP_THREAD] = "thread",
 413     [EXCP_MDMX] = "MDMX",
 414     [EXCP_C2E] = "precise coprocessor 2",
 415     [EXCP_CACHE] = "cache error",
 416     [EXCP_TLBXI] = "TLB execute-inhibit",
 417     [EXCP_TLBRI] = "TLB read-inhibit",
 418     [EXCP_MSADIS] = "MSA disabled",
 419     [EXCP_MSAFPE] = "MSA floating point",
 420 };
 421 #endif
 422
 423 target_ulong exception_resume_pc (CPUMIPSState *env)
 424 {
 425     target_ulong bad_pc;
 426     target_ulong isa_mode;
 427
 428     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 429     bad_pc = env->active_tc.PC | isa_mode;
 430     if (env->hflags & MIPS_HFLAG_BMASK) {
 431         /* If the exception was raised from a delay slot, come back to
 432            the jump.  */
 433         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 434     }
 435
 436     return bad_pc;
 437 }
 438
 439 #if !defined(CONFIG_USER_ONLY)
 440 static void set_hflags_for_handler (CPUMIPSState *env)
 441 {
 442     /* Exception handlers are entered in 32-bit mode.  */
 443     env->hflags &= ~(MIPS_HFLAG_M16);
 444     /* ...except that microMIPS lets you choose.  */
 445     if (env->insn_flags & ASE_MICROMIPS) {
 446         env->hflags |= (!!(env->CP0_Config3
 447                            & (1 << CP0C3_ISA_ON_EXC))
 448                         << MIPS_HFLAG_M16_SHIFT);
 449     }
 450 }
 451
 452 static inline void set_badinstr_registers(CPUMIPSState *env)
 453 {
 454     if (env->hflags & MIPS_HFLAG_M16) {
 455         /* TODO: add BadInstr support for microMIPS */
 456         return;
 457     }
 458     if (env->CP0_Config3 & (1 << CP0C3_BI)) {
 459         env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
 460     }
 461     if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
 462         (env->hflags & MIPS_HFLAG_BMASK)) {
 463         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
 464     }
 465 }
 466 #endif
 467
 468 void mips_cpu_do_interrupt(CPUState *cs)
 469 {
 470 #if !defined(CONFIG_USER_ONLY)
 471     MIPSCPU *cpu = MIPS_CPU(cs);
 472     CPUMIPSState *env = &cpu->env;
 473     bool update_badinstr = 0;
 474     target_ulong offset;
 475     int cause = -1;
 476     const char *name;
 477
 478     if (qemu_loglevel_mask(CPU_LOG_INT)
 479         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 480         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 481             name = "unknown";
 482         } else {
 483             name = excp_names[cs->exception_index];
 484         }
 485
 486         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
 487                  " %s exception\n",
 488                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 489     }
 490     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 491         (env->hflags & MIPS_HFLAG_DM)) {
 492         cs->exception_index = EXCP_DINT;
 493     }
 494     offset = 0x180;
 495     switch (cs->exception_index) {
 496     case EXCP_DSS:
 497         env->CP0_Debug |= 1 << CP0DB_DSS;
 498         /* Debug single step cannot be raised inside a delay slot and
 499            resume will always occur on the next instruction
 500            (but we assume the pc has always been updated during
 501            code translation). */
 502         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 503         goto enter_debug_mode;
 504     case EXCP_DINT:
 505         env->CP0_Debug |= 1 << CP0DB_DINT;
 506         goto set_DEPC;
 507     case EXCP_DIB:
 508         env->CP0_Debug |= 1 << CP0DB_DIB;
 509         goto set_DEPC;
 510     case EXCP_DBp:
 511         env->CP0_Debug |= 1 << CP0DB_DBp;
 512         goto set_DEPC;
 513     case EXCP_DDBS:
 514         env->CP0_Debug |= 1 << CP0DB_DDBS;
 515         goto set_DEPC;
 516     case EXCP_DDBL:
 517         env->CP0_Debug |= 1 << CP0DB_DDBL;
 518     set_DEPC:
 519         env->CP0_DEPC = exception_resume_pc(env);
 520         env->hflags &= ~MIPS_HFLAG_BMASK;
 521  enter_debug_mode:
 522         if (env->insn_flags & ISA_MIPS3) {
 523             env->hflags |= MIPS_HFLAG_64;
 524             if (!(env->insn_flags & ISA_MIPS64R6) ||
 525                 env->CP0_Status & (1 << CP0St_KX)) {
 526                 env->hflags &= ~MIPS_HFLAG_AWRAP;
 527             }
 528         }
 529         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
 530         env->hflags &= ~(MIPS_HFLAG_KSU);
 531         /* EJTAG probe trap enable is not implemented... */
 532         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 533             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 534         env->active_tc.PC = (int32_t)0xBFC00480;
 535         set_hflags_for_handler(env);
 536         break;
 537     case EXCP_RESET:
 538         cpu_reset(CPU(cpu));
 539         break;
 540     case EXCP_SRESET:
 541         env->CP0_Status |= (1 << CP0St_SR);
 542         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 543         goto set_error_EPC;
 544     case EXCP_NMI:
 545         env->CP0_Status |= (1 << CP0St_NMI);
 546  set_error_EPC:
 547         env->CP0_ErrorEPC = exception_resume_pc(env);
 548         env->hflags &= ~MIPS_HFLAG_BMASK;
 549         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 550         if (env->insn_flags & ISA_MIPS3) {
 551             env->hflags |= MIPS_HFLAG_64;
 552             if (!(env->insn_flags & ISA_MIPS64R6) ||
 553                 env->CP0_Status & (1 << CP0St_KX)) {
 554                 env->hflags &= ~MIPS_HFLAG_AWRAP;
 555             }
 556         }
 557         env->hflags |= MIPS_HFLAG_CP0;
 558         env->hflags &= ~(MIPS_HFLAG_KSU);
 559         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 560             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 561         env->active_tc.PC = (int32_t)0xBFC00000;
 562         set_hflags_for_handler(env);
 563         break;
 564     case EXCP_EXT_INTERRUPT:
 565         cause = 0;
 566         if (env->CP0_Cause & (1 << CP0Ca_IV)) {
 567             uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
 568
 569             if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
 570                 offset = 0x200;
 571             } else {
 572                 uint32_t vector = 0;
 573                 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
 574
 575                 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 576                     /* For VEIC mode, the external interrupt controller feeds
 577                      * the vector through the CP0Cause IP lines.  */
 578                     vector = pending;
 579                 } else {
 580                     /* Vectored Interrupts
 581                      * Mask with Status.IM7-IM0 to get enabled interrupts. */
 582                     pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
 583                     /* Find the highest-priority interrupt. */
 584                     while (pending >>= 1) {
 585                         vector++;
 586                     }
 587                 }
 588                 offset = 0x200 + (vector * (spacing << 5));
 589             }
 590         }
 591         goto set_EPC;
 592     case EXCP_LTLBL:
 593         cause = 1;
 594         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 595         goto set_EPC;
 596     case EXCP_TLBL:
 597         cause = 2;
 598         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 599         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 600             !(env->CP0_Status & (1 << CP0St_EXL))) {
 601 #if defined(TARGET_MIPS64)
 602             int R = env->CP0_BadVAddr >> 62;
 603             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 604             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 605             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 606
 607             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 608                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 609                 offset = 0x080;
 610             else
 611 #endif
 612                 offset = 0x000;
 613         }
 614         goto set_EPC;
 615     case EXCP_TLBS:
 616         cause = 3;
 617         update_badinstr = 1;
 618         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 619             !(env->CP0_Status & (1 << CP0St_EXL))) {
 620 #if defined(TARGET_MIPS64)
 621             int R = env->CP0_BadVAddr >> 62;
 622             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 623             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 624             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 625
 626             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 627                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 628                 offset = 0x080;
 629             else
 630 #endif
 631                 offset = 0x000;
 632         }
 633         goto set_EPC;
 634     case EXCP_AdEL:
 635         cause = 4;
 636         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 637         goto set_EPC;
 638     case EXCP_AdES:
 639         cause = 5;
 640         update_badinstr = 1;
 641         goto set_EPC;
 642     case EXCP_IBE:
 643         cause = 6;
 644         goto set_EPC;
 645     case EXCP_DBE:
 646         cause = 7;
 647         goto set_EPC;
 648     case EXCP_SYSCALL:
 649         cause = 8;
 650         update_badinstr = 1;
 651         goto set_EPC;
 652     case EXCP_BREAK:
 653         cause = 9;
 654         update_badinstr = 1;
 655         goto set_EPC;
 656     case EXCP_RI:
 657         cause = 10;
 658         update_badinstr = 1;
 659         goto set_EPC;
 660     case EXCP_CpU:
 661         cause = 11;
 662         update_badinstr = 1;
 663         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 664                          (env->error_code << CP0Ca_CE);
 665         goto set_EPC;
 666     case EXCP_OVERFLOW:
 667         cause = 12;
 668         update_badinstr = 1;
 669         goto set_EPC;
 670     case EXCP_TRAP:
 671         cause = 13;
 672         update_badinstr = 1;
 673         goto set_EPC;
 674     case EXCP_MSAFPE:
 675         cause = 14;
 676         update_badinstr = 1;
 677         goto set_EPC;
 678     case EXCP_FPE:
 679         cause = 15;
 680         update_badinstr = 1;
 681         goto set_EPC;
 682     case EXCP_C2E:
 683         cause = 18;
 684         goto set_EPC;
 685     case EXCP_TLBRI:
 686         cause = 19;
 687         update_badinstr = 1;
 688         goto set_EPC;
 689     case EXCP_TLBXI:
 690         cause = 20;
 691         goto set_EPC;
 692     case EXCP_MSADIS:
 693         cause = 21;
 694         update_badinstr = 1;
 695         goto set_EPC;
 696     case EXCP_MDMX:
 697         cause = 22;
 698         goto set_EPC;
 699     case EXCP_DWATCH:
 700         cause = 23;
 701         /* XXX: TODO: manage deferred watch exceptions */
 702         goto set_EPC;
 703     case EXCP_MCHECK:
 704         cause = 24;
 705         goto set_EPC;
 706     case EXCP_THREAD:
 707         cause = 25;
 708         goto set_EPC;
 709     case EXCP_DSPDIS:
 710         cause = 26;
 711         goto set_EPC;
 712     case EXCP_CACHE:
 713         cause = 30;
 714         if (env->CP0_Status & (1 << CP0St_BEV)) {
 715             offset = 0x100;
 716         } else {
 717             offset = 0x20000100;
 718         }
 719  set_EPC:
 720         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 721             env->CP0_EPC = exception_resume_pc(env);
 722             if (update_badinstr) {
 723                 set_badinstr_registers(env);
 724             }
 725             if (env->hflags & MIPS_HFLAG_BMASK) {
 726                 env->CP0_Cause |= (1U << CP0Ca_BD);
 727             } else {
 728                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 729             }
 730             env->CP0_Status |= (1 << CP0St_EXL);
 731             if (env->insn_flags & ISA_MIPS3) {
 732                 env->hflags |= MIPS_HFLAG_64;
 733                 if (!(env->insn_flags & ISA_MIPS64R6) ||
 734                     env->CP0_Status & (1 << CP0St_KX)) {
 735                     env->hflags &= ~MIPS_HFLAG_AWRAP;
 736                 }
 737             }
 738             env->hflags |= MIPS_HFLAG_CP0;
 739             env->hflags &= ~(MIPS_HFLAG_KSU);
 740         }
 741         env->hflags &= ~MIPS_HFLAG_BMASK;
 742         if (env->CP0_Status & (1 << CP0St_BEV)) {
 743             env->active_tc.PC = (int32_t)0xBFC00200;
 744         } else {
 745             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 746         }
 747         env->active_tc.PC += offset;
 748         set_hflags_for_handler(env);
 749         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 750         break;
 751     default:
 752         abort();
 753     }
 754     if (qemu_loglevel_mask(CPU_LOG_INT)
 755         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 756         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 757                  "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 758                  __func__, env->active_tc.PC, env->CP0_EPC, cause,
 759                  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 760                  env->CP0_DEPC);
 761     }
 762 #endif
 763     cs->exception_index = EXCP_NONE;
 764 }
 765
 766 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 767 {
 768     if (interrupt_request & CPU_INTERRUPT_HARD) {
 769         MIPSCPU *cpu = MIPS_CPU(cs);
 770         CPUMIPSState *env = &cpu->env;
 771
 772         if (cpu_mips_hw_interrupts_enabled(env) &&
 773             cpu_mips_hw_interrupts_pending(env)) {
 774             /* Raise it */
 775             cs->exception_index = EXCP_EXT_INTERRUPT;
 776             env->error_code = 0;
 777             mips_cpu_do_interrupt(cs);
 778             return true;
 779         }
 780     }
 781     return false;
 782 }
 783
 784 #if !defined(CONFIG_USER_ONLY)
 785 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 786 {
 787     MIPSCPU *cpu = mips_env_get_cpu(env);
 788     CPUState *cs;
 789     r4k_tlb_t *tlb;
 790     target_ulong addr;
 791     target_ulong end;
 792     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 793     target_ulong mask;
 794
 795     tlb = &env->tlb->mmu.r4k.tlb[idx];
 796     /* The qemu TLB is flushed when the ASID changes, so no need to
 797        flush these entries again.  */
 798     if (tlb->G == 0 && tlb->ASID != ASID) {
 799         return;
 800     }
 801
 802     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 803         /* For tlbwr, we can shadow the discarded entry into
 804            a new (fake) TLB entry, as long as the guest can not
 805            tell that it's there.  */
 806         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 807         env->tlb->tlb_in_use++;
 808         return;
 809     }
 810
 811     /* 1k pages are not supported. */
 812     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 813     if (tlb->V0) {
 814         cs = CPU(cpu);
 815         addr = tlb->VPN & ~mask;
 816 #if defined(TARGET_MIPS64)
 817         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 818             addr |= 0x3FFFFF0000000000ULL;
 819         }
 820 #endif
 821         end = addr | (mask >> 1);
 822         while (addr < end) {
 823             tlb_flush_page(cs, addr);
 824             addr += TARGET_PAGE_SIZE;
 825         }
 826     }
 827     if (tlb->V1) {
 828         cs = CPU(cpu);
 829         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 830 #if defined(TARGET_MIPS64)
 831         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 832             addr |= 0x3FFFFF0000000000ULL;
 833         }
 834 #endif
 835         end = addr | mask;
 836         while (addr - 1 < end) {
 837             tlb_flush_page(cs, addr);
 838             addr += TARGET_PAGE_SIZE;
 839         }
 840     }
 841 }
 842 #endif