4 #include "qemu-common.h"
7 #include "exec/memory.h"
8 #include "sysemu/dma.h"
10 /* PCI includes legacy ISA access. */
13 #include "hw/pci/pcie.h"
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 #include "hw/pci/pci_ids.h"
26 /* QEMU-specific Vendor and Device ID definitions */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
63 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
66 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
67 #define PCI_DEVICE_ID_INTEL_82557 0x1229
68 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
70 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
71 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
73 #define PCI_SUBDEVICE_ID_QEMU 0x1100
75 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
76 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
77 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
78 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
79 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
80 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
81 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
83 #define PCI_VENDOR_ID_REDHAT 0x1b36
84 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
85 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
86 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
87 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
88 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
90 #define FMT_PCIBUS PRIx64
92 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
93 uint32_t address
, uint32_t data
, int len
);
94 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
95 uint32_t address
, int len
);
96 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
97 pcibus_t addr
, pcibus_t size
, int type
);
98 typedef void PCIUnregisterFunc(PCIDevice
*pci_dev
);
100 typedef struct PCIIORegion
{
101 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
102 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
105 MemoryRegion
*memory
;
106 MemoryRegion
*address_space
;
109 #define PCI_ROM_SLOT 6
110 #define PCI_NUM_REGIONS 7
112 #include "hw/pci/pci_regs.h"
114 /* PCI HEADER_TYPE */
115 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
117 /* Size of the standard PCI config header */
118 #define PCI_CONFIG_HEADER_SIZE 0x40
119 /* Size of the standard PCI config space */
120 #define PCI_CONFIG_SPACE_SIZE 0x100
121 /* Size of the standart PCIe config space: 4KB */
122 #define PCIE_CONFIG_SPACE_SIZE 0x1000
124 #define PCI_NUM_PINS 4 /* A-D */
126 /* Bits in cap_present field. */
128 QEMU_PCI_CAP_MSI
= 0x1,
129 QEMU_PCI_CAP_MSIX
= 0x2,
130 QEMU_PCI_CAP_EXPRESS
= 0x4,
132 /* multifunction capable device */
133 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
134 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
136 /* command register SERR bit enabled */
137 #define QEMU_PCI_CAP_SERR_BITNR 4
138 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
139 /* Standard hot plug controller. */
140 #define QEMU_PCI_SHPC_BITNR 5
141 QEMU_PCI_CAP_SHPC
= (1 << QEMU_PCI_SHPC_BITNR
),
142 #define QEMU_PCI_SLOTID_BITNR 6
143 QEMU_PCI_CAP_SLOTID
= (1 << QEMU_PCI_SLOTID_BITNR
),
146 #define TYPE_PCI_DEVICE "pci-device"
147 #define PCI_DEVICE(obj) \
148 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
149 #define PCI_DEVICE_CLASS(klass) \
150 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
151 #define PCI_DEVICE_GET_CLASS(obj) \
152 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
154 typedef struct PCIINTxRoute
{
163 typedef struct PCIDeviceClass
{
164 DeviceClass parent_class
;
166 int (*init
)(PCIDevice
*dev
);
167 PCIUnregisterFunc
*exit
;
168 PCIConfigReadFunc
*config_read
;
169 PCIConfigWriteFunc
*config_write
;
175 uint16_t subsystem_vendor_id
; /* only for header type = 0 */
176 uint16_t subsystem_id
; /* only for header type = 0 */
179 * pci-to-pci bridge or normal device.
180 * This doesn't mean pci host switch.
181 * When card bus bridge is supported, this would be enhanced.
186 int is_express
; /* is this device pci express? */
188 /* device isn't hot-pluggable */
195 typedef void (*PCIINTxRoutingNotifier
)(PCIDevice
*dev
);
196 typedef int (*MSIVectorUseNotifier
)(PCIDevice
*dev
, unsigned int vector
,
198 typedef void (*MSIVectorReleaseNotifier
)(PCIDevice
*dev
, unsigned int vector
);
199 typedef void (*MSIVectorPollNotifier
)(PCIDevice
*dev
,
200 unsigned int vector_start
,
201 unsigned int vector_end
);
206 /* PCI config space */
209 /* Used to enable config checks on load. Note that writable bits are
210 * never checked even if set in cmask. */
213 /* Used to implement R/W bytes */
216 /* Used to implement RW1C(Write 1 to Clear) bytes */
219 /* Used to allocate config space for capabilities. */
222 /* the following fields are read only */
226 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
227 AddressSpace bus_master_as
;
228 MemoryRegion bus_master_enable_region
;
231 /* do not access the following fields */
232 PCIConfigReadFunc
*config_read
;
233 PCIConfigWriteFunc
*config_write
;
235 /* IRQ objects for the INTA-INTD pins. */
238 /* Current IRQ levels. Used internally by the generic PCI code. */
241 /* Capability bits */
242 uint32_t cap_present
;
244 /* Offset of MSI-X capability in config space */
250 /* Space to store MSIX table & pending bit array */
253 /* MemoryRegion container for msix exclusive BAR setup */
254 MemoryRegion msix_exclusive_bar
;
255 /* Memory Regions for MSIX table and pending bit entries. */
256 MemoryRegion msix_table_mmio
;
257 MemoryRegion msix_pba_mmio
;
258 /* Reference-count for entries actually in use by driver. */
259 unsigned *msix_entry_used
;
260 /* MSIX function mask set or MSIX disabled */
261 bool msix_function_masked
;
262 /* Version id needed for VMState */
265 /* Offset of MSI capability in config space */
269 PCIExpressDevice exp
;
274 /* Location of option rom */
280 /* INTx routing notifier */
281 PCIINTxRoutingNotifier intx_routing_notifier
;
283 /* MSI-X notifiers */
284 MSIVectorUseNotifier msix_vector_use_notifier
;
285 MSIVectorReleaseNotifier msix_vector_release_notifier
;
286 MSIVectorPollNotifier msix_vector_poll_notifier
;
289 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
290 uint8_t attr
, MemoryRegion
*memory
);
291 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
);
293 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
294 uint8_t offset
, uint8_t size
);
296 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
298 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
301 uint32_t pci_default_read_config(PCIDevice
*d
,
302 uint32_t address
, int len
);
303 void pci_default_write_config(PCIDevice
*d
,
304 uint32_t address
, uint32_t val
, int len
);
305 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
306 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
307 MemoryRegion
*pci_address_space(PCIDevice
*dev
);
308 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
);
310 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
311 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
312 typedef PCIINTxRoute (*pci_route_irq_fn
)(void *opaque
, int pin
);
315 PCI_HOTPLUG_DISABLED
,
317 PCI_COLDPLUG_ENABLED
,
320 typedef int (*pci_hotplug_fn
)(DeviceState
*qdev
, PCIDevice
*pci_dev
,
321 PCIHotplugState state
);
322 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
324 MemoryRegion
*address_space_mem
,
325 MemoryRegion
*address_space_io
,
327 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
328 MemoryRegion
*address_space_mem
,
329 MemoryRegion
*address_space_io
,
331 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
332 void *irq_opaque
, int nirq
);
333 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
);
334 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*dev
);
335 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
336 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
);
337 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
338 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
340 MemoryRegion
*address_space_mem
,
341 MemoryRegion
*address_space_io
,
342 uint8_t devfn_min
, int nirq
);
343 void pci_bus_set_route_irq_fn(PCIBus
*, pci_route_irq_fn
);
344 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
);
345 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new);
346 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
);
347 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
348 PCIINTxRoutingNotifier notifier
);
349 void pci_device_reset(PCIDevice
*dev
);
350 void pci_bus_reset(PCIBus
*bus
);
352 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
353 const char *default_devaddr
);
354 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
355 const char *default_devaddr
);
357 PCIDevice
*pci_vga_init(PCIBus
*bus
);
359 int pci_bus_num(PCIBus
*s
);
360 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
361 void (*fn
)(PCIBus
*bus
, PCIDevice
*d
, void *opaque
),
363 PCIBus
*pci_find_root_bus(int domain
);
364 int pci_find_domain(const PCIBus
*bus
);
365 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
);
366 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
);
367 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
);
369 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
372 void pci_device_deassert_intx(PCIDevice
*dev
);
374 typedef DMAContext
*(*PCIDMAContextFunc
)(PCIBus
*, void *, int);
376 void pci_setup_iommu(PCIBus
*bus
, PCIDMAContextFunc fn
, void *opaque
);
379 pci_set_byte(uint8_t *config
, uint8_t val
)
384 static inline uint8_t
385 pci_get_byte(const uint8_t *config
)
391 pci_set_word(uint8_t *config
, uint16_t val
)
393 cpu_to_le16wu((uint16_t *)config
, val
);
396 static inline uint16_t
397 pci_get_word(const uint8_t *config
)
399 return le16_to_cpupu((const uint16_t *)config
);
403 pci_set_long(uint8_t *config
, uint32_t val
)
405 cpu_to_le32wu((uint32_t *)config
, val
);
408 static inline uint32_t
409 pci_get_long(const uint8_t *config
)
411 return le32_to_cpupu((const uint32_t *)config
);
415 pci_set_quad(uint8_t *config
, uint64_t val
)
417 cpu_to_le64w((uint64_t *)config
, val
);
420 static inline uint64_t
421 pci_get_quad(const uint8_t *config
)
423 return le64_to_cpup((const uint64_t *)config
);
427 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
429 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
433 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
435 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
439 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
441 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
445 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
447 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
451 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
453 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
457 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
459 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
463 * helper functions to do bit mask operation on configuration space.
464 * Just to set bit, use test-and-set and discard returned value.
465 * Just to clear bit, use test-and-clear and discard returned value.
466 * NOTE: They aren't atomic.
468 static inline uint8_t
469 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
471 uint8_t val
= pci_get_byte(config
);
472 pci_set_byte(config
, val
& ~mask
);
476 static inline uint8_t
477 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
479 uint8_t val
= pci_get_byte(config
);
480 pci_set_byte(config
, val
| mask
);
484 static inline uint16_t
485 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
487 uint16_t val
= pci_get_word(config
);
488 pci_set_word(config
, val
& ~mask
);
492 static inline uint16_t
493 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
495 uint16_t val
= pci_get_word(config
);
496 pci_set_word(config
, val
| mask
);
500 static inline uint32_t
501 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
503 uint32_t val
= pci_get_long(config
);
504 pci_set_long(config
, val
& ~mask
);
508 static inline uint32_t
509 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
511 uint32_t val
= pci_get_long(config
);
512 pci_set_long(config
, val
| mask
);
516 static inline uint64_t
517 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
519 uint64_t val
= pci_get_quad(config
);
520 pci_set_quad(config
, val
& ~mask
);
524 static inline uint64_t
525 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
527 uint64_t val
= pci_get_quad(config
);
528 pci_set_quad(config
, val
| mask
);
532 /* Access a register specified by a mask */
534 pci_set_byte_by_mask(uint8_t *config
, uint8_t mask
, uint8_t reg
)
536 uint8_t val
= pci_get_byte(config
);
537 uint8_t rval
= reg
<< (ffs(mask
) - 1);
538 pci_set_byte(config
, (~mask
& val
) | (mask
& rval
));
541 static inline uint8_t
542 pci_get_byte_by_mask(uint8_t *config
, uint8_t mask
)
544 uint8_t val
= pci_get_byte(config
);
545 return (val
& mask
) >> (ffs(mask
) - 1);
549 pci_set_word_by_mask(uint8_t *config
, uint16_t mask
, uint16_t reg
)
551 uint16_t val
= pci_get_word(config
);
552 uint16_t rval
= reg
<< (ffs(mask
) - 1);
553 pci_set_word(config
, (~mask
& val
) | (mask
& rval
));
556 static inline uint16_t
557 pci_get_word_by_mask(uint8_t *config
, uint16_t mask
)
559 uint16_t val
= pci_get_word(config
);
560 return (val
& mask
) >> (ffs(mask
) - 1);
564 pci_set_long_by_mask(uint8_t *config
, uint32_t mask
, uint32_t reg
)
566 uint32_t val
= pci_get_long(config
);
567 uint32_t rval
= reg
<< (ffs(mask
) - 1);
568 pci_set_long(config
, (~mask
& val
) | (mask
& rval
));
571 static inline uint32_t
572 pci_get_long_by_mask(uint8_t *config
, uint32_t mask
)
574 uint32_t val
= pci_get_long(config
);
575 return (val
& mask
) >> (ffs(mask
) - 1);
579 pci_set_quad_by_mask(uint8_t *config
, uint64_t mask
, uint64_t reg
)
581 uint64_t val
= pci_get_quad(config
);
582 uint64_t rval
= reg
<< (ffs(mask
) - 1);
583 pci_set_quad(config
, (~mask
& val
) | (mask
& rval
));
586 static inline uint64_t
587 pci_get_quad_by_mask(uint8_t *config
, uint64_t mask
)
589 uint64_t val
= pci_get_quad(config
);
590 return (val
& mask
) >> (ffs(mask
) - 1);
593 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
595 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
598 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
599 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
601 static inline int pci_is_express(const PCIDevice
*d
)
603 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
606 static inline uint32_t pci_config_size(const PCIDevice
*d
)
608 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;
611 /* DMA access functions */
612 static inline DMAContext
*pci_dma_context(PCIDevice
*dev
)
617 static inline int pci_dma_rw(PCIDevice
*dev
, dma_addr_t addr
,
618 void *buf
, dma_addr_t len
, DMADirection dir
)
620 dma_memory_rw(pci_dma_context(dev
), addr
, buf
, len
, dir
);
624 static inline int pci_dma_read(PCIDevice
*dev
, dma_addr_t addr
,
625 void *buf
, dma_addr_t len
)
627 return pci_dma_rw(dev
, addr
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
630 static inline int pci_dma_write(PCIDevice
*dev
, dma_addr_t addr
,
631 const void *buf
, dma_addr_t len
)
633 return pci_dma_rw(dev
, addr
, (void *) buf
, len
, DMA_DIRECTION_FROM_DEVICE
);
636 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
637 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
640 return ld##_l##_dma(pci_dma_context(dev), addr); \
642 static inline void st##_s##_pci_dma(PCIDevice *dev, \
643 dma_addr_t addr, uint##_bits##_t val) \
645 st##_s##_dma(pci_dma_context(dev), addr, val); \
648 PCI_DMA_DEFINE_LDST(ub
, b
, 8);
649 PCI_DMA_DEFINE_LDST(uw_le
, w_le
, 16)
650 PCI_DMA_DEFINE_LDST(l_le
, l_le
, 32);
651 PCI_DMA_DEFINE_LDST(q_le
, q_le
, 64);
652 PCI_DMA_DEFINE_LDST(uw_be
, w_be
, 16)
653 PCI_DMA_DEFINE_LDST(l_be
, l_be
, 32);
654 PCI_DMA_DEFINE_LDST(q_be
, q_be
, 64);
656 #undef PCI_DMA_DEFINE_LDST
658 static inline void *pci_dma_map(PCIDevice
*dev
, dma_addr_t addr
,
659 dma_addr_t
*plen
, DMADirection dir
)
663 buf
= dma_memory_map(pci_dma_context(dev
), addr
, plen
, dir
);
667 static inline void pci_dma_unmap(PCIDevice
*dev
, void *buffer
, dma_addr_t len
,
668 DMADirection dir
, dma_addr_t access_len
)
670 dma_memory_unmap(pci_dma_context(dev
), buffer
, len
, dir
, access_len
);
673 static inline void pci_dma_sglist_init(QEMUSGList
*qsg
, PCIDevice
*dev
,
676 qemu_sglist_init(qsg
, alloc_hint
, pci_dma_context(dev
));
679 extern const VMStateDescription vmstate_pci_device
;
681 #define VMSTATE_PCI_DEVICE(_field, _state) { \
682 .name = (stringify(_field)), \
683 .size = sizeof(PCIDevice), \
684 .vmsd = &vmstate_pci_device, \
685 .flags = VMS_STRUCT, \
686 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
689 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
690 .name = (stringify(_field)), \
691 .size = sizeof(PCIDevice), \
692 .vmsd = &vmstate_pci_device, \
693 .flags = VMS_STRUCT|VMS_POINTER, \
694 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \