target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
[qemu.git] / hw / arm / mainstone.c
blob0da02a67ec34f53a75090c3532e6dd33b0676dcf
1 /*
2 * PXA270-based Intel Mainstone platforms.
4 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
5 * <akuster@mvista.com>
7 * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
9 * This code is licensed under the GNU GPL v2.
11 * Contributions after 2012-01-13 are licensed under the terms of the
12 * GNU GPL, version 2 or (at your option) any later version.
14 #include "hw/hw.h"
15 #include "hw/arm/pxa.h"
16 #include "hw/arm/arm.h"
17 #include "net/net.h"
18 #include "hw/devices.h"
19 #include "hw/boards.h"
20 #include "hw/block/flash.h"
21 #include "sysemu/block-backend.h"
22 #include "hw/sysbus.h"
23 #include "exec/address-spaces.h"
24 #include "sysemu/qtest.h"
26 /* Device addresses */
27 #define MST_FPGA_PHYS 0x08000000
28 #define MST_ETH_PHYS 0x10000300
29 #define MST_FLASH_0 0x00000000
30 #define MST_FLASH_1 0x04000000
32 /* IRQ definitions */
33 #define MMC_IRQ 0
34 #define USIM_IRQ 1
35 #define USBC_IRQ 2
36 #define ETHERNET_IRQ 3
37 #define AC97_IRQ 4
38 #define PEN_IRQ 5
39 #define MSINS_IRQ 6
40 #define EXBRD_IRQ 7
41 #define S0_CD_IRQ 9
42 #define S0_STSCHG_IRQ 10
43 #define S0_IRQ 11
44 #define S1_CD_IRQ 13
45 #define S1_STSCHG_IRQ 14
46 #define S1_IRQ 15
48 static const struct keymap map[0xE0] = {
49 [0 ... 0xDF] = { -1, -1 },
50 [0x1e] = {0,0}, /* a */
51 [0x30] = {0,1}, /* b */
52 [0x2e] = {0,2}, /* c */
53 [0x20] = {0,3}, /* d */
54 [0x12] = {0,4}, /* e */
55 [0x21] = {0,5}, /* f */
56 [0x22] = {1,0}, /* g */
57 [0x23] = {1,1}, /* h */
58 [0x17] = {1,2}, /* i */
59 [0x24] = {1,3}, /* j */
60 [0x25] = {1,4}, /* k */
61 [0x26] = {1,5}, /* l */
62 [0x32] = {2,0}, /* m */
63 [0x31] = {2,1}, /* n */
64 [0x18] = {2,2}, /* o */
65 [0x19] = {2,3}, /* p */
66 [0x10] = {2,4}, /* q */
67 [0x13] = {2,5}, /* r */
68 [0x1f] = {3,0}, /* s */
69 [0x14] = {3,1}, /* t */
70 [0x16] = {3,2}, /* u */
71 [0x2f] = {3,3}, /* v */
72 [0x11] = {3,4}, /* w */
73 [0x2d] = {3,5}, /* x */
74 [0x15] = {4,2}, /* y */
75 [0x2c] = {4,3}, /* z */
76 [0xc7] = {5,0}, /* Home */
77 [0x2a] = {5,1}, /* shift */
79 * There are two matrix positions which map to space,
80 * but QEMU can only use one of them for the reverse
81 * mapping, so simply use the second one.
83 /* [0x39] = {5,2}, space */
84 [0x39] = {5,3}, /* space */
86 * Matrix position {5,4} and other keys are missing here.
87 * TODO: Compare with Linux code and test real hardware.
89 [0x1c] = {5,5}, /* enter (TODO: might be wrong) */
90 [0xc8] = {6,0}, /* up */
91 [0xd0] = {6,1}, /* down */
92 [0xcb] = {6,2}, /* left */
93 [0xcd] = {6,3}, /* right */
96 enum mainstone_model_e { mainstone };
98 #define MAINSTONE_RAM 0x04000000
99 #define MAINSTONE_ROM 0x00800000
100 #define MAINSTONE_FLASH 0x02000000
102 static struct arm_boot_info mainstone_binfo = {
103 .loader_start = PXA2XX_SDRAM_BASE,
104 .ram_size = 0x04000000,
107 static void mainstone_common_init(MemoryRegion *address_space_mem,
108 MachineState *machine,
109 enum mainstone_model_e model, int arm_id)
111 uint32_t sector_len = 256 * 1024;
112 hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
113 PXA2xxState *mpu;
114 DeviceState *mst_irq;
115 DriveInfo *dinfo;
116 int i;
117 int be;
118 MemoryRegion *rom = g_new(MemoryRegion, 1);
119 const char *cpu_model = machine->cpu_model;
121 if (!cpu_model)
122 cpu_model = "pxa270-c5";
124 /* Setup CPU & memory */
125 mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
126 memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
127 &error_abort);
128 vmstate_register_ram_global(rom);
129 memory_region_set_readonly(rom, true);
130 memory_region_add_subregion(address_space_mem, 0, rom);
132 #ifdef TARGET_WORDS_BIGENDIAN
133 be = 1;
134 #else
135 be = 0;
136 #endif
137 /* There are two 32MiB flash devices on the board */
138 for (i = 0; i < 2; i ++) {
139 dinfo = drive_get(IF_PFLASH, 0, i);
140 if (!dinfo) {
141 if (qtest_enabled()) {
142 break;
144 fprintf(stderr, "Two flash images must be given with the "
145 "'pflash' parameter\n");
146 exit(1);
149 if (!pflash_cfi01_register(mainstone_flash_base[i], NULL,
150 i ? "mainstone.flash1" : "mainstone.flash0",
151 MAINSTONE_FLASH,
152 blk_by_legacy_dinfo(dinfo),
153 sector_len, MAINSTONE_FLASH / sector_len,
154 4, 0, 0, 0, 0, be)) {
155 fprintf(stderr, "qemu: Error registering flash memory.\n");
156 exit(1);
160 mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
161 qdev_get_gpio_in(mpu->gpio, 0));
163 /* setup keypad */
164 pxa27x_register_keypad(mpu->kp, map, 0xe0);
166 /* MMC/SD host */
167 pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
169 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
170 qdev_get_gpio_in(mst_irq, S0_IRQ),
171 qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
172 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
173 qdev_get_gpio_in(mst_irq, S1_IRQ),
174 qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
176 smc91c111_init(&nd_table[0], MST_ETH_PHYS,
177 qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
179 mainstone_binfo.kernel_filename = machine->kernel_filename;
180 mainstone_binfo.kernel_cmdline = machine->kernel_cmdline;
181 mainstone_binfo.initrd_filename = machine->initrd_filename;
182 mainstone_binfo.board_id = arm_id;
183 arm_load_kernel(mpu->cpu, &mainstone_binfo);
186 static void mainstone_init(MachineState *machine)
188 mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
191 static QEMUMachine mainstone2_machine = {
192 .name = "mainstone",
193 .desc = "Mainstone II (PXA27x)",
194 .init = mainstone_init,
197 static void mainstone_machine_init(void)
199 qemu_register_machine(&mainstone2_machine);
202 machine_init(mainstone_machine_init);