pc-bios/s390-ccw: Remove duplicate blk_factor adjustment
[qemu.git] / exec.c
blob96e3ac98e158061990bb91d7e5892973a10c1232
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #ifndef _WIN32
22 #endif
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "tcg.h"
28 #include "hw/qdev-core.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <fcntl.h>
53 #include <linux/falloc.h>
54 #endif
56 #endif
57 #include "exec/cpu-all.h"
58 #include "qemu/rcu_queue.h"
59 #include "qemu/main-loop.h"
60 #include "translate-all.h"
61 #include "sysemu/replay.h"
63 #include "exec/memory-internal.h"
64 #include "exec/ram_addr.h"
65 #include "exec/log.h"
67 #include "migration/vmstate.h"
69 #include "qemu/range.h"
70 #ifndef _WIN32
71 #include "qemu/mmap-alloc.h"
72 #endif
74 #include "monitor/monitor.h"
76 //#define DEBUG_SUBPAGE
78 #if !defined(CONFIG_USER_ONLY)
79 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
80 * are protected by the ramlist lock.
82 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
84 static MemoryRegion *system_memory;
85 static MemoryRegion *system_io;
87 AddressSpace address_space_io;
88 AddressSpace address_space_memory;
90 MemoryRegion io_mem_rom, io_mem_notdirty;
91 static MemoryRegion io_mem_unassigned;
93 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
94 #define RAM_PREALLOC (1 << 0)
96 /* RAM is mmap-ed with MAP_SHARED */
97 #define RAM_SHARED (1 << 1)
99 /* Only a portion of RAM (used_length) is actually used, and migrated.
100 * This used_length size can change across reboots.
102 #define RAM_RESIZEABLE (1 << 2)
104 #endif
106 #ifdef TARGET_PAGE_BITS_VARY
107 int target_page_bits;
108 bool target_page_bits_decided;
109 #endif
111 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
112 /* current CPU in the current thread. It is only valid inside
113 cpu_exec() */
114 __thread CPUState *current_cpu;
115 /* 0 = Do not count executed instructions.
116 1 = Precise instruction counting.
117 2 = Adaptive rate instruction counting. */
118 int use_icount;
120 bool set_preferred_target_page_bits(int bits)
122 /* The target page size is the lowest common denominator for all
123 * the CPUs in the system, so we can only make it smaller, never
124 * larger. And we can't make it smaller once we've committed to
125 * a particular size.
127 #ifdef TARGET_PAGE_BITS_VARY
128 assert(bits >= TARGET_PAGE_BITS_MIN);
129 if (target_page_bits == 0 || target_page_bits > bits) {
130 if (target_page_bits_decided) {
131 return false;
133 target_page_bits = bits;
135 #endif
136 return true;
139 #if !defined(CONFIG_USER_ONLY)
141 static void finalize_target_page_bits(void)
143 #ifdef TARGET_PAGE_BITS_VARY
144 if (target_page_bits == 0) {
145 target_page_bits = TARGET_PAGE_BITS_MIN;
147 target_page_bits_decided = true;
148 #endif
151 typedef struct PhysPageEntry PhysPageEntry;
153 struct PhysPageEntry {
154 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
155 uint32_t skip : 6;
156 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
157 uint32_t ptr : 26;
160 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
162 /* Size of the L2 (and L3, etc) page tables. */
163 #define ADDR_SPACE_BITS 64
165 #define P_L2_BITS 9
166 #define P_L2_SIZE (1 << P_L2_BITS)
168 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
170 typedef PhysPageEntry Node[P_L2_SIZE];
172 typedef struct PhysPageMap {
173 struct rcu_head rcu;
175 unsigned sections_nb;
176 unsigned sections_nb_alloc;
177 unsigned nodes_nb;
178 unsigned nodes_nb_alloc;
179 Node *nodes;
180 MemoryRegionSection *sections;
181 } PhysPageMap;
183 struct AddressSpaceDispatch {
184 struct rcu_head rcu;
186 MemoryRegionSection *mru_section;
187 /* This is a multi-level map on the physical address space.
188 * The bottom level has pointers to MemoryRegionSections.
190 PhysPageEntry phys_map;
191 PhysPageMap map;
192 AddressSpace *as;
195 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
196 typedef struct subpage_t {
197 MemoryRegion iomem;
198 AddressSpace *as;
199 hwaddr base;
200 uint16_t sub_section[];
201 } subpage_t;
203 #define PHYS_SECTION_UNASSIGNED 0
204 #define PHYS_SECTION_NOTDIRTY 1
205 #define PHYS_SECTION_ROM 2
206 #define PHYS_SECTION_WATCH 3
208 static void io_mem_init(void);
209 static void memory_map_init(void);
210 static void tcg_commit(MemoryListener *listener);
212 static MemoryRegion io_mem_watch;
215 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
216 * @cpu: the CPU whose AddressSpace this is
217 * @as: the AddressSpace itself
218 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
219 * @tcg_as_listener: listener for tracking changes to the AddressSpace
221 struct CPUAddressSpace {
222 CPUState *cpu;
223 AddressSpace *as;
224 struct AddressSpaceDispatch *memory_dispatch;
225 MemoryListener tcg_as_listener;
228 struct DirtyBitmapSnapshot {
229 ram_addr_t start;
230 ram_addr_t end;
231 unsigned long dirty[];
234 #endif
236 #if !defined(CONFIG_USER_ONLY)
238 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
240 static unsigned alloc_hint = 16;
241 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
242 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
243 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
244 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
245 alloc_hint = map->nodes_nb_alloc;
249 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
251 unsigned i;
252 uint32_t ret;
253 PhysPageEntry e;
254 PhysPageEntry *p;
256 ret = map->nodes_nb++;
257 p = map->nodes[ret];
258 assert(ret != PHYS_MAP_NODE_NIL);
259 assert(ret != map->nodes_nb_alloc);
261 e.skip = leaf ? 0 : 1;
262 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
263 for (i = 0; i < P_L2_SIZE; ++i) {
264 memcpy(&p[i], &e, sizeof(e));
266 return ret;
269 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
270 hwaddr *index, hwaddr *nb, uint16_t leaf,
271 int level)
273 PhysPageEntry *p;
274 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
276 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
277 lp->ptr = phys_map_node_alloc(map, level == 0);
279 p = map->nodes[lp->ptr];
280 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
282 while (*nb && lp < &p[P_L2_SIZE]) {
283 if ((*index & (step - 1)) == 0 && *nb >= step) {
284 lp->skip = 0;
285 lp->ptr = leaf;
286 *index += step;
287 *nb -= step;
288 } else {
289 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
291 ++lp;
295 static void phys_page_set(AddressSpaceDispatch *d,
296 hwaddr index, hwaddr nb,
297 uint16_t leaf)
299 /* Wildly overreserve - it doesn't matter much. */
300 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
302 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
305 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
306 * and update our entry so we can skip it and go directly to the destination.
308 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
310 unsigned valid_ptr = P_L2_SIZE;
311 int valid = 0;
312 PhysPageEntry *p;
313 int i;
315 if (lp->ptr == PHYS_MAP_NODE_NIL) {
316 return;
319 p = nodes[lp->ptr];
320 for (i = 0; i < P_L2_SIZE; i++) {
321 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
322 continue;
325 valid_ptr = i;
326 valid++;
327 if (p[i].skip) {
328 phys_page_compact(&p[i], nodes);
332 /* We can only compress if there's only one child. */
333 if (valid != 1) {
334 return;
337 assert(valid_ptr < P_L2_SIZE);
339 /* Don't compress if it won't fit in the # of bits we have. */
340 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
341 return;
344 lp->ptr = p[valid_ptr].ptr;
345 if (!p[valid_ptr].skip) {
346 /* If our only child is a leaf, make this a leaf. */
347 /* By design, we should have made this node a leaf to begin with so we
348 * should never reach here.
349 * But since it's so simple to handle this, let's do it just in case we
350 * change this rule.
352 lp->skip = 0;
353 } else {
354 lp->skip += p[valid_ptr].skip;
358 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
360 if (d->phys_map.skip) {
361 phys_page_compact(&d->phys_map, d->map.nodes);
365 static inline bool section_covers_addr(const MemoryRegionSection *section,
366 hwaddr addr)
368 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
369 * the section must cover the entire address space.
371 return int128_gethi(section->size) ||
372 range_covers_byte(section->offset_within_address_space,
373 int128_getlo(section->size), addr);
376 static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr,
377 Node *nodes, MemoryRegionSection *sections)
379 PhysPageEntry *p;
380 hwaddr index = addr >> TARGET_PAGE_BITS;
381 int i;
383 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
384 if (lp.ptr == PHYS_MAP_NODE_NIL) {
385 return &sections[PHYS_SECTION_UNASSIGNED];
387 p = nodes[lp.ptr];
388 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
391 if (section_covers_addr(&sections[lp.ptr], addr)) {
392 return &sections[lp.ptr];
393 } else {
394 return &sections[PHYS_SECTION_UNASSIGNED];
398 bool memory_region_is_unassigned(MemoryRegion *mr)
400 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
401 && mr != &io_mem_watch;
404 /* Called from RCU critical section */
405 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
406 hwaddr addr,
407 bool resolve_subpage)
409 MemoryRegionSection *section = atomic_read(&d->mru_section);
410 subpage_t *subpage;
411 bool update;
413 if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
414 section_covers_addr(section, addr)) {
415 update = false;
416 } else {
417 section = phys_page_find(d->phys_map, addr, d->map.nodes,
418 d->map.sections);
419 update = true;
421 if (resolve_subpage && section->mr->subpage) {
422 subpage = container_of(section->mr, subpage_t, iomem);
423 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
425 if (update) {
426 atomic_set(&d->mru_section, section);
428 return section;
431 /* Called from RCU critical section */
432 static MemoryRegionSection *
433 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
434 hwaddr *plen, bool resolve_subpage)
436 MemoryRegionSection *section;
437 MemoryRegion *mr;
438 Int128 diff;
440 section = address_space_lookup_region(d, addr, resolve_subpage);
441 /* Compute offset within MemoryRegionSection */
442 addr -= section->offset_within_address_space;
444 /* Compute offset within MemoryRegion */
445 *xlat = addr + section->offset_within_region;
447 mr = section->mr;
449 /* MMIO registers can be expected to perform full-width accesses based only
450 * on their address, without considering adjacent registers that could
451 * decode to completely different MemoryRegions. When such registers
452 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
453 * regions overlap wildly. For this reason we cannot clamp the accesses
454 * here.
456 * If the length is small (as is the case for address_space_ldl/stl),
457 * everything works fine. If the incoming length is large, however,
458 * the caller really has to do the clamping through memory_access_size.
460 if (memory_region_is_ram(mr)) {
461 diff = int128_sub(section->size, int128_make64(addr));
462 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
464 return section;
467 /* Called from RCU critical section */
468 static MemoryRegionSection address_space_do_translate(AddressSpace *as,
469 hwaddr addr,
470 hwaddr *xlat,
471 hwaddr *plen,
472 bool is_write,
473 bool is_mmio)
475 IOMMUTLBEntry iotlb;
476 MemoryRegionSection *section;
477 MemoryRegion *mr;
479 for (;;) {
480 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
481 section = address_space_translate_internal(d, addr, &addr, plen, is_mmio);
482 mr = section->mr;
484 if (!mr->iommu_ops) {
485 break;
488 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
489 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
490 | (addr & iotlb.addr_mask));
491 *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1);
492 if (!(iotlb.perm & (1 << is_write))) {
493 goto translate_fail;
496 as = iotlb.target_as;
499 *xlat = addr;
501 return *section;
503 translate_fail:
504 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
507 /* Called from RCU critical section */
508 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
509 bool is_write)
511 MemoryRegionSection section;
512 hwaddr xlat, plen;
514 /* Try to get maximum page mask during translation. */
515 plen = (hwaddr)-1;
517 /* This can never be MMIO. */
518 section = address_space_do_translate(as, addr, &xlat, &plen,
519 is_write, false);
521 /* Illegal translation */
522 if (section.mr == &io_mem_unassigned) {
523 goto iotlb_fail;
526 /* Convert memory region offset into address space offset */
527 xlat += section.offset_within_address_space -
528 section.offset_within_region;
530 if (plen == (hwaddr)-1) {
532 * We use default page size here. Logically it only happens
533 * for identity mappings.
535 plen = TARGET_PAGE_SIZE;
538 /* Convert to address mask */
539 plen -= 1;
541 return (IOMMUTLBEntry) {
542 .target_as = section.address_space,
543 .iova = addr & ~plen,
544 .translated_addr = xlat & ~plen,
545 .addr_mask = plen,
546 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
547 .perm = IOMMU_RW,
550 iotlb_fail:
551 return (IOMMUTLBEntry) {0};
554 /* Called from RCU critical section */
555 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
556 hwaddr *xlat, hwaddr *plen,
557 bool is_write)
559 MemoryRegion *mr;
560 MemoryRegionSection section;
562 /* This can be MMIO, so setup MMIO bit. */
563 section = address_space_do_translate(as, addr, xlat, plen, is_write, true);
564 mr = section.mr;
566 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
567 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
568 *plen = MIN(page, *plen);
571 return mr;
574 /* Called from RCU critical section */
575 MemoryRegionSection *
576 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
577 hwaddr *xlat, hwaddr *plen)
579 MemoryRegionSection *section;
580 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
582 section = address_space_translate_internal(d, addr, xlat, plen, false);
584 assert(!section->mr->iommu_ops);
585 return section;
587 #endif
589 #if !defined(CONFIG_USER_ONLY)
591 static int cpu_common_post_load(void *opaque, int version_id)
593 CPUState *cpu = opaque;
595 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
596 version_id is increased. */
597 cpu->interrupt_request &= ~0x01;
598 tlb_flush(cpu);
600 return 0;
603 static int cpu_common_pre_load(void *opaque)
605 CPUState *cpu = opaque;
607 cpu->exception_index = -1;
609 return 0;
612 static bool cpu_common_exception_index_needed(void *opaque)
614 CPUState *cpu = opaque;
616 return tcg_enabled() && cpu->exception_index != -1;
619 static const VMStateDescription vmstate_cpu_common_exception_index = {
620 .name = "cpu_common/exception_index",
621 .version_id = 1,
622 .minimum_version_id = 1,
623 .needed = cpu_common_exception_index_needed,
624 .fields = (VMStateField[]) {
625 VMSTATE_INT32(exception_index, CPUState),
626 VMSTATE_END_OF_LIST()
630 static bool cpu_common_crash_occurred_needed(void *opaque)
632 CPUState *cpu = opaque;
634 return cpu->crash_occurred;
637 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
638 .name = "cpu_common/crash_occurred",
639 .version_id = 1,
640 .minimum_version_id = 1,
641 .needed = cpu_common_crash_occurred_needed,
642 .fields = (VMStateField[]) {
643 VMSTATE_BOOL(crash_occurred, CPUState),
644 VMSTATE_END_OF_LIST()
648 const VMStateDescription vmstate_cpu_common = {
649 .name = "cpu_common",
650 .version_id = 1,
651 .minimum_version_id = 1,
652 .pre_load = cpu_common_pre_load,
653 .post_load = cpu_common_post_load,
654 .fields = (VMStateField[]) {
655 VMSTATE_UINT32(halted, CPUState),
656 VMSTATE_UINT32(interrupt_request, CPUState),
657 VMSTATE_END_OF_LIST()
659 .subsections = (const VMStateDescription*[]) {
660 &vmstate_cpu_common_exception_index,
661 &vmstate_cpu_common_crash_occurred,
662 NULL
666 #endif
668 CPUState *qemu_get_cpu(int index)
670 CPUState *cpu;
672 CPU_FOREACH(cpu) {
673 if (cpu->cpu_index == index) {
674 return cpu;
678 return NULL;
681 #if !defined(CONFIG_USER_ONLY)
682 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx)
684 CPUAddressSpace *newas;
686 /* Target code should have set num_ases before calling us */
687 assert(asidx < cpu->num_ases);
689 if (asidx == 0) {
690 /* address space 0 gets the convenience alias */
691 cpu->as = as;
694 /* KVM cannot currently support multiple address spaces. */
695 assert(asidx == 0 || !kvm_enabled());
697 if (!cpu->cpu_ases) {
698 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
701 newas = &cpu->cpu_ases[asidx];
702 newas->cpu = cpu;
703 newas->as = as;
704 if (tcg_enabled()) {
705 newas->tcg_as_listener.commit = tcg_commit;
706 memory_listener_register(&newas->tcg_as_listener, as);
710 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
712 /* Return the AddressSpace corresponding to the specified index */
713 return cpu->cpu_ases[asidx].as;
715 #endif
717 void cpu_exec_unrealizefn(CPUState *cpu)
719 CPUClass *cc = CPU_GET_CLASS(cpu);
721 cpu_list_remove(cpu);
723 if (cc->vmsd != NULL) {
724 vmstate_unregister(NULL, cc->vmsd, cpu);
726 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
727 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
731 void cpu_exec_initfn(CPUState *cpu)
733 cpu->as = NULL;
734 cpu->num_ases = 0;
736 #ifndef CONFIG_USER_ONLY
737 cpu->thread_id = qemu_get_thread_id();
739 /* This is a softmmu CPU object, so create a property for it
740 * so users can wire up its memory. (This can't go in qom/cpu.c
741 * because that file is compiled only once for both user-mode
742 * and system builds.) The default if no link is set up is to use
743 * the system address space.
745 object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION,
746 (Object **)&cpu->memory,
747 qdev_prop_allow_set_link_before_realize,
748 OBJ_PROP_LINK_UNREF_ON_RELEASE,
749 &error_abort);
750 cpu->memory = system_memory;
751 object_ref(OBJECT(cpu->memory));
752 #endif
755 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
757 CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
759 cpu_list_add(cpu);
761 #ifndef CONFIG_USER_ONLY
762 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
763 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
765 if (cc->vmsd != NULL) {
766 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
768 #endif
771 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
773 /* Flush the whole TB as this will not have race conditions
774 * even if we don't have proper locking yet.
775 * Ideally we would just invalidate the TBs for the
776 * specified PC.
778 tb_flush(cpu);
781 #if defined(CONFIG_USER_ONLY)
782 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
787 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
788 int flags)
790 return -ENOSYS;
793 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
797 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
798 int flags, CPUWatchpoint **watchpoint)
800 return -ENOSYS;
802 #else
803 /* Add a watchpoint. */
804 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
805 int flags, CPUWatchpoint **watchpoint)
807 CPUWatchpoint *wp;
809 /* forbid ranges which are empty or run off the end of the address space */
810 if (len == 0 || (addr + len - 1) < addr) {
811 error_report("tried to set invalid watchpoint at %"
812 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
813 return -EINVAL;
815 wp = g_malloc(sizeof(*wp));
817 wp->vaddr = addr;
818 wp->len = len;
819 wp->flags = flags;
821 /* keep all GDB-injected watchpoints in front */
822 if (flags & BP_GDB) {
823 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
824 } else {
825 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
828 tlb_flush_page(cpu, addr);
830 if (watchpoint)
831 *watchpoint = wp;
832 return 0;
835 /* Remove a specific watchpoint. */
836 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
837 int flags)
839 CPUWatchpoint *wp;
841 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
842 if (addr == wp->vaddr && len == wp->len
843 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
844 cpu_watchpoint_remove_by_ref(cpu, wp);
845 return 0;
848 return -ENOENT;
851 /* Remove a specific watchpoint by reference. */
852 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
854 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
856 tlb_flush_page(cpu, watchpoint->vaddr);
858 g_free(watchpoint);
861 /* Remove all matching watchpoints. */
862 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
864 CPUWatchpoint *wp, *next;
866 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
867 if (wp->flags & mask) {
868 cpu_watchpoint_remove_by_ref(cpu, wp);
873 /* Return true if this watchpoint address matches the specified
874 * access (ie the address range covered by the watchpoint overlaps
875 * partially or completely with the address range covered by the
876 * access).
878 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
879 vaddr addr,
880 vaddr len)
882 /* We know the lengths are non-zero, but a little caution is
883 * required to avoid errors in the case where the range ends
884 * exactly at the top of the address space and so addr + len
885 * wraps round to zero.
887 vaddr wpend = wp->vaddr + wp->len - 1;
888 vaddr addrend = addr + len - 1;
890 return !(addr > wpend || wp->vaddr > addrend);
893 #endif
895 /* Add a breakpoint. */
896 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
897 CPUBreakpoint **breakpoint)
899 CPUBreakpoint *bp;
901 bp = g_malloc(sizeof(*bp));
903 bp->pc = pc;
904 bp->flags = flags;
906 /* keep all GDB-injected breakpoints in front */
907 if (flags & BP_GDB) {
908 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
909 } else {
910 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
913 breakpoint_invalidate(cpu, pc);
915 if (breakpoint) {
916 *breakpoint = bp;
918 return 0;
921 /* Remove a specific breakpoint. */
922 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
924 CPUBreakpoint *bp;
926 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
927 if (bp->pc == pc && bp->flags == flags) {
928 cpu_breakpoint_remove_by_ref(cpu, bp);
929 return 0;
932 return -ENOENT;
935 /* Remove a specific breakpoint by reference. */
936 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
938 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
940 breakpoint_invalidate(cpu, breakpoint->pc);
942 g_free(breakpoint);
945 /* Remove all matching breakpoints. */
946 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
948 CPUBreakpoint *bp, *next;
950 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
951 if (bp->flags & mask) {
952 cpu_breakpoint_remove_by_ref(cpu, bp);
957 /* enable or disable single step mode. EXCP_DEBUG is returned by the
958 CPU loop after each instruction */
959 void cpu_single_step(CPUState *cpu, int enabled)
961 if (cpu->singlestep_enabled != enabled) {
962 cpu->singlestep_enabled = enabled;
963 if (kvm_enabled()) {
964 kvm_update_guest_debug(cpu, 0);
965 } else {
966 /* must flush all the translated code to avoid inconsistencies */
967 /* XXX: only flush what is necessary */
968 tb_flush(cpu);
973 void cpu_abort(CPUState *cpu, const char *fmt, ...)
975 va_list ap;
976 va_list ap2;
978 va_start(ap, fmt);
979 va_copy(ap2, ap);
980 fprintf(stderr, "qemu: fatal: ");
981 vfprintf(stderr, fmt, ap);
982 fprintf(stderr, "\n");
983 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
984 if (qemu_log_separate()) {
985 qemu_log_lock();
986 qemu_log("qemu: fatal: ");
987 qemu_log_vprintf(fmt, ap2);
988 qemu_log("\n");
989 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
990 qemu_log_flush();
991 qemu_log_unlock();
992 qemu_log_close();
994 va_end(ap2);
995 va_end(ap);
996 replay_finish();
997 #if defined(CONFIG_USER_ONLY)
999 struct sigaction act;
1000 sigfillset(&act.sa_mask);
1001 act.sa_handler = SIG_DFL;
1002 sigaction(SIGABRT, &act, NULL);
1004 #endif
1005 abort();
1008 #if !defined(CONFIG_USER_ONLY)
1009 /* Called from RCU critical section */
1010 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1012 RAMBlock *block;
1014 block = atomic_rcu_read(&ram_list.mru_block);
1015 if (block && addr - block->offset < block->max_length) {
1016 return block;
1018 RAMBLOCK_FOREACH(block) {
1019 if (addr - block->offset < block->max_length) {
1020 goto found;
1024 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1025 abort();
1027 found:
1028 /* It is safe to write mru_block outside the iothread lock. This
1029 * is what happens:
1031 * mru_block = xxx
1032 * rcu_read_unlock()
1033 * xxx removed from list
1034 * rcu_read_lock()
1035 * read mru_block
1036 * mru_block = NULL;
1037 * call_rcu(reclaim_ramblock, xxx);
1038 * rcu_read_unlock()
1040 * atomic_rcu_set is not needed here. The block was already published
1041 * when it was placed into the list. Here we're just making an extra
1042 * copy of the pointer.
1044 ram_list.mru_block = block;
1045 return block;
1048 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1050 CPUState *cpu;
1051 ram_addr_t start1;
1052 RAMBlock *block;
1053 ram_addr_t end;
1055 end = TARGET_PAGE_ALIGN(start + length);
1056 start &= TARGET_PAGE_MASK;
1058 rcu_read_lock();
1059 block = qemu_get_ram_block(start);
1060 assert(block == qemu_get_ram_block(end - 1));
1061 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1062 CPU_FOREACH(cpu) {
1063 tlb_reset_dirty(cpu, start1, length);
1065 rcu_read_unlock();
1068 /* Note: start and end must be within the same ram block. */
1069 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1070 ram_addr_t length,
1071 unsigned client)
1073 DirtyMemoryBlocks *blocks;
1074 unsigned long end, page;
1075 bool dirty = false;
1077 if (length == 0) {
1078 return false;
1081 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1082 page = start >> TARGET_PAGE_BITS;
1084 rcu_read_lock();
1086 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1088 while (page < end) {
1089 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1090 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1091 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1093 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1094 offset, num);
1095 page += num;
1098 rcu_read_unlock();
1100 if (dirty && tcg_enabled()) {
1101 tlb_reset_dirty_range_all(start, length);
1104 return dirty;
1107 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1108 (ram_addr_t start, ram_addr_t length, unsigned client)
1110 DirtyMemoryBlocks *blocks;
1111 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1112 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1113 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1114 DirtyBitmapSnapshot *snap;
1115 unsigned long page, end, dest;
1117 snap = g_malloc0(sizeof(*snap) +
1118 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1119 snap->start = first;
1120 snap->end = last;
1122 page = first >> TARGET_PAGE_BITS;
1123 end = last >> TARGET_PAGE_BITS;
1124 dest = 0;
1126 rcu_read_lock();
1128 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1130 while (page < end) {
1131 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1132 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1133 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1135 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1136 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1137 offset >>= BITS_PER_LEVEL;
1139 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1140 blocks->blocks[idx] + offset,
1141 num);
1142 page += num;
1143 dest += num >> BITS_PER_LEVEL;
1146 rcu_read_unlock();
1148 if (tcg_enabled()) {
1149 tlb_reset_dirty_range_all(start, length);
1152 return snap;
1155 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1156 ram_addr_t start,
1157 ram_addr_t length)
1159 unsigned long page, end;
1161 assert(start >= snap->start);
1162 assert(start + length <= snap->end);
1164 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1165 page = (start - snap->start) >> TARGET_PAGE_BITS;
1167 while (page < end) {
1168 if (test_bit(page, snap->dirty)) {
1169 return true;
1171 page++;
1173 return false;
1176 /* Called from RCU critical section */
1177 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1178 MemoryRegionSection *section,
1179 target_ulong vaddr,
1180 hwaddr paddr, hwaddr xlat,
1181 int prot,
1182 target_ulong *address)
1184 hwaddr iotlb;
1185 CPUWatchpoint *wp;
1187 if (memory_region_is_ram(section->mr)) {
1188 /* Normal RAM. */
1189 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1190 if (!section->readonly) {
1191 iotlb |= PHYS_SECTION_NOTDIRTY;
1192 } else {
1193 iotlb |= PHYS_SECTION_ROM;
1195 } else {
1196 AddressSpaceDispatch *d;
1198 d = atomic_rcu_read(&section->address_space->dispatch);
1199 iotlb = section - d->map.sections;
1200 iotlb += xlat;
1203 /* Make accesses to pages with watchpoints go via the
1204 watchpoint trap routines. */
1205 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1206 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1207 /* Avoid trapping reads of pages with a write breakpoint. */
1208 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1209 iotlb = PHYS_SECTION_WATCH + paddr;
1210 *address |= TLB_MMIO;
1211 break;
1216 return iotlb;
1218 #endif /* defined(CONFIG_USER_ONLY) */
1220 #if !defined(CONFIG_USER_ONLY)
1222 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1223 uint16_t section);
1224 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
1226 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1227 qemu_anon_ram_alloc;
1230 * Set a custom physical guest memory alloator.
1231 * Accelerators with unusual needs may need this. Hopefully, we can
1232 * get rid of it eventually.
1234 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1236 phys_mem_alloc = alloc;
1239 static uint16_t phys_section_add(PhysPageMap *map,
1240 MemoryRegionSection *section)
1242 /* The physical section number is ORed with a page-aligned
1243 * pointer to produce the iotlb entries. Thus it should
1244 * never overflow into the page-aligned value.
1246 assert(map->sections_nb < TARGET_PAGE_SIZE);
1248 if (map->sections_nb == map->sections_nb_alloc) {
1249 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1250 map->sections = g_renew(MemoryRegionSection, map->sections,
1251 map->sections_nb_alloc);
1253 map->sections[map->sections_nb] = *section;
1254 memory_region_ref(section->mr);
1255 return map->sections_nb++;
1258 static void phys_section_destroy(MemoryRegion *mr)
1260 bool have_sub_page = mr->subpage;
1262 memory_region_unref(mr);
1264 if (have_sub_page) {
1265 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1266 object_unref(OBJECT(&subpage->iomem));
1267 g_free(subpage);
1271 static void phys_sections_free(PhysPageMap *map)
1273 while (map->sections_nb > 0) {
1274 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1275 phys_section_destroy(section->mr);
1277 g_free(map->sections);
1278 g_free(map->nodes);
1281 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
1283 subpage_t *subpage;
1284 hwaddr base = section->offset_within_address_space
1285 & TARGET_PAGE_MASK;
1286 MemoryRegionSection *existing = phys_page_find(d->phys_map, base,
1287 d->map.nodes, d->map.sections);
1288 MemoryRegionSection subsection = {
1289 .offset_within_address_space = base,
1290 .size = int128_make64(TARGET_PAGE_SIZE),
1292 hwaddr start, end;
1294 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1296 if (!(existing->mr->subpage)) {
1297 subpage = subpage_init(d->as, base);
1298 subsection.address_space = d->as;
1299 subsection.mr = &subpage->iomem;
1300 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1301 phys_section_add(&d->map, &subsection));
1302 } else {
1303 subpage = container_of(existing->mr, subpage_t, iomem);
1305 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1306 end = start + int128_get64(section->size) - 1;
1307 subpage_register(subpage, start, end,
1308 phys_section_add(&d->map, section));
1312 static void register_multipage(AddressSpaceDispatch *d,
1313 MemoryRegionSection *section)
1315 hwaddr start_addr = section->offset_within_address_space;
1316 uint16_t section_index = phys_section_add(&d->map, section);
1317 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1318 TARGET_PAGE_BITS));
1320 assert(num_pages);
1321 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1324 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
1326 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1327 AddressSpaceDispatch *d = as->next_dispatch;
1328 MemoryRegionSection now = *section, remain = *section;
1329 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1331 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1332 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1333 - now.offset_within_address_space;
1335 now.size = int128_min(int128_make64(left), now.size);
1336 register_subpage(d, &now);
1337 } else {
1338 now.size = int128_zero();
1340 while (int128_ne(remain.size, now.size)) {
1341 remain.size = int128_sub(remain.size, now.size);
1342 remain.offset_within_address_space += int128_get64(now.size);
1343 remain.offset_within_region += int128_get64(now.size);
1344 now = remain;
1345 if (int128_lt(remain.size, page_size)) {
1346 register_subpage(d, &now);
1347 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1348 now.size = page_size;
1349 register_subpage(d, &now);
1350 } else {
1351 now.size = int128_and(now.size, int128_neg(page_size));
1352 register_multipage(d, &now);
1357 void qemu_flush_coalesced_mmio_buffer(void)
1359 if (kvm_enabled())
1360 kvm_flush_coalesced_mmio_buffer();
1363 void qemu_mutex_lock_ramlist(void)
1365 qemu_mutex_lock(&ram_list.mutex);
1368 void qemu_mutex_unlock_ramlist(void)
1370 qemu_mutex_unlock(&ram_list.mutex);
1373 void ram_block_dump(Monitor *mon)
1375 RAMBlock *block;
1376 char *psize;
1378 rcu_read_lock();
1379 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1380 "Block Name", "PSize", "Offset", "Used", "Total");
1381 RAMBLOCK_FOREACH(block) {
1382 psize = size_to_str(block->page_size);
1383 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1384 " 0x%016" PRIx64 "\n", block->idstr, psize,
1385 (uint64_t)block->offset,
1386 (uint64_t)block->used_length,
1387 (uint64_t)block->max_length);
1388 g_free(psize);
1390 rcu_read_unlock();
1393 #ifdef __linux__
1395 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1396 * may or may not name the same files / on the same filesystem now as
1397 * when we actually open and map them. Iterate over the file
1398 * descriptors instead, and use qemu_fd_getpagesize().
1400 static int find_max_supported_pagesize(Object *obj, void *opaque)
1402 char *mem_path;
1403 long *hpsize_min = opaque;
1405 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1406 mem_path = object_property_get_str(obj, "mem-path", NULL);
1407 if (mem_path) {
1408 long hpsize = qemu_mempath_getpagesize(mem_path);
1409 if (hpsize < *hpsize_min) {
1410 *hpsize_min = hpsize;
1412 } else {
1413 *hpsize_min = getpagesize();
1417 return 0;
1420 long qemu_getrampagesize(void)
1422 long hpsize = LONG_MAX;
1423 long mainrampagesize;
1424 Object *memdev_root;
1426 if (mem_path) {
1427 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1428 } else {
1429 mainrampagesize = getpagesize();
1432 /* it's possible we have memory-backend objects with
1433 * hugepage-backed RAM. these may get mapped into system
1434 * address space via -numa parameters or memory hotplug
1435 * hooks. we want to take these into account, but we
1436 * also want to make sure these supported hugepage
1437 * sizes are applicable across the entire range of memory
1438 * we may boot from, so we take the min across all
1439 * backends, and assume normal pages in cases where a
1440 * backend isn't backed by hugepages.
1442 memdev_root = object_resolve_path("/objects", NULL);
1443 if (memdev_root) {
1444 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1446 if (hpsize == LONG_MAX) {
1447 /* No additional memory regions found ==> Report main RAM page size */
1448 return mainrampagesize;
1451 /* If NUMA is disabled or the NUMA nodes are not backed with a
1452 * memory-backend, then there is at least one node using "normal" RAM,
1453 * so if its page size is smaller we have got to report that size instead.
1455 if (hpsize > mainrampagesize &&
1456 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1457 static bool warned;
1458 if (!warned) {
1459 error_report("Huge page support disabled (n/a for main memory).");
1460 warned = true;
1462 return mainrampagesize;
1465 return hpsize;
1467 #else
1468 long qemu_getrampagesize(void)
1470 return getpagesize();
1472 #endif
1474 #ifdef __linux__
1475 static int64_t get_file_size(int fd)
1477 int64_t size = lseek(fd, 0, SEEK_END);
1478 if (size < 0) {
1479 return -errno;
1481 return size;
1484 static void *file_ram_alloc(RAMBlock *block,
1485 ram_addr_t memory,
1486 const char *path,
1487 Error **errp)
1489 bool unlink_on_error = false;
1490 char *filename;
1491 char *sanitized_name;
1492 char *c;
1493 void *area = MAP_FAILED;
1494 int fd = -1;
1495 int64_t file_size;
1497 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1498 error_setg(errp,
1499 "host lacks kvm mmu notifiers, -mem-path unsupported");
1500 return NULL;
1503 for (;;) {
1504 fd = open(path, O_RDWR);
1505 if (fd >= 0) {
1506 /* @path names an existing file, use it */
1507 break;
1509 if (errno == ENOENT) {
1510 /* @path names a file that doesn't exist, create it */
1511 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1512 if (fd >= 0) {
1513 unlink_on_error = true;
1514 break;
1516 } else if (errno == EISDIR) {
1517 /* @path names a directory, create a file there */
1518 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1519 sanitized_name = g_strdup(memory_region_name(block->mr));
1520 for (c = sanitized_name; *c != '\0'; c++) {
1521 if (*c == '/') {
1522 *c = '_';
1526 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1527 sanitized_name);
1528 g_free(sanitized_name);
1530 fd = mkstemp(filename);
1531 if (fd >= 0) {
1532 unlink(filename);
1533 g_free(filename);
1534 break;
1536 g_free(filename);
1538 if (errno != EEXIST && errno != EINTR) {
1539 error_setg_errno(errp, errno,
1540 "can't open backing store %s for guest RAM",
1541 path);
1542 goto error;
1545 * Try again on EINTR and EEXIST. The latter happens when
1546 * something else creates the file between our two open().
1550 block->page_size = qemu_fd_getpagesize(fd);
1551 block->mr->align = block->page_size;
1552 #if defined(__s390x__)
1553 if (kvm_enabled()) {
1554 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1556 #endif
1558 file_size = get_file_size(fd);
1560 if (memory < block->page_size) {
1561 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1562 "or larger than page size 0x%zx",
1563 memory, block->page_size);
1564 goto error;
1567 if (file_size > 0 && file_size < memory) {
1568 error_setg(errp, "backing store %s size 0x%" PRIx64
1569 " does not match 'size' option 0x" RAM_ADDR_FMT,
1570 path, file_size, memory);
1571 goto error;
1574 memory = ROUND_UP(memory, block->page_size);
1577 * ftruncate is not supported by hugetlbfs in older
1578 * hosts, so don't bother bailing out on errors.
1579 * If anything goes wrong with it under other filesystems,
1580 * mmap will fail.
1582 * Do not truncate the non-empty backend file to avoid corrupting
1583 * the existing data in the file. Disabling shrinking is not
1584 * enough. For example, the current vNVDIMM implementation stores
1585 * the guest NVDIMM labels at the end of the backend file. If the
1586 * backend file is later extended, QEMU will not be able to find
1587 * those labels. Therefore, extending the non-empty backend file
1588 * is disabled as well.
1590 if (!file_size && ftruncate(fd, memory)) {
1591 perror("ftruncate");
1594 area = qemu_ram_mmap(fd, memory, block->mr->align,
1595 block->flags & RAM_SHARED);
1596 if (area == MAP_FAILED) {
1597 error_setg_errno(errp, errno,
1598 "unable to map backing store for guest RAM");
1599 goto error;
1602 if (mem_prealloc) {
1603 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1604 if (errp && *errp) {
1605 goto error;
1609 block->fd = fd;
1610 return area;
1612 error:
1613 if (area != MAP_FAILED) {
1614 qemu_ram_munmap(area, memory);
1616 if (unlink_on_error) {
1617 unlink(path);
1619 if (fd != -1) {
1620 close(fd);
1622 return NULL;
1624 #endif
1626 /* Called with the ramlist lock held. */
1627 static ram_addr_t find_ram_offset(ram_addr_t size)
1629 RAMBlock *block, *next_block;
1630 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1632 assert(size != 0); /* it would hand out same offset multiple times */
1634 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1635 return 0;
1638 RAMBLOCK_FOREACH(block) {
1639 ram_addr_t end, next = RAM_ADDR_MAX;
1641 end = block->offset + block->max_length;
1643 RAMBLOCK_FOREACH(next_block) {
1644 if (next_block->offset >= end) {
1645 next = MIN(next, next_block->offset);
1648 if (next - end >= size && next - end < mingap) {
1649 offset = end;
1650 mingap = next - end;
1654 if (offset == RAM_ADDR_MAX) {
1655 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1656 (uint64_t)size);
1657 abort();
1660 return offset;
1663 unsigned long last_ram_page(void)
1665 RAMBlock *block;
1666 ram_addr_t last = 0;
1668 rcu_read_lock();
1669 RAMBLOCK_FOREACH(block) {
1670 last = MAX(last, block->offset + block->max_length);
1672 rcu_read_unlock();
1673 return last >> TARGET_PAGE_BITS;
1676 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1678 int ret;
1680 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1681 if (!machine_dump_guest_core(current_machine)) {
1682 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1683 if (ret) {
1684 perror("qemu_madvise");
1685 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1686 "but dump_guest_core=off specified\n");
1691 const char *qemu_ram_get_idstr(RAMBlock *rb)
1693 return rb->idstr;
1696 bool qemu_ram_is_shared(RAMBlock *rb)
1698 return rb->flags & RAM_SHARED;
1701 /* Called with iothread lock held. */
1702 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1704 RAMBlock *block;
1706 assert(new_block);
1707 assert(!new_block->idstr[0]);
1709 if (dev) {
1710 char *id = qdev_get_dev_path(dev);
1711 if (id) {
1712 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1713 g_free(id);
1716 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1718 rcu_read_lock();
1719 RAMBLOCK_FOREACH(block) {
1720 if (block != new_block &&
1721 !strcmp(block->idstr, new_block->idstr)) {
1722 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1723 new_block->idstr);
1724 abort();
1727 rcu_read_unlock();
1730 /* Called with iothread lock held. */
1731 void qemu_ram_unset_idstr(RAMBlock *block)
1733 /* FIXME: arch_init.c assumes that this is not called throughout
1734 * migration. Ignore the problem since hot-unplug during migration
1735 * does not work anyway.
1737 if (block) {
1738 memset(block->idstr, 0, sizeof(block->idstr));
1742 size_t qemu_ram_pagesize(RAMBlock *rb)
1744 return rb->page_size;
1747 /* Returns the largest size of page in use */
1748 size_t qemu_ram_pagesize_largest(void)
1750 RAMBlock *block;
1751 size_t largest = 0;
1753 RAMBLOCK_FOREACH(block) {
1754 largest = MAX(largest, qemu_ram_pagesize(block));
1757 return largest;
1760 static int memory_try_enable_merging(void *addr, size_t len)
1762 if (!machine_mem_merge(current_machine)) {
1763 /* disabled by the user */
1764 return 0;
1767 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1770 /* Only legal before guest might have detected the memory size: e.g. on
1771 * incoming migration, or right after reset.
1773 * As memory core doesn't know how is memory accessed, it is up to
1774 * resize callback to update device state and/or add assertions to detect
1775 * misuse, if necessary.
1777 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1779 assert(block);
1781 newsize = HOST_PAGE_ALIGN(newsize);
1783 if (block->used_length == newsize) {
1784 return 0;
1787 if (!(block->flags & RAM_RESIZEABLE)) {
1788 error_setg_errno(errp, EINVAL,
1789 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1790 " in != 0x" RAM_ADDR_FMT, block->idstr,
1791 newsize, block->used_length);
1792 return -EINVAL;
1795 if (block->max_length < newsize) {
1796 error_setg_errno(errp, EINVAL,
1797 "Length too large: %s: 0x" RAM_ADDR_FMT
1798 " > 0x" RAM_ADDR_FMT, block->idstr,
1799 newsize, block->max_length);
1800 return -EINVAL;
1803 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1804 block->used_length = newsize;
1805 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1806 DIRTY_CLIENTS_ALL);
1807 memory_region_set_size(block->mr, newsize);
1808 if (block->resized) {
1809 block->resized(block->idstr, newsize, block->host);
1811 return 0;
1814 /* Called with ram_list.mutex held */
1815 static void dirty_memory_extend(ram_addr_t old_ram_size,
1816 ram_addr_t new_ram_size)
1818 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1819 DIRTY_MEMORY_BLOCK_SIZE);
1820 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1821 DIRTY_MEMORY_BLOCK_SIZE);
1822 int i;
1824 /* Only need to extend if block count increased */
1825 if (new_num_blocks <= old_num_blocks) {
1826 return;
1829 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1830 DirtyMemoryBlocks *old_blocks;
1831 DirtyMemoryBlocks *new_blocks;
1832 int j;
1834 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1835 new_blocks = g_malloc(sizeof(*new_blocks) +
1836 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1838 if (old_num_blocks) {
1839 memcpy(new_blocks->blocks, old_blocks->blocks,
1840 old_num_blocks * sizeof(old_blocks->blocks[0]));
1843 for (j = old_num_blocks; j < new_num_blocks; j++) {
1844 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1847 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1849 if (old_blocks) {
1850 g_free_rcu(old_blocks, rcu);
1855 static void ram_block_add(RAMBlock *new_block, Error **errp)
1857 RAMBlock *block;
1858 RAMBlock *last_block = NULL;
1859 ram_addr_t old_ram_size, new_ram_size;
1860 Error *err = NULL;
1862 old_ram_size = last_ram_page();
1864 qemu_mutex_lock_ramlist();
1865 new_block->offset = find_ram_offset(new_block->max_length);
1867 if (!new_block->host) {
1868 if (xen_enabled()) {
1869 xen_ram_alloc(new_block->offset, new_block->max_length,
1870 new_block->mr, &err);
1871 if (err) {
1872 error_propagate(errp, err);
1873 qemu_mutex_unlock_ramlist();
1874 return;
1876 } else {
1877 new_block->host = phys_mem_alloc(new_block->max_length,
1878 &new_block->mr->align);
1879 if (!new_block->host) {
1880 error_setg_errno(errp, errno,
1881 "cannot set up guest memory '%s'",
1882 memory_region_name(new_block->mr));
1883 qemu_mutex_unlock_ramlist();
1884 return;
1886 memory_try_enable_merging(new_block->host, new_block->max_length);
1890 new_ram_size = MAX(old_ram_size,
1891 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1892 if (new_ram_size > old_ram_size) {
1893 dirty_memory_extend(old_ram_size, new_ram_size);
1895 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1896 * QLIST (which has an RCU-friendly variant) does not have insertion at
1897 * tail, so save the last element in last_block.
1899 RAMBLOCK_FOREACH(block) {
1900 last_block = block;
1901 if (block->max_length < new_block->max_length) {
1902 break;
1905 if (block) {
1906 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1907 } else if (last_block) {
1908 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1909 } else { /* list is empty */
1910 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1912 ram_list.mru_block = NULL;
1914 /* Write list before version */
1915 smp_wmb();
1916 ram_list.version++;
1917 qemu_mutex_unlock_ramlist();
1919 cpu_physical_memory_set_dirty_range(new_block->offset,
1920 new_block->used_length,
1921 DIRTY_CLIENTS_ALL);
1923 if (new_block->host) {
1924 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1925 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1926 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1927 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1928 ram_block_notify_add(new_block->host, new_block->max_length);
1932 #ifdef __linux__
1933 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1934 bool share, const char *mem_path,
1935 Error **errp)
1937 RAMBlock *new_block;
1938 Error *local_err = NULL;
1940 if (xen_enabled()) {
1941 error_setg(errp, "-mem-path not supported with Xen");
1942 return NULL;
1945 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1947 * file_ram_alloc() needs to allocate just like
1948 * phys_mem_alloc, but we haven't bothered to provide
1949 * a hook there.
1951 error_setg(errp,
1952 "-mem-path not supported with this accelerator");
1953 return NULL;
1956 size = HOST_PAGE_ALIGN(size);
1957 new_block = g_malloc0(sizeof(*new_block));
1958 new_block->mr = mr;
1959 new_block->used_length = size;
1960 new_block->max_length = size;
1961 new_block->flags = share ? RAM_SHARED : 0;
1962 new_block->host = file_ram_alloc(new_block, size,
1963 mem_path, errp);
1964 if (!new_block->host) {
1965 g_free(new_block);
1966 return NULL;
1969 ram_block_add(new_block, &local_err);
1970 if (local_err) {
1971 g_free(new_block);
1972 error_propagate(errp, local_err);
1973 return NULL;
1975 return new_block;
1977 #endif
1979 static
1980 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
1981 void (*resized)(const char*,
1982 uint64_t length,
1983 void *host),
1984 void *host, bool resizeable,
1985 MemoryRegion *mr, Error **errp)
1987 RAMBlock *new_block;
1988 Error *local_err = NULL;
1990 size = HOST_PAGE_ALIGN(size);
1991 max_size = HOST_PAGE_ALIGN(max_size);
1992 new_block = g_malloc0(sizeof(*new_block));
1993 new_block->mr = mr;
1994 new_block->resized = resized;
1995 new_block->used_length = size;
1996 new_block->max_length = max_size;
1997 assert(max_size >= size);
1998 new_block->fd = -1;
1999 new_block->page_size = getpagesize();
2000 new_block->host = host;
2001 if (host) {
2002 new_block->flags |= RAM_PREALLOC;
2004 if (resizeable) {
2005 new_block->flags |= RAM_RESIZEABLE;
2007 ram_block_add(new_block, &local_err);
2008 if (local_err) {
2009 g_free(new_block);
2010 error_propagate(errp, local_err);
2011 return NULL;
2013 return new_block;
2016 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2017 MemoryRegion *mr, Error **errp)
2019 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
2022 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
2024 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
2027 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2028 void (*resized)(const char*,
2029 uint64_t length,
2030 void *host),
2031 MemoryRegion *mr, Error **errp)
2033 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
2036 static void reclaim_ramblock(RAMBlock *block)
2038 if (block->flags & RAM_PREALLOC) {
2040 } else if (xen_enabled()) {
2041 xen_invalidate_map_cache_entry(block->host);
2042 #ifndef _WIN32
2043 } else if (block->fd >= 0) {
2044 qemu_ram_munmap(block->host, block->max_length);
2045 close(block->fd);
2046 #endif
2047 } else {
2048 qemu_anon_ram_free(block->host, block->max_length);
2050 g_free(block);
2053 void qemu_ram_free(RAMBlock *block)
2055 if (!block) {
2056 return;
2059 if (block->host) {
2060 ram_block_notify_remove(block->host, block->max_length);
2063 qemu_mutex_lock_ramlist();
2064 QLIST_REMOVE_RCU(block, next);
2065 ram_list.mru_block = NULL;
2066 /* Write list before version */
2067 smp_wmb();
2068 ram_list.version++;
2069 call_rcu(block, reclaim_ramblock, rcu);
2070 qemu_mutex_unlock_ramlist();
2073 #ifndef _WIN32
2074 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2076 RAMBlock *block;
2077 ram_addr_t offset;
2078 int flags;
2079 void *area, *vaddr;
2081 RAMBLOCK_FOREACH(block) {
2082 offset = addr - block->offset;
2083 if (offset < block->max_length) {
2084 vaddr = ramblock_ptr(block, offset);
2085 if (block->flags & RAM_PREALLOC) {
2087 } else if (xen_enabled()) {
2088 abort();
2089 } else {
2090 flags = MAP_FIXED;
2091 if (block->fd >= 0) {
2092 flags |= (block->flags & RAM_SHARED ?
2093 MAP_SHARED : MAP_PRIVATE);
2094 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2095 flags, block->fd, offset);
2096 } else {
2098 * Remap needs to match alloc. Accelerators that
2099 * set phys_mem_alloc never remap. If they did,
2100 * we'd need a remap hook here.
2102 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2104 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2105 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2106 flags, -1, 0);
2108 if (area != vaddr) {
2109 fprintf(stderr, "Could not remap addr: "
2110 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
2111 length, addr);
2112 exit(1);
2114 memory_try_enable_merging(vaddr, length);
2115 qemu_ram_setup_dump(vaddr, length);
2120 #endif /* !_WIN32 */
2122 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2123 * This should not be used for general purpose DMA. Use address_space_map
2124 * or address_space_rw instead. For local memory (e.g. video ram) that the
2125 * device owns, use memory_region_get_ram_ptr.
2127 * Called within RCU critical section.
2129 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2131 RAMBlock *block = ram_block;
2133 if (block == NULL) {
2134 block = qemu_get_ram_block(addr);
2135 addr -= block->offset;
2138 if (xen_enabled() && block->host == NULL) {
2139 /* We need to check if the requested address is in the RAM
2140 * because we don't want to map the entire memory in QEMU.
2141 * In that case just map until the end of the page.
2143 if (block->offset == 0) {
2144 return xen_map_cache(addr, 0, 0, false);
2147 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2149 return ramblock_ptr(block, addr);
2152 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2153 * but takes a size argument.
2155 * Called within RCU critical section.
2157 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2158 hwaddr *size)
2160 RAMBlock *block = ram_block;
2161 if (*size == 0) {
2162 return NULL;
2165 if (block == NULL) {
2166 block = qemu_get_ram_block(addr);
2167 addr -= block->offset;
2169 *size = MIN(*size, block->max_length - addr);
2171 if (xen_enabled() && block->host == NULL) {
2172 /* We need to check if the requested address is in the RAM
2173 * because we don't want to map the entire memory in QEMU.
2174 * In that case just map the requested area.
2176 if (block->offset == 0) {
2177 return xen_map_cache(addr, *size, 1, true);
2180 block->host = xen_map_cache(block->offset, block->max_length, 1, true);
2183 return ramblock_ptr(block, addr);
2187 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2188 * in that RAMBlock.
2190 * ptr: Host pointer to look up
2191 * round_offset: If true round the result offset down to a page boundary
2192 * *ram_addr: set to result ram_addr
2193 * *offset: set to result offset within the RAMBlock
2195 * Returns: RAMBlock (or NULL if not found)
2197 * By the time this function returns, the returned pointer is not protected
2198 * by RCU anymore. If the caller is not within an RCU critical section and
2199 * does not hold the iothread lock, it must have other means of protecting the
2200 * pointer, such as a reference to the region that includes the incoming
2201 * ram_addr_t.
2203 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2204 ram_addr_t *offset)
2206 RAMBlock *block;
2207 uint8_t *host = ptr;
2209 if (xen_enabled()) {
2210 ram_addr_t ram_addr;
2211 rcu_read_lock();
2212 ram_addr = xen_ram_addr_from_mapcache(ptr);
2213 block = qemu_get_ram_block(ram_addr);
2214 if (block) {
2215 *offset = ram_addr - block->offset;
2217 rcu_read_unlock();
2218 return block;
2221 rcu_read_lock();
2222 block = atomic_rcu_read(&ram_list.mru_block);
2223 if (block && block->host && host - block->host < block->max_length) {
2224 goto found;
2227 RAMBLOCK_FOREACH(block) {
2228 /* This case append when the block is not mapped. */
2229 if (block->host == NULL) {
2230 continue;
2232 if (host - block->host < block->max_length) {
2233 goto found;
2237 rcu_read_unlock();
2238 return NULL;
2240 found:
2241 *offset = (host - block->host);
2242 if (round_offset) {
2243 *offset &= TARGET_PAGE_MASK;
2245 rcu_read_unlock();
2246 return block;
2250 * Finds the named RAMBlock
2252 * name: The name of RAMBlock to find
2254 * Returns: RAMBlock (or NULL if not found)
2256 RAMBlock *qemu_ram_block_by_name(const char *name)
2258 RAMBlock *block;
2260 RAMBLOCK_FOREACH(block) {
2261 if (!strcmp(name, block->idstr)) {
2262 return block;
2266 return NULL;
2269 /* Some of the softmmu routines need to translate from a host pointer
2270 (typically a TLB entry) back to a ram offset. */
2271 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2273 RAMBlock *block;
2274 ram_addr_t offset;
2276 block = qemu_ram_block_from_host(ptr, false, &offset);
2277 if (!block) {
2278 return RAM_ADDR_INVALID;
2281 return block->offset + offset;
2284 /* Called within RCU critical section. */
2285 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2286 uint64_t val, unsigned size)
2288 bool locked = false;
2290 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2291 locked = true;
2292 tb_lock();
2293 tb_invalidate_phys_page_fast(ram_addr, size);
2295 switch (size) {
2296 case 1:
2297 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2298 break;
2299 case 2:
2300 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2301 break;
2302 case 4:
2303 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2304 break;
2305 default:
2306 abort();
2309 if (locked) {
2310 tb_unlock();
2313 /* Set both VGA and migration bits for simplicity and to remove
2314 * the notdirty callback faster.
2316 cpu_physical_memory_set_dirty_range(ram_addr, size,
2317 DIRTY_CLIENTS_NOCODE);
2318 /* we remove the notdirty callback only if the code has been
2319 flushed */
2320 if (!cpu_physical_memory_is_clean(ram_addr)) {
2321 tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr);
2325 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2326 unsigned size, bool is_write)
2328 return is_write;
2331 static const MemoryRegionOps notdirty_mem_ops = {
2332 .write = notdirty_mem_write,
2333 .valid.accepts = notdirty_mem_accepts,
2334 .endianness = DEVICE_NATIVE_ENDIAN,
2337 /* Generate a debug exception if a watchpoint has been hit. */
2338 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2340 CPUState *cpu = current_cpu;
2341 CPUClass *cc = CPU_GET_CLASS(cpu);
2342 CPUArchState *env = cpu->env_ptr;
2343 target_ulong pc, cs_base;
2344 target_ulong vaddr;
2345 CPUWatchpoint *wp;
2346 uint32_t cpu_flags;
2348 if (cpu->watchpoint_hit) {
2349 /* We re-entered the check after replacing the TB. Now raise
2350 * the debug interrupt so that is will trigger after the
2351 * current instruction. */
2352 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2353 return;
2355 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2356 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2357 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2358 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2359 && (wp->flags & flags)) {
2360 if (flags == BP_MEM_READ) {
2361 wp->flags |= BP_WATCHPOINT_HIT_READ;
2362 } else {
2363 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2365 wp->hitaddr = vaddr;
2366 wp->hitattrs = attrs;
2367 if (!cpu->watchpoint_hit) {
2368 if (wp->flags & BP_CPU &&
2369 !cc->debug_check_watchpoint(cpu, wp)) {
2370 wp->flags &= ~BP_WATCHPOINT_HIT;
2371 continue;
2373 cpu->watchpoint_hit = wp;
2375 /* Both tb_lock and iothread_mutex will be reset when
2376 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2377 * back into the cpu_exec main loop.
2379 tb_lock();
2380 tb_check_watchpoint(cpu);
2381 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2382 cpu->exception_index = EXCP_DEBUG;
2383 cpu_loop_exit(cpu);
2384 } else {
2385 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2386 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
2387 cpu_loop_exit_noexc(cpu);
2390 } else {
2391 wp->flags &= ~BP_WATCHPOINT_HIT;
2396 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2397 so these check for a hit then pass through to the normal out-of-line
2398 phys routines. */
2399 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2400 unsigned size, MemTxAttrs attrs)
2402 MemTxResult res;
2403 uint64_t data;
2404 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2405 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2407 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2408 switch (size) {
2409 case 1:
2410 data = address_space_ldub(as, addr, attrs, &res);
2411 break;
2412 case 2:
2413 data = address_space_lduw(as, addr, attrs, &res);
2414 break;
2415 case 4:
2416 data = address_space_ldl(as, addr, attrs, &res);
2417 break;
2418 default: abort();
2420 *pdata = data;
2421 return res;
2424 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2425 uint64_t val, unsigned size,
2426 MemTxAttrs attrs)
2428 MemTxResult res;
2429 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2430 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2432 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2433 switch (size) {
2434 case 1:
2435 address_space_stb(as, addr, val, attrs, &res);
2436 break;
2437 case 2:
2438 address_space_stw(as, addr, val, attrs, &res);
2439 break;
2440 case 4:
2441 address_space_stl(as, addr, val, attrs, &res);
2442 break;
2443 default: abort();
2445 return res;
2448 static const MemoryRegionOps watch_mem_ops = {
2449 .read_with_attrs = watch_mem_read,
2450 .write_with_attrs = watch_mem_write,
2451 .endianness = DEVICE_NATIVE_ENDIAN,
2454 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2455 unsigned len, MemTxAttrs attrs)
2457 subpage_t *subpage = opaque;
2458 uint8_t buf[8];
2459 MemTxResult res;
2461 #if defined(DEBUG_SUBPAGE)
2462 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2463 subpage, len, addr);
2464 #endif
2465 res = address_space_read(subpage->as, addr + subpage->base,
2466 attrs, buf, len);
2467 if (res) {
2468 return res;
2470 switch (len) {
2471 case 1:
2472 *data = ldub_p(buf);
2473 return MEMTX_OK;
2474 case 2:
2475 *data = lduw_p(buf);
2476 return MEMTX_OK;
2477 case 4:
2478 *data = ldl_p(buf);
2479 return MEMTX_OK;
2480 case 8:
2481 *data = ldq_p(buf);
2482 return MEMTX_OK;
2483 default:
2484 abort();
2488 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2489 uint64_t value, unsigned len, MemTxAttrs attrs)
2491 subpage_t *subpage = opaque;
2492 uint8_t buf[8];
2494 #if defined(DEBUG_SUBPAGE)
2495 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2496 " value %"PRIx64"\n",
2497 __func__, subpage, len, addr, value);
2498 #endif
2499 switch (len) {
2500 case 1:
2501 stb_p(buf, value);
2502 break;
2503 case 2:
2504 stw_p(buf, value);
2505 break;
2506 case 4:
2507 stl_p(buf, value);
2508 break;
2509 case 8:
2510 stq_p(buf, value);
2511 break;
2512 default:
2513 abort();
2515 return address_space_write(subpage->as, addr + subpage->base,
2516 attrs, buf, len);
2519 static bool subpage_accepts(void *opaque, hwaddr addr,
2520 unsigned len, bool is_write)
2522 subpage_t *subpage = opaque;
2523 #if defined(DEBUG_SUBPAGE)
2524 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2525 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2526 #endif
2528 return address_space_access_valid(subpage->as, addr + subpage->base,
2529 len, is_write);
2532 static const MemoryRegionOps subpage_ops = {
2533 .read_with_attrs = subpage_read,
2534 .write_with_attrs = subpage_write,
2535 .impl.min_access_size = 1,
2536 .impl.max_access_size = 8,
2537 .valid.min_access_size = 1,
2538 .valid.max_access_size = 8,
2539 .valid.accepts = subpage_accepts,
2540 .endianness = DEVICE_NATIVE_ENDIAN,
2543 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2544 uint16_t section)
2546 int idx, eidx;
2548 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2549 return -1;
2550 idx = SUBPAGE_IDX(start);
2551 eidx = SUBPAGE_IDX(end);
2552 #if defined(DEBUG_SUBPAGE)
2553 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2554 __func__, mmio, start, end, idx, eidx, section);
2555 #endif
2556 for (; idx <= eidx; idx++) {
2557 mmio->sub_section[idx] = section;
2560 return 0;
2563 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
2565 subpage_t *mmio;
2567 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2568 mmio->as = as;
2569 mmio->base = base;
2570 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2571 NULL, TARGET_PAGE_SIZE);
2572 mmio->iomem.subpage = true;
2573 #if defined(DEBUG_SUBPAGE)
2574 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2575 mmio, base, TARGET_PAGE_SIZE);
2576 #endif
2577 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2579 return mmio;
2582 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
2583 MemoryRegion *mr)
2585 assert(as);
2586 MemoryRegionSection section = {
2587 .address_space = as,
2588 .mr = mr,
2589 .offset_within_address_space = 0,
2590 .offset_within_region = 0,
2591 .size = int128_2_64(),
2594 return phys_section_add(map, &section);
2597 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2599 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2600 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2601 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2602 MemoryRegionSection *sections = d->map.sections;
2604 return sections[index & ~TARGET_PAGE_MASK].mr;
2607 static void io_mem_init(void)
2609 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
2610 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2611 NULL, UINT64_MAX);
2613 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2614 * which can be called without the iothread mutex.
2616 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2617 NULL, UINT64_MAX);
2618 memory_region_clear_global_locking(&io_mem_notdirty);
2620 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2621 NULL, UINT64_MAX);
2624 static void mem_begin(MemoryListener *listener)
2626 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2627 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2628 uint16_t n;
2630 n = dummy_section(&d->map, as, &io_mem_unassigned);
2631 assert(n == PHYS_SECTION_UNASSIGNED);
2632 n = dummy_section(&d->map, as, &io_mem_notdirty);
2633 assert(n == PHYS_SECTION_NOTDIRTY);
2634 n = dummy_section(&d->map, as, &io_mem_rom);
2635 assert(n == PHYS_SECTION_ROM);
2636 n = dummy_section(&d->map, as, &io_mem_watch);
2637 assert(n == PHYS_SECTION_WATCH);
2639 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2640 d->as = as;
2641 as->next_dispatch = d;
2644 static void address_space_dispatch_free(AddressSpaceDispatch *d)
2646 phys_sections_free(&d->map);
2647 g_free(d);
2650 static void mem_commit(MemoryListener *listener)
2652 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2653 AddressSpaceDispatch *cur = as->dispatch;
2654 AddressSpaceDispatch *next = as->next_dispatch;
2656 phys_page_compact_all(next, next->map.nodes_nb);
2658 atomic_rcu_set(&as->dispatch, next);
2659 if (cur) {
2660 call_rcu(cur, address_space_dispatch_free, rcu);
2664 static void tcg_commit(MemoryListener *listener)
2666 CPUAddressSpace *cpuas;
2667 AddressSpaceDispatch *d;
2669 /* since each CPU stores ram addresses in its TLB cache, we must
2670 reset the modified entries */
2671 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2672 cpu_reloading_memory_map();
2673 /* The CPU and TLB are protected by the iothread lock.
2674 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2675 * may have split the RCU critical section.
2677 d = atomic_rcu_read(&cpuas->as->dispatch);
2678 atomic_rcu_set(&cpuas->memory_dispatch, d);
2679 tlb_flush(cpuas->cpu);
2682 void address_space_init_dispatch(AddressSpace *as)
2684 as->dispatch = NULL;
2685 as->dispatch_listener = (MemoryListener) {
2686 .begin = mem_begin,
2687 .commit = mem_commit,
2688 .region_add = mem_add,
2689 .region_nop = mem_add,
2690 .priority = 0,
2692 memory_listener_register(&as->dispatch_listener, as);
2695 void address_space_unregister(AddressSpace *as)
2697 memory_listener_unregister(&as->dispatch_listener);
2700 void address_space_destroy_dispatch(AddressSpace *as)
2702 AddressSpaceDispatch *d = as->dispatch;
2704 atomic_rcu_set(&as->dispatch, NULL);
2705 if (d) {
2706 call_rcu(d, address_space_dispatch_free, rcu);
2710 static void memory_map_init(void)
2712 system_memory = g_malloc(sizeof(*system_memory));
2714 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2715 address_space_init(&address_space_memory, system_memory, "memory");
2717 system_io = g_malloc(sizeof(*system_io));
2718 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2719 65536);
2720 address_space_init(&address_space_io, system_io, "I/O");
2723 MemoryRegion *get_system_memory(void)
2725 return system_memory;
2728 MemoryRegion *get_system_io(void)
2730 return system_io;
2733 #endif /* !defined(CONFIG_USER_ONLY) */
2735 /* physical memory access (slow version, mainly for debug) */
2736 #if defined(CONFIG_USER_ONLY)
2737 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2738 uint8_t *buf, int len, int is_write)
2740 int l, flags;
2741 target_ulong page;
2742 void * p;
2744 while (len > 0) {
2745 page = addr & TARGET_PAGE_MASK;
2746 l = (page + TARGET_PAGE_SIZE) - addr;
2747 if (l > len)
2748 l = len;
2749 flags = page_get_flags(page);
2750 if (!(flags & PAGE_VALID))
2751 return -1;
2752 if (is_write) {
2753 if (!(flags & PAGE_WRITE))
2754 return -1;
2755 /* XXX: this code should not depend on lock_user */
2756 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2757 return -1;
2758 memcpy(p, buf, l);
2759 unlock_user(p, addr, l);
2760 } else {
2761 if (!(flags & PAGE_READ))
2762 return -1;
2763 /* XXX: this code should not depend on lock_user */
2764 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2765 return -1;
2766 memcpy(buf, p, l);
2767 unlock_user(p, addr, 0);
2769 len -= l;
2770 buf += l;
2771 addr += l;
2773 return 0;
2776 #else
2778 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2779 hwaddr length)
2781 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2782 addr += memory_region_get_ram_addr(mr);
2784 /* No early return if dirty_log_mask is or becomes 0, because
2785 * cpu_physical_memory_set_dirty_range will still call
2786 * xen_modified_memory.
2788 if (dirty_log_mask) {
2789 dirty_log_mask =
2790 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2792 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2793 tb_lock();
2794 tb_invalidate_phys_range(addr, addr + length);
2795 tb_unlock();
2796 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2798 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2801 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2803 unsigned access_size_max = mr->ops->valid.max_access_size;
2805 /* Regions are assumed to support 1-4 byte accesses unless
2806 otherwise specified. */
2807 if (access_size_max == 0) {
2808 access_size_max = 4;
2811 /* Bound the maximum access by the alignment of the address. */
2812 if (!mr->ops->impl.unaligned) {
2813 unsigned align_size_max = addr & -addr;
2814 if (align_size_max != 0 && align_size_max < access_size_max) {
2815 access_size_max = align_size_max;
2819 /* Don't attempt accesses larger than the maximum. */
2820 if (l > access_size_max) {
2821 l = access_size_max;
2823 l = pow2floor(l);
2825 return l;
2828 static bool prepare_mmio_access(MemoryRegion *mr)
2830 bool unlocked = !qemu_mutex_iothread_locked();
2831 bool release_lock = false;
2833 if (unlocked && mr->global_locking) {
2834 qemu_mutex_lock_iothread();
2835 unlocked = false;
2836 release_lock = true;
2838 if (mr->flush_coalesced_mmio) {
2839 if (unlocked) {
2840 qemu_mutex_lock_iothread();
2842 qemu_flush_coalesced_mmio_buffer();
2843 if (unlocked) {
2844 qemu_mutex_unlock_iothread();
2848 return release_lock;
2851 /* Called within RCU critical section. */
2852 static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
2853 MemTxAttrs attrs,
2854 const uint8_t *buf,
2855 int len, hwaddr addr1,
2856 hwaddr l, MemoryRegion *mr)
2858 uint8_t *ptr;
2859 uint64_t val;
2860 MemTxResult result = MEMTX_OK;
2861 bool release_lock = false;
2863 for (;;) {
2864 if (!memory_access_is_direct(mr, true)) {
2865 release_lock |= prepare_mmio_access(mr);
2866 l = memory_access_size(mr, l, addr1);
2867 /* XXX: could force current_cpu to NULL to avoid
2868 potential bugs */
2869 switch (l) {
2870 case 8:
2871 /* 64 bit write access */
2872 val = ldq_p(buf);
2873 result |= memory_region_dispatch_write(mr, addr1, val, 8,
2874 attrs);
2875 break;
2876 case 4:
2877 /* 32 bit write access */
2878 val = (uint32_t)ldl_p(buf);
2879 result |= memory_region_dispatch_write(mr, addr1, val, 4,
2880 attrs);
2881 break;
2882 case 2:
2883 /* 16 bit write access */
2884 val = lduw_p(buf);
2885 result |= memory_region_dispatch_write(mr, addr1, val, 2,
2886 attrs);
2887 break;
2888 case 1:
2889 /* 8 bit write access */
2890 val = ldub_p(buf);
2891 result |= memory_region_dispatch_write(mr, addr1, val, 1,
2892 attrs);
2893 break;
2894 default:
2895 abort();
2897 } else {
2898 /* RAM case */
2899 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2900 memcpy(ptr, buf, l);
2901 invalidate_and_set_dirty(mr, addr1, l);
2904 if (release_lock) {
2905 qemu_mutex_unlock_iothread();
2906 release_lock = false;
2909 len -= l;
2910 buf += l;
2911 addr += l;
2913 if (!len) {
2914 break;
2917 l = len;
2918 mr = address_space_translate(as, addr, &addr1, &l, true);
2921 return result;
2924 MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2925 const uint8_t *buf, int len)
2927 hwaddr l;
2928 hwaddr addr1;
2929 MemoryRegion *mr;
2930 MemTxResult result = MEMTX_OK;
2932 if (len > 0) {
2933 rcu_read_lock();
2934 l = len;
2935 mr = address_space_translate(as, addr, &addr1, &l, true);
2936 result = address_space_write_continue(as, addr, attrs, buf, len,
2937 addr1, l, mr);
2938 rcu_read_unlock();
2941 return result;
2944 /* Called within RCU critical section. */
2945 MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr,
2946 MemTxAttrs attrs, uint8_t *buf,
2947 int len, hwaddr addr1, hwaddr l,
2948 MemoryRegion *mr)
2950 uint8_t *ptr;
2951 uint64_t val;
2952 MemTxResult result = MEMTX_OK;
2953 bool release_lock = false;
2955 for (;;) {
2956 if (!memory_access_is_direct(mr, false)) {
2957 /* I/O case */
2958 release_lock |= prepare_mmio_access(mr);
2959 l = memory_access_size(mr, l, addr1);
2960 switch (l) {
2961 case 8:
2962 /* 64 bit read access */
2963 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
2964 attrs);
2965 stq_p(buf, val);
2966 break;
2967 case 4:
2968 /* 32 bit read access */
2969 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
2970 attrs);
2971 stl_p(buf, val);
2972 break;
2973 case 2:
2974 /* 16 bit read access */
2975 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
2976 attrs);
2977 stw_p(buf, val);
2978 break;
2979 case 1:
2980 /* 8 bit read access */
2981 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
2982 attrs);
2983 stb_p(buf, val);
2984 break;
2985 default:
2986 abort();
2988 } else {
2989 /* RAM case */
2990 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2991 memcpy(buf, ptr, l);
2994 if (release_lock) {
2995 qemu_mutex_unlock_iothread();
2996 release_lock = false;
2999 len -= l;
3000 buf += l;
3001 addr += l;
3003 if (!len) {
3004 break;
3007 l = len;
3008 mr = address_space_translate(as, addr, &addr1, &l, false);
3011 return result;
3014 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3015 MemTxAttrs attrs, uint8_t *buf, int len)
3017 hwaddr l;
3018 hwaddr addr1;
3019 MemoryRegion *mr;
3020 MemTxResult result = MEMTX_OK;
3022 if (len > 0) {
3023 rcu_read_lock();
3024 l = len;
3025 mr = address_space_translate(as, addr, &addr1, &l, false);
3026 result = address_space_read_continue(as, addr, attrs, buf, len,
3027 addr1, l, mr);
3028 rcu_read_unlock();
3031 return result;
3034 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3035 uint8_t *buf, int len, bool is_write)
3037 if (is_write) {
3038 return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
3039 } else {
3040 return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
3044 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3045 int len, int is_write)
3047 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3048 buf, len, is_write);
3051 enum write_rom_type {
3052 WRITE_DATA,
3053 FLUSH_CACHE,
3056 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3057 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3059 hwaddr l;
3060 uint8_t *ptr;
3061 hwaddr addr1;
3062 MemoryRegion *mr;
3064 rcu_read_lock();
3065 while (len > 0) {
3066 l = len;
3067 mr = address_space_translate(as, addr, &addr1, &l, true);
3069 if (!(memory_region_is_ram(mr) ||
3070 memory_region_is_romd(mr))) {
3071 l = memory_access_size(mr, l, addr1);
3072 } else {
3073 /* ROM/RAM case */
3074 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3075 switch (type) {
3076 case WRITE_DATA:
3077 memcpy(ptr, buf, l);
3078 invalidate_and_set_dirty(mr, addr1, l);
3079 break;
3080 case FLUSH_CACHE:
3081 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3082 break;
3085 len -= l;
3086 buf += l;
3087 addr += l;
3089 rcu_read_unlock();
3092 /* used for ROM loading : can write in RAM and ROM */
3093 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3094 const uint8_t *buf, int len)
3096 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3099 void cpu_flush_icache_range(hwaddr start, int len)
3102 * This function should do the same thing as an icache flush that was
3103 * triggered from within the guest. For TCG we are always cache coherent,
3104 * so there is no need to flush anything. For KVM / Xen we need to flush
3105 * the host's instruction cache at least.
3107 if (tcg_enabled()) {
3108 return;
3111 cpu_physical_memory_write_rom_internal(&address_space_memory,
3112 start, NULL, len, FLUSH_CACHE);
3115 typedef struct {
3116 MemoryRegion *mr;
3117 void *buffer;
3118 hwaddr addr;
3119 hwaddr len;
3120 bool in_use;
3121 } BounceBuffer;
3123 static BounceBuffer bounce;
3125 typedef struct MapClient {
3126 QEMUBH *bh;
3127 QLIST_ENTRY(MapClient) link;
3128 } MapClient;
3130 QemuMutex map_client_list_lock;
3131 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3132 = QLIST_HEAD_INITIALIZER(map_client_list);
3134 static void cpu_unregister_map_client_do(MapClient *client)
3136 QLIST_REMOVE(client, link);
3137 g_free(client);
3140 static void cpu_notify_map_clients_locked(void)
3142 MapClient *client;
3144 while (!QLIST_EMPTY(&map_client_list)) {
3145 client = QLIST_FIRST(&map_client_list);
3146 qemu_bh_schedule(client->bh);
3147 cpu_unregister_map_client_do(client);
3151 void cpu_register_map_client(QEMUBH *bh)
3153 MapClient *client = g_malloc(sizeof(*client));
3155 qemu_mutex_lock(&map_client_list_lock);
3156 client->bh = bh;
3157 QLIST_INSERT_HEAD(&map_client_list, client, link);
3158 if (!atomic_read(&bounce.in_use)) {
3159 cpu_notify_map_clients_locked();
3161 qemu_mutex_unlock(&map_client_list_lock);
3164 void cpu_exec_init_all(void)
3166 qemu_mutex_init(&ram_list.mutex);
3167 /* The data structures we set up here depend on knowing the page size,
3168 * so no more changes can be made after this point.
3169 * In an ideal world, nothing we did before we had finished the
3170 * machine setup would care about the target page size, and we could
3171 * do this much later, rather than requiring board models to state
3172 * up front what their requirements are.
3174 finalize_target_page_bits();
3175 io_mem_init();
3176 memory_map_init();
3177 qemu_mutex_init(&map_client_list_lock);
3180 void cpu_unregister_map_client(QEMUBH *bh)
3182 MapClient *client;
3184 qemu_mutex_lock(&map_client_list_lock);
3185 QLIST_FOREACH(client, &map_client_list, link) {
3186 if (client->bh == bh) {
3187 cpu_unregister_map_client_do(client);
3188 break;
3191 qemu_mutex_unlock(&map_client_list_lock);
3194 static void cpu_notify_map_clients(void)
3196 qemu_mutex_lock(&map_client_list_lock);
3197 cpu_notify_map_clients_locked();
3198 qemu_mutex_unlock(&map_client_list_lock);
3201 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
3203 MemoryRegion *mr;
3204 hwaddr l, xlat;
3206 rcu_read_lock();
3207 while (len > 0) {
3208 l = len;
3209 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3210 if (!memory_access_is_direct(mr, is_write)) {
3211 l = memory_access_size(mr, l, addr);
3212 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3213 rcu_read_unlock();
3214 return false;
3218 len -= l;
3219 addr += l;
3221 rcu_read_unlock();
3222 return true;
3225 static hwaddr
3226 address_space_extend_translation(AddressSpace *as, hwaddr addr, hwaddr target_len,
3227 MemoryRegion *mr, hwaddr base, hwaddr len,
3228 bool is_write)
3230 hwaddr done = 0;
3231 hwaddr xlat;
3232 MemoryRegion *this_mr;
3234 for (;;) {
3235 target_len -= len;
3236 addr += len;
3237 done += len;
3238 if (target_len == 0) {
3239 return done;
3242 len = target_len;
3243 this_mr = address_space_translate(as, addr, &xlat, &len, is_write);
3244 if (this_mr != mr || xlat != base + done) {
3245 return done;
3250 /* Map a physical memory region into a host virtual address.
3251 * May map a subset of the requested range, given by and returned in *plen.
3252 * May return NULL if resources needed to perform the mapping are exhausted.
3253 * Use only for reads OR writes - not for read-modify-write operations.
3254 * Use cpu_register_map_client() to know when retrying the map operation is
3255 * likely to succeed.
3257 void *address_space_map(AddressSpace *as,
3258 hwaddr addr,
3259 hwaddr *plen,
3260 bool is_write)
3262 hwaddr len = *plen;
3263 hwaddr l, xlat;
3264 MemoryRegion *mr;
3265 void *ptr;
3267 if (len == 0) {
3268 return NULL;
3271 l = len;
3272 rcu_read_lock();
3273 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3275 if (!memory_access_is_direct(mr, is_write)) {
3276 if (atomic_xchg(&bounce.in_use, true)) {
3277 rcu_read_unlock();
3278 return NULL;
3280 /* Avoid unbounded allocations */
3281 l = MIN(l, TARGET_PAGE_SIZE);
3282 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3283 bounce.addr = addr;
3284 bounce.len = l;
3286 memory_region_ref(mr);
3287 bounce.mr = mr;
3288 if (!is_write) {
3289 address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
3290 bounce.buffer, l);
3293 rcu_read_unlock();
3294 *plen = l;
3295 return bounce.buffer;
3299 memory_region_ref(mr);
3300 *plen = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3301 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen);
3302 rcu_read_unlock();
3304 return ptr;
3307 /* Unmaps a memory region previously mapped by address_space_map().
3308 * Will also mark the memory as dirty if is_write == 1. access_len gives
3309 * the amount of memory that was actually read or written by the caller.
3311 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3312 int is_write, hwaddr access_len)
3314 if (buffer != bounce.buffer) {
3315 MemoryRegion *mr;
3316 ram_addr_t addr1;
3318 mr = memory_region_from_host(buffer, &addr1);
3319 assert(mr != NULL);
3320 if (is_write) {
3321 invalidate_and_set_dirty(mr, addr1, access_len);
3323 if (xen_enabled()) {
3324 xen_invalidate_map_cache_entry(buffer);
3326 memory_region_unref(mr);
3327 return;
3329 if (is_write) {
3330 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3331 bounce.buffer, access_len);
3333 qemu_vfree(bounce.buffer);
3334 bounce.buffer = NULL;
3335 memory_region_unref(bounce.mr);
3336 atomic_mb_set(&bounce.in_use, false);
3337 cpu_notify_map_clients();
3340 void *cpu_physical_memory_map(hwaddr addr,
3341 hwaddr *plen,
3342 int is_write)
3344 return address_space_map(&address_space_memory, addr, plen, is_write);
3347 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3348 int is_write, hwaddr access_len)
3350 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3353 #define ARG1_DECL AddressSpace *as
3354 #define ARG1 as
3355 #define SUFFIX
3356 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3357 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3358 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3359 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3360 #define RCU_READ_LOCK(...) rcu_read_lock()
3361 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3362 #include "memory_ldst.inc.c"
3364 int64_t address_space_cache_init(MemoryRegionCache *cache,
3365 AddressSpace *as,
3366 hwaddr addr,
3367 hwaddr len,
3368 bool is_write)
3370 cache->len = len;
3371 cache->as = as;
3372 cache->xlat = addr;
3373 return len;
3376 void address_space_cache_invalidate(MemoryRegionCache *cache,
3377 hwaddr addr,
3378 hwaddr access_len)
3382 void address_space_cache_destroy(MemoryRegionCache *cache)
3384 cache->as = NULL;
3387 #define ARG1_DECL MemoryRegionCache *cache
3388 #define ARG1 cache
3389 #define SUFFIX _cached
3390 #define TRANSLATE(addr, ...) \
3391 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3392 #define IS_DIRECT(mr, is_write) true
3393 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3394 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3395 #define RCU_READ_LOCK() rcu_read_lock()
3396 #define RCU_READ_UNLOCK() rcu_read_unlock()
3397 #include "memory_ldst.inc.c"
3399 /* virtual memory access for debug (includes writing to ROM) */
3400 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3401 uint8_t *buf, int len, int is_write)
3403 int l;
3404 hwaddr phys_addr;
3405 target_ulong page;
3407 cpu_synchronize_state(cpu);
3408 while (len > 0) {
3409 int asidx;
3410 MemTxAttrs attrs;
3412 page = addr & TARGET_PAGE_MASK;
3413 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3414 asidx = cpu_asidx_from_attrs(cpu, attrs);
3415 /* if no physical page mapped, return an error */
3416 if (phys_addr == -1)
3417 return -1;
3418 l = (page + TARGET_PAGE_SIZE) - addr;
3419 if (l > len)
3420 l = len;
3421 phys_addr += (addr & ~TARGET_PAGE_MASK);
3422 if (is_write) {
3423 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3424 phys_addr, buf, l);
3425 } else {
3426 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3427 MEMTXATTRS_UNSPECIFIED,
3428 buf, l, 0);
3430 len -= l;
3431 buf += l;
3432 addr += l;
3434 return 0;
3438 * Allows code that needs to deal with migration bitmaps etc to still be built
3439 * target independent.
3441 size_t qemu_target_page_size(void)
3443 return TARGET_PAGE_SIZE;
3446 #endif
3449 * A helper function for the _utterly broken_ virtio device model to find out if
3450 * it's running on a big endian machine. Don't do this at home kids!
3452 bool target_words_bigendian(void);
3453 bool target_words_bigendian(void)
3455 #if defined(TARGET_WORDS_BIGENDIAN)
3456 return true;
3457 #else
3458 return false;
3459 #endif
3462 #ifndef CONFIG_USER_ONLY
3463 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3465 MemoryRegion*mr;
3466 hwaddr l = 1;
3467 bool res;
3469 rcu_read_lock();
3470 mr = address_space_translate(&address_space_memory,
3471 phys_addr, &phys_addr, &l, false);
3473 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3474 rcu_read_unlock();
3475 return res;
3478 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3480 RAMBlock *block;
3481 int ret = 0;
3483 rcu_read_lock();
3484 RAMBLOCK_FOREACH(block) {
3485 ret = func(block->idstr, block->host, block->offset,
3486 block->used_length, opaque);
3487 if (ret) {
3488 break;
3491 rcu_read_unlock();
3492 return ret;
3496 * Unmap pages of memory from start to start+length such that
3497 * they a) read as 0, b) Trigger whatever fault mechanism
3498 * the OS provides for postcopy.
3499 * The pages must be unmapped by the end of the function.
3500 * Returns: 0 on success, none-0 on failure
3503 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3505 int ret = -1;
3507 uint8_t *host_startaddr = rb->host + start;
3509 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3510 error_report("ram_block_discard_range: Unaligned start address: %p",
3511 host_startaddr);
3512 goto err;
3515 if ((start + length) <= rb->used_length) {
3516 uint8_t *host_endaddr = host_startaddr + length;
3517 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3518 error_report("ram_block_discard_range: Unaligned end address: %p",
3519 host_endaddr);
3520 goto err;
3523 errno = ENOTSUP; /* If we are missing MADVISE etc */
3525 if (rb->page_size == qemu_host_page_size) {
3526 #if defined(CONFIG_MADVISE)
3527 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3528 * freeing the page.
3530 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3531 #endif
3532 } else {
3533 /* Huge page case - unfortunately it can't do DONTNEED, but
3534 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3535 * huge page file.
3537 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3538 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3539 start, length);
3540 #endif
3542 if (ret) {
3543 ret = -errno;
3544 error_report("ram_block_discard_range: Failed to discard range "
3545 "%s:%" PRIx64 " +%zx (%d)",
3546 rb->idstr, start, length, ret);
3548 } else {
3549 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3550 "/%zx/" RAM_ADDR_FMT")",
3551 rb->idstr, start, length, rb->used_length);
3554 err:
3555 return ret;
3558 #endif