target-arm/helper.c

   1 #include "cpu.h"
   2 #include "gdbstub.h"
   3 #include "helper.h"
   4 #include "host-utils.h"
   5 #include "sysemu.h"
   6
   7 #ifndef CONFIG_USER_ONLY
   8 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
   9                                 int access_type, int is_user,
  10                                 target_phys_addr_t *phys_ptr, int *prot,
  11                                 target_ulong *page_size);
  12 #endif
  13
  14 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  15 {
  16     int nregs;
  17
  18     /* VFP data registers are always little-endian.  */
  19     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  20     if (reg < nregs) {
  21         stfq_le_p(buf, env->vfp.regs[reg]);
  22         return 8;
  23     }
  24     if (arm_feature(env, ARM_FEATURE_NEON)) {
  25         /* Aliases for Q regs.  */
  26         nregs += 16;
  27         if (reg < nregs) {
  28             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  29             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  30             return 16;
  31         }
  32     }
  33     switch (reg - nregs) {
  34     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  35     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  36     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  37     }
  38     return 0;
  39 }
  40
  41 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  42 {
  43     int nregs;
  44
  45     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  46     if (reg < nregs) {
  47         env->vfp.regs[reg] = ldfq_le_p(buf);
  48         return 8;
  49     }
  50     if (arm_feature(env, ARM_FEATURE_NEON)) {
  51         nregs += 16;
  52         if (reg < nregs) {
  53             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  54             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  55             return 16;
  56         }
  57     }
  58     switch (reg - nregs) {
  59     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  60     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  61     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  62     }
  63     return 0;
  64 }
  65
  66 static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
  67 {
  68     env->cp15.c3 = value;
  69     tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
  70     return 0;
  71 }
  72
  73 static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
  74 {
  75     if (env->cp15.c13_fcse != value) {
  76         /* Unlike real hardware the qemu TLB uses virtual addresses,
  77          * not modified virtual addresses, so this causes a TLB flush.
  78          */
  79         tlb_flush(env, 1);
  80         env->cp15.c13_fcse = value;
  81     }
  82     return 0;
  83 }
  84 static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
  85                             uint64_t value)
  86 {
  87     if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
  88         /* For VMSA (when not using the LPAE long descriptor page table
  89          * format) this register includes the ASID, so do a TLB flush.
  90          * For PMSA it is purely a process ID and no action is needed.
  91          */
  92         tlb_flush(env, 1);
  93     }
  94     env->cp15.c13_context = value;
  95     return 0;
  96 }
  97
  98 static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
  99                          uint64_t value)
 100 {
 101     /* Invalidate all (TLBIALL) */
 102     tlb_flush(env, 1);
 103     return 0;
 104 }
 105
 106 static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 107                          uint64_t value)
 108 {
 109     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 110     tlb_flush_page(env, value & TARGET_PAGE_MASK);
 111     return 0;
 112 }
 113
 114 static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 115                           uint64_t value)
 116 {
 117     /* Invalidate by ASID (TLBIASID) */
 118     tlb_flush(env, value == 0);
 119     return 0;
 120 }
 121
 122 static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 123                           uint64_t value)
 124 {
 125     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 126     tlb_flush_page(env, value & TARGET_PAGE_MASK);
 127     return 0;
 128 }
 129
 130 static const ARMCPRegInfo cp_reginfo[] = {
 131     /* DBGDIDR: just RAZ. In particular this means the "debug architecture
 132      * version" bits will read as a reserved value, which should cause
 133      * Linux to not try to use the debug hardware.
 134      */
 135     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 136       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 137     /* MMU Domain access control / MPU write buffer control */
 138     { .name = "DACR", .cp = 15,
 139       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 140       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 141       .resetvalue = 0, .writefn = dacr_write },
 142     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 143       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 144       .resetvalue = 0, .writefn = fcse_write },
 145     { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
 146       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 147       .resetvalue = 0, .writefn = contextidr_write },
 148     /* ??? This covers not just the impdef TLB lockdown registers but also
 149      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 150      */
 151     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 152       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 153     /* MMU TLB control. Note that the wildcarding means we cover not just
 154      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 155      */
 156     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 157       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
 158     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 159       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
 160     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 161       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
 162     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 163       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
 164     /* Cache maintenance ops; some of this space may be overridden later. */
 165     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 166       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 167       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 168     REGINFO_SENTINEL
 169 };
 170
 171 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 172     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 173      * over-broad.
 174      */
 175     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 176       .access = PL1_W, .type = ARM_CP_WFI },
 177     REGINFO_SENTINEL
 178 };
 179
 180 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 181     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 182      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 183      */
 184     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 185       .access = PL1_W, .type = ARM_CP_WFI },
 186     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 187      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 188      * OMAPCP will override this space.
 189      */
 190     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 191       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 192       .resetvalue = 0 },
 193     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 194       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 195       .resetvalue = 0 },
 196     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 197     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 198       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 199     REGINFO_SENTINEL
 200 };
 201
 202 static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 203 {
 204     if (env->cp15.c1_coproc != value) {
 205         env->cp15.c1_coproc = value;
 206         /* ??? Is this safe when called from within a TB?  */
 207         tb_flush(env);
 208     }
 209     return 0;
 210 }
 211
 212 static const ARMCPRegInfo v6_cp_reginfo[] = {
 213     /* prefetch by MVA in v6, NOP in v7 */
 214     { .name = "MVA_prefetch",
 215       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 216       .access = PL1_W, .type = ARM_CP_NOP },
 217     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 218       .access = PL0_W, .type = ARM_CP_NOP },
 219     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 220       .access = PL0_W, .type = ARM_CP_NOP },
 221     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 222       .access = PL0_W, .type = ARM_CP_NOP },
 223     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 224       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 225       .resetvalue = 0, },
 226     /* Watchpoint Fault Address Register : should actually only be present
 227      * for 1136, 1176, 11MPCore.
 228      */
 229     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 230       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 231     { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 232       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 233       .resetvalue = 0, .writefn = cpacr_write },
 234     REGINFO_SENTINEL
 235 };
 236
 237 static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
 238                       uint64_t *value)
 239 {
 240     /* Generic performance monitor register read function for where
 241      * user access may be allowed by PMUSERENR.
 242      */
 243     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 244         return EXCP_UDEF;
 245     }
 246     *value = CPREG_FIELD32(env, ri);
 247     return 0;
 248 }
 249
 250 static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 251                       uint64_t value)
 252 {
 253     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 254         return EXCP_UDEF;
 255     }
 256     /* only the DP, X, D and E bits are writable */
 257     env->cp15.c9_pmcr &= ~0x39;
 258     env->cp15.c9_pmcr |= (value & 0x39);
 259     return 0;
 260 }
 261
 262 static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 263                             uint64_t value)
 264 {
 265     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 266         return EXCP_UDEF;
 267     }
 268     value &= (1 << 31);
 269     env->cp15.c9_pmcnten |= value;
 270     return 0;
 271 }
 272
 273 static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 274                             uint64_t value)
 275 {
 276     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 277         return EXCP_UDEF;
 278     }
 279     value &= (1 << 31);
 280     env->cp15.c9_pmcnten &= ~value;
 281     return 0;
 282 }
 283
 284 static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 285                         uint64_t value)
 286 {
 287     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 288         return EXCP_UDEF;
 289     }
 290     env->cp15.c9_pmovsr &= ~value;
 291     return 0;
 292 }
 293
 294 static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 295                             uint64_t value)
 296 {
 297     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 298         return EXCP_UDEF;
 299     }
 300     env->cp15.c9_pmxevtyper = value & 0xff;
 301     return 0;
 302 }
 303
 304 static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 305                             uint64_t value)
 306 {
 307     env->cp15.c9_pmuserenr = value & 1;
 308     return 0;
 309 }
 310
 311 static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 312                             uint64_t value)
 313 {
 314     /* We have no event counters so only the C bit can be changed */
 315     value &= (1 << 31);
 316     env->cp15.c9_pminten |= value;
 317     return 0;
 318 }
 319
 320 static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 321                             uint64_t value)
 322 {
 323     value &= (1 << 31);
 324     env->cp15.c9_pminten &= ~value;
 325     return 0;
 326 }
 327
 328 static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 329                        uint64_t *value)
 330 {
 331     ARMCPU *cpu = arm_env_get_cpu(env);
 332     *value = cpu->ccsidr[env->cp15.c0_cssel];
 333     return 0;
 334 }
 335
 336 static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 337                         uint64_t value)
 338 {
 339     env->cp15.c0_cssel = value & 0xf;
 340     return 0;
 341 }
 342
 343 static const ARMCPRegInfo v7_cp_reginfo[] = {
 344     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
 345      * debug components
 346      */
 347     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
 348       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 349     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
 350       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 351     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 352     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 353       .access = PL1_W, .type = ARM_CP_NOP },
 354     /* Performance monitors are implementation defined in v7,
 355      * but with an ARM recommended set of registers, which we
 356      * follow (although we don't actually implement any counters)
 357      *
 358      * Performance registers fall into three categories:
 359      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 360      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 361      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 362      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 363      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 364      */
 365     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 366       .access = PL0_RW, .resetvalue = 0,
 367       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 368       .readfn = pmreg_read, .writefn = pmcntenset_write },
 369     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 370       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 371       .readfn = pmreg_read, .writefn = pmcntenclr_write },
 372     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 373       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 374       .readfn = pmreg_read, .writefn = pmovsr_write },
 375     /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
 376      * respect PMUSERENR.
 377      */
 378     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 379       .access = PL0_W, .type = ARM_CP_NOP },
 380     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 381      * We choose to RAZ/WI. XXX should respect PMUSERENR.
 382      */
 383     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 384       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 385     /* Unimplemented, RAZ/WI. XXX PMUSERENR */
 386     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 387       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 388     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 389       .access = PL0_RW,
 390       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 391       .readfn = pmreg_read, .writefn = pmxevtyper_write },
 392     /* Unimplemented, RAZ/WI. XXX PMUSERENR */
 393     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 394       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 395     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 396       .access = PL0_R | PL1_RW,
 397       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 398       .resetvalue = 0,
 399       .writefn = pmuserenr_write },
 400     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 401       .access = PL1_RW,
 402       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 403       .resetvalue = 0,
 404       .writefn = pmintenset_write },
 405     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 406       .access = PL1_RW,
 407       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 408       .resetvalue = 0,
 409       .writefn = pmintenclr_write },
 410     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 411       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 412       .resetvalue = 0, },
 413     { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 414       .access = PL1_R, .readfn = ccsidr_read },
 415     { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 416       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 417       .writefn = csselr_write, .resetvalue = 0 },
 418     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 419      * just RAZ for all cores:
 420      */
 421     { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
 422       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 423     REGINFO_SENTINEL
 424 };
 425
 426 static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 427 {
 428     value &= 1;
 429     env->teecr = value;
 430     return 0;
 431 }
 432
 433 static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 434                        uint64_t *value)
 435 {
 436     /* This is a helper function because the user access rights
 437      * depend on the value of the TEECR.
 438      */
 439     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 440         return EXCP_UDEF;
 441     }
 442     *value = env->teehbr;
 443     return 0;
 444 }
 445
 446 static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 447                         uint64_t value)
 448 {
 449     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 450         return EXCP_UDEF;
 451     }
 452     env->teehbr = value;
 453     return 0;
 454 }
 455
 456 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 457     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 458       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 459       .resetvalue = 0,
 460       .writefn = teecr_write },
 461     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 462       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 463       .resetvalue = 0,
 464       .readfn = teehbr_read, .writefn = teehbr_write },
 465     REGINFO_SENTINEL
 466 };
 467
 468 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 469     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 470       .access = PL0_RW,
 471       .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
 472       .resetvalue = 0 },
 473     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 474       .access = PL0_R|PL1_W,
 475       .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
 476       .resetvalue = 0 },
 477     { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
 478       .access = PL1_RW,
 479       .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
 480       .resetvalue = 0 },
 481     REGINFO_SENTINEL
 482 };
 483
 484 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
 485     /* Dummy implementation: RAZ/WI the whole crn=14 space */
 486     { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
 487       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 488       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 489     REGINFO_SENTINEL
 490 };
 491
 492 static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 493 {
 494     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 495         env->cp15.c7_par = value;
 496     } else if (arm_feature(env, ARM_FEATURE_V7)) {
 497         env->cp15.c7_par = value & 0xfffff6ff;
 498     } else {
 499         env->cp15.c7_par = value & 0xfffff1ff;
 500     }
 501     return 0;
 502 }
 503
 504 #ifndef CONFIG_USER_ONLY
 505 /* get_phys_addr() isn't present for user-mode-only targets */
 506 static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 507 {
 508     target_phys_addr_t phys_addr;
 509     target_ulong page_size;
 510     int prot;
 511     int ret, is_user = ri->opc2 & 2;
 512     int access_type = ri->opc2 & 1;
 513
 514     if (ri->opc2 & 4) {
 515         /* Other states are only available with TrustZone */
 516         return EXCP_UDEF;
 517     }
 518     ret = get_phys_addr(env, value, access_type, is_user,
 519                         &phys_addr, &prot, &page_size);
 520     if (ret == 0) {
 521         /* We do not set any attribute bits in the PAR */
 522         if (page_size == (1 << 24)
 523             && arm_feature(env, ARM_FEATURE_V7)) {
 524             env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
 525         } else {
 526             env->cp15.c7_par = phys_addr & 0xfffff000;
 527         }
 528     } else {
 529         env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
 530             ((ret & (12 << 1)) >> 6) |
 531             ((ret & 0xf) << 1) | 1;
 532     }
 533     env->cp15.c7_par_hi = 0;
 534     return 0;
 535 }
 536 #endif
 537
 538 static const ARMCPRegInfo vapa_cp_reginfo[] = {
 539     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
 540       .access = PL1_RW, .resetvalue = 0,
 541       .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
 542       .writefn = par_write },
 543 #ifndef CONFIG_USER_ONLY
 544     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
 545       .access = PL1_W, .writefn = ats_write },
 546 #endif
 547     REGINFO_SENTINEL
 548 };
 549
 550 /* Return basic MPU access permission bits.  */
 551 static uint32_t simple_mpu_ap_bits(uint32_t val)
 552 {
 553     uint32_t ret;
 554     uint32_t mask;
 555     int i;
 556     ret = 0;
 557     mask = 3;
 558     for (i = 0; i < 16; i += 2) {
 559         ret |= (val >> i) & mask;
 560         mask <<= 2;
 561     }
 562     return ret;
 563 }
 564
 565 /* Pad basic MPU access permission bits to extended format.  */
 566 static uint32_t extended_mpu_ap_bits(uint32_t val)
 567 {
 568     uint32_t ret;
 569     uint32_t mask;
 570     int i;
 571     ret = 0;
 572     mask = 3;
 573     for (i = 0; i < 16; i += 2) {
 574         ret |= (val & mask) << i;
 575         mask <<= 2;
 576     }
 577     return ret;
 578 }
 579
 580 static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 581                                 uint64_t value)
 582 {
 583     env->cp15.c5_data = extended_mpu_ap_bits(value);
 584     return 0;
 585 }
 586
 587 static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
 588                                uint64_t *value)
 589 {
 590     *value = simple_mpu_ap_bits(env->cp15.c5_data);
 591     return 0;
 592 }
 593
 594 static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 595                                 uint64_t value)
 596 {
 597     env->cp15.c5_insn = extended_mpu_ap_bits(value);
 598     return 0;
 599 }
 600
 601 static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
 602                                uint64_t *value)
 603 {
 604     *value = simple_mpu_ap_bits(env->cp15.c5_insn);
 605     return 0;
 606 }
 607
 608 static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
 609                             uint64_t *value)
 610 {
 611     if (ri->crm > 8) {
 612         return EXCP_UDEF;
 613     }
 614     *value = env->cp15.c6_region[ri->crm];
 615     return 0;
 616 }
 617
 618 static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
 619                              uint64_t value)
 620 {
 621     if (ri->crm > 8) {
 622         return EXCP_UDEF;
 623     }
 624     env->cp15.c6_region[ri->crm] = value;
 625     return 0;
 626 }
 627
 628 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
 629     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
 630       .access = PL1_RW,
 631       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
 632       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
 633     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
 634       .access = PL1_RW,
 635       .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
 636       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
 637     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
 638       .access = PL1_RW,
 639       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
 640     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
 641       .access = PL1_RW,
 642       .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
 643     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
 644       .access = PL1_RW,
 645       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
 646     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
 647       .access = PL1_RW,
 648       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
 649     /* Protection region base and size registers */
 650     { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
 651       .opc2 = CP_ANY, .access = PL1_RW,
 652       .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
 653     REGINFO_SENTINEL
 654 };
 655
 656 static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 657                             uint64_t value)
 658 {
 659     value &= 7;
 660     env->cp15.c2_control = value;
 661     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
 662     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
 663     return 0;
 664 }
 665
 666 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 667 {
 668     env->cp15.c2_base_mask = 0xffffc000u;
 669     env->cp15.c2_control = 0;
 670     env->cp15.c2_mask = 0;
 671 }
 672
 673 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
 674     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
 675       .access = PL1_RW,
 676       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
 677     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
 678       .access = PL1_RW,
 679       .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
 680     { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
 681       .access = PL1_RW,
 682       .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
 683     { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
 684       .access = PL1_RW,
 685       .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
 686     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
 687       .access = PL1_RW, .writefn = vmsa_ttbcr_write,
 688       .resetfn = vmsa_ttbcr_reset,
 689       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
 690     { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
 691       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
 692       .resetvalue = 0, },
 693     REGINFO_SENTINEL
 694 };
 695
 696 static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
 697                                uint64_t value)
 698 {
 699     env->cp15.c15_ticonfig = value & 0xe7;
 700     /* The OS_TYPE bit in this register changes the reported CPUID! */
 701     env->cp15.c0_cpuid = (value & (1 << 5)) ?
 702         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
 703     return 0;
 704 }
 705
 706 static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 707                                uint64_t value)
 708 {
 709     env->cp15.c15_threadid = value & 0xffff;
 710     return 0;
 711 }
 712
 713 static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
 714                           uint64_t value)
 715 {
 716     /* Wait-for-interrupt (deprecated) */
 717     cpu_interrupt(env, CPU_INTERRUPT_HALT);
 718     return 0;
 719 }
 720
 721 static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
 722                                  uint64_t value)
 723 {
 724     /* On OMAP there are registers indicating the max/min index of dcache lines
 725      * containing a dirty line; cache flush operations have to reset these.
 726      */
 727     env->cp15.c15_i_max = 0x000;
 728     env->cp15.c15_i_min = 0xff0;
 729     return 0;
 730 }
 731
 732 static const ARMCPRegInfo omap_cp_reginfo[] = {
 733     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
 734       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
 735       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
 736     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 737       .access = PL1_RW, .type = ARM_CP_NOP },
 738     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 739       .access = PL1_RW,
 740       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
 741       .writefn = omap_ticonfig_write },
 742     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
 743       .access = PL1_RW,
 744       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
 745     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
 746       .access = PL1_RW, .resetvalue = 0xff0,
 747       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
 748     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
 749       .access = PL1_RW,
 750       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
 751       .writefn = omap_threadid_write },
 752     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
 753       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
 754       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
 755     /* TODO: Peripheral port remap register:
 756      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
 757      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
 758      * when MMU is off.
 759      */
 760     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 761       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
 762       .writefn = omap_cachemaint_write },
 763     { .name = "C9", .cp = 15, .crn = 9,
 764       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
 765       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
 766     REGINFO_SENTINEL
 767 };
 768
 769 static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 770                              uint64_t value)
 771 {
 772     value &= 0x3fff;
 773     if (env->cp15.c15_cpar != value) {
 774         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
 775         tb_flush(env);
 776         env->cp15.c15_cpar = value;
 777     }
 778     return 0;
 779 }
 780
 781 static const ARMCPRegInfo xscale_cp_reginfo[] = {
 782     { .name = "XSCALE_CPAR",
 783       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
 784       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
 785       .writefn = xscale_cpar_write, },
 786     { .name = "XSCALE_AUXCR",
 787       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
 788       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
 789       .resetvalue = 0, },
 790     REGINFO_SENTINEL
 791 };
 792
 793 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
 794     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
 795      * implementation of this implementation-defined space.
 796      * Ideally this should eventually disappear in favour of actually
 797      * implementing the correct behaviour for all cores.
 798      */
 799     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
 800       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 801       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 802     REGINFO_SENTINEL
 803 };
 804
 805 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
 806     /* Cache status: RAZ because we have no cache so it's always clean */
 807     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
 808       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 809     REGINFO_SENTINEL
 810 };
 811
 812 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
 813     /* We never have a a block transfer operation in progress */
 814     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
 815       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 816     /* The cache ops themselves: these all NOP for QEMU */
 817     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
 818       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 819     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
 820       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 821     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
 822       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 823     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
 824       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 825     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
 826       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 827     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
 828       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 829     REGINFO_SENTINEL
 830 };
 831
 832 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
 833     /* The cache test-and-clean instructions always return (1 << 30)
 834      * to indicate that there are no dirty cache lines.
 835      */
 836     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
 837       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
 838     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
 839       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
 840     REGINFO_SENTINEL
 841 };
 842
 843 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
 844     /* Ignore ReadBuffer accesses */
 845     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
 846       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 847       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
 848       .resetvalue = 0 },
 849     REGINFO_SENTINEL
 850 };
 851
 852 static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 853                       uint64_t *value)
 854 {
 855     uint32_t mpidr = env->cpu_index;
 856     /* We don't support setting cluster ID ([8..11])
 857      * so these bits always RAZ.
 858      */
 859     if (arm_feature(env, ARM_FEATURE_V7MP)) {
 860         mpidr |= (1 << 31);
 861         /* Cores which are uniprocessor (non-coherent)
 862          * but still implement the MP extensions set
 863          * bit 30. (For instance, A9UP.) However we do
 864          * not currently model any of those cores.
 865          */
 866     }
 867     *value = mpidr;
 868     return 0;
 869 }
 870
 871 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
 872     { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
 873       .access = PL1_R, .readfn = mpidr_read },
 874     REGINFO_SENTINEL
 875 };
 876
 877 static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
 878 {
 879     *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
 880     return 0;
 881 }
 882
 883 static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 884 {
 885     env->cp15.c7_par_hi = value >> 32;
 886     env->cp15.c7_par = value;
 887     return 0;
 888 }
 889
 890 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 891 {
 892     env->cp15.c7_par_hi = 0;
 893     env->cp15.c7_par = 0;
 894 }
 895
 896 static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
 897                         uint64_t *value)
 898 {
 899     *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
 900     return 0;
 901 }
 902
 903 static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
 904                          uint64_t value)
 905 {
 906     env->cp15.c2_base0_hi = value >> 32;
 907     env->cp15.c2_base0 = value;
 908     /* Writes to the 64 bit format TTBRs may change the ASID */
 909     tlb_flush(env, 1);
 910     return 0;
 911 }
 912
 913 static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 914 {
 915     env->cp15.c2_base0_hi = 0;
 916     env->cp15.c2_base0 = 0;
 917 }
 918
 919 static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
 920                         uint64_t *value)
 921 {
 922     *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
 923     return 0;
 924 }
 925
 926 static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
 927                          uint64_t value)
 928 {
 929     env->cp15.c2_base1_hi = value >> 32;
 930     env->cp15.c2_base1 = value;
 931     return 0;
 932 }
 933
 934 static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 935 {
 936     env->cp15.c2_base1_hi = 0;
 937     env->cp15.c2_base1 = 0;
 938 }
 939
 940 static const ARMCPRegInfo lpae_cp_reginfo[] = {
 941     /* NOP AMAIR0/1: the override is because these clash with tha rather
 942      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
 943      */
 944     { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
 945       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
 946       .resetvalue = 0 },
 947     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
 948       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
 949       .resetvalue = 0 },
 950     /* 64 bit access versions of the (dummy) debug registers */
 951     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
 952       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 953     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
 954       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 955     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
 956       .access = PL1_RW, .type = ARM_CP_64BIT,
 957       .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
 958     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
 959       .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
 960       .writefn = ttbr064_write, .resetfn = ttbr064_reset },
 961     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
 962       .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
 963       .writefn = ttbr164_write, .resetfn = ttbr164_reset },
 964     REGINFO_SENTINEL
 965 };
 966
 967 static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 968 {
 969     env->cp15.c1_sys = value;
 970     /* ??? Lots of these bits are not implemented.  */
 971     /* This may enable/disable the MMU, so do a TLB flush.  */
 972     tlb_flush(env, 1);
 973     return 0;
 974 }
 975
 976 void register_cp_regs_for_features(ARMCPU *cpu)
 977 {
 978     /* Register all the coprocessor registers based on feature bits */
 979     CPUARMState *env = &cpu->env;
 980     if (arm_feature(env, ARM_FEATURE_M)) {
 981         /* M profile has no coprocessor registers */
 982         return;
 983     }
 984
 985     define_arm_cp_regs(cpu, cp_reginfo);
 986     if (arm_feature(env, ARM_FEATURE_V6)) {
 987         /* The ID registers all have impdef reset values */
 988         ARMCPRegInfo v6_idregs[] = {
 989             { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
 990               .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
 991               .resetvalue = cpu->id_pfr0 },
 992             { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
 993               .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
 994               .resetvalue = cpu->id_pfr1 },
 995             { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
 996               .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
 997               .resetvalue = cpu->id_dfr0 },
 998             { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
 999               .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1000               .resetvalue = cpu->id_afr0 },
1001             { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1002               .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1003               .resetvalue = cpu->id_mmfr0 },
1004             { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1005               .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1006               .resetvalue = cpu->id_mmfr1 },
1007             { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1008               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1009               .resetvalue = cpu->id_mmfr2 },
1010             { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1011               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1012               .resetvalue = cpu->id_mmfr3 },
1013             { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1014               .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1015               .resetvalue = cpu->id_isar0 },
1016             { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1017               .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1018               .resetvalue = cpu->id_isar1 },
1019             { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1020               .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1021               .resetvalue = cpu->id_isar2 },
1022             { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1023               .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1024               .resetvalue = cpu->id_isar3 },
1025             { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1026               .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1027               .resetvalue = cpu->id_isar4 },
1028             { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1029               .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1030               .resetvalue = cpu->id_isar5 },
1031             /* 6..7 are as yet unallocated and must RAZ */
1032             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1033               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1034               .resetvalue = 0 },
1035             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1036               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1037               .resetvalue = 0 },
1038             REGINFO_SENTINEL
1039         };
1040         define_arm_cp_regs(cpu, v6_idregs);
1041         define_arm_cp_regs(cpu, v6_cp_reginfo);
1042     } else {
1043         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1044     }
1045     if (arm_feature(env, ARM_FEATURE_V6K)) {
1046         define_arm_cp_regs(cpu, v6k_cp_reginfo);
1047     }
1048     if (arm_feature(env, ARM_FEATURE_V7)) {
1049         /* v7 performance monitor control register: same implementor
1050          * field as main ID register, and we implement no event counters.
1051          */
1052         ARMCPRegInfo pmcr = {
1053             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1054             .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1055             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1056             .readfn = pmreg_read, .writefn = pmcr_write
1057         };
1058         ARMCPRegInfo clidr = {
1059             .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1060             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1061         };
1062         define_one_arm_cp_reg(cpu, &pmcr);
1063         define_one_arm_cp_reg(cpu, &clidr);
1064         define_arm_cp_regs(cpu, v7_cp_reginfo);
1065     } else {
1066         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1067     }
1068     if (arm_feature(env, ARM_FEATURE_MPU)) {
1069         /* These are the MPU registers prior to PMSAv6. Any new
1070          * PMSA core later than the ARM946 will require that we
1071          * implement the PMSAv6 or PMSAv7 registers, which are
1072          * completely different.
1073          */
1074         assert(!arm_feature(env, ARM_FEATURE_V6));
1075         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1076     } else {
1077         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1078     }
1079     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1080         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1081     }
1082     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1083         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1084     }
1085     if (arm_feature(env, ARM_FEATURE_VAPA)) {
1086         define_arm_cp_regs(cpu, vapa_cp_reginfo);
1087     }
1088     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1089         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1090     }
1091     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1092         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1093     }
1094     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1095         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1096     }
1097     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1098         define_arm_cp_regs(cpu, omap_cp_reginfo);
1099     }
1100     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1101         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1102     }
1103     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1104         define_arm_cp_regs(cpu, xscale_cp_reginfo);
1105     }
1106     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1107         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1108     }
1109     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1110         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1111     }
1112     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1113         define_arm_cp_regs(cpu, lpae_cp_reginfo);
1114     }
1115     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1116      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1117      * be read-only (ie write causes UNDEF exception).
1118      */
1119     {
1120         ARMCPRegInfo id_cp_reginfo[] = {
1121             /* Note that the MIDR isn't a simple constant register because
1122              * of the TI925 behaviour where writes to another register can
1123              * cause the MIDR value to change.
1124              */
1125             { .name = "MIDR",
1126               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1127               .access = PL1_R, .resetvalue = cpu->midr,
1128               .writefn = arm_cp_write_ignore,
1129               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1130             { .name = "CTR",
1131               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1132               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1133             { .name = "TCMTR",
1134               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1135               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1136             { .name = "TLBTR",
1137               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1138               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1139             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1140             { .name = "DUMMY",
1141               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1142               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1143             { .name = "DUMMY",
1144               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1145               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1146             { .name = "DUMMY",
1147               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1148               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1149             { .name = "DUMMY",
1150               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1151               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1152             { .name = "DUMMY",
1153               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1154               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1155             REGINFO_SENTINEL
1156         };
1157         ARMCPRegInfo crn0_wi_reginfo = {
1158             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1159             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1160             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1161         };
1162         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1163             arm_feature(env, ARM_FEATURE_STRONGARM)) {
1164             ARMCPRegInfo *r;
1165             /* Register the blanket "writes ignored" value first to cover the
1166              * whole space. Then define the specific ID registers, but update
1167              * their access field to allow write access, so that they ignore
1168              * writes rather than causing them to UNDEF.
1169              */
1170             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1171             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1172                 r->access = PL1_RW;
1173                 define_one_arm_cp_reg(cpu, r);
1174             }
1175         } else {
1176             /* Just register the standard ID registers (read-only, meaning
1177              * that writes will UNDEF).
1178              */
1179             define_arm_cp_regs(cpu, id_cp_reginfo);
1180         }
1181     }
1182
1183     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1184         ARMCPRegInfo auxcr = {
1185             .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1186             .access = PL1_RW, .type = ARM_CP_CONST,
1187             .resetvalue = cpu->reset_auxcr
1188         };
1189         define_one_arm_cp_reg(cpu, &auxcr);
1190     }
1191
1192     /* Generic registers whose values depend on the implementation */
1193     {
1194         ARMCPRegInfo sctlr = {
1195             .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1196             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1197             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
1198         };
1199         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1200             /* Normally we would always end the TB on an SCTLR write, but Linux
1201              * arch/arm/mach-pxa/sleep.S expects two instructions following
1202              * an MMU enable to execute from cache.  Imitate this behaviour.
1203              */
1204             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1205         }
1206         define_one_arm_cp_reg(cpu, &sctlr);
1207     }
1208 }
1209
1210 ARMCPU *cpu_arm_init(const char *cpu_model)
1211 {
1212     ARMCPU *cpu;
1213     CPUARMState *env;
1214     static int inited = 0;
1215
1216     if (!object_class_by_name(cpu_model)) {
1217         return NULL;
1218     }
1219     cpu = ARM_CPU(object_new(cpu_model));
1220     env = &cpu->env;
1221     env->cpu_model_str = cpu_model;
1222     arm_cpu_realize(cpu);
1223
1224     if (tcg_enabled() && !inited) {
1225         inited = 1;
1226         arm_translate_init();
1227     }
1228
1229     cpu_reset(CPU(cpu));
1230     if (arm_feature(env, ARM_FEATURE_NEON)) {
1231         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1232                                  51, "arm-neon.xml", 0);
1233     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1234         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1235                                  35, "arm-vfp3.xml", 0);
1236     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1237         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1238                                  19, "arm-vfp.xml", 0);
1239     }
1240     qemu_init_vcpu(env);
1241     return cpu;
1242 }
1243
1244 typedef struct ARMCPUListState {
1245     fprintf_function cpu_fprintf;
1246     FILE *file;
1247 } ARMCPUListState;
1248
1249 /* Sort alphabetically by type name, except for "any". */
1250 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1251 {
1252     ObjectClass *class_a = (ObjectClass *)a;
1253     ObjectClass *class_b = (ObjectClass *)b;
1254     const char *name_a, *name_b;
1255
1256     name_a = object_class_get_name(class_a);
1257     name_b = object_class_get_name(class_b);
1258     if (strcmp(name_a, "any") == 0) {
1259         return 1;
1260     } else if (strcmp(name_b, "any") == 0) {
1261         return -1;
1262     } else {
1263         return strcmp(name_a, name_b);
1264     }
1265 }
1266
1267 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1268 {
1269     ObjectClass *oc = data;
1270     ARMCPUListState *s = user_data;
1271
1272     (*s->cpu_fprintf)(s->file, "  %s\n",
1273                       object_class_get_name(oc));
1274 }
1275
1276 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1277 {
1278     ARMCPUListState s = {
1279         .file = f,
1280         .cpu_fprintf = cpu_fprintf,
1281     };
1282     GSList *list;
1283
1284     list = object_class_get_list(TYPE_ARM_CPU, false);
1285     list = g_slist_sort(list, arm_cpu_list_compare);
1286     (*cpu_fprintf)(f, "Available CPUs:\n");
1287     g_slist_foreach(list, arm_cpu_list_entry, &s);
1288     g_slist_free(list);
1289 }
1290
1291 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1292                                        const ARMCPRegInfo *r, void *opaque)
1293 {
1294     /* Define implementations of coprocessor registers.
1295      * We store these in a hashtable because typically
1296      * there are less than 150 registers in a space which
1297      * is 16*16*16*8*8 = 262144 in size.
1298      * Wildcarding is supported for the crm, opc1 and opc2 fields.
1299      * If a register is defined twice then the second definition is
1300      * used, so this can be used to define some generic registers and
1301      * then override them with implementation specific variations.
1302      * At least one of the original and the second definition should
1303      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1304      * against accidental use.
1305      */
1306     int crm, opc1, opc2;
1307     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1308     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1309     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1310     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1311     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1312     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1313     /* 64 bit registers have only CRm and Opc1 fields */
1314     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1315     /* Check that the register definition has enough info to handle
1316      * reads and writes if they are permitted.
1317      */
1318     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1319         if (r->access & PL3_R) {
1320             assert(r->fieldoffset || r->readfn);
1321         }
1322         if (r->access & PL3_W) {
1323             assert(r->fieldoffset || r->writefn);
1324         }
1325     }
1326     /* Bad type field probably means missing sentinel at end of reg list */
1327     assert(cptype_valid(r->type));
1328     for (crm = crmmin; crm <= crmmax; crm++) {
1329         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1330             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1331                 uint32_t *key = g_new(uint32_t, 1);
1332                 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1333                 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1334                 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1335                 r2->opaque = opaque;
1336                 /* Make sure reginfo passed to helpers for wildcarded regs
1337                  * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1338                  */
1339                 r2->crm = crm;
1340                 r2->opc1 = opc1;
1341                 r2->opc2 = opc2;
1342                 /* Overriding of an existing definition must be explicitly
1343                  * requested.
1344                  */
1345                 if (!(r->type & ARM_CP_OVERRIDE)) {
1346                     ARMCPRegInfo *oldreg;
1347                     oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1348                     if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1349                         fprintf(stderr, "Register redefined: cp=%d %d bit "
1350                                 "crn=%d crm=%d opc1=%d opc2=%d, "
1351                                 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1352                                 r2->crn, r2->crm, r2->opc1, r2->opc2,
1353                                 oldreg->name, r2->name);
1354                         assert(0);
1355                     }
1356                 }
1357                 g_hash_table_insert(cpu->cp_regs, key, r2);
1358             }
1359         }
1360     }
1361 }
1362
1363 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1364                                     const ARMCPRegInfo *regs, void *opaque)
1365 {
1366     /* Define a whole list of registers */
1367     const ARMCPRegInfo *r;
1368     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1369         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1370     }
1371 }
1372
1373 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1374 {
1375     return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1376 }
1377
1378 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1379                         uint64_t value)
1380 {
1381     /* Helper coprocessor write function for write-ignore registers */
1382     return 0;
1383 }
1384
1385 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1386 {
1387     /* Helper coprocessor write function for read-as-zero registers */
1388     *value = 0;
1389     return 0;
1390 }
1391
1392 static int bad_mode_switch(CPUARMState *env, int mode)
1393 {
1394     /* Return true if it is not valid for us to switch to
1395      * this CPU mode (ie all the UNPREDICTABLE cases in
1396      * the ARM ARM CPSRWriteByInstr pseudocode).
1397      */
1398     switch (mode) {
1399     case ARM_CPU_MODE_USR:
1400     case ARM_CPU_MODE_SYS:
1401     case ARM_CPU_MODE_SVC:
1402     case ARM_CPU_MODE_ABT:
1403     case ARM_CPU_MODE_UND:
1404     case ARM_CPU_MODE_IRQ:
1405     case ARM_CPU_MODE_FIQ:
1406         return 0;
1407     default:
1408         return 1;
1409     }
1410 }
1411
1412 uint32_t cpsr_read(CPUARMState *env)
1413 {
1414     int ZF;
1415     ZF = (env->ZF == 0);
1416     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
1417         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1418         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1419         | ((env->condexec_bits & 0xfc) << 8)
1420         | (env->GE << 16);
1421 }
1422
1423 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1424 {
1425     if (mask & CPSR_NZCV) {
1426         env->ZF = (~val) & CPSR_Z;
1427         env->NF = val;
1428         env->CF = (val >> 29) & 1;
1429         env->VF = (val << 3) & 0x80000000;
1430     }
1431     if (mask & CPSR_Q)
1432         env->QF = ((val & CPSR_Q) != 0);
1433     if (mask & CPSR_T)
1434         env->thumb = ((val & CPSR_T) != 0);
1435     if (mask & CPSR_IT_0_1) {
1436         env->condexec_bits &= ~3;
1437         env->condexec_bits |= (val >> 25) & 3;
1438     }
1439     if (mask & CPSR_IT_2_7) {
1440         env->condexec_bits &= 3;
1441         env->condexec_bits |= (val >> 8) & 0xfc;
1442     }
1443     if (mask & CPSR_GE) {
1444         env->GE = (val >> 16) & 0xf;
1445     }
1446
1447     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
1448         if (bad_mode_switch(env, val & CPSR_M)) {
1449             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1450              * We choose to ignore the attempt and leave the CPSR M field
1451              * untouched.
1452              */
1453             mask &= ~CPSR_M;
1454         } else {
1455             switch_mode(env, val & CPSR_M);
1456         }
1457     }
1458     mask &= ~CACHED_CPSR_BITS;
1459     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1460 }
1461
1462 /* Sign/zero extend */
1463 uint32_t HELPER(sxtb16)(uint32_t x)
1464 {
1465     uint32_t res;
1466     res = (uint16_t)(int8_t)x;
1467     res |= (uint32_t)(int8_t)(x >> 16) << 16;
1468     return res;
1469 }
1470
1471 uint32_t HELPER(uxtb16)(uint32_t x)
1472 {
1473     uint32_t res;
1474     res = (uint16_t)(uint8_t)x;
1475     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1476     return res;
1477 }
1478
1479 uint32_t HELPER(clz)(uint32_t x)
1480 {
1481     return clz32(x);
1482 }
1483
1484 int32_t HELPER(sdiv)(int32_t num, int32_t den)
1485 {
1486     if (den == 0)
1487       return 0;
1488     if (num == INT_MIN && den == -1)
1489       return INT_MIN;
1490     return num / den;
1491 }
1492
1493 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1494 {
1495     if (den == 0)
1496       return 0;
1497     return num / den;
1498 }
1499
1500 uint32_t HELPER(rbit)(uint32_t x)
1501 {
1502     x =  ((x & 0xff000000) >> 24)
1503        | ((x & 0x00ff0000) >> 8)
1504        | ((x & 0x0000ff00) << 8)
1505        | ((x & 0x000000ff) << 24);
1506     x =  ((x & 0xf0f0f0f0) >> 4)
1507        | ((x & 0x0f0f0f0f) << 4);
1508     x =  ((x & 0x88888888) >> 3)
1509        | ((x & 0x44444444) >> 1)
1510        | ((x & 0x22222222) << 1)
1511        | ((x & 0x11111111) << 3);
1512     return x;
1513 }
1514
1515 uint32_t HELPER(abs)(uint32_t x)
1516 {
1517     return ((int32_t)x < 0) ? -x : x;
1518 }
1519
1520 #if defined(CONFIG_USER_ONLY)
1521
1522 void do_interrupt (CPUARMState *env)
1523 {
1524     env->exception_index = -1;
1525 }
1526
1527 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
1528                               int mmu_idx)
1529 {
1530     if (rw == 2) {
1531         env->exception_index = EXCP_PREFETCH_ABORT;
1532         env->cp15.c6_insn = address;
1533     } else {
1534         env->exception_index = EXCP_DATA_ABORT;
1535         env->cp15.c6_data = address;
1536     }
1537     return 1;
1538 }
1539
1540 /* These should probably raise undefined insn exceptions.  */
1541 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
1542 {
1543     cpu_abort(env, "v7m_mrs %d\n", reg);
1544 }
1545
1546 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
1547 {
1548     cpu_abort(env, "v7m_mrs %d\n", reg);
1549     return 0;
1550 }
1551
1552 void switch_mode(CPUARMState *env, int mode)
1553 {
1554     if (mode != ARM_CPU_MODE_USR)
1555         cpu_abort(env, "Tried to switch out of user mode\n");
1556 }
1557
1558 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
1559 {
1560     cpu_abort(env, "banked r13 write\n");
1561 }
1562
1563 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
1564 {
1565     cpu_abort(env, "banked r13 read\n");
1566     return 0;
1567 }
1568
1569 #else
1570
1571 /* Map CPU modes onto saved register banks.  */
1572 static inline int bank_number(CPUARMState *env, int mode)
1573 {
1574     switch (mode) {
1575     case ARM_CPU_MODE_USR:
1576     case ARM_CPU_MODE_SYS:
1577         return 0;
1578     case ARM_CPU_MODE_SVC:
1579         return 1;
1580     case ARM_CPU_MODE_ABT:
1581         return 2;
1582     case ARM_CPU_MODE_UND:
1583         return 3;
1584     case ARM_CPU_MODE_IRQ:
1585         return 4;
1586     case ARM_CPU_MODE_FIQ:
1587         return 5;
1588     }
1589     cpu_abort(env, "Bad mode %x\n", mode);
1590     return -1;
1591 }
1592
1593 void switch_mode(CPUARMState *env, int mode)
1594 {
1595     int old_mode;
1596     int i;
1597
1598     old_mode = env->uncached_cpsr & CPSR_M;
1599     if (mode == old_mode)
1600         return;
1601
1602     if (old_mode == ARM_CPU_MODE_FIQ) {
1603         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
1604         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
1605     } else if (mode == ARM_CPU_MODE_FIQ) {
1606         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
1607         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
1608     }
1609
1610     i = bank_number(env, old_mode);
1611     env->banked_r13[i] = env->regs[13];
1612     env->banked_r14[i] = env->regs[14];
1613     env->banked_spsr[i] = env->spsr;
1614
1615     i = bank_number(env, mode);
1616     env->regs[13] = env->banked_r13[i];
1617     env->regs[14] = env->banked_r14[i];
1618     env->spsr = env->banked_spsr[i];
1619 }
1620
1621 static void v7m_push(CPUARMState *env, uint32_t val)
1622 {
1623     env->regs[13] -= 4;
1624     stl_phys(env->regs[13], val);
1625 }
1626
1627 static uint32_t v7m_pop(CPUARMState *env)
1628 {
1629     uint32_t val;
1630     val = ldl_phys(env->regs[13]);
1631     env->regs[13] += 4;
1632     return val;
1633 }
1634
1635 /* Switch to V7M main or process stack pointer.  */
1636 static void switch_v7m_sp(CPUARMState *env, int process)
1637 {
1638     uint32_t tmp;
1639     if (env->v7m.current_sp != process) {
1640         tmp = env->v7m.other_sp;
1641         env->v7m.other_sp = env->regs[13];
1642         env->regs[13] = tmp;
1643         env->v7m.current_sp = process;
1644     }
1645 }
1646
1647 static void do_v7m_exception_exit(CPUARMState *env)
1648 {
1649     uint32_t type;
1650     uint32_t xpsr;
1651
1652     type = env->regs[15];
1653     if (env->v7m.exception != 0)
1654         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
1655
1656     /* Switch to the target stack.  */
1657     switch_v7m_sp(env, (type & 4) != 0);
1658     /* Pop registers.  */
1659     env->regs[0] = v7m_pop(env);
1660     env->regs[1] = v7m_pop(env);
1661     env->regs[2] = v7m_pop(env);
1662     env->regs[3] = v7m_pop(env);
1663     env->regs[12] = v7m_pop(env);
1664     env->regs[14] = v7m_pop(env);
1665     env->regs[15] = v7m_pop(env);
1666     xpsr = v7m_pop(env);
1667     xpsr_write(env, xpsr, 0xfffffdff);
1668     /* Undo stack alignment.  */
1669     if (xpsr & 0x200)
1670         env->regs[13] |= 4;
1671     /* ??? The exception return type specifies Thread/Handler mode.  However
1672        this is also implied by the xPSR value. Not sure what to do
1673        if there is a mismatch.  */
1674     /* ??? Likewise for mismatches between the CONTROL register and the stack
1675        pointer.  */
1676 }
1677
1678 static void do_interrupt_v7m(CPUARMState *env)
1679 {
1680     uint32_t xpsr = xpsr_read(env);
1681     uint32_t lr;
1682     uint32_t addr;
1683
1684     lr = 0xfffffff1;
1685     if (env->v7m.current_sp)
1686         lr |= 4;
1687     if (env->v7m.exception == 0)
1688         lr |= 8;
1689
1690     /* For exceptions we just mark as pending on the NVIC, and let that
1691        handle it.  */
1692     /* TODO: Need to escalate if the current priority is higher than the
1693        one we're raising.  */
1694     switch (env->exception_index) {
1695     case EXCP_UDEF:
1696         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
1697         return;
1698     case EXCP_SWI:
1699         env->regs[15] += 2;
1700         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
1701         return;
1702     case EXCP_PREFETCH_ABORT:
1703     case EXCP_DATA_ABORT:
1704         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
1705         return;
1706     case EXCP_BKPT:
1707         if (semihosting_enabled) {
1708             int nr;
1709             nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
1710             if (nr == 0xab) {
1711                 env->regs[15] += 2;
1712                 env->regs[0] = do_arm_semihosting(env);
1713                 return;
1714             }
1715         }
1716         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
1717         return;
1718     case EXCP_IRQ:
1719         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
1720         break;
1721     case EXCP_EXCEPTION_EXIT:
1722         do_v7m_exception_exit(env);
1723         return;
1724     default:
1725         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1726         return; /* Never happens.  Keep compiler happy.  */
1727     }
1728
1729     /* Align stack pointer.  */
1730     /* ??? Should only do this if Configuration Control Register
1731        STACKALIGN bit is set.  */
1732     if (env->regs[13] & 4) {
1733         env->regs[13] -= 4;
1734         xpsr |= 0x200;
1735     }
1736     /* Switch to the handler mode.  */
1737     v7m_push(env, xpsr);
1738     v7m_push(env, env->regs[15]);
1739     v7m_push(env, env->regs[14]);
1740     v7m_push(env, env->regs[12]);
1741     v7m_push(env, env->regs[3]);
1742     v7m_push(env, env->regs[2]);
1743     v7m_push(env, env->regs[1]);
1744     v7m_push(env, env->regs[0]);
1745     switch_v7m_sp(env, 0);
1746     /* Clear IT bits */
1747     env->condexec_bits = 0;
1748     env->regs[14] = lr;
1749     addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1750     env->regs[15] = addr & 0xfffffffe;
1751     env->thumb = addr & 1;
1752 }
1753
1754 /* Handle a CPU exception.  */
1755 void do_interrupt(CPUARMState *env)
1756 {
1757     uint32_t addr;
1758     uint32_t mask;
1759     int new_mode;
1760     uint32_t offset;
1761
1762     if (IS_M(env)) {
1763         do_interrupt_v7m(env);
1764         return;
1765     }
1766     /* TODO: Vectored interrupt controller.  */
1767     switch (env->exception_index) {
1768     case EXCP_UDEF:
1769         new_mode = ARM_CPU_MODE_UND;
1770         addr = 0x04;
1771         mask = CPSR_I;
1772         if (env->thumb)
1773             offset = 2;
1774         else
1775             offset = 4;
1776         break;
1777     case EXCP_SWI:
1778         if (semihosting_enabled) {
1779             /* Check for semihosting interrupt.  */
1780             if (env->thumb) {
1781                 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
1782             } else {
1783                 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
1784                     & 0xffffff;
1785             }
1786             /* Only intercept calls from privileged modes, to provide some
1787                semblance of security.  */
1788             if (((mask == 0x123456 && !env->thumb)
1789                     || (mask == 0xab && env->thumb))
1790                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1791                 env->regs[0] = do_arm_semihosting(env);
1792                 return;
1793             }
1794         }
1795         new_mode = ARM_CPU_MODE_SVC;
1796         addr = 0x08;
1797         mask = CPSR_I;
1798         /* The PC already points to the next instruction.  */
1799         offset = 0;
1800         break;
1801     case EXCP_BKPT:
1802         /* See if this is a semihosting syscall.  */
1803         if (env->thumb && semihosting_enabled) {
1804             mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
1805             if (mask == 0xab
1806                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1807                 env->regs[15] += 2;
1808                 env->regs[0] = do_arm_semihosting(env);
1809                 return;
1810             }
1811         }
1812         env->cp15.c5_insn = 2;
1813         /* Fall through to prefetch abort.  */
1814     case EXCP_PREFETCH_ABORT:
1815         new_mode = ARM_CPU_MODE_ABT;
1816         addr = 0x0c;
1817         mask = CPSR_A | CPSR_I;
1818         offset = 4;
1819         break;
1820     case EXCP_DATA_ABORT:
1821         new_mode = ARM_CPU_MODE_ABT;
1822         addr = 0x10;
1823         mask = CPSR_A | CPSR_I;
1824         offset = 8;
1825         break;
1826     case EXCP_IRQ:
1827         new_mode = ARM_CPU_MODE_IRQ;
1828         addr = 0x18;
1829         /* Disable IRQ and imprecise data aborts.  */
1830         mask = CPSR_A | CPSR_I;
1831         offset = 4;
1832         break;
1833     case EXCP_FIQ:
1834         new_mode = ARM_CPU_MODE_FIQ;
1835         addr = 0x1c;
1836         /* Disable FIQ, IRQ and imprecise data aborts.  */
1837         mask = CPSR_A | CPSR_I | CPSR_F;
1838         offset = 4;
1839         break;
1840     default:
1841         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1842         return; /* Never happens.  Keep compiler happy.  */
1843     }
1844     /* High vectors.  */
1845     if (env->cp15.c1_sys & (1 << 13)) {
1846         addr += 0xffff0000;
1847     }
1848     switch_mode (env, new_mode);
1849     env->spsr = cpsr_read(env);
1850     /* Clear IT bits.  */
1851     env->condexec_bits = 0;
1852     /* Switch to the new mode, and to the correct instruction set.  */
1853     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
1854     env->uncached_cpsr |= mask;
1855     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1856      * and we should just guard the thumb mode on V4 */
1857     if (arm_feature(env, ARM_FEATURE_V4T)) {
1858         env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1859     }
1860     env->regs[14] = env->regs[15] + offset;
1861     env->regs[15] = addr;
1862     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1863 }
1864
1865 /* Check section/page access permissions.
1866    Returns the page protection flags, or zero if the access is not
1867    permitted.  */
1868 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
1869                            int access_type, int is_user)
1870 {
1871   int prot_ro;
1872
1873   if (domain_prot == 3) {
1874     return PAGE_READ | PAGE_WRITE;
1875   }
1876
1877   if (access_type == 1)
1878       prot_ro = 0;
1879   else
1880       prot_ro = PAGE_READ;
1881
1882   switch (ap) {
1883   case 0:
1884       if (access_type == 1)
1885           return 0;
1886       switch ((env->cp15.c1_sys >> 8) & 3) {
1887       case 1:
1888           return is_user ? 0 : PAGE_READ;
1889       case 2:
1890           return PAGE_READ;
1891       default:
1892           return 0;
1893       }
1894   case 1:
1895       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1896   case 2:
1897       if (is_user)
1898           return prot_ro;
1899       else
1900           return PAGE_READ | PAGE_WRITE;
1901   case 3:
1902       return PAGE_READ | PAGE_WRITE;
1903   case 4: /* Reserved.  */
1904       return 0;
1905   case 5:
1906       return is_user ? 0 : prot_ro;
1907   case 6:
1908       return prot_ro;
1909   case 7:
1910       if (!arm_feature (env, ARM_FEATURE_V6K))
1911           return 0;
1912       return prot_ro;
1913   default:
1914       abort();
1915   }
1916 }
1917
1918 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
1919 {
1920     uint32_t table;
1921
1922     if (address & env->cp15.c2_mask)
1923         table = env->cp15.c2_base1 & 0xffffc000;
1924     else
1925         table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1926
1927     table |= (address >> 18) & 0x3ffc;
1928     return table;
1929 }
1930
1931 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
1932                             int is_user, target_phys_addr_t *phys_ptr,
1933                             int *prot, target_ulong *page_size)
1934 {
1935     int code;
1936     uint32_t table;
1937     uint32_t desc;
1938     int type;
1939     int ap;
1940     int domain;
1941     int domain_prot;
1942     target_phys_addr_t phys_addr;
1943
1944     /* Pagetable walk.  */
1945     /* Lookup l1 descriptor.  */
1946     table = get_level1_table_address(env, address);
1947     desc = ldl_phys(table);
1948     type = (desc & 3);
1949     domain = (desc >> 5) & 0x0f;
1950     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1951     if (type == 0) {
1952         /* Section translation fault.  */
1953         code = 5;
1954         goto do_fault;
1955     }
1956     if (domain_prot == 0 || domain_prot == 2) {
1957         if (type == 2)
1958             code = 9; /* Section domain fault.  */
1959         else
1960             code = 11; /* Page domain fault.  */
1961         goto do_fault;
1962     }
1963     if (type == 2) {
1964         /* 1Mb section.  */
1965         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1966         ap = (desc >> 10) & 3;
1967         code = 13;
1968         *page_size = 1024 * 1024;
1969     } else {
1970         /* Lookup l2 entry.  */
1971         if (type == 1) {
1972             /* Coarse pagetable.  */
1973             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1974         } else {
1975             /* Fine pagetable.  */
1976             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1977         }
1978         desc = ldl_phys(table);
1979         switch (desc & 3) {
1980         case 0: /* Page translation fault.  */
1981             code = 7;
1982             goto do_fault;
1983         case 1: /* 64k page.  */
1984             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1985             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
1986             *page_size = 0x10000;
1987             break;
1988         case 2: /* 4k page.  */
1989             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1990             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
1991             *page_size = 0x1000;
1992             break;
1993         case 3: /* 1k page.  */
1994             if (type == 1) {
1995                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1996                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1997                 } else {
1998                     /* Page translation fault.  */
1999                     code = 7;
2000                     goto do_fault;
2001                 }
2002             } else {
2003                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2004             }
2005             ap = (desc >> 4) & 3;
2006             *page_size = 0x400;
2007             break;
2008         default:
2009             /* Never happens, but compiler isn't smart enough to tell.  */
2010             abort();
2011         }
2012         code = 15;
2013     }
2014     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
2015     if (!*prot) {
2016         /* Access permission fault.  */
2017         goto do_fault;
2018     }
2019     *prot |= PAGE_EXEC;
2020     *phys_ptr = phys_addr;
2021     return 0;
2022 do_fault:
2023     return code | (domain << 4);
2024 }
2025
2026 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2027                             int is_user, target_phys_addr_t *phys_ptr,
2028                             int *prot, target_ulong *page_size)
2029 {
2030     int code;
2031     uint32_t table;
2032     uint32_t desc;
2033     uint32_t xn;
2034     uint32_t pxn = 0;
2035     int type;
2036     int ap;
2037     int domain = 0;
2038     int domain_prot;
2039     target_phys_addr_t phys_addr;
2040
2041     /* Pagetable walk.  */
2042     /* Lookup l1 descriptor.  */
2043     table = get_level1_table_address(env, address);
2044     desc = ldl_phys(table);
2045     type = (desc & 3);
2046     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2047         /* Section translation fault, or attempt to use the encoding
2048          * which is Reserved on implementations without PXN.
2049          */
2050         code = 5;
2051         goto do_fault;
2052     }
2053     if ((type == 1) || !(desc & (1 << 18))) {
2054         /* Page or Section.  */
2055         domain = (desc >> 5) & 0x0f;
2056     }
2057     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2058     if (domain_prot == 0 || domain_prot == 2) {
2059         if (type != 1) {
2060             code = 9; /* Section domain fault.  */
2061         } else {
2062             code = 11; /* Page domain fault.  */
2063         }
2064         goto do_fault;
2065     }
2066     if (type != 1) {
2067         if (desc & (1 << 18)) {
2068             /* Supersection.  */
2069             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2070             *page_size = 0x1000000;
2071         } else {
2072             /* Section.  */
2073             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2074             *page_size = 0x100000;
2075         }
2076         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2077         xn = desc & (1 << 4);
2078         pxn = desc & 1;
2079         code = 13;
2080     } else {
2081         if (arm_feature(env, ARM_FEATURE_PXN)) {
2082             pxn = (desc >> 2) & 1;
2083         }
2084         /* Lookup l2 entry.  */
2085         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2086         desc = ldl_phys(table);
2087         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2088         switch (desc & 3) {
2089         case 0: /* Page translation fault.  */
2090             code = 7;
2091             goto do_fault;
2092         case 1: /* 64k page.  */
2093             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2094             xn = desc & (1 << 15);
2095             *page_size = 0x10000;
2096             break;
2097         case 2: case 3: /* 4k page.  */
2098             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2099             xn = desc & 1;
2100             *page_size = 0x1000;
2101             break;
2102         default:
2103             /* Never happens, but compiler isn't smart enough to tell.  */
2104             abort();
2105         }
2106         code = 15;
2107     }
2108     if (domain_prot == 3) {
2109         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2110     } else {
2111         if (pxn && !is_user) {
2112             xn = 1;
2113         }
2114         if (xn && access_type == 2)
2115             goto do_fault;
2116
2117         /* The simplified model uses AP[0] as an access control bit.  */
2118         if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2119             /* Access flag fault.  */
2120             code = (code == 15) ? 6 : 3;
2121             goto do_fault;
2122         }
2123         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
2124         if (!*prot) {
2125             /* Access permission fault.  */
2126             goto do_fault;
2127         }
2128         if (!xn) {
2129             *prot |= PAGE_EXEC;
2130         }
2131     }
2132     *phys_ptr = phys_addr;
2133     return 0;
2134 do_fault:
2135     return code | (domain << 4);
2136 }
2137
2138 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2139                              int access_type, int is_user,
2140                              target_phys_addr_t *phys_ptr, int *prot)
2141 {
2142     int n;
2143     uint32_t mask;
2144     uint32_t base;
2145
2146     *phys_ptr = address;
2147     for (n = 7; n >= 0; n--) {
2148         base = env->cp15.c6_region[n];
2149         if ((base & 1) == 0)
2150             continue;
2151         mask = 1 << ((base >> 1) & 0x1f);
2152         /* Keep this shift separate from the above to avoid an
2153            (undefined) << 32.  */
2154         mask = (mask << 1) - 1;
2155         if (((base ^ address) & ~mask) == 0)
2156             break;
2157     }
2158     if (n < 0)
2159         return 2;
2160
2161     if (access_type == 2) {
2162         mask = env->cp15.c5_insn;
2163     } else {
2164         mask = env->cp15.c5_data;
2165     }
2166     mask = (mask >> (n * 4)) & 0xf;
2167     switch (mask) {
2168     case 0:
2169         return 1;
2170     case 1:
2171         if (is_user)
2172           return 1;
2173         *prot = PAGE_READ | PAGE_WRITE;
2174         break;
2175     case 2:
2176         *prot = PAGE_READ;
2177         if (!is_user)
2178             *prot |= PAGE_WRITE;
2179         break;
2180     case 3:
2181         *prot = PAGE_READ | PAGE_WRITE;
2182         break;
2183     case 5:
2184         if (is_user)
2185             return 1;
2186         *prot = PAGE_READ;
2187         break;
2188     case 6:
2189         *prot = PAGE_READ;
2190         break;
2191     default:
2192         /* Bad permission.  */
2193         return 1;
2194     }
2195     *prot |= PAGE_EXEC;
2196     return 0;
2197 }
2198
2199 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
2200                                 int access_type, int is_user,
2201                                 target_phys_addr_t *phys_ptr, int *prot,
2202                                 target_ulong *page_size)
2203 {
2204     /* Fast Context Switch Extension.  */
2205     if (address < 0x02000000)
2206         address += env->cp15.c13_fcse;
2207
2208     if ((env->cp15.c1_sys & 1) == 0) {
2209         /* MMU/MPU disabled.  */
2210         *phys_ptr = address;
2211         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2212         *page_size = TARGET_PAGE_SIZE;
2213         return 0;
2214     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
2215         *page_size = TARGET_PAGE_SIZE;
2216         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2217                                  prot);
2218     } else if (env->cp15.c1_sys & (1 << 23)) {
2219         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
2220                                 prot, page_size);
2221     } else {
2222         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
2223                                 prot, page_size);
2224     }
2225 }
2226
2227 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
2228                               int access_type, int mmu_idx)
2229 {
2230     target_phys_addr_t phys_addr;
2231     target_ulong page_size;
2232     int prot;
2233     int ret, is_user;
2234
2235     is_user = mmu_idx == MMU_USER_IDX;
2236     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2237                         &page_size);
2238     if (ret == 0) {
2239         /* Map a single [sub]page.  */
2240         phys_addr &= ~(target_phys_addr_t)0x3ff;
2241         address &= ~(uint32_t)0x3ff;
2242         tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
2243         return 0;
2244     }
2245
2246     if (access_type == 2) {
2247         env->cp15.c5_insn = ret;
2248         env->cp15.c6_insn = address;
2249         env->exception_index = EXCP_PREFETCH_ABORT;
2250     } else {
2251         env->cp15.c5_data = ret;
2252         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2253             env->cp15.c5_data |= (1 << 11);
2254         env->cp15.c6_data = address;
2255         env->exception_index = EXCP_DATA_ABORT;
2256     }
2257     return 1;
2258 }
2259
2260 target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
2261 {
2262     target_phys_addr_t phys_addr;
2263     target_ulong page_size;
2264     int prot;
2265     int ret;
2266
2267     ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
2268
2269     if (ret != 0)
2270         return -1;
2271
2272     return phys_addr;
2273 }
2274
2275 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2276 {
2277     if ((env->uncached_cpsr & CPSR_M) == mode) {
2278         env->regs[13] = val;
2279     } else {
2280         env->banked_r13[bank_number(env, mode)] = val;
2281     }
2282 }
2283
2284 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2285 {
2286     if ((env->uncached_cpsr & CPSR_M) == mode) {
2287         return env->regs[13];
2288     } else {
2289         return env->banked_r13[bank_number(env, mode)];
2290     }
2291 }
2292
2293 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2294 {
2295     switch (reg) {
2296     case 0: /* APSR */
2297         return xpsr_read(env) & 0xf8000000;
2298     case 1: /* IAPSR */
2299         return xpsr_read(env) & 0xf80001ff;
2300     case 2: /* EAPSR */
2301         return xpsr_read(env) & 0xff00fc00;
2302     case 3: /* xPSR */
2303         return xpsr_read(env) & 0xff00fdff;
2304     case 5: /* IPSR */
2305         return xpsr_read(env) & 0x000001ff;
2306     case 6: /* EPSR */
2307         return xpsr_read(env) & 0x0700fc00;
2308     case 7: /* IEPSR */
2309         return xpsr_read(env) & 0x0700edff;
2310     case 8: /* MSP */
2311         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2312     case 9: /* PSP */
2313         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2314     case 16: /* PRIMASK */
2315         return (env->uncached_cpsr & CPSR_I) != 0;
2316     case 17: /* BASEPRI */
2317     case 18: /* BASEPRI_MAX */
2318         return env->v7m.basepri;
2319     case 19: /* FAULTMASK */
2320         return (env->uncached_cpsr & CPSR_F) != 0;
2321     case 20: /* CONTROL */
2322         return env->v7m.control;
2323     default:
2324         /* ??? For debugging only.  */
2325         cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2326         return 0;
2327     }
2328 }
2329
2330 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2331 {
2332     switch (reg) {
2333     case 0: /* APSR */
2334         xpsr_write(env, val, 0xf8000000);
2335         break;
2336     case 1: /* IAPSR */
2337         xpsr_write(env, val, 0xf8000000);
2338         break;
2339     case 2: /* EAPSR */
2340         xpsr_write(env, val, 0xfe00fc00);
2341         break;
2342     case 3: /* xPSR */
2343         xpsr_write(env, val, 0xfe00fc00);
2344         break;
2345     case 5: /* IPSR */
2346         /* IPSR bits are readonly.  */
2347         break;
2348     case 6: /* EPSR */
2349         xpsr_write(env, val, 0x0600fc00);
2350         break;
2351     case 7: /* IEPSR */
2352         xpsr_write(env, val, 0x0600fc00);
2353         break;
2354     case 8: /* MSP */
2355         if (env->v7m.current_sp)
2356             env->v7m.other_sp = val;
2357         else
2358             env->regs[13] = val;
2359         break;
2360     case 9: /* PSP */
2361         if (env->v7m.current_sp)
2362             env->regs[13] = val;
2363         else
2364             env->v7m.other_sp = val;
2365         break;
2366     case 16: /* PRIMASK */
2367         if (val & 1)
2368             env->uncached_cpsr |= CPSR_I;
2369         else
2370             env->uncached_cpsr &= ~CPSR_I;
2371         break;
2372     case 17: /* BASEPRI */
2373         env->v7m.basepri = val & 0xff;
2374         break;
2375     case 18: /* BASEPRI_MAX */
2376         val &= 0xff;
2377         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2378             env->v7m.basepri = val;
2379         break;
2380     case 19: /* FAULTMASK */
2381         if (val & 1)
2382             env->uncached_cpsr |= CPSR_F;
2383         else
2384             env->uncached_cpsr &= ~CPSR_F;
2385         break;
2386     case 20: /* CONTROL */
2387         env->v7m.control = val & 3;
2388         switch_v7m_sp(env, (val & 2) != 0);
2389         break;
2390     default:
2391         /* ??? For debugging only.  */
2392         cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2393         return;
2394     }
2395 }
2396
2397 #endif
2398
2399 /* Note that signed overflow is undefined in C.  The following routines are
2400    careful to use unsigned types where modulo arithmetic is required.
2401    Failure to do so _will_ break on newer gcc.  */
2402
2403 /* Signed saturating arithmetic.  */
2404
2405 /* Perform 16-bit signed saturating addition.  */
2406 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2407 {
2408     uint16_t res;
2409
2410     res = a + b;
2411     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2412         if (a & 0x8000)
2413             res = 0x8000;
2414         else
2415             res = 0x7fff;
2416     }
2417     return res;
2418 }
2419
2420 /* Perform 8-bit signed saturating addition.  */
2421 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2422 {
2423     uint8_t res;
2424
2425     res = a + b;
2426     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2427         if (a & 0x80)
2428             res = 0x80;
2429         else
2430             res = 0x7f;
2431     }
2432     return res;
2433 }
2434
2435 /* Perform 16-bit signed saturating subtraction.  */
2436 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2437 {
2438     uint16_t res;
2439
2440     res = a - b;
2441     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2442         if (a & 0x8000)
2443             res = 0x8000;
2444         else
2445             res = 0x7fff;
2446     }
2447     return res;
2448 }
2449
2450 /* Perform 8-bit signed saturating subtraction.  */
2451 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2452 {
2453     uint8_t res;
2454
2455     res = a - b;
2456     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2457         if (a & 0x80)
2458             res = 0x80;
2459         else
2460             res = 0x7f;
2461     }
2462     return res;
2463 }
2464
2465 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2466 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2467 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
2468 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
2469 #define PFX q
2470
2471 #include "op_addsub.h"
2472
2473 /* Unsigned saturating arithmetic.  */
2474 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
2475 {
2476     uint16_t res;
2477     res = a + b;
2478     if (res < a)
2479         res = 0xffff;
2480     return res;
2481 }
2482
2483 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
2484 {
2485     if (a > b)
2486         return a - b;
2487     else
2488         return 0;
2489 }
2490
2491 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2492 {
2493     uint8_t res;
2494     res = a + b;
2495     if (res < a)
2496         res = 0xff;
2497     return res;
2498 }
2499
2500 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2501 {
2502     if (a > b)
2503         return a - b;
2504     else
2505         return 0;
2506 }
2507
2508 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2509 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2510 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
2511 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
2512 #define PFX uq
2513
2514 #include "op_addsub.h"
2515
2516 /* Signed modulo arithmetic.  */
2517 #define SARITH16(a, b, n, op) do { \
2518     int32_t sum; \
2519     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2520     RESULT(sum, n, 16); \
2521     if (sum >= 0) \
2522         ge |= 3 << (n * 2); \
2523     } while(0)
2524
2525 #define SARITH8(a, b, n, op) do { \
2526     int32_t sum; \
2527     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2528     RESULT(sum, n, 8); \
2529     if (sum >= 0) \
2530         ge |= 1 << n; \
2531     } while(0)
2532
2533
2534 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2535 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2536 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
2537 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
2538 #define PFX s
2539 #define ARITH_GE
2540
2541 #include "op_addsub.h"
2542
2543 /* Unsigned modulo arithmetic.  */
2544 #define ADD16(a, b, n) do { \
2545     uint32_t sum; \
2546     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2547     RESULT(sum, n, 16); \
2548     if ((sum >> 16) == 1) \
2549         ge |= 3 << (n * 2); \
2550     } while(0)
2551
2552 #define ADD8(a, b, n) do { \
2553     uint32_t sum; \
2554     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2555     RESULT(sum, n, 8); \
2556     if ((sum >> 8) == 1) \
2557         ge |= 1 << n; \
2558     } while(0)
2559
2560 #define SUB16(a, b, n) do { \
2561     uint32_t sum; \
2562     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2563     RESULT(sum, n, 16); \
2564     if ((sum >> 16) == 0) \
2565         ge |= 3 << (n * 2); \
2566     } while(0)
2567
2568 #define SUB8(a, b, n) do { \
2569     uint32_t sum; \
2570     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2571     RESULT(sum, n, 8); \
2572     if ((sum >> 8) == 0) \
2573         ge |= 1 << n; \
2574     } while(0)
2575
2576 #define PFX u
2577 #define ARITH_GE
2578
2579 #include "op_addsub.h"
2580
2581 /* Halved signed arithmetic.  */
2582 #define ADD16(a, b, n) \
2583   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2584 #define SUB16(a, b, n) \
2585   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2586 #define ADD8(a, b, n) \
2587   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2588 #define SUB8(a, b, n) \
2589   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2590 #define PFX sh
2591
2592 #include "op_addsub.h"
2593
2594 /* Halved unsigned arithmetic.  */
2595 #define ADD16(a, b, n) \
2596   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2597 #define SUB16(a, b, n) \
2598   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2599 #define ADD8(a, b, n) \
2600   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2601 #define SUB8(a, b, n) \
2602   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2603 #define PFX uh
2604
2605 #include "op_addsub.h"
2606
2607 static inline uint8_t do_usad(uint8_t a, uint8_t b)
2608 {
2609     if (a > b)
2610         return a - b;
2611     else
2612         return b - a;
2613 }
2614
2615 /* Unsigned sum of absolute byte differences.  */
2616 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2617 {
2618     uint32_t sum;
2619     sum = do_usad(a, b);
2620     sum += do_usad(a >> 8, b >> 8);
2621     sum += do_usad(a >> 16, b >>16);
2622     sum += do_usad(a >> 24, b >> 24);
2623     return sum;
2624 }
2625
2626 /* For ARMv6 SEL instruction.  */
2627 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2628 {
2629     uint32_t mask;
2630
2631     mask = 0;
2632     if (flags & 1)
2633         mask |= 0xff;
2634     if (flags & 2)
2635         mask |= 0xff00;
2636     if (flags & 4)
2637         mask |= 0xff0000;
2638     if (flags & 8)
2639         mask |= 0xff000000;
2640     return (a & mask) | (b & ~mask);
2641 }
2642
2643 uint32_t HELPER(logicq_cc)(uint64_t val)
2644 {
2645     return (val >> 32) | (val != 0);
2646 }
2647
2648 /* VFP support.  We follow the convention used for VFP instrunctions:
2649    Single precition routines have a "s" suffix, double precision a
2650    "d" suffix.  */
2651
2652 /* Convert host exception flags to vfp form.  */
2653 static inline int vfp_exceptbits_from_host(int host_bits)
2654 {
2655     int target_bits = 0;
2656
2657     if (host_bits & float_flag_invalid)
2658         target_bits |= 1;
2659     if (host_bits & float_flag_divbyzero)
2660         target_bits |= 2;
2661     if (host_bits & float_flag_overflow)
2662         target_bits |= 4;
2663     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
2664         target_bits |= 8;
2665     if (host_bits & float_flag_inexact)
2666         target_bits |= 0x10;
2667     if (host_bits & float_flag_input_denormal)
2668         target_bits |= 0x80;
2669     return target_bits;
2670 }
2671
2672 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
2673 {
2674     int i;
2675     uint32_t fpscr;
2676
2677     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2678             | (env->vfp.vec_len << 16)
2679             | (env->vfp.vec_stride << 20);
2680     i = get_float_exception_flags(&env->vfp.fp_status);
2681     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
2682     fpscr |= vfp_exceptbits_from_host(i);
2683     return fpscr;
2684 }
2685
2686 uint32_t vfp_get_fpscr(CPUARMState *env)
2687 {
2688     return HELPER(vfp_get_fpscr)(env);
2689 }
2690
2691 /* Convert vfp exception flags to target form.  */
2692 static inline int vfp_exceptbits_to_host(int target_bits)
2693 {
2694     int host_bits = 0;
2695
2696     if (target_bits & 1)
2697         host_bits |= float_flag_invalid;
2698     if (target_bits & 2)
2699         host_bits |= float_flag_divbyzero;
2700     if (target_bits & 4)
2701         host_bits |= float_flag_overflow;
2702     if (target_bits & 8)
2703         host_bits |= float_flag_underflow;
2704     if (target_bits & 0x10)
2705         host_bits |= float_flag_inexact;
2706     if (target_bits & 0x80)
2707         host_bits |= float_flag_input_denormal;
2708     return host_bits;
2709 }
2710
2711 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
2712 {
2713     int i;
2714     uint32_t changed;
2715
2716     changed = env->vfp.xregs[ARM_VFP_FPSCR];
2717     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2718     env->vfp.vec_len = (val >> 16) & 7;
2719     env->vfp.vec_stride = (val >> 20) & 3;
2720
2721     changed ^= val;
2722     if (changed & (3 << 22)) {
2723         i = (val >> 22) & 3;
2724         switch (i) {
2725         case 0:
2726             i = float_round_nearest_even;
2727             break;
2728         case 1:
2729             i = float_round_up;
2730             break;
2731         case 2:
2732             i = float_round_down;
2733             break;
2734         case 3:
2735             i = float_round_to_zero;
2736             break;
2737         }
2738         set_float_rounding_mode(i, &env->vfp.fp_status);
2739     }
2740     if (changed & (1 << 24)) {
2741         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2742         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2743     }
2744     if (changed & (1 << 25))
2745         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2746
2747     i = vfp_exceptbits_to_host(val);
2748     set_float_exception_flags(i, &env->vfp.fp_status);
2749     set_float_exception_flags(0, &env->vfp.standard_fp_status);
2750 }
2751
2752 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
2753 {
2754     HELPER(vfp_set_fpscr)(env, val);
2755 }
2756
2757 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2758
2759 #define VFP_BINOP(name) \
2760 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2761 { \
2762     float_status *fpst = fpstp; \
2763     return float32_ ## name(a, b, fpst); \
2764 } \
2765 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2766 { \
2767     float_status *fpst = fpstp; \
2768     return float64_ ## name(a, b, fpst); \
2769 }
2770 VFP_BINOP(add)
2771 VFP_BINOP(sub)
2772 VFP_BINOP(mul)
2773 VFP_BINOP(div)
2774 #undef VFP_BINOP
2775
2776 float32 VFP_HELPER(neg, s)(float32 a)
2777 {
2778     return float32_chs(a);
2779 }
2780
2781 float64 VFP_HELPER(neg, d)(float64 a)
2782 {
2783     return float64_chs(a);
2784 }
2785
2786 float32 VFP_HELPER(abs, s)(float32 a)
2787 {
2788     return float32_abs(a);
2789 }
2790
2791 float64 VFP_HELPER(abs, d)(float64 a)
2792 {
2793     return float64_abs(a);
2794 }
2795
2796 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
2797 {
2798     return float32_sqrt(a, &env->vfp.fp_status);
2799 }
2800
2801 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
2802 {
2803     return float64_sqrt(a, &env->vfp.fp_status);
2804 }
2805
2806 /* XXX: check quiet/signaling case */
2807 #define DO_VFP_cmp(p, type) \
2808 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
2809 { \
2810     uint32_t flags; \
2811     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2812     case 0: flags = 0x6; break; \
2813     case -1: flags = 0x8; break; \
2814     case 1: flags = 0x2; break; \
2815     default: case 2: flags = 0x3; break; \
2816     } \
2817     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2818         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2819 } \
2820 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2821 { \
2822     uint32_t flags; \
2823     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2824     case 0: flags = 0x6; break; \
2825     case -1: flags = 0x8; break; \
2826     case 1: flags = 0x2; break; \
2827     default: case 2: flags = 0x3; break; \
2828     } \
2829     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2830         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2831 }
2832 DO_VFP_cmp(s, float32)
2833 DO_VFP_cmp(d, float64)
2834 #undef DO_VFP_cmp
2835
2836 /* Integer to float and float to integer conversions */
2837
2838 #define CONV_ITOF(name, fsz, sign) \
2839     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2840 { \
2841     float_status *fpst = fpstp; \
2842     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2843 }
2844
2845 #define CONV_FTOI(name, fsz, sign, round) \
2846 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2847 { \
2848     float_status *fpst = fpstp; \
2849     if (float##fsz##_is_any_nan(x)) { \
2850         float_raise(float_flag_invalid, fpst); \
2851         return 0; \
2852     } \
2853     return float##fsz##_to_##sign##int32##round(x, fpst); \
2854 }
2855
2856 #define FLOAT_CONVS(name, p, fsz, sign) \
2857 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2858 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2859 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2860
2861 FLOAT_CONVS(si, s, 32, )
2862 FLOAT_CONVS(si, d, 64, )
2863 FLOAT_CONVS(ui, s, 32, u)
2864 FLOAT_CONVS(ui, d, 64, u)
2865
2866 #undef CONV_ITOF
2867 #undef CONV_FTOI
2868 #undef FLOAT_CONVS
2869
2870 /* floating point conversion */
2871 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
2872 {
2873     float64 r = float32_to_float64(x, &env->vfp.fp_status);
2874     /* ARM requires that S<->D conversion of any kind of NaN generates
2875      * a quiet NaN by forcing the most significant frac bit to 1.
2876      */
2877     return float64_maybe_silence_nan(r);
2878 }
2879
2880 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
2881 {
2882     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
2883     /* ARM requires that S<->D conversion of any kind of NaN generates
2884      * a quiet NaN by forcing the most significant frac bit to 1.
2885      */
2886     return float32_maybe_silence_nan(r);
2887 }
2888
2889 /* VFP3 fixed point conversion.  */
2890 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2891 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t  x, uint32_t shift, \
2892                                     void *fpstp) \
2893 { \
2894     float_status *fpst = fpstp; \
2895     float##fsz tmp; \
2896     tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2897     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2898 } \
2899 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2900                                        void *fpstp) \
2901 { \
2902     float_status *fpst = fpstp; \
2903     float##fsz tmp; \
2904     if (float##fsz##_is_any_nan(x)) { \
2905         float_raise(float_flag_invalid, fpst); \
2906         return 0; \
2907     } \
2908     tmp = float##fsz##_scalbn(x, shift, fpst); \
2909     return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2910 }
2911
2912 VFP_CONV_FIX(sh, d, 64, int16, )
2913 VFP_CONV_FIX(sl, d, 64, int32, )
2914 VFP_CONV_FIX(uh, d, 64, uint16, u)
2915 VFP_CONV_FIX(ul, d, 64, uint32, u)
2916 VFP_CONV_FIX(sh, s, 32, int16, )
2917 VFP_CONV_FIX(sl, s, 32, int32, )
2918 VFP_CONV_FIX(uh, s, 32, uint16, u)
2919 VFP_CONV_FIX(ul, s, 32, uint32, u)
2920 #undef VFP_CONV_FIX
2921
2922 /* Half precision conversions.  */
2923 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
2924 {
2925     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2926     float32 r = float16_to_float32(make_float16(a), ieee, s);
2927     if (ieee) {
2928         return float32_maybe_silence_nan(r);
2929     }
2930     return r;
2931 }
2932
2933 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
2934 {
2935     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2936     float16 r = float32_to_float16(a, ieee, s);
2937     if (ieee) {
2938         r = float16_maybe_silence_nan(r);
2939     }
2940     return float16_val(r);
2941 }
2942
2943 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2944 {
2945     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2946 }
2947
2948 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2949 {
2950     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2951 }
2952
2953 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2954 {
2955     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2956 }
2957
2958 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2959 {
2960     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2961 }
2962
2963 #define float32_two make_float32(0x40000000)
2964 #define float32_three make_float32(0x40400000)
2965 #define float32_one_point_five make_float32(0x3fc00000)
2966
2967 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
2968 {
2969     float_status *s = &env->vfp.standard_fp_status;
2970     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2971         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
2972         if (!(float32_is_zero(a) || float32_is_zero(b))) {
2973             float_raise(float_flag_input_denormal, s);
2974         }
2975         return float32_two;
2976     }
2977     return float32_sub(float32_two, float32_mul(a, b, s), s);
2978 }
2979
2980 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
2981 {
2982     float_status *s = &env->vfp.standard_fp_status;
2983     float32 product;
2984     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2985         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
2986         if (!(float32_is_zero(a) || float32_is_zero(b))) {
2987             float_raise(float_flag_input_denormal, s);
2988         }
2989         return float32_one_point_five;
2990     }
2991     product = float32_mul(a, b, s);
2992     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
2993 }
2994
2995 /* NEON helpers.  */
2996
2997 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2998  * int->float conversions at run-time.  */
2999 #define float64_256 make_float64(0x4070000000000000LL)
3000 #define float64_512 make_float64(0x4080000000000000LL)
3001
3002 /* The algorithm that must be used to calculate the estimate
3003  * is specified by the ARM ARM.
3004  */
3005 static float64 recip_estimate(float64 a, CPUARMState *env)
3006 {
3007     /* These calculations mustn't set any fp exception flags,
3008      * so we use a local copy of the fp_status.
3009      */
3010     float_status dummy_status = env->vfp.standard_fp_status;
3011     float_status *s = &dummy_status;
3012     /* q = (int)(a * 512.0) */
3013     float64 q = float64_mul(float64_512, a, s);
3014     int64_t q_int = float64_to_int64_round_to_zero(q, s);
3015
3016     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3017     q = int64_to_float64(q_int, s);
3018     q = float64_add(q, float64_half, s);
3019     q = float64_div(q, float64_512, s);
3020     q = float64_div(float64_one, q, s);
3021
3022     /* s = (int)(256.0 * r + 0.5) */
3023     q = float64_mul(q, float64_256, s);
3024     q = float64_add(q, float64_half, s);
3025     q_int = float64_to_int64_round_to_zero(q, s);
3026
3027     /* return (double)s / 256.0 */
3028     return float64_div(int64_to_float64(q_int, s), float64_256, s);
3029 }
3030
3031 float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
3032 {
3033     float_status *s = &env->vfp.standard_fp_status;
3034     float64 f64;
3035     uint32_t val32 = float32_val(a);
3036
3037     int result_exp;
3038     int a_exp = (val32  & 0x7f800000) >> 23;
3039     int sign = val32 & 0x80000000;
3040
3041     if (float32_is_any_nan(a)) {
3042         if (float32_is_signaling_nan(a)) {
3043             float_raise(float_flag_invalid, s);
3044         }
3045         return float32_default_nan;
3046     } else if (float32_is_infinity(a)) {
3047         return float32_set_sign(float32_zero, float32_is_neg(a));
3048     } else if (float32_is_zero_or_denormal(a)) {
3049         if (!float32_is_zero(a)) {
3050             float_raise(float_flag_input_denormal, s);
3051         }
3052         float_raise(float_flag_divbyzero, s);
3053         return float32_set_sign(float32_infinity, float32_is_neg(a));
3054     } else if (a_exp >= 253) {
3055         float_raise(float_flag_underflow, s);
3056         return float32_set_sign(float32_zero, float32_is_neg(a));
3057     }
3058
3059     f64 = make_float64((0x3feULL << 52)
3060                        | ((int64_t)(val32 & 0x7fffff) << 29));
3061
3062     result_exp = 253 - a_exp;
3063
3064     f64 = recip_estimate(f64, env);
3065
3066     val32 = sign
3067         | ((result_exp & 0xff) << 23)
3068         | ((float64_val(f64) >> 29) & 0x7fffff);
3069     return make_float32(val32);
3070 }
3071
3072 /* The algorithm that must be used to calculate the estimate
3073  * is specified by the ARM ARM.
3074  */
3075 static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
3076 {
3077     /* These calculations mustn't set any fp exception flags,
3078      * so we use a local copy of the fp_status.
3079      */
3080     float_status dummy_status = env->vfp.standard_fp_status;
3081     float_status *s = &dummy_status;
3082     float64 q;
3083     int64_t q_int;
3084
3085     if (float64_lt(a, float64_half, s)) {
3086         /* range 0.25 <= a < 0.5 */
3087
3088         /* a in units of 1/512 rounded down */
3089         /* q0 = (int)(a * 512.0);  */
3090         q = float64_mul(float64_512, a, s);
3091         q_int = float64_to_int64_round_to_zero(q, s);
3092
3093         /* reciprocal root r */
3094         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
3095         q = int64_to_float64(q_int, s);
3096         q = float64_add(q, float64_half, s);
3097         q = float64_div(q, float64_512, s);
3098         q = float64_sqrt(q, s);
3099         q = float64_div(float64_one, q, s);
3100     } else {
3101         /* range 0.5 <= a < 1.0 */
3102
3103         /* a in units of 1/256 rounded down */
3104         /* q1 = (int)(a * 256.0); */
3105         q = float64_mul(float64_256, a, s);
3106         int64_t q_int = float64_to_int64_round_to_zero(q, s);
3107
3108         /* reciprocal root r */
3109         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3110         q = int64_to_float64(q_int, s);
3111         q = float64_add(q, float64_half, s);
3112         q = float64_div(q, float64_256, s);
3113         q = float64_sqrt(q, s);
3114         q = float64_div(float64_one, q, s);
3115     }
3116     /* r in units of 1/256 rounded to nearest */
3117     /* s = (int)(256.0 * r + 0.5); */
3118
3119     q = float64_mul(q, float64_256,s );
3120     q = float64_add(q, float64_half, s);
3121     q_int = float64_to_int64_round_to_zero(q, s);
3122
3123     /* return (double)s / 256.0;*/
3124     return float64_div(int64_to_float64(q_int, s), float64_256, s);
3125 }
3126
3127 float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
3128 {
3129     float_status *s = &env->vfp.standard_fp_status;
3130     int result_exp;
3131     float64 f64;
3132     uint32_t val;
3133     uint64_t val64;
3134
3135     val = float32_val(a);
3136
3137     if (float32_is_any_nan(a)) {
3138         if (float32_is_signaling_nan(a)) {
3139             float_raise(float_flag_invalid, s);
3140         }
3141         return float32_default_nan;
3142     } else if (float32_is_zero_or_denormal(a)) {
3143         if (!float32_is_zero(a)) {
3144             float_raise(float_flag_input_denormal, s);
3145         }
3146         float_raise(float_flag_divbyzero, s);
3147         return float32_set_sign(float32_infinity, float32_is_neg(a));
3148     } else if (float32_is_neg(a)) {
3149         float_raise(float_flag_invalid, s);
3150         return float32_default_nan;
3151     } else if (float32_is_infinity(a)) {
3152         return float32_zero;
3153     }
3154
3155     /* Normalize to a double-precision value between 0.25 and 1.0,
3156      * preserving the parity of the exponent.  */
3157     if ((val & 0x800000) == 0) {
3158         f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3159                            | (0x3feULL << 52)
3160                            | ((uint64_t)(val & 0x7fffff) << 29));
3161     } else {
3162         f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3163                            | (0x3fdULL << 52)
3164                            | ((uint64_t)(val & 0x7fffff) << 29));
3165     }
3166
3167     result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3168
3169     f64 = recip_sqrt_estimate(f64, env);
3170
3171     val64 = float64_val(f64);
3172
3173     val = ((result_exp & 0xff) << 23)
3174         | ((val64 >> 29)  & 0x7fffff);
3175     return make_float32(val);
3176 }
3177
3178 uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
3179 {
3180     float64 f64;
3181
3182     if ((a & 0x80000000) == 0) {
3183         return 0xffffffff;
3184     }
3185
3186     f64 = make_float64((0x3feULL << 52)
3187                        | ((int64_t)(a & 0x7fffffff) << 21));
3188
3189     f64 = recip_estimate (f64, env);
3190
3191     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
3192 }
3193
3194 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
3195 {
3196     float64 f64;
3197
3198     if ((a & 0xc0000000) == 0) {
3199         return 0xffffffff;
3200     }
3201
3202     if (a & 0x80000000) {
3203         f64 = make_float64((0x3feULL << 52)
3204                            | ((uint64_t)(a & 0x7fffffff) << 21));
3205     } else { /* bits 31-30 == '01' */
3206         f64 = make_float64((0x3fdULL << 52)
3207                            | ((uint64_t)(a & 0x3fffffff) << 22));
3208     }
3209
3210     f64 = recip_sqrt_estimate(f64, env);
3211
3212     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
3213 }
3214
3215 /* VFPv4 fused multiply-accumulate */
3216 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3217 {
3218     float_status *fpst = fpstp;
3219     return float32_muladd(a, b, c, 0, fpst);
3220 }
3221
3222 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3223 {
3224     float_status *fpst = fpstp;
3225     return float64_muladd(a, b, c, 0, fpst);
3226 }